Semiconductor logic circuits containing nonvolatile memory cells

Abstract

A phase change memory (PCM) device includes a bottom electrode, a bottom heater on the bottom electrode, a bottom buffer layer on the bottom heater, a PCM region on the bottom buffer layer, an top buffer layer on the PCM region, an top heater on the top buffer layer, and an top electrode on the top heater.

Description

[Technical Field]

[0001] The present disclosure relates generally to semiconductor logic circuits, and more particularly to exclusive OR (XOR) circuits and exclusive NOR (XNOR) circuits that include a single non-volatile memory cell. [Background technology]

[0002] Phase change memory (PCM) devices are non-volatile memory devices that can maintain the state of their storage element for days to decades without consuming power. Examples of volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM); DRAM requires its storage element to be constantly refreshed, while SRAM requires a constant supply of energy to maintain the state of its storage element.

[0003] In phase-change memory, information is stored in a material that can be manipulated to assume different phases. Each of these phases exhibits different electrical properties that can be used to store information. The amorphous and crystalline phases are typically the two phases used for bit storage (0 and 1) because they have a detectable difference in electrical resistance. Specifically, the amorphous phase has a higher electrical resistance than the crystalline phase.

[0004] Chalcogenides are a group of materials commonly used as phase change materials. This group of materials includes chalcogens (Group 16 / VIA of the Periodic Table) and other elements. Selenium (Se) and tellurium (Te) are the two most common semiconductors in the group used to create chalcogenides in making phase change memory cells. Examples of this would be Ge2Sb2Te5 (GST-225), SbTe, and In2Se3.

[0005] Phase change memory cell designs also attempt to minimize the area of ​​each cell in order to maximize the density of the memory cell array and thereby reduce the overall die footprint of the associated circuitry. Reducing the number of circuit components required for a logic device provides a means to reduce the overall logic die footprint. Summary of the Invention

[0006] The following summary is presented in order to provide a basic understanding of one or more embodiments of the present disclosure. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented below. In one or more embodiments described herein, a device, system, computer-implemented method, apparatus, or computer program product, or combination thereof, enables computer logic circuits with a reduced number of components and a reduced die footprint.

[0007] An embodiment of the invention includes a semiconductor device having a lower electrode, a lower heater on the lower electrode, a lower buffer layer on the lower heater, a PCM region on the lower buffer layer, an upper buffer layer on the PCM region, an upper heater on the upper buffer layer, and an upper electrode on the upper heater.

[0008] Aspects of the present invention disclose methods, systems, and computer logic circuits related to a semiconductor logic circuit including nonvolatile memory cells arranged in series between a first node and a second node, where a first node is configured to receive a first write pulse, a second node is configured to receive a second write pulse, and the circuit is configured to receive a read pulse across the first node and the second node. The method includes, prior to a logic write operation, simultaneously applying a first write pulse and a second write pulse to the nonvolatile memory cells, simultaneously writing a first logic state at the first node and a second logic state at the second node to the nonvolatile memory, applying a read pulse across the first node and the second node, and interpreting the logic state of the circuit according to a response associated with the read pulse.

[0009] The above and other objects, features and advantages of the present disclosure will become more apparent from a more detailed description of several embodiments of the present disclosure in the accompanying drawings, in which like reference numerals generally refer to like components in the embodiments of the present disclosure. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a semiconductor device under fabrication according to one embodiment of the present invention. [Figure 2] 1 is a cross-sectional view of a semiconductor device under fabrication according to one embodiment of the present invention. [Figure 3] 1 is a cross-sectional view of a semiconductor device under fabrication according to one embodiment of the present invention. [Figure 4] 1 is a cross-sectional view of a semiconductor device under fabrication according to one embodiment of the present invention. [Figure 5] FIG. 2 is a graph of input voltage and device state, according to one embodiment of the present invention. [Figure 6] FIG. 2 is a schematic diagram of logic circuit components according to one embodiment of the present invention. [Figure 7] FIG. 4 is a schematic diagram of logic circuitry controlling write and read signals, according to one embodiment of the present invention. [Figure 8] 8 illustrates device logic state changes for a device receiving the signals shown in FIG. 7, according to one embodiment of the present invention. [Figure 9] 4 is a flowchart illustrating a sequence of operations according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Various embodiments of the present invention are described herein with reference to the associated drawings. Other embodiments may be devised without departing from the scope of the present invention. It should be noted that the following description and drawings describe various connections and relationships (e.g., above, below, adjacent, etc.) between elements. These connections and / or relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, the coupling of entities may refer to a direct coupling or an indirect coupling, and the relationship between entities may be a direct relationship or an indirect relationship. As an example of an indirect relationship, when the description refers to forming layer "A" on layer "B," it includes the situation where there are one or more intervening layers (e.g., layer "C") between layer "A" and layer "B," so long as the relative properties and functions of layer "A" and layer "B" are not substantially altered by the intervening layers.

[0012] The following definitions and abbreviations shall be used for the interpretation of the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that comprises listed elements is not necessarily limited to only those elements and may include other elements not expressly described or inherent to such composition, mixture, process, method, article, or device.

[0013] Moreover, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer number greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "plurality" is understood to include any integer number greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "coupled" can include indirect and direct "coupled."

[0014] When used herein, the term "one embodiment," "an embodiment," "an example embodiment," or the like indicates that the embodiment being described may include a particular feature, structure, or characteristic, but that not all embodiments may include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is recognized that it is within the knowledge of one skilled in the art to use that feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0015] In the following description, the terms "top," "bottom," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives refer to the structures and methods described and oriented in the drawings. The terms "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is above a second element, such as a second structure, where there may be an intervening element, such as an interface structure, between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface between the two elements. Note that the term "selective to," e.g., "a first element selective to a second element," means that the first element can be etched and the second element can function as an etch stop.

[0016] For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. Also, various operations and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned herein without providing details of the well-known processes or are omitted entirely.

[0017] However, as background, the following provides a more general description of semiconductor device manufacturing processes that can be used in implementing one or more embodiments of the present invention. While the specific manufacturing operations used in implementing one or more embodiments of the present invention may be individually known, the described combination of operations and / or resulting structures of the present invention is unique. Thus, the unique combination of operations described in connection with fabricating semiconductor devices in accordance with the present invention uses a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the following paragraphs.

[0018] PCM materials exploit the large difference in resistance between the amorphous and crystalline states. The amorphous phase has high electrical resistivity, while the crystalline phase has low resistivity. The difference in resistivity is often three to four orders of magnitude. Therefore, the change in read current is quite large, providing the possibility of multiple analog levels necessary for multilevel cell technology operation.

[0019] PCM materials can be set from a high-resistivity amorphous phase to a low-resistivity crystalline phase by applying a current sufficient to raise the temperature of the PCM material above the threshold temperature required to crystallize the amorphous phase. The PCM material can then be reset by applying a current sufficient to raise the temperature of the PCM material above the material's melting temperature, melting the crystals. The molten material is then quenched by rapidly removing the current. Quenching the PCM material returns the material to the amorphous glassy phase.

[0020] Efforts to miniaturize computer processors have focused on shrinking individual circuit components and reducing the number of required circuit components. The disclosed embodiments enable a reduced die footprint for exclusive OR (XOR) circuits and exclusive negated OR (XNOR) circuits by reducing the number of required circuit components. The disclosed circuits include a single non-volatile phase change memory cell for each of the XOR and XNOR types.

[0021] This embodiment may include an integrated circuit chip design that can be written in a graphical computer programming language and stored on a computer storage medium (disk, tape, physical hard drive, or virtual hard drive, such as in a storage access network). If the designer does not fabricate the chip or the photolithography masks used to fabricate the chip, the designer can directly or indirectly transfer the resulting design to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into a format (e.g., GDSII) suitable for fabrication of photolithography masks, which typically contain multiple copies of the target chip design to be formed on a wafer. The photolithography masks are used to define areas of the wafer (and / or layers thereon) to be processed by etching or otherwise.

[0022] The methods described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in raw wafer form (i.e., as a single wafer containing multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in single-chip packages (such as plastic carriers with leads attached to a motherboard or other higher-level carrier) or multi-chip packages (such as ceramic carriers with single-sided or double-sided interconnects or embedded interconnects). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices, or a combination thereof, as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to sophisticated computer products with displays, keyboards, or other input devices, and central processors.

[0023] 1 illustrates a semiconductor device 100 under fabrication in accordance with one embodiment of the present invention. As shown, device 100 includes a bottom electrode 130 disposed on a dielectric layer, such as a SiO layer 120, which is in turn disposed on a substrate 110. Each layer can be formed, for example, by sputtering or chemical vapor deposition (CVD) using a metal, typically tungsten or titanium nitride, to form bottom electrode 130.

[0024] The semiconductor substrate 110 may include any semiconductor material, including, for example, silicon. The substrate may include circuitry such as logic and memory circuits that are connectable to devices taught by the present invention. The term "semiconductor material" is used throughout this application to refer to a material that has semiconducting properties. In addition to silicon, the semiconductor material may be strained Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon germanium), SiGeC (silicon germanium carbon), Si alloys, Ge alloys, III-V semiconductor materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CaSe (cadmium selenide), CaS (cadmium sulfide), CaTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. By "III-V semiconductor material" it is meant that the semiconductor material includes at least one element from Group IIIA (i.e., Group 13) of the Periodic Table of the Elements and at least one element from Group VA (i.e., Group 15) of the Periodic Table of the Elements.

[0025] 1 further shows device 100 after the formation of lower heater layer 140, examples of lower heater 140 materials include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), and electrically similar materials. Typically, the lower heater 140 material choice is one that does not react or intermix with upper buffer layer 150 at elevated operating temperatures, as described below.

[0026] FIG. 1 further shows the device after deposition of the lower buffer layer 150, PCM region layer 160, upper buffer layer 170, and upper heater layer 180. Examples of upper and lower buffer layer materials include carbon (C), TiN, TaN, TiC, TaC, TiAlN, TaAlN, TiAlC, TaAlC, HfN, and WN. PCM region 160 materials include germanium telluride (GeTe), antimony telluride (Sb2Te3), gallium antimonide (GaSb), aluminum antimonide (AlSb), germanium antimony tellurium (Ge2Sb2Te5), or GST. Other compositions of Ge(x)Sb(y)Te(z) are also possible, where x, y, and z are integers that define the chemical composition. For example, for Ge2Sb2Te5, x=2, y=2, and z=5. Examples of top heater 180 materials include those described for bottom heater 140. After deposition of each layer, CMP may be performed before deposition of the next layer.

[0027] In one embodiment, the PCM region 160 has a thickness of about 100 nm. In one embodiment, the PCM region has a thickness of about 20 nm. In one embodiment, the PCM region 160 has a thickness between about 20 nm and about 100 nm. The switching speed of a PCM device is related to the thickness of the PCM region. For a constant, fixed rate of energy application to the PCM region, thicker layers require longer heating times to change phase and switch logic states. Thinner PCM regions require less overall energy and take less time to change phase and switch logic states.

[0028] Figure 2 shows the device after PCM pillars have been formed from layers 140, 150, 160, 170, and 180 using reactive ion etching or other suitable etching methods. After the PCM pillars are formed, a layer 310 of isolation layer dielectric (ILD) material is deposited. Examples of ILD materials are SiN and low-k dielectrics. The ILD supports, protects, and passivates the PCM pillar structure as shown in Figure 3. CMP is used to planarize the structure and expose the top heater 180.

[0029] 4 shows the device after the addition of ILD material 420, etching of vias for top electrode 430, and deposition of top electrode material similar to that described for bottom electrode 130. The figure further shows etching of vias for the top of bottom electrode 130 through ILD material 310 and deposition of bottom electrode 130 material.

[0030] In one embodiment, one or more components of the system may employ hardware and / or software to solve problems of a highly technical nature (e.g., applying simultaneous write pulses to non-volatile memory cells, reading the state of non-volatile memory cells, interpreting the logic state of a circuit, etc.). These solutions are not abstract and cannot be performed as a series of mental acts by a human, for example, because of the processing power required to facilitate computer logic interpretation. Also, some of the processes performed may be performed by a special-purpose computer to perform defined tasks related to logic circuit operation. For example, a special-purpose computer may be employed to perform tasks related to computer logic, etc.

[0031] In one embodiment, the disclosed logic circuit reduces the processing cycles required to use an XOR circuit. In this embodiment, the method resets the XOR circuit in a first clock cycle by simultaneously applying a first write pulse and a second write pulse to the PCM memory cell. During the second clock cycle, the method writes the logic states of the two nodes X1 and X2 to the XOR circuit memory cell. During the third clock cycle, the method reads the state of the XOR circuit by applying a read voltage to the PCM memory cell.

[0032] The logic truth table for an XOR circuit is shown in Table 1. As shown in the table, an XOR circuit with inputs X1 and X2 and an output Y will output a logic "0" output for matching input values, where both input values ​​are logic "0" or logic "1", and a logic "1" output for mismatching input values, where one input is logic "0" and the other is logic "1".

[0033] [Table 1]

[0034] The logic truth table for the XNOR circuit is shown in Table 2. As shown in the table, an XNOR circuit with inputs X1 and X2 and an output Y will output a logic "1" output for matching input values ​​where both inputs are logic "0" or logic "1", and a logic "0" output for mismatching input values ​​where one input is logic "0" and the other input is logic "1".

[0035] [Table 2]

[0036] Phase-change memory (PCM) cells, such as PCMs using chalcogenide materials, transition between logic "0" and logic "1" by changing the material phase of the constituent chalcogenide material between an amorphous glass, which has a relatively high resistance, and a crystalline lattice, which has a relatively low resistance. As shown in graph 500 of FIG. 5, writing or setting a PCM from its initial logic "0" state to a logic "1" state requires the application of a sufficiently high voltage set pulse 510 to the PCM material such that the associated current flowing through the material raises the material's temperature above its glass-to-crystalline transition temperature 515. By holding the material at a voltage-temperature-length sufficient, the material can be crystallized. Resetting a PCM from logic "1" to logic "0" requires the application of a higher reset voltage pulse 520 and associated higher current to the material. This higher voltage / current generates a higher temperature that exceeds the material's crystalline melting temperature 525, melting the crystals. Rapidly removing this voltage causes the material to reset from its molten state to the amorphous, glassy phase, which represents the logic "0" state. Reading the logic state of the PCM requires applying a read voltage pulse 530 to the PCM material and measuring the resistance and / or current associated with that known read voltage. As shown in Figure 5, the read voltage 530 is below the glass-to-crystalline transition threshold 515. Reading the logic state of the PCM cell neither sets nor resets the PCM cell material because the electrical signal applied to the PCM cell to read its state does not raise the temperature of the PCM cell sufficiently to crystallize or melt the PCM material.

[0037] 6 illustrates components of a semiconductor logic circuit. As shown, the exemplary circuit portion includes a PCM cell 610 in series with a first node X1 and a second node X2. In one embodiment, the first node X1 connects to a word line and one or more voltage pulse generators and peripheral switching elements that provide control over the signals passing through X1 and the PCM cell 610. Similarly, the second node X2 connects to a bit line and at least one voltage pulse generator. The bit line further connects the second node X2 to a switching element that provides control over the signals passing through X2 and the PCM cell 610. In this embodiment, the voltage pulse generators connected to X1 and the voltage pulse generators connected to X2 have opposite polarities. In this embodiment, a read circuit connects to X1 and X2 and enables application of a low-level read voltage to X1, the PCM cell 610, X2, and the series components, and measurement of the resistance of the PCM through a current generated using a known read voltage.

[0038] FIG. 7 shows a set of timeline diagrams 700 illustrating signals applied to an XOR gate of one embodiment of the present invention relative to a series of clock pulses 710. In one embodiment, prior to each logic write and logic operand read cycle, a parent device including the disclosed logic circuit of FIG. 6 simultaneously applies write pulses to the PCM cell 610 from the X1 and X2 nodes, respectively. As shown in FIG. 7, upon a high clock pulse, the method applies two write pulses 720 to the PCM. The two pulses may fully or only partially overlap when applied to the PCM cell 610. The two pulses are from voltage pulse generators with opposite polarities and combine into a single pulse (not shown) with a voltage amplitude equal to the sum of the two individual voltage amplitudes. In this embodiment, the sum of the two write pulse voltages exceeds the PCM cell 610 material melting voltage threshold, and the passage of a corresponding current increases the temperature of the PCM cell 610. The increased temperature melts the material. Rapid removal of the voltage / current cools the material to the amorphous glass phase, thereby resetting the PCM cell 610 to the high-resistivity amorphous glass state. After an intervening low clock pulse, upon the next high clock pulse, the method writes to X1 and X2, respectively, the logic states of the two underlying logic registers. As shown in the figure, Scenario 7A illustrates no pulses at X1 and X2 associated with the logic states of X1=0 and X2=0. Scenario 7B illustrates a single X1 write pulse when X1=1, X2=0. Scenario 7C illustrates a single X2 write pulse when X1=0, X2=1. Scenario 7D illustrates simultaneous X1 and X2 write pulses when X1=1, X2=1. In each scenario, the method applies a read pulse 330 to the PCM cell 610 to determine the current physical state (current and resistance levels) of the PCM cell 610 for use in interpreting the current logic state of the XOR or XNOR logic gate.

[0039] Each of the write pulses applied to PCM cell 610 from X1 or X2 has a high enough voltage amplitude to raise the temperature of PCM cell 610 above the glass-to-crystal threshold of PCM cell 610, but not high enough to raise the temperature above the melting threshold of PCM cell 610. Each pulse alone changes the state of the PCM from glass to crystalline. Combined, the two signals raise the PCM temperature above the melting threshold, thereby resetting the PCM to the glassy state.

[0040] FIG. 8 illustrates the changes made to the logic state of PCM cell 610 when the signals of FIG. 7 are applied. As shown, for each scenario, the method resets the logic state 810 of the PCM from an initial logic state value of "1" to a logic value of "0." When the method applies the combined pre-logic operation pulse 720 to PCM cell 610 of FIG. 6, the logic state resets to "0." In other cases not shown, the initial logic value "0" remains "0" both when and after the combined write pulse is applied to the PCM material. The non-volatile PCM cell maintains this state until a "set" pulse is applied. Regardless of the initial logic state of the circuit, the logic state resets to "0" after application of the combined pulse 720.

[0041] For Scenario 8A, which corresponds to the signal in Scenario 7A, no pulse is applied because X1 and X2 each have a current logic state of "0." The state of the PCM remains the same, and the method reads the logic state of the PCM as high resistance, low current, or logic "0."

[0042] For Scenario 8B, the method applies a single "set" voltage pulse at X1, corresponding to X1=1. The method applies no pulse at X2 because X2=0. The application of the single X1 "set" pulse changes PCM cell 610 from an amorphous glass to a low-resistivity crystalline lattice. The method then reads the logic state of PCM cell 610 as low resistance, high current, or logic "1."

[0043] Similarly, for scenario 8C, the method applies a single write pulse from node X2 to PCM cell 610 because X2 = 1. The method applies no pulse to X1 because X1 = 0. The application of a single X2 "set" pulse again changes PCM cell 610 from an amorphous glass to a crystalline lattice, and the method again reads the current logic state of low resistance, high current, or logic "1."

[0044] In scenario 8D, the method simultaneously applies write pulses from X1 and X2, corresponding to X1=1 and X2=1, respectively. The simultaneous application of the two write pulses raises the temperature of PCM cell 610 above its crystalline melting point, changing the state of PCM cell 610 to a high-resistance amorphous state. The method reads the logic state of PCM cell 610 as high resistance, low current, or logic "0."

[0045] In an exemplary embodiment, application of a reverse polarity voltage pulse may result in a transient PCM cell 610 current that exceeds the melting current threshold of the PCM. In this embodiment, adding an appropriately sized resistor in series between the PCM cell 610 and node X2, or the voltage pulse generator of the node X2 write pulse, allows a write pulse at node X2 with less risk of excessive write pulse current from the X2 write pulse. In some embodiments, a resistor may be placed in series between X1 and the PCM cell 610 to similarly limit the current applied to the PCM cell 610 during a write pulse from X1.

[0046] In one embodiment, the method interprets the logical readout represented by the measured current. A high current corresponds to a logic "1" and a low current corresponds to a logic "0." For this embodiment, the logical readout corresponds to an XOR gate having inputs and corresponding outputs as set forth in Table 1 above. In one embodiment, the method interprets the logical readout represented by the PCM cell 610 resistance. For this embodiment, a high resistance corresponds to a logic "1" and a low resistance corresponds to a logic "0." In one embodiment, the method utilizes the different polarities of the X1 and X2 nodes to shift the amplitude of the voltage sensor from a 0>1 scale to a -1>0 scale. For such an embodiment, the method views the circuit as a logical XNOR gate having inputs and outputs as set forth in Table 2 above.

[0047] In one embodiment, the method uses the different polarities of the X1 and X2 nodes to interpret the circuit as an XNOR circuit rather than an XOR circuit.

[0048] FIG. 9 illustrates a flowchart 900 depicting example activities associated with implementing an embodiment of the present disclosure. After programming begins, at block 910, the logic circuit control program method applies simultaneous write pulses to the PCM cell 610 from nodes X1 and X2, respectively, as referenced above in FIG. 8. The two pulses overlap in time of application to the PCM. The pulses may be simultaneous in application or may simply overlap at least partially. The simultaneous application of two write voltage pulses from voltage pulse generators with opposite polarities results in a combined voltage pulse having an amplitude equal to the sum of the voltage amplitudes of the two underlying voltage pulses. This single write pulse has a voltage amplitude high enough to exceed the melting voltage threshold of the PCM cell 610, raising the temperature of the PCM cell 610 above its melting temperature and resetting the PCM cell 610 to an amorphous state with high resistance.

[0049] At block 920, the logic circuit control program method applies write pulses to the PCM cell 610 via nodes X1 and X2 according to the current logic states of the registers associated with X1 and X2. A write pulse is sent for a logic "1" state, and no pulse is sent for a logic "0" state. Each individual write pulse has a voltage amplitude high enough to transition the PCM cell 610 from glass to crystalline, setting the logic value of the PCM cell 610 from "0" to "1," but not high enough to transition the PCM material to an amorphous state. When combined, the two write pulse voltage amplitudes combine to exceed the melting voltage threshold of the PCM material. The combined pulse melts the PCM and transitions it to a reset, high-resistance amorphous state.

[0050] In this embodiment, for the X1=0, X2=0 logic state, no pulses are applied, and the PCM maintains the glassy state achieved by the application of two simultaneous write pulses prior to the logic write. For the X1=1, X2=0 or X1=0, X2=1 logic states, a single write pulse is applied to PCM cell 610. This single pulse has a voltage amplitude sufficient to transition the PCM from the reset glassy state to the set crystalline state. For the X1=1, X2=1 logic condition, two write pulses are again applied to the PCM. The PCM cell 610 transitions from the reset glassy state to the molten state and then back to the high-resistivity glassy state.

[0051] At block 930, the logic circuit control program method applies a low read voltage pulse to X1, PCM cell 610, X2, and a series of circuit elements. The method reads the current and associated resistance level across these elements, with a high current indicating a low resistance and a low current indicating a high resistance. The read pulse voltage has an amplitude less than the set voltage threshold of the PCM material.

[0052] At block 940, the logic circuit control program method interprets the results of the logic read operation performed at block 930. For an XOR gate operation, the method interprets a high current as a logic "1" and a low current as a logic "0." For an XNOR operation, the method interprets a high current-low resistance as a logic "0" and a low current-high resistance as a logic "0."

[0053] The disclosed circuit embodiments can be fabricated using standard complementary metal oxide semiconductor (CMOS) fabrication techniques. Phase change memory cell structures can include mushroom cell, sealed cell, pillar cell, pore cell, and other structures.

[0054] The present invention may be a system, method, or computer program product, or combination thereof, at any possible level of technical detail of integration. The present invention may be advantageously implemented in any system, single or parallel, that processes instruction streams. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions stored thereon that cause a processor to implement aspects of the present invention.

[0055] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media also includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, punch cards, or mechanically encoded devices such as ridge structures in grooves with instructions recorded thereon, and any suitable combination thereof. As used herein, computer-readable storage medium or computer-readable storage device should not be construed as a transitory signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses through a fiber optic cable), or electrical signals transmitted over wires.

[0056] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to a computer-readable storage medium within the respective computing / processing device for storage.

[0057] Computer-readable program instructions for carrying out the operations of the present invention may be source or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or procedural programming languages, such as object-oriented programming languages ​​such as Smalltalk®, C++, and the "C" programming language, or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer as a standalone software package, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer-readable program instructions by personalizing the electronic circuitry using state information of the computer-readable program instructions.

[0058] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams that illustrate methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0059] These computer-readable program instructions may be supplied to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, form means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium capable of instructing a computer, programmable data processing apparatus, or other apparatus, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are collectively stored comprises an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0060] The computer readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0061] Spatially relative terms, such as "below," "lower," "bottom," "above," "top," etc., may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures were inverted, elements described as being "below" or "below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" encompasses both above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative terms used herein would be interpreted accordingly.

[0062] The terms "about," "substantially," "approximately," and variations thereof are intended to include the error associated with measurement of the particular quantity based on equipment available at the time of filing of this application. For example, "about" can include a range of ±8%, or 5%, or 2% of the stated value.

[0063] The term "selective to," e.g., "a first element selective to a second element," means that the first element can be etched and the second element can act as an etch stop.

[0064] The term "conformal" (eg, a conformal layer) means that the thickness of the layer is substantially the same on all surfaces or that the thickness varies by less than 15% of the nominal thickness of the layer.

[0065] As previously described herein, for the sake of brevity, conventional techniques relating to semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. However, as background, a more general description of a semiconductor device manufacturing process that may be used in implementing one or more embodiments of the present invention follows. While the specific manufacturing operations used in implementing one or more embodiments of the present invention may be individually known, the described combination of operations and / or resulting structures of the present invention is unique. Thus, the unique combination of operations described in connection with the fabrication of semiconductor devices in accordance with the present invention uses a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the following paragraphs.

[0066] Generally, the various processes used to form microchips that are packaged into ICs fall into four broad categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry) and chemical-mechanical planarization (CMP). For example, reactive ion etching (RIE) is a type of dry etching that removes material, such as a masked pattern in a semiconductor material, by exposing the material to a bombardment of ions that remove portions of the material from the exposed surface using a chemically reactive plasma. The plasma is typically generated under low pressure (vacuum) by an electromagnetic field. Semiconductor doping is the modification of electrical properties, typically by doping the source and drain of a transistor via diffusion, ion implantation, or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). The annealing serves to activate the implanted dopants. Both conducting (e.g., polysilicon, aluminum, copper, etc.) and insulating (e.g., various forms of silicon dioxide and silicon nitride, etc.) films are used to connect and separate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the substrate's conductivity to be changed with the application of a voltage. By forming structures composed of these various components, millions of transistors can be fabricated and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the creation of a three-dimensional relief image or pattern on a semiconductor substrate for later transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed using a photosensitive polymer called a photoresist.To create the complex structures that make up the transistors and the many wires that connect the circuit's millions of transistors, multiple lithography and etch pattern transfer steps are used: each pattern printed on the wafer is aligned with the one before it, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0067] The flowcharts and block diagrams in the figures illustrate possible implementations of manufacturing and / or operational methods according to various embodiments of the present invention. Various functions / operations of the methods are represented by blocks in the flowcharts. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially in parallel, or the blocks may be executed in the reverse order, depending on the functionality involved.

[0068] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or to be limited to the embodiments described herein. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the present invention. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technology, or to enable those skilled in the art to understand the embodiments described herein. One embodiment of the present invention is as follows. [Section 1] 1. A phase change memory (PCM) device comprising: A lower electrode; a lower heater above the lower electrode; a lower buffer layer above the lower heater; a PCM region on the lower buffer layer; an upper buffer layer over the PCM region; an upper heater above the upper buffer layer; an upper electrode on the upper heater; PCM devices, including: [Section 2] Item 2. The PCM device of item 1, wherein the lower buffer layer comprises a material selected from the group consisting of C, TiN, TaN, TiC, TaC, TiAlN, TaAlN, TiAlC, TaAlC, HfN, and WN. [Section 3] Item 1. The PCM device of item 1, wherein the lower heater comprises titanium nitride or tantalum nitride. [Section 4] Item 1. The PCM device of item 1, wherein the PCM region comprises a material selected from the group consisting of Sb(x)Te(y), Ge(x)Sb(y)Te(z) and In(x)Se(y), where x, y and z are integers. [Section 5] Item 1. The PCM device of item 1, wherein the PCM region has a thickness of less than 100 nm. [Section 6] Item 1. The PCM device of item 1, wherein the PCM region has a thickness of less than 20 nm. [Section 7] the PCM region has a thickness of 1 nm to 100 nm; Item 1. The PCM device of item 1, wherein the PCM region comprises a material selected from the group consisting of Sb(x)Te(y), Ge(x)Sb(y)Te(z) and In(x)Se(y), where x, y and z are integers. [Section 8] 1. A method of fabricating a semiconductor device, comprising: forming a bottom electrode on a substrate; forming a lower heater on the lower electrode; forming a lower buffer layer on the lower heater; forming a PCM region on the lower buffer layer; forming a top buffer layer over the PCM region; forming an upper heater on the upper buffer layer; forming an upper electrode on the upper heater; A method comprising: [Section 9] Item 9. The method of item 8, wherein the lower buffer layer comprises a material selected from the group consisting of C, TiN, TaN, TiC, TaC, TiAlN, TaAlN, TiAlC, TaAlC, HfN, and WN. [Section 10] Item 9. The method of item 8, wherein the buffer layer comprises germanium telluride. [Section 11] Item 9. The method of item 8, wherein the bottom heater comprises tantalum nitride. [Section 12] 9. The method of claim 8, wherein the PCM region comprises a material selected from the group consisting of Sb(x)Te(y), Ge(x)Sb(y)Te(z), and In(x)Se(y), where x, y, and z are integers. [Section 13] Item 9. The method of item 8, wherein the PCM region has a thickness of less than 100 nm. [Section 14] Item 9. The method of item 8, wherein the PCM region has a thickness of less than 20 nm. [Section 15] 1. A method of using a phase change memory (PCM) semiconductor logic circuit, the circuit including a PCM cell arranged in series between a first node and a second node, the first node configured to receive a first write pulse, the second node configured to receive a second write pulse, and the circuit configured to receive a read pulse across the first node and the second node; The method comprises: simultaneously applying a first write pulse and a second write pulse to the PCM cell prior to a logic write operation, the first write pulse and the second write pulse having a combined voltage amplitude that exceeds a reset voltage amplitude of the PCM cell; simultaneously writing a first logic state of the first node to the PCM cell and a second logic state of the second node to a non-volatile memory; applying a read pulse across the first node and the second node; interpreting the logic state of the circuit according to a current associated with the read pulse; A method comprising: [Section 16] Item 16. The method of item 15, wherein the voltage amplitude of the second write pulse is greater than the set voltage of the PCM cell and less than the reset voltage of the PCM cell. [Section 17] Item 16. The method of item 15, wherein the first write pulse and the second write pulse have different polarities. [Section 18] Item 16. The method of item 15, wherein the voltage amplitude of the first write pulse is greater than the set threshold of the PCM cell and less than the reset voltage of the PCM cell. [Section 19] Item 16. The method of item 15, wherein the voltage amplitude of the read pulse is less than the set threshold of the PCM cell. [Section 20] 16. The method of claim 15, wherein the circuitry includes an XOR logic circuit.

Claims

1. 1. A phase change memory (PCM) device comprising: a semiconductor substrate; a dielectric layer directly over the semiconductor substrate; a lower electrode directly above the dielectric layer; a lower heater on a portion directly above the lower electrode; a lower buffer layer directly above the lower heater; a PCM region directly above the lower buffer layer; an upper buffer layer directly above the PCM region; an upper heater directly above the upper buffer layer; an upper electrode directly above the upper heater; It is equipped with a PCM pillar is formed from the lower heater to the upper heater; a layer of isolation layer dielectric (ILD) material on each side of the PCM pillar; a layer of isolation layer dielectric (ILD) material on each side of the top electrode; one end of the top electrode contacts a portion of an upper surface of a layer of isolation layer dielectric (ILD) material on one side of the PCM pillar, and the other end of the top electrode contacts a portion of an upper surface of a layer of isolation layer dielectric (ILD) material on the other side of the PCM pillar; a via is provided through the layer of isolation layer dielectric (ILD) material on one side of the PCM pillar and directly above the bottom electrode, the via extending to an upper surface of the layer of isolation layer dielectric (ILD) material disposed on one side of the top electrode, and the same material as the bottom electrode is deposited in the via; The PCM device.

2. 2. The PCM device of claim 1, wherein the lower buffer layer comprises a material selected from the group consisting of C, TiN, TaN, TiC, TaC, TiAlN, TaAlN, TiAlC, TaAlC, HfN, and WN.

3. The PCM device of claim 1 , wherein the bottom heater comprises tungsten, titanium nitride, or tantalum nitride.

4. 2. The PCM device of claim 1, wherein the PCM region comprises a material selected from the group consisting of Sb(x)Te(y) and Ge(x)Sb(y)Te(z), where x, y, and z are integers.

5. The PCM device of claim 1 , wherein the PCM region comprises a thickness of 20 nm to 100 nm.

6. The PCM region is made of germanium telluride (GeTe), antimony telluride (Sb ２ Te ３ ), gallium antimonide (GaSb), aluminum antimonide (AlSb), germanium antimony tellurium (Ge ２ Sb ２ Te ５ 10. The PCM device of claim 1, comprising a material selected from the group consisting of SiO.sub.2, ...

7. 2. The PCM device of claim 1, wherein the top buffer layer comprises a material selected from the group consisting of C, TiN, TaN, TiC, TaC, TiAlN, TaAlN, TiAlC, TaAlC, HfN, and WN.

8. 1. A method of fabricating a semiconductor device, comprising: forming a dielectric layer directly over a semiconductor substrate; forming a bottom electrode directly above the dielectric layer; forming a lower heater directly above the lower electrode; forming a lower buffer layer directly above the lower heater; forming a PCM region directly above the lower buffer layer; forming a top buffer layer directly above the PCM region; forming an upper heater directly above the upper buffer layer; Etching from the lower heater to the upper heater to form a PCM pillar from the lower heater to the upper heater; depositing a layer of isolation layer dielectric (ILD) material on both sides of the PCM pillar; forming a top electrode directly above the top heater and forming a layer of isolation layer dielectric (ILD) material on either side of the top electrode; Including, one end of the top electrode contacts a portion of an upper surface of a layer of isolation layer dielectric (ILD) material on one side of the PCM pillar, and the other end of the top electrode contacts a portion of an upper surface of a layer of isolation layer dielectric (ILD) material on the other side of the PCM pillar; a via is provided through the layer of isolation layer dielectric (ILD) material on one side of the PCM pillar and directly above the bottom electrode, the via extending to an upper surface of the layer of isolation layer dielectric (ILD) material disposed on one side of the top electrode, and the same material as the bottom electrode is deposited in the via; The method.

9. 9. The method of claim 8, wherein the lower buffer layer comprises a material selected from the group consisting of C, TiN, TaN, TiC, TaC, TiAlN, TaAlN, TiAlC, TaAlC, HfN, and WN.

10. The method of claim 8 , wherein the bottom heater comprises tungsten, titanium nitride, or tantalum nitride.

11. 9. The method of claim 8, wherein the PCM region comprises a material selected from the group consisting of Sb(x)Te(y) and Ge(x)Sb(y)Te(z), where x, y, and z are integers.

12. The method of claim 8, wherein the PCM region comprises a thickness of 20 nm to 100 nm.

13. The PCM region is made of germanium telluride (GeTe), antimony telluride (Sb ２ Te ３ ), gallium antimonide (GaSb), aluminum antimonide (AlSb), germanium antimony tellurium (Ge ２ Sb ２ Te ５ 9. The method of claim 8, wherein the material comprises a material selected from the group consisting of PEG-100, PEG-200, PEG-300, PEG-4 ...

14. 9. The method of claim 8, wherein the top buffer layer comprises a material selected from the group consisting of C, TiN, TaN, TiC, TaC, TiAlN, TaAlN, TiAlC, TaAlC, HfN, and WN.

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