Method for manufacturing and polishing conductive semiconductor substrate

Abstract

To provide a technique capable of performing polishing while suppressing damage to a surface of a conductive semiconductor substrate.SOLUTION: Provided is a polishing pad used for polishing a surface to be polished of a conductive semiconductor substrate, the polishing pad having a film containing a solid polymer electrolyte on at least part of a polishing surface in contact with the surface to be polished.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a polishing pad, a method for producing a conductive semiconductor substrate, and a polishing method. [Background technology]

[0002] Various methods for polishing the surfaces of conductive semiconductor substrates such as gallium nitride (GaN) substrates and silicon carbide (SiC) substrates have been disclosed. For example, Patent Document 1 discloses a catalyst-referred etching (CARE) method that uses a catalyst such as platinum to promote the etching reaction. Patent Document 2 also discloses a chemical mechanical polishing (CMP) method that uses an oxidizing polishing liquid. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-114632 [Patent Document 2] International Publication No. 2015 / 152021 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a technique that can perform polishing while suppressing damage to the surface of a conductive semiconductor substrate. [Means for solving the problem]

[0005] According to one aspect of the present invention, A polishing pad used for polishing a surface to be polished of a conductive semiconductor substrate, A polishing pad is provided, which has a film containing a solid polymer electrolyte on at least a portion of the polishing surface that contacts the surface to be polished.

[0006] According to another aspect of the present invention, preparing a polishing pad having a film containing a solid polymer electrolyte on at least a portion of a polishing surface that contacts a surface to be polished of a conductive semiconductor substrate; a step of bringing the polishing surface of the polishing pad into contact with the surface to be polished of the conductive semiconductor substrate under pressure while water molecules are in contact with the solid polymer electrolyte, and polishing the surface to be polished by moving the polishing pad and the conductive semiconductor substrate relative to each other while applying a voltage between the polishing pad and the conductive semiconductor substrate; A method for manufacturing a conductive semiconductor substrate is provided, comprising:

[0007] According to yet another aspect of the present invention, preparing a polishing pad having a film containing a solid polymer electrolyte on at least a portion of a polishing surface that contacts a surface to be polished of a conductive semiconductor substrate; a step of bringing the polishing surface of the polishing pad into contact with the surface to be polished of the conductive semiconductor substrate under pressure while water molecules are in contact with the solid polymer electrolyte, and polishing the surface to be polished by moving the polishing pad and the conductive semiconductor substrate relative to each other while applying a voltage between the polishing pad and the conductive semiconductor substrate; A method for polishing a conductive semiconductor substrate is provided, comprising: [Effects of the Invention]

[0008] According to the present invention, polishing can be performed while suppressing damage to the surface of a conductive semiconductor substrate. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1(a) is a plan view schematically showing an example of the polishing surface 13 of the polishing pad 10 of the first embodiment of the present invention, and FIG. 1(b) is a cross-sectional schematic view taken along line AA in FIG. 1(a). [Figure 2] 2(a) and 2(b) are enlarged plan views showing an example of the surface of the SPE film 15 according to the first embodiment of the present invention. [Figure 3]FIG. 3 is a schematic diagram of a polishing apparatus used in the first embodiment of the present invention. [Figure 4] FIG. 4 is a flowchart showing an example of a method for manufacturing the conductive semiconductor substrate 20 according to the first embodiment of the present invention. [Figure 5] Fig. 5(a) is a cross-sectional view schematically showing the polishing surface 14 of the SiC substrate in the preparation step S100 of the first embodiment of the present invention. Fig. 5(b) is a cross-sectional view schematically showing the polishing surface 14 of the SiC substrate and the polishing surface 13 of the polishing pad 10 in the oxidation step S111 of the first embodiment of the present invention. Fig. 5(c) is a cross-sectional view schematically showing the polishing surface 14 of the SiC substrate and the polishing surface 13 of the polishing pad 10 in the removal step S112 of the first embodiment of the present invention. [Figure 6] FIG. 6 is a graph schematically showing the current flowing through the polishing pad 10 in the polishing step S110 of the first embodiment of the present invention. [Figure 7] FIG. 7 is a plan view schematically showing an example of polishing surface 13 of polishing pad 10A according to a second embodiment of the present invention. [Figure 8] Fig. 8(a) is an enlarged schematic view of polishing surface 13 when a nonwoven fabric is used as the substrate of polishing pad 10A according to a second embodiment of the present invention. Fig. 8(b) is an enlarged schematic view of polishing surface 13 when a substrate having an open-cell structure is used in polishing pad 10A according to the second embodiment of the present invention. [Figure 9] FIG. 9 is a plan view schematically showing another example of polishing surface 13 of polishing pad 10A according to the second embodiment of the present invention. [Figure 10] FIG. 10 is an enlarged schematic view of polishing surface 13 of polishing pad 10A according to a second embodiment of the present invention, in which abrasive grains 32 are dispersed on polishing surface 13. As shown in FIG. [Figure 11] FIG. 11 is a flowchart showing an example of a method for manufacturing the conductive semiconductor substrate 20 according to the second embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional photograph of the vicinity of the polished surface 14 of the GaN substrate in the polishing step S110 of the second embodiment of the present invention. [Figure 13]13(a) and 13(b) are plan views schematically showing polishing surface 13 of polishing pad 10B according to a third embodiment of the present invention. [Figure 14] FIG. 14 is a graph schematically showing the current flowing through the polishing pad 10B in the polishing step S110 according to the third embodiment of the present invention. [Figure 15] FIG. 15 is a graph showing the amount of polishing according to Example 1 of the present invention. [Figure 16] FIG. 16 is a diagram showing the arithmetic mean roughness Ra before and after polishing according to Example 1 of the present invention. [Figure 17] FIG. 17(a) is a graph showing the polishing rate (MRR) and current efficiency when the current value is changed according to Example 3 of the present invention, and FIG. 17(b) is a graph showing the change in voltage when polishing is performed with a current value of 250 mA, a duty ratio D of 50%, and a period T of 20 seconds according to Example 3 of the present invention. [Figure 18] FIG. 18(a) is a graph showing the arithmetic mean roughness Ra of a SiC substrate according to Example 3 of the present invention, and FIG. 18(b) is a phase-shifting interference microscope image of the surface of the SiC substrate according to Example 3 of the present invention. [Figure 19] FIG. 19(a) is a phase-shifting interference microscope image at each position on the surface of a SiC substrate according to Example 3 of the present invention, and FIG. 19(b) is a graph showing the surface roughness distribution at each position on the surface of a SiC substrate according to Example 3 of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] <Insights gained by the inventor> First, the findings of the inventors will be explained.

[0011] Various methods have been disclosed for polishing the surfaces of conductive semiconductor substrates such as GaN substrates, SiC substrates, etc. However, because group III nitrides such as GaN are chemically and mechanically more stable than silicon (Si), which is widely used in semiconductor devices, it is extremely difficult to polish the surfaces of GaN substrates or the like at a practical polishing rate (e.g., 100 nm / h or more).

[0012] The modified Mohs hardness of GaN and SiC is 13, making them second only to diamond in hardness. This means that when mechanically polishing the surface of a GaN substrate, etc., it is necessary to use hard abrasives such as diamond abrasives, which may introduce damage to the substrate surface. Another problem is that using diamond abrasives increases the polishing cost.

[0013] Furthermore, because the surface of a GaN substrate, especially the +c plane, is chemically very stable, chemical modification using a chemical solution requires the use of a strong oxidizing agent such as potassium permanganate. Therefore, when polishing the surface of a GaN substrate using CMP, there are problems such as corrosion of the components constituting the polishing equipment by the oxidizing agent and high polishing costs.

[0014] The present inventors have conducted extensive research into the above-mentioned phenomenon. As a result, they have discovered that by using a polishing pad having a film containing a solid polymer electrolyte on at least a portion of the polishing surface, polishing can be performed while suppressing damage to the surface of a conductive semiconductor substrate. In the following embodiments of the present invention, there is no need to use a special oxidizing agent, etc., so polishing can be performed in a neutral range, which has the advantage of facilitating wastewater treatment.

[0015] [Details of the embodiment of the present invention] Next, an embodiment of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0016] <First embodiment of the present invention> (1) Configuration of the polishing pad 10 First, the configuration of the polishing pad 10 of this embodiment will be described. In this embodiment, the case where the polishing pad 10 is used to polish the surface of a conductive semiconductor substrate 20 (hereinafter also referred to as the surface to be polished 14) will be described.

[0017] The polishing pad 10 is used to polish the surface 14 to be polished of the conductive semiconductor substrate 20. In this specification, the surface of the main surfaces of the polishing pad 10 that comes into contact with the surface 14 to be polished of the conductive semiconductor substrate 20 is referred to as the "polishing surface 13," and the surface opposite the polishing surface 13 is referred to as the "back surface." In other words, the polishing surface 13 is the upper surface of the polishing pad 10 when viewed from the surface 14 to be polished (from a direction parallel to the normal direction of the surface 14 to be polished), and is the main surface facing the surface 14 to be polished. The back surface is the main surface facing the upper surface of a platen 21, which will be described later. In this specification, the polishing pad 10 refers to a structure that is disposed between the upper surface of the platen 21 and the surface 14 to be polished, for example.

[0018] The polishing surface 13 of the polishing pad 10 is preferably circular, for example, with a diameter of 500 mm or more and 2000 mm or less. This allows polishing of the polished surface 14 of a conductive semiconductor substrate 20 with a large diameter (for example, 4 inches or more). The thickness of the polishing pad 10 is preferably 0.1 mm or more and 10 mm or less. If the thickness of the polishing pad 10 is less than 0.1 mm, the durability of the polishing pad 10 may be reduced. In contrast, by making the thickness of the polishing pad 10 0.1 mm or more, the durability of the polishing pad 10 can be improved. On the other hand, if the thickness of the polishing pad 10 exceeds 10 mm, the resistance in the thickness direction of the polishing pad 10 may increase. In contrast, by making the thickness of the polishing pad 10 10 mm or less, the resistance in the thickness direction of the polishing pad 10 can be reduced.

[0019] 1(a) is a plan view schematically illustrating an example of the polishing surface 13 of the polishing pad 10 of this embodiment. The polishing pad 10 of this embodiment has a membrane containing a solid polymer electrolyte (SPE) (hereinafter also referred to as an SPE membrane 15) on at least a portion of the polishing surface 13. The SPE membrane 15 may be a membrane made of a solid polymer electrolyte, or may contain a material other than the solid polymer electrolyte as long as it functions as the polishing pad 10.

[0020] The solid polymer electrolyte contained in the SPE membrane 15 is, for example, Nafion (registered trademark, chemical formula: CHF), which is a polymer having a fluorocarbon skeleton and a fluorocarbon ether side chain having a sulfonic acid group at the end. 13 5S·C2F4) can be used. In this embodiment, the SPE film 15 is a film made of Nafion. Nafion can generate OH radicals from water by applying a voltage, for example. By generating OH radicals, the polishing surface 14 of the conductive semiconductor substrate 20 can be oxidized. The oxide 31 (e.g., Ga2O3 or SiO2) generated by oxidizing the conductive semiconductor 30 (e.g., GaN or SiC) that constitutes the polishing surface 14 is softer than the conductive semiconductor 30. Therefore, the oxide 31 generated by oxidizing the polishing surface 14 of the conductive semiconductor substrate 20 can be removed more easily than the conductive semiconductor 30. In this specification, oxidizing the conductive semiconductor 30 that constitutes the polishing surface 14 of the conductive semiconductor substrate 20 is also referred to as "oxidizing the polishing surface 14 of the conductive semiconductor substrate 20" to avoid complication.

[0021] FIG. 1(b) is a schematic cross-sectional view taken along the line AA in FIG. 1(a). As shown in FIG. 1(b), the SPE film 15 may be provided on a conductive substrate (hereinafter also referred to as a conductive substrate 19). In this case, the SPE film 15 is preferably attached to the conductive substrate 19 using, for example, a conductive adhesive. The conductive substrate 19 may be, for example, a stainless steel plate. By providing the SPE film 15 on the conductive substrate 19, the strength of the polishing pad 10 can be improved. Note that if the SPE film 15 has a sufficient thickness, the conductive substrate 19 may be omitted.

[0022] The thickness of the SPE film 15 is preferably, for example, 0.1 mm or more and 1 mm or less. If the thickness of the SPE film 15 is less than 0.1 mm, the life of the polishing pad 10 may be shortened. In contrast, by making the thickness of the SPE film 15 0.1 mm or more, the life of the polishing pad 10 can be improved. On the other hand, if the thickness of the SPE film 15 exceeds 1 mm, the resistance in the thickness direction of the polishing pad 10 may increase. In contrast, by making the thickness of the SPE film 15 1 mm or less, the resistance in the thickness direction of the polishing pad 10 can be reduced. In addition, the cost of the polishing pad 10 can be reduced.

[0023] Since Nafion exhibits electrical conductivity in the presence of water, it is preferable that electrical conduction be established between the polishing surface 13 and the back surface at least when water molecules are in contact with Nafion.

[0024] At least a portion of the surface of the SPE film 15 on the polishing surface 13 comes into contact (slides) with the polishing surface 14 during polishing. However, as described above, when a film made of Nafion is used as the SPE film 15, there is a problem of poor sliding properties relative to the conductive semiconductor substrate 20. This problem is particularly pronounced when polishing the polishing surface 14 of a conductive semiconductor substrate 20 with a large diameter (e.g., 4 inches or more). If the sliding properties relative to the conductive semiconductor substrate 20 are poor, it becomes difficult to move the polishing pad 10 and the conductive semiconductor substrate 20 relative to each other while maintaining contact during polishing. In this embodiment, the problem of sliding properties is solved by providing a textured structure on the surface of the SPE film 15 on the polishing surface 13.

[0025] The textured structure on the surface of the SPE film 15 of this embodiment refers to a structure having microscopic irregularities with a maximum height Rz (see JIS B 0601-2001) of 20 μm or more and 200 μm or less. FIGS. 2(a) and 2(b) are SEM images showing an example of the surface of the SPE film 15. The textured structure may have a periodic pattern (e.g., a honeycomb pattern) as shown in FIG. 2(a) or a randomly irregular structure as shown in FIG. 2(b). From the viewpoint of uniformly oxidizing the polished surface 14 and reducing polishing unevenness, the textured structure preferably has a randomly irregular structure as shown in FIG. 2(b). This has the advantage that the textured structure is easy to form and can be easily reformed in the dressing process step S120 described later. Furthermore, from the viewpoint of easily retaining the abrasive grains 32 described later, the maximum height Rz of the textured structure is preferably greater than the average particle size (D50) of the abrasive grains 32 as determined by a laser diffraction / scattering method.

[0026] The arithmetic mean roughness Ra (see JIS B 0601-2001) of the surface of the SPE film 15 on the polishing surface 13 is preferably 5 μm or more and 50 μm or less. If the arithmetic mean roughness Ra of the surface of the SPE film 15 is less than 5 μm, the slidability relative to the conductive semiconductor substrate 20 may be insufficient. In contrast, by setting the arithmetic mean roughness Ra of the surface of the SPE film 15 to 5 μm or more, the slidability relative to the conductive semiconductor substrate 20 can be sufficiently ensured. On the other hand, if the arithmetic mean roughness Ra of the surface of the SPE film 15 exceeds 50 μm, the irregularities on the surface of the SPE film 15 may be transferred to the conductive semiconductor substrate 20 during polishing. In contrast, by setting the arithmetic mean roughness Ra of the surface of the SPE film 15 to 50 μm or less, the irregularities on the surface of the SPE film 15 may be reduced from being transferred to the conductive semiconductor substrate 20 during polishing. Furthermore, the arithmetic mean roughness Ra of the surface of the SPE film 15 is more preferably 10 μm or more and 20 μm or less. As a result, when abrasive grains 32 having an average particle size (D50) of about 1 μm (for example, 0.5 μm or more and 2 μm or less) measured by laser diffraction / scattering method are used during polishing, the abrasive grains 32 can be held in place while preventing the abrasive grains 32 from becoming embedded in the unevenness of the surface of the SPE film 15.

[0027] As shown in FIGS. 1(a) and 1(b), the polishing surface 13 preferably has grooves 33. While the textured structure described above is a microscopic irregularity designed to solve the sliding problem, the grooves 33 are macroscopic irregularities designed to facilitate the supply of a slurry containing abrasive grains 32 and water (pure water) to the polished surface 14 of the conductive semiconductor substrate 20. The provision of grooves 33 on the polishing surface 13 also contributes to the prevention of the conductive semiconductor substrate 20 from adhering to the polishing pad 10 and the ease of discharging polishing debris from the polishing pad 10. The width of the grooves 33 is preferably, for example, 1 mm to 5 mm, the depth of the grooves 33 is preferably, for example, 0.1 mm to 1 mm, and the pitch of the grooves 33 is preferably, for example, 10 mm to 50 mm. Providing grooves 33 of such sizes allows for more efficient supply of slurry. The grooves 33 may be, for example, spiral-shaped, in addition to the lattice-shaped grooves shown in FIG. 1(a). Also, Figure 1(b) shows a case where a groove 33 is provided with a depth equal to the thickness of the SPE film 15, but the depth of the groove 33 may be less than the thickness of the SPE film 15 or may be greater than the thickness of the SPE film 15.

[0028] The polishing pad 10 of this embodiment is preferably configured to perform polishing by supplying a slurry containing abrasive grains 32 and water to the polishing surface 13. In this case, the abrasive grains 32 are not fixed (or dispersed) in advance in the polishing pad 10, and function as free abrasive grains. This allows a larger amount of abrasive grains 32 to be supplied to the polishing surface 13 than when the abrasive grains 32 are dispersed in advance on the polishing surface 13, thereby improving the polishing rate. In addition, the risk of a decrease in the polishing rate due to the abrasive grains 32 falling off the polishing pad 10 can be reduced.

[0029] Furthermore, the polishing pad 10 of this embodiment is preferably configured so that water molecules are supplied to Nafion by water, which is the dispersion medium of the abrasive grains 32. In this case, water serves both as the dispersion medium of the abrasive grains 32 and as a supply of water molecules to Nafion.

[0030] The abrasive grains 32 preferably have a lower hardness than the conductive semiconductor 30 that constitutes the polishing surface 14 of the conductive semiconductor substrate 20. Examples of such abrasive grains 32 include cerium oxide (CeO), silicon oxide (SiO), and zirconium oxide (ZrO). While mechanical polishing typically uses abrasive grains harder than the object being polished, this embodiment removes only the oxide 31, so the polishing surface 14 of the conductive semiconductor substrate 20 can be polished even using abrasive grains 32 that are softer than the conductive semiconductor 30. As a result, polishing can be performed while minimizing damage to the polishing surface 14 of the conductive semiconductor substrate 20. While Vickers hardness, Knoop hardness, and other hardness scales are used to express hardness, it is important that the hardness scale used here simply expresses resistance to scratches. Therefore, Mohs hardness or modified Mohs hardness is preferably used as the hardness scale.

[0031] The polishing pad 10 preferably has a conductive adhesive on the back side. Alternatively, a conductive aluminum tape or the like may be used instead of the conductive adhesive. This ensures conductivity between the polishing pad 10 and the surface plate 21, for example, when the polishing pad 10 is attached to the surface plate 21 described below.

[0032] (2) Manufacturing method of polishing pad 10 Next, a method for manufacturing the polishing pad 10 of this embodiment will be described. In this embodiment, a case where a film made of Nafion is used as the SPE film 15 will be described.

[0033] Commercially available Nafion membranes (e.g., Nafion 117 manufactured by Sigma-Aldrich) have a flat surface, resulting in a large contact area (real contact area) with the polished surface 14. This makes it difficult to move the polishing pad 10 and the conductive semiconductor substrate 20 relative to each other while maintaining contact during polishing. Therefore, a textured structure as shown in FIG. 2(b) is formed on the surface of the SPE membrane 15 by rubbing the surface of the SPE membrane 15 against, for example, a grindstone or sandpaper. The surface of the SPE membrane 15 with the textured structure formed thereon is used as the polishing surface 13. This solves the aforementioned problem of sliding properties.

[0034] Alternatively, a textured SPE membrane 15 can be obtained using a Nafion dispersion (e.g., Sigma-Aldrich, product numbers 274704, 527084, 510211, 527106, 663492, and 527122 are preferably used). First, for example, polydimethylsiloxane (PDMS) prepolymer is injected into a mold having a honeycomb pattern and thermally cured. Next, for example, the Nafion dispersion is cast onto the cured PDMS and dried, thereby obtaining a textured SPE membrane 15 as shown in FIG. 2(a).

[0035] It is also possible to increase the thickness of SPE film 15 by stacking a plurality of commercially available Nafion films and thermocompression bonding them together, thereby improving the life of polishing pad 10.

[0036] To facilitate the supply of a slurry containing abrasive grains 32 and water, it is preferable to provide grooves 33 on the polishing surface 13. First, for example, a textured SPE film 15 is cut into a square shape (e.g., 18 mm × 18 mm). Next, for example, the cut SPE film 15 is adhered in a grid pattern to a stainless steel plate serving as a conductive substrate 19 using a conductive adhesive, thereby providing grooves 33 on the polishing surface 13, as shown in FIGS. 1( a) and 1(b). Note that if a conductive substrate 19 is not used, the grooves 33 may be provided by adhering the cut SPE film 15 to a surface plate 21, which will be described later. Alternatively, the grooves 33 may be formed in the SPE film 15 itself by laser processing or the like, without cutting the SPE film 15.

[0037] As a result of the above, polishing pad 10 can be obtained, which has SPE film 15 with a textured structure on polishing surface 13 and grooves 33. In this embodiment, even when SPE film 15 is cut as described above, the entire film adhered to conductive substrate 19 (platen 21) is collectively referred to as SPE film 15.

[0038] (3) Polishing equipment configuration Next, the configuration of the polishing apparatus used in this embodiment will be described. Fig. 3 is a schematic diagram of the polishing apparatus used in this embodiment. As shown in Fig. 3, the polishing apparatus of this embodiment includes, for example, a surface plate 21, a substrate holder 22, a power source 23, and a slurry supply unit 24. Note that grooves 33 provided in polishing surface 13 are omitted in Fig. 3.

[0039] The surface plate 21 is, for example, a stainless steel disk, and is configured so that the polishing pad 10 is attached to the upper surface. The surface plate 21 is configured to rotate horizontally at a predetermined rotation speed with the polishing pad 10 attached to the upper surface. The surface plate 21 is not limited to being made of stainless steel, and may be made of any material that is conductive and rigid.

[0040] The substrate holder 22 is made of, for example, stainless steel, and is configured so that the conductive semiconductor substrate 20 is attached to its bottom surface. The conductive semiconductor substrate 20 is preferably attached to the substrate holder 22 using, for example, a conductive adhesive, with the polishing surface 14 exposed. That is, it is preferable to electrically connect the back surface of the conductive semiconductor substrate 20 (the surface opposite the polishing surface 14) to the substrate holder 22. This allows the polishing surface 14 of the conductive semiconductor substrate 20 to be entirely exposed, and the entire polishing surface 14 can be polished. Note that if the substrate holder 22 is not conductive, the conductive semiconductor substrate 20 may be electrically connected to the power source 23 using, for example, a conductive rotating shaft for rotating the substrate holder 22.

[0041] The substrate holder 22 is configured to rotate horizontally at a predetermined rotation speed with the conductive semiconductor substrate 20 attached to its bottom surface. The substrate holder 22 is also configured to press the polished surface 14 of the conductive semiconductor substrate 20 against the polishing surface 13 of the polishing pad 10 with a predetermined pressure. The substrate holder 22 is not limited to being made of stainless steel, and may be made of any material that is rigid enough to hold the conductive semiconductor substrate 20.

[0042] The power supply 23 is electrically connected to, for example, the surface plate 21 and the substrate holder 22, and is configured to apply a predetermined voltage to the polishing pad 10. The power supply 23 is configured so that the substrate holder 22 side (the conductive semiconductor substrate 20 side) serves as the anode. When the power supply 23 applies a voltage to the polishing pad 10, OH radicals can be generated from water on the surface of the SPE film 15 (i.e., the surface of Nafion) present on the polishing surface 13. The power supply 23 can be, for example, a combination of a commercially available potentiostat and a function generator.

[0043] The slurry supply unit 24 is configured to supply a slurry containing, for example, abrasive grains 32 and water (pure water) to the polishing surface 13 of the polishing pad 10. By supplying the abrasive grains 32 to the polishing surface 13, the oxides 31 can be removed. Furthermore, by supplying water to the polishing surface 13, the conductivity of the polishing pad 10 can be improved. Furthermore, OH radicals can be generated from the water on the surface of Nafion. Furthermore, the oxides 31 removed from the polishing surface 14 of the conductive semiconductor substrate 20 can be discharged from the polishing surface 13. In this specification, pure water means, for example, water having a resistivity of 0.1 MΩ·cm or more and 18 MΩ·cm or less.

[0044] (4) Manufacturing Method of Conductive Semiconductor Substrate 20 Next, a method for manufacturing a conductive semiconductor substrate 20 using the polishing pad 10 of this embodiment will be described. FIG. 4 is a flowchart showing an example of a method for manufacturing a conductive semiconductor substrate 20 of this embodiment. As shown in FIG. 4, the method for manufacturing a conductive semiconductor substrate 20 of this embodiment includes, for example, a preparation step S100, an oxidation step S111, a removal step S112, and a dressing treatment step S120. The oxidation step S111 and the removal step S112 are collectively referred to as a polishing step S110. In this embodiment, a case will be described in which the polishing pad 10 is used to polish the polished surface 14 of a SiC substrate serving as the conductive semiconductor substrate 20, thereby producing a conductive semiconductor substrate 20 (SiC substrate) having a polished surface.

[0045] (Preparation step S100) In the preparation step S100, a polishing pad 10 and a SiC substrate serving as a conductive semiconductor substrate 20 are prepared. The SiC substrate is, for example, a disk-shaped, freestanding substrate made of a 4H-SiC single crystal. The diameter of the SiC substrate is, for example, 2 inches to 6 inches. The thickness of the SiC substrate is, for example, 0.25 mm or more. Such a SiC substrate is obtained, for example, by growing a seed crystal by a sublimation method (modified Lely process) or the like and slicing the resulting 4H-SiC single crystal (ingot). The polishing surface 14 of the SiC substrate is, for example, a Si face and is an as-sliced ​​surface. Therefore, polishing of the polishing surface 14 is necessary for use in the manufacture of semiconductor devices, etc. In this specification, the term "Si face" is intended to include a surface slightly inclined (for example, at an off-angle of 5° or less) from the (0001) plane of the SiC crystal.

[0046] 5(a) is a cross-sectional view schematically showing the polishing surface 14 of the SiC substrate in the preparation step S100 of this embodiment. FIG. 5(b) is a cross-sectional view schematically showing the polishing surface 14 of the SiC substrate and the polishing surface 13 of the polishing pad 10 in the oxidation step S111 of this embodiment. FIG. 5(c) is a cross-sectional view schematically showing the polishing surface 14 of the SiC substrate and the polishing surface 13 of the polishing pad 10 in the removal step S112 of this embodiment. As shown in FIG. 5(a), the polishing surface 14 of the SiC substrate in the preparation step S100 is made of a conductive semiconductor 30 (SiC), and has many irregularities due to being an as-sliced ​​surface.

[0047] (Polishing process S110) In the polishing step S110, for example, polishing surface 14 of the SiC substrate is polished using polishing pad 10 and the above-mentioned polishing apparatus. First, polishing pad 10 is attached to platen 21 so that polishing surface 13 is exposed, and the SiC substrate is attached to substrate holder 22 so that polishing surface 14 is exposed.

[0048] In the polishing step S110, with water molecules in contact with Nafion, the polishing surface 13 of the polishing pad 10 is brought into contact with the polished surface 14 of the SiC substrate under pressure, and the polishing pad 10 and the SiC substrate are moved relative to each other while a voltage is applied between them, thereby polishing the polished surface 14.

[0049] In the polishing step S110, the surface 14 to be polished of the SiC substrate is pressed against the polishing surface 13 of the polishing pad 10 with a predetermined pressure. The pressure (polishing pressure) applied between the polishing surface 13 and the surface 14 to be polished is preferably, for example, 10 kPa or more and 100 kPa or less. Furthermore, it is preferable to press the surface 14 to be polished of the SiC substrate so that pressure is applied uniformly to the surface 14 to be polished of the SiC substrate. This makes it possible to polish the surface 14 to be polished of the SiC substrate uniformly within the surface.

[0050] In the polishing step S110, a predetermined voltage is applied to the polishing pad 10 using a power supply 23 while the polishing surface 14 of the SiC substrate is pressed against the polishing surface 13 of the polishing pad 10 with a predetermined pressure, thereby oxidizing the polishing surface 14. The power supply 23 is electrically connected to the substrate holder 22, the SiC substrate, the polishing pad 10, and the surface plate 21, for example, in this order from the anode side.

[0051] The voltage applied by the power supply 23 is preferably 20 V or more and 300 V or less. If the voltage applied by the power supply 23 is less than 20 V, it is difficult to generate OH radicals from water on the surface of Nafion. In contrast, if the voltage applied by the power supply 23 is 20 V or more, OH radicals are more easily generated. On the other hand, if the voltage applied by the power supply 23 exceeds 300 V, the polishing surface 14 of the SiC substrate may become rough. In contrast, if the voltage applied by the power supply 23 is 300 V or less, the polishing surface 14 of the SiC substrate can be polished smoothly and at an appropriate polishing rate.

[0052] In the polishing step S110, with a predetermined voltage applied to the polishing pad 10, the surface plate 21 and the substrate holder 22 are each rotated horizontally at a predetermined rotational speed. The rotational speed of the surface plate 21 is preferably, for example, 10 rpm or more and 300 rpm or less. The rotational speed of the substrate holder 22 is preferably, for example, 10 rpm or more and 300 rpm or less. The rotational speeds of the surface plate 21 and the substrate holder 22 may be the same or different. The rotational directions of the surface plate 21 and the substrate holder 22 may be the same or different.

[0053] In the polishing step S110, it is preferable to supply a slurry containing abrasive grains 32 and water to the polishing surface 13 using, for example, a slurry supply unit 24. This allows the abrasive grains 32 to remove oxides 31. Furthermore, the conductivity of the polishing pad 10 can be improved. The amount of water supplied by the slurry supply unit 24 is preferably, for example, 10 mL / min or more. If the water supply rate is less than 10 mL / min, the conductivity of the polishing pad 10 may be insufficient. In contrast, by setting the water supply rate to 10 mL / min or more, the conductivity of the polishing pad 10 can be sufficiently improved. On the other hand, the upper limit of the water supply rate is not particularly limited, but from a cost perspective, it is preferably 50 mL / min or less. In this embodiment, compared to the second embodiment described later, there is no need to worry about Nafion or abrasive grains 32 falling off the polishing pad 10, so more abrasive grains 32 and water can be supplied. This allows the conductivity of the polishing pad 10 to be sufficiently improved. Furthermore, the polishing rate can be improved.

[0054] In this embodiment, since an oxidizing agent such as potassium permanganate is not used, polishing can be performed in a neutral range. In this specification, "polishing in a neutral range" means, for example, performing the polishing step S110 while maintaining the pH of the polishing surface 13 of the polishing pad 10 at 6.0 or higher and 8.0 or lower. The pH of the polishing surface 13 can be measured, for example, using a pH meter. If necessary, the pH of the polishing surface 13 may be adjusted to a value outside the above range.

[0055] 6 is a graph schematically showing the current flowing through the polishing pad 10 in the polishing step S110 of this embodiment. In this embodiment, it is preferable to apply a pulse voltage (i.e., apply a voltage intermittently) to the polishing pad 10 using the power supply 23, for example, to cause a current to flow intermittently through the polishing pad 10. As shown in FIG. 6, the oxidation step S111 is performed while a current is flowing through the polishing pad 10. On the other hand, the removal step S112 is performed continuously regardless of whether a current is flowing through the polishing pad 10. That is, in this embodiment, the oxidation step S111 and the removal step S112 are performed simultaneously while a current is flowing through the polishing pad 10.

[0056] In this embodiment, the oxidation step S111 and the removal step S112 are performed simultaneously while a current is flowing through the polishing pad 10. This allows the oxides 31 formed on the polished surface 14 of the SiC substrate to be quickly removed by the abrasive grains 32, thereby improving the polishing rate. Furthermore, the removal step S112 is performed while no current is flowing through the polishing pad 10. At this time, the removed oxides 31 can be discharged from the polishing surface 13 by, for example, water supplied to the polishing surface 13 by the slurry supply unit 24.

[0057] In this embodiment, while the polishing pad 10 and the SiC substrate are moved relative to each other while in contact with each other, the entire surface of the polished surface 14 of the SiC substrate is always in contact with the polishing surface 13. This allows the polished surface 14 of the SiC substrate to be oxidized uniformly within the surface. As a result, the polished surface 14 of the SiC substrate can be polished uniformly within the surface.

[0058] 6, where T is the pulse period and t is the time during which current flows in one period, the duty ratio D is defined as D=t / T. The duty ratio D is preferably set to, for example, 1% or more and 100% or less. In this embodiment, by controlling the duty ratio D, the rate at which the polished surface 14 is oxidized can be adjusted, thereby making it possible to control the polishing rate.

[0059] In the polishing step S110, it is preferable that all of the oxides 31 generated during one cycle of the oxidation step S111 be removed before the next oxidation step S111 is performed. In other words, it is preferable to control the current flowing through the polishing pad 10 so that the amount of oxides 31 generated during one cycle of the oxidation step S111 does not exceed the amount of oxides 31 that can be removed during the period T. This allows the polished surface 14 to be polished smoothly and at an appropriate polishing rate.

[0060] (Oxidation step S111) In the oxidation step S111, OH radicals are generated from water on the surface of Nafion, and the OH radicals oxidize the SiC that constitutes the polishing surface 14 of the SiC substrate, generating oxide 31. When a current flows through polishing pad 10, OH radicals are generated from water on the surface of Nafion by the reaction shown in the following reaction formula (1).

[0061] HO → OH + H + +e - ···(1)

[0062] When OH radicals are generated, SiC is oxidized on the polished surface 14 of the SiC substrate by the reaction shown in the following reaction formula (2), and an oxide 31 (here, silicon oxide) is generated.

[0063] SiC+8OH·→SiO2+CO2+4H2O···(2)

[0064] 5(b), in the oxidation step S111, the convex portions of the conductive semiconductor 30 are preferentially oxidized to generate oxides 31. That is, of the polished surface 14 of the SiC substrate, the portions that are in contact with (or close to) the polishing surface 13 are preferentially oxidized. As a result, in the removal step S112 described below, the oxides 31 generated on the convex portions are removed, thereby enabling the polished surface 14 of the SiC substrate to be efficiently planarized.

[0065] OH radicals usually have a short lifespan and cannot exist for a long time. However, in the polishing pad 10 of this embodiment, OH radicals are generated on the polishing surface 13 that is in contact with the polished surface 14 of the SiC substrate, so that the generation of OH radicals and the oxidation of the polished surface 14 of the SiC substrate can be performed simultaneously. Therefore, the polished surface 14 of the SiC substrate can be oxidized before the OH radicals disappear.

[0066] Furthermore, OH radicals may decompose the side chains of Nafion, potentially degrading it. However, in the polishing pad 10 of this embodiment, the generated OH radicals are used to oxidize the polishing surface 14 of the SiC substrate, thereby suppressing the degradation of Nafion caused by OH radicals.

[0067] (Removal step S112) In the removal step S112, oxides 31 generated by the oxidation of the conductive semiconductor 30 by OH radicals are removed. Specifically, for example, as shown in FIG. 5(c), the oxides 31 are mechanically removed by abrasive grains 32 supplied to the polishing surface 13. Because the abrasive grains 32 are less hard than the conductive semiconductor 30, only the oxides 31 can be removed without damaging the conductive semiconductor 30. As a result, it is possible to polish the polishing surface 14 of the SiC substrate while suppressing damage to the polishing surface 14 of the SiC substrate. Note that in this specification, polishing the polishing surface 14 of the SiC substrate means, for example, scraping off a portion of the conductive semiconductor 30 constituting the polishing surface 14 of the SiC substrate to flatten the surface, as shown in FIG. 5(c), for example.

[0068] The time for performing the polishing step S110 can be set arbitrarily depending on the application of the SiC substrate, etc.

[0069] In the polishing step S110, the surface of the SiC substrate can be planarized by repeatedly performing the oxidation step S111 and the removal step S112. The arithmetic mean roughness Ra of the surface (polished surface) of the SiC substrate after the polishing step S110 is preferably, for example, 0.7 nm or less. This makes the SiC substrate after the polishing step S110 suitable for use in the manufacture of semiconductor devices, etc. The lower limit of the arithmetic mean roughness Ra of the surface of the SiC substrate after the polishing step S110 is not particularly limited, but is, for example, 0.1 nm or more.

[0070] In the polishing step S110, the polishing surface 14 of the SiC substrate is efficiently oxidized by highly reactive OH radicals and the oxides 31 are removed to polish the polishing surface 14 of the SiC substrate, thereby improving the polishing rate compared to conventional methods. Specifically, the polishing rate in the polishing step S110 can be, for example, 100 nm / h or more and 10,000 nm / h or less. In this specification, the polishing rate means the thickness removed per unit time of polishing.

[0071] When polishing step S110 is completed (also referred to as finish polishing), it is preferable to apply a voltage so that the current flowing between polishing pad 10 and SiC substrate gradually decreases. During finish polishing, reducing the current and thinning the thickness of oxide 31 produced can further flatten polished surface 14. The current may be decreased stepwise or continuously.

[0072] When polishing step S110 is completed, it is preferable to stop power supply 23 for a predetermined time, and move polishing pad 10 and SiC substrate relative to each other while maintaining contact with each other, without applying voltage to polishing pad 10. This allows polishing step S110 to be completed without oxide 31 remaining on polished surface 14 of conductive semiconductor substrate 20. Furthermore, uneven polishing due to the distribution of in-plane electrical properties of polished surface 14 can be reduced.

[0073] In the polishing step S110, the rate v1 of oxide 31 generation in the oxidation step S111 can be controlled, for example, by the value of the current flowing between the polishing pad 10 and the SiC substrate. Also, in the polishing step S110, the rate v2 of oxide 31 removal in the removal step S112 can be controlled, for example, by changing at least one of the amount of abrasive grains 32 supplied to the polishing surface 13, the polishing pressure, or the relative speed between the polishing pad 10 and the SiC substrate. In other words, in this embodiment, the rate v1 of oxide 31 generation and the rate v2 of oxide 31 removal can be controlled separately. This makes it possible to control the polishing rate, the arithmetic mean roughness Ra of the polished surface 14, and the like.

[0074] In the polishing step S110, for example, it is preferable to control the speed v1 and the speed v2 so that they satisfy the relationship v1≦v2. This allows polishing to be performed so that no oxide 31 remains on the polished surface 14, thereby making the polished surface 14 more planar. It also improves current efficiency and reduces energy loss. Note that, for example, in the initial stage of the polishing step S110, if it is desired to increase the polishing rate, the speed v1 and the speed v2 may be controlled so that they satisfy the relationship v1>v2. In this case, it is preferable to change the polishing conditions during the finish polishing so that the relationship v1≦v2 is satisfied.

[0075] (Dressing treatment step S120) During the polishing of the conductive semiconductor substrate 20, the surface of the SPE film 15 may be worn away, possibly losing its textured structure. Loss of the textured structure will result in poor sliding properties with respect to the conductive semiconductor substrate 20. Therefore, when polishing another conductive semiconductor substrate 20 after the polishing step S110, it is preferable to perform the dressing step S120 as needed. The dressing step S120 is a step of roughening the surface of the SPE film 15 (also referred to as a dressing process) to re-form the textured structure on the surface of the SPE film 15. The dressing process can be performed, for example, by rubbing a grindstone, sandpaper, or the like against the surface of the SPE film 15. When the polishing step S110 is performed again after the dressing step S120, it is preferable to perform the dressing process so that the arithmetic mean roughness Ra of the surface of the SPE film 15 is 5 μm or more and 50 μm or less at the start of the polishing step S110. As a result, even if the surface of the SPE film 15 is worn, the textured structure can be formed again, thereby improving the life of the polishing pad 10. Whether or not the dressing process step S120 needs to be performed can be determined, for example, by monitoring the load when rotating the surface plate 21 or the substrate holder 22, and if the load exceeds a predetermined value, it can be determined that the dressing process step S120 needs to be performed.

[0076] Through the above steps, a conductive semiconductor substrate 20 having a polished surface can be manufactured. Note that steps other than those described in this embodiment may be well-known steps performed as necessary. The method for manufacturing the conductive semiconductor substrate 20 of this embodiment can also be applied as a polishing method for the conductive semiconductor substrate 20.

[0077] (5) Effects of this embodiment According to this embodiment, one or more of the following effects can be achieved.

[0078] (a) The polishing pad 10 of this embodiment has, on at least a portion of the polishing surface 13, a film (SPE film 15) containing a solid polymer electrolyte for generating OH radicals and oxidizing the polishing surface 14 of the conductive semiconductor substrate 20 with the OH radicals. Therefore, the polishing surface 14 of the conductive semiconductor substrate 20 can be oxidized. As a result, polishing can be performed while suppressing damage to the polishing surface 14 of the conductive semiconductor substrate 20. Furthermore, in this embodiment, the polishing surface 14 of the conductive semiconductor substrate 20 is efficiently oxidized by highly reactive OH radicals, thereby improving the polishing rate compared to conventional methods. Furthermore, in this embodiment, polishing can be performed in a neutral range because an oxidizing agent such as potassium permanganate is not used.

[0079] (b) In the polishing pad 10 of this embodiment, at least a portion of the polishing surface 13 has a film (SPE film 15) made of Nafion, a solid polymer electrolyte that generates OH radicals from water when a voltage is applied. Therefore, the generation of OH radicals and the oxidation of the polished surface 14 of the conductive semiconductor substrate 20 can be performed simultaneously. Therefore, the polished surface 14 of the conductive semiconductor substrate 20 can be oxidized before the OH radicals disappear. Furthermore, in the polishing pad 10 of this embodiment, the generated OH radicals are used to oxidize the polished surface 14 of the conductive semiconductor substrate 20, so degradation of Nafion by OH radicals can be suppressed.

[0080] (c) In the polishing pad 10 of this embodiment, a film made of Nafion and having a thickness of 0.1 mm or more is used as the SPE film 15. This reduces the risk of Nafion present on the polishing surface 13 falling off compared to the second embodiment described later, and therefore the life of the polishing pad 10 can be improved.

[0081] (d) In the polishing pad 10 of this embodiment, a textured structure is provided on the surface of the SPE film 15 on the polishing surface 13. This solves the problem of poor sliding properties with respect to the conductive semiconductor substrate 20 when a film made of Nafion is used as the SPE film 15.

[0082] (e) In the polishing pad 10 of this embodiment, grooves 33 are provided on the polishing surface 13. This makes it easier to supply a slurry containing abrasive grains 32 and water to the polished surface 14. In addition, the conductive semiconductor substrate 20 is less likely to stick to the polishing pad 10, and polishing debris is more easily discharged from the polishing pad 10.

[0083] (f) The method for manufacturing the conductive semiconductor substrate 20 of this embodiment includes a dressing process step S120 in which a roughening process is performed on the surface of the SPE film 15. This allows the textured structure to be formed again even if the surface of the SPE film 15 is worn, thereby improving the life of the polishing pad 10.

[0084] <Second embodiment of the present invention> Next, a second embodiment of the present invention will be described, focusing on the differences from the first embodiment. Elements that are substantially the same as those described in the first embodiment will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0085] (1) Structure of the polishing pad 10A FIG. 7 is a plan view schematically illustrating an example of the polishing surface 13 of a polishing pad 10A of this embodiment. The polishing pad 10A of this embodiment also has a membrane (SPE membrane 15) containing a solid polymer electrolyte on at least a portion of the polishing surface 13. However, unlike the first embodiment, the SPE membrane 15 is attached to the substrate surface of the polishing pad 10A (or covers at least a portion of the substrate surface). The substrate of the polishing pad 10A can be made of a nonwoven fabric, a urethane resin, an epoxy resin, suede, or the like. From the viewpoint of ensuring slidability with respect to the polished surface 14, it is preferable to use a nonwoven fabric as the substrate of the polishing pad 10A. Furthermore, from the viewpoint of ensuring electrical conductivity in the thickness direction of the polishing pad 10A, it is preferable to use a nonwoven fabric or a substrate having an open-cell structure as the substrate of the polishing pad 10A.

[0086] In the polishing pad 10A of this embodiment, the polishing surface 13 is impregnated with at least a solid polymer electrolyte (Nafion in this embodiment). In this embodiment, the solid polymer electrolyte is attached to the substrate surface of the polishing pad 10A (or at least a portion of the substrate surface is coated) by impregnation (i.e., by impregnating the substrate of the polishing pad 10A with a liquid substance containing the solid polymer electrolyte, evaporating the liquid, and leaving the solid polymer electrolyte in the polishing pad 10A). In this specification, the solid polymer electrolyte being attached to the substrate surface of the polishing pad 10A (or coating at least a portion of the substrate surface) is referred to as the polishing pad 10A being impregnated with the solid polymer electrolyte.

[0087] It is preferable that Nafion is also impregnated in the thickness direction of polishing pad 10 A. Since Nafion has ion conductivity, this ensures ion conductivity in the thickness direction of polishing pad 10 A.

[0088] In the polishing pad 10A, Nafion is, for example, 3 mg / cm 3 More than 20mg / cm 3 It is preferable that the density of Nafion is 3 mg / cm or less. 3 If the density is less than 3 mg / cm3, it is difficult to obtain the effect of oxidizing the polished surface 14. 3 By setting the density to 20 mg / cm or more, it becomes easier to oxidize the polished surface 14. On the other hand, when the density of Nafion is 20 mg / cm 3 If the density of Nafion is more than 20 mg / cm, the flexibility of the polishing pad 10A will decrease, and the polished surface 14 may be scratched during polishing. 3 By satisfying the following conditions, the flexibility of polishing pad 10A is maintained, thereby reducing the possibility of scratching polished surface 14 during polishing. In this specification, the density of Nafion is the value obtained by dividing the mass of Nafion contained in polishing pad 10A by the apparent volume of polishing pad 10 (volume including internal voids).

[0089] FIG. 8(a) is an enlarged schematic diagram of the polishing surface 13 when a nonwoven fabric is used as the substrate of the polishing pad 10A. As shown in FIG. 8(a), Nafion is preferably attached to the surface of the fibers 16 of the nonwoven fabric (or covers at least a portion of the surface) and exists as a thin SPE film 15. In this embodiment, Nafion is attached to the surface of the fibers 16 of the nonwoven fabric, which improves the sliding properties with respect to the conductive semiconductor substrate 20 compared to when a film made of Nafion is used as the SPE film 15. To confirm that Nafion is attached to the surface of the fibers 16, for example, the fibers 16 may be cut and the vicinity of the cross section of the fibers 16 may be measured using energy dispersive X-ray analysis (EDX) to determine whether fluorine (F) is detected.

[0090] Nafion is preferably present so as to connect multiple fibers 16. This allows the Nafion to be connected in polishing pad 10A, thereby improving the conductivity of polishing pad 10A. FIG. 8(b) is an enlarged schematic diagram of polishing surface 13 when a substrate having an open-cell structure is used. In this case, as shown in FIG. 8(b), the Nafion (SPE film 15) covering the inside of cells 17 is connected, thereby improving the conductivity of polishing pad 10A.

[0091] 9 is a plan view schematically illustrating another example of the polishing surface 13 of the polishing pad 10A of this embodiment. As shown in FIG. 9, abrasive grains 32 may be dispersed on the polishing surface 13. This makes it possible to remove oxides 31 generated when the conductive semiconductor 30 constituting the polished surface 14 of the conductive semiconductor substrate 20 is oxidized by OH radicals. In this case, it is also preferable that the abrasive grains 32 are impregnated in the thickness direction of the polishing pad 10A. This makes it possible to maintain the polishing rate even when the polishing surface 13 is worn during polishing.

[0092] When cerium oxide having an average particle size (D50) of about 1 μm (for example, 0.5 μm or more and 2 μm or less) as determined by a laser diffraction / scattering method is used as the abrasive grains 32, the abrasive grains 32 in the polishing pad 10A have a density of, for example, 0.1 g / cm 3 More than 0.5g / cm 3 It is preferable that the density of the abrasive grains 32 is 0.1 g / cm or less. 3 If the density of the abrasive grains 32 is less than 0.1 mg / cm, it is difficult to obtain the effect of removing the oxides 31. 3 By setting the density of the abrasive grains 32 to 0.5 g / cm or more, it becomes easier to remove the oxides 31. 3 If an attempt is made to manufacture a polishing pad 10A exceeding this density, the viscosity of the dispersion liquid of the abrasive grains 32 may become too high when the dispersion liquid is impregnated into the polishing pad 10A. 3 The following makes it easier to impregnate the polishing pad 10A with a dispersion of abrasive grains 32. In this specification, the density of abrasive grains 32 is the value obtained by dividing the mass of abrasive grains 32 contained in the polishing pad 10A by the apparent volume of the polishing pad 10A (volume including internal voids).

[0093] Fig. 10 is an enlarged schematic view of polishing surface 13 when abrasive grains 32 are dispersed on polishing surface 13. As shown in Fig. 10, Nafion (SPE film 15) is preferably attached also to the surfaces of abrasive grains 32. This can improve the conductivity of polishing pad 10A.

[0094] If the abrasive grains 32 are not dispersed on the polishing surface 13, polishing can be performed while supplying a slurry containing the abrasive grains 32 and water to the polishing surface 13, as in the first embodiment. In this case, the risk of a decrease in the polishing rate due to the abrasive grains 32 falling off the polishing pad 10A can be reduced. From the viewpoint of reducing the consumption of the abrasive grains 32, it is preferable that the abrasive grains 32 are dispersed on the polishing surface 13 in advance.

[0095] The polishing pad 10A preferably has water retention properties. This allows for efficient generation of OH radicals from water. Furthermore, Nafion exhibits conductivity in the presence of water, which can improve the conductivity of the polishing pad 10A. Specifically, for example, the water retention properties of the polishing pad 10A can be improved by dispersing a small amount of water-absorbing polymer in the polishing pad 10A.

[0096] (2) Manufacturing method of polishing pad 10A Next, a method for manufacturing the polishing pad 10A of this embodiment will be described. In this embodiment, a nonwoven fabric is used as the base material of the polishing pad 10A, and the polishing surface 13 is impregnated with Nafion as a solid polymer electrolyte and dispersed with cerium oxide as abrasive grains 32. In this embodiment, since a nonwoven fabric is used as the base material of the polishing pad 10A, it is easy to impregnate the polishing pad 10A with Nafion in the thickness direction as well, and it is easy to disperse the abrasive grains 32.

[0097] First, a nonwoven fabric is impregnated with a cerium oxide dispersion (e.g., 60% by weight, average particle size (D50) 1 μm). A small amount of sodium alginate (e.g., 0.25% by weight) is preferably added to the cerium oxide dispersion. This increases the viscosity of the cerium oxide dispersion, making it easier to disperse cerium oxide in polishing pad 10A (on polishing surface 13 and in the thickness direction of polishing pad 10A).

[0098] After the nonwoven fabric is impregnated with the cerium oxide dispersion, it is preferable to place the nonwoven fabric in an aqueous calcium chloride solution (e.g., 20% by weight), which causes the sodium alginate and calcium chloride to react and gel, making it easier to disperse the cerium oxide in the polishing pad 10A.

[0099] Furthermore, rare earth oxides such as praseodymium oxide, neodymium oxide, and lanthanum oxide may be added to the cerium oxide dispersion liquid, which makes it easier for the abrasive grains 32 to remove the oxides 31.

[0100] After the nonwoven fabric is impregnated with the cerium oxide dispersion, excess cerium oxide dispersion is removed using, for example, a squeezer, and then the fabric is dried at 70°C for 30 minutes using a constant temperature dryer, etc. In this manner, cerium oxide as abrasive grains 32 can be dispersed on the polishing surface 13.

[0101] Next, the nonwoven fabric is impregnated with a Nafion dispersion (5 to 20% by weight, for example, it is preferable to use any one of product numbers 274704, 527084, 510211, 527106, 663492, and 527122 manufactured by Sigma-Aldrich).

[0102] After the nonwoven fabric is impregnated with the Nafion dispersion, excess Nafion dispersion is removed using, for example, a squeezer, and the nonwoven fabric impregnated with the Nafion dispersion is then dried for 30 minutes at 70°C using a constant temperature dryer, etc. In this way, Nafion can be impregnated into the polishing surface 13. Note that the impregnation with the Nafion dispersion and drying may be repeated multiple times.

[0103] By using a Nafion dispersion when impregnating the nonwoven fabric with Nafion, the sliding properties of polishing pad 10A can be improved compared to when a film made of Nafion is used. As a result, polishing pad 10A and conductive semiconductor substrate 20 can be easily moved relative to each other while in contact with each other, and polishing surface 14 of conductive semiconductor substrate 20 can be efficiently polished.

[0104] As a result, polishing pad 10A can be obtained in which polishing surface 13 is impregnated with Nafion and has abrasive grains 32 dispersed therein. Preferably, abrasive grains 32 are dispersed in the nonwoven fabric first, and then Nafion is impregnated into the nonwoven fabric. In this case, Nafion is more likely to adhere to the surface of abrasive grains 32, thereby improving the conductivity of polishing pad 10A.

[0105] (3) Polishing equipment configuration In this embodiment, a polishing apparatus similar to that in the first embodiment can be used. When using a polishing pad 10A in which abrasive grains 32 are pre-dispersed on the polishing surface 13, the slurry supply unit 24 may be replaced with a pure water supply unit that supplies pure water to the polishing surface 13.

[0106] (4) Manufacturing Method of Conductive Semiconductor Substrate 20 Next, a method for manufacturing a conductive semiconductor substrate 20 using the polishing pad 10A of this embodiment will be described, focusing on the differences from the first embodiment. FIG. 11 is a flowchart showing an example of the method for manufacturing a conductive semiconductor substrate 20 of this embodiment. As shown in FIG. 11, the method for manufacturing a conductive semiconductor substrate 20 of this embodiment differs from the first embodiment in that it does not include the dressing treatment step S120. In this embodiment, a case will be described in which the polishing pad 10A is used to polish the polished surface 14 of a GaN substrate serving as the conductive semiconductor substrate 20, and a conductive semiconductor substrate 20 (GaN substrate) having a polished surface is manufactured.

[0107] In the preparation step S100 of this embodiment, a polishing pad 10A and a GaN substrate serving as a conductive semiconductor substrate 20 are prepared. The GaN substrate is, for example, a disk-shaped, freestanding substrate made of a GaN single crystal. The diameter of the GaN substrate is, for example, 2 inches to 6 inches. The thickness of the GaN substrate is, for example, 0.25 mm or more. Such a GaN substrate is obtained by slicing a GaN crystal grown epitaxially by, for example, HVPE (hydride vapor phase epitaxy). The polishing surface 14 of the GaN substrate is, for example, the +c plane, which is an as-sliced ​​surface. Therefore, polishing of the polishing surface 14 is necessary for use in the manufacture of semiconductor devices, etc. In this specification, the "+c plane" includes a plane slightly inclined (for example, at an off-angle of 5° or less) from the (0001) plane of the GaN crystal.

[0108] The carrier concentration of the polished surface 14 of the GaN substrate is, for example, 1.0×10 16 cm -3This makes it possible to ensure electrical conductivity in the thickness direction of the GaN substrate. The upper limit of the carrier concentration of the polished surface 14 of the GaN substrate is not particularly limited, but is preferably 1.0×10 20 cm -3 The following is an example:

[0109] In this embodiment, the polishing rate varies depending on the voltage V applied by the power supply 23, and the polishing rate may reach a maximum (local maximum) at a certain voltage Vm. In this case, it is preferable to control the voltage V applied by the power supply 23 so that it does not exceed the voltage Vm at which the polishing rate reaches a maximum (local maximum). If the voltage V exceeds the voltage Vm, the removal of the oxides 31 becomes rate-determining, and the polished surface 14 may become rough. In contrast, by controlling the voltage V so that it does not exceed the voltage Vm, the polished surface 14 can be polished smoothly and at an appropriate polishing rate.

[0110] In the polishing step S110 of this embodiment, it is preferable to use a pure water supply unit to supply pure water to the polishing surface 13 in a spray-like manner. This improves the conductivity of the polishing pad 10A. Furthermore, the water supply rate from the pure water supply unit is preferably, for example, 0.1 mL / min to 5 mL / min. If the water supply rate is less than 0.1 mL / min, the conductivity of the polishing pad 10A may be insufficient. By setting the water supply rate to 0.1 mL / min or more, the conductivity of the polishing pad 10A can be sufficiently improved. On the other hand, if the water supply rate exceeds 5 mL / min, the Nafion or abrasive grains 32 may be washed away by the pure water. By setting the water supply rate to 5 mL / min or less, the risk of the Nafion or abrasive grains 32 being washed away by the pure water can be reduced.

[0111] In the polishing step S110 of this embodiment, it is preferable to supply water to polishing surface 13 so as to maintain the humidity of polishing surface 13 within a certain range (for example, 60% or more and 100% or less). That is, since the value of the current flowing through polishing pad 10A varies depending on the humidity of polishing surface 13, it is preferable to monitor the value of the current flowing through polishing pad 10A using, for example, a digital multimeter, and control the humidity of polishing surface 13 so that the current value is constant. This makes it possible to stabilize the polishing rate.

[0112] When using a polishing pad 10A in which abrasive grains 32 are not dispersed on the polishing surface 13, it is preferable to supply a slurry containing abrasive grains 32 and water to the polishing surface 13 in the polishing step S110, as in the first embodiment. This makes it possible to polish the surface 14 in the same way as when using a polishing pad 10A in which abrasive grains 32 are dispersed in advance. In addition, the risk of a decrease in the polishing rate due to abrasive grains 32 falling off the polishing pad 10A can be reduced.

[0113] In the oxidation step S111 of this embodiment, GaN is oxidized on the polished surface 14 of the GaN substrate by the reaction shown in the following reaction formula (3), and an oxide 31 (here, gallium oxide) is produced.

[0114] 2GaN+6OH·→Ga2O3+N2+3H2O···(3)

[0115] FIG. 12 is a cross-sectional photograph of the vicinity of the polished surface 14 of a GaN substrate in the polishing step S110 of this embodiment. In the polishing step S110, it is preferable to form a porous structure on the polished surface 14 of the GaN substrate and then remove the porous structure. In this specification, a porous structure refers to a structure in which multiple voids are formed in a crystal. In FIG. 12, multiple void layers (porous layers 18) are formed parallel to the polished surface 14. By forming a porous structure, the crystal above it is easier to remove, thereby improving the polishing rate. Furthermore, the porous structure is easily formed when polishing a conductive semiconductor substrate 20, particularly a GaN substrate.

[0116] As described above, in this embodiment as well, a conductive semiconductor substrate 20 having a polished surface can be manufactured. Note that, as for the steps other than those described in this embodiment, the same steps as in the first embodiment or known steps may be performed as necessary. Furthermore, the method for manufacturing the conductive semiconductor substrate 20 of this embodiment can also be applied as a method for polishing the conductive semiconductor substrate 20.

[0117] (5) Effects of this embodiment According to this embodiment, one or more of the following effects can be achieved.

[0118] (a) In polishing pad 10A of this embodiment, Nafion is attached to the surface of nonwoven fabric fiber 16, and therefore, compared to when a film made of Nafion is used as SPE film 15, it is possible to improve the sliding properties with respect to conductive semiconductor substrate 20. However, since SPE film 15 of this embodiment is thinner (for example, 10 μm or less) than that of the first embodiment, polishing pad 10 of the first embodiment is more advantageous in terms of pad life.

[0119] (b) In the polishing pad 10A of this embodiment, abrasive grains 32 for removing oxides 31 may be dispersed on the polishing surface 13. This allows for a reduction in the amount of abrasive grains 32 consumed compared to the first embodiment.

[0120] Third Embodiment of the Present Invention Next, a third embodiment of the present invention will be described, focusing on differences from the first and second embodiments. Elements that are substantially the same as those described in the first and second embodiments will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0121] (1) Structure of the polishing pad 10B 13(a) and 13(b) are plan views schematically illustrating the polishing surface 13 of a polishing pad 10B of this embodiment. As shown in FIGS. 13(a) and 13(b), the polishing pad 10B of this embodiment has a first region 11 and a second region 12 on the polishing surface 13. The first region 11 and the second region 12 are, for example, fan-shaped and arranged adjacent to each other. FIG. 13(a) illustrates an example in which the first region 11 is fan-shaped with a central angle of 90 degrees and the second region 12 is fan-shaped with a central angle of 270 degrees. Note that the arrangement of the first region 11 and the second region 12 is not limited to the above-described arrangement and can be modified in various ways. For example, as shown in FIG. 13(b), multiple fan-shaped first regions 11 and multiple fan-shaped second regions 12 may be arranged adjacent to each other.

[0122] In the polishing pad 10B of this embodiment, the first region 11 and the second region 12 are arranged so as to alternately come into contact with the polished surface 14 of the conductive semiconductor substrate 20 due to the relative movement between the polishing pad 10B and the conductive semiconductor substrate 20. The effect of this will be described later.

[0123] The first region 11 is a region for generating OH radicals and oxidizing the conductive semiconductor 30 that constitutes the polishing target surface 14 of the conductive semiconductor substrate 20 with the OH radicals.

[0124] The first region 11 is impregnated with, for example, Nafion as a solid polymer electrolyte. In other words, the first region 11 has an SPE membrane 15, and it can be said that the polishing pad 10B of this embodiment also has an SPE membrane 15 on at least a portion of the polishing surface 13. Nafion is preferably impregnated throughout the entire thickness of the polishing pad 10B. Because Nafion has ionic conductivity, this ensures ionic conductivity in the thickness direction of the polishing pad 10B.

[0125] The second region 12 is a region for removing oxides 31 generated when conductive semiconductor 30 constituting polishing surface 14 of conductive semiconductor substrate 20 is oxidized by OH radicals. Since polishing pad 10B of this embodiment has first region 11 and second region 12 on polishing surface 13, it is possible to oxidize and remove oxides 31 from polishing surface 14 of conductive semiconductor substrate 20 using a single polishing pad 10B.

[0126] In the second region 12, for example, abrasive grains 32 for removing oxides 31 are dispersed. The abrasive grains 32 preferably have a lower hardness than the conductive semiconductor 30 that constitutes the polished surface 14 of the conductive semiconductor substrate 20. Examples of such abrasive grains 32 include cerium oxide (CeO2), silicon oxide (SiO2), and zirconium oxide (ZrO2).

[0127] (2) Manufacturing Method of Polishing Pad 10B First, the nonwoven fabric is impregnated with the Nafion dispersion. At this time, for example, only the first region 11 may be immersed in the Nafion dispersion so that only the first region 11 is impregnated with the Nafion dispersion, or wax or the like may be applied to the portion other than the first region 11. By applying wax or the like to the portion other than the first region 11, only the first region 11 can be impregnated with the Nafion dispersion. Note that the Nafion dispersion may be the same as that described in the first and second embodiments.

[0128] After the first region 11 is impregnated with the Nafion dispersion, excess Nafion dispersion is removed using, for example, a squeezer, and then the nonwoven fabric impregnated with the Nafion dispersion is dried for 30 minutes at 70°C using a constant temperature dryer, etc. In this manner, the first region 11 can be impregnated with Nafion. Note that the impregnation with the Nafion dispersion and drying may be repeated multiple times.

[0129] After the first region 11 is impregnated with Nafion, the nonwoven fabric is impregnated with a cerium oxide dispersion. At this time, for example, only the second region 12 may be immersed in the cerium oxide dispersion, or wax or the like may be applied to the portions other than the second region 12 so that only the second region 12 is impregnated with the cerium oxide dispersion. By applying wax or the like to the portions other than the second region 12, only the second region 12 can be impregnated with the cerium oxide dispersion. It is also preferable to add a small amount of sodium alginate (e.g., 0.25 wt %) to the cerium oxide dispersion. This increases the viscosity of the cerium oxide dispersion, making it easier to disperse cerium oxide in the second region 12. The cerium oxide dispersion may be the same as that described in the second embodiment.

[0130] After the second region 12 is impregnated with the cerium oxide dispersion, it is preferable to place the nonwoven fabric in an aqueous calcium chloride solution (for example, 20% by weight). This causes sodium alginate and calcium chloride to react and gel, making it easier to disperse cerium oxide in the second region 12.

[0131] Furthermore, rare earth oxides such as praseodymium oxide, neodymium oxide, and lanthanum oxide may be added to the cerium oxide dispersion liquid, which makes it easier for the abrasive grains 32 to remove the oxides 31.

[0132] After second region 12 has been impregnated with the cerium oxide dispersion, excess cerium oxide dispersion is removed using, for example, a squeezer, and then the resulting product is dried for 30 minutes at 70° C. using a constant temperature dryer, etc. In this manner, polishing pad 10B having first region 11 and second region 12 on polishing surface 13 can be obtained.

[0133] (3) Method for manufacturing a conductive semiconductor substrate In the polishing step S110 of this embodiment, the polishing pad 10B and the conductive semiconductor substrate 20 are moved relative to each other to alternately bring the first region 11 and the second region 12 into contact with the polished surface 14 of the conductive semiconductor substrate 20. Specifically, for example, the conductive semiconductor substrate 20 is positioned such that the center of the polished surface 14 is located at a predetermined radial distance from the center of the polishing surface 13, and the surface plate 21 is rotated horizontally at a predetermined rotation speed to alternately bring the first region 11 and the second region 12 into contact with the polished surface 14 of the conductive semiconductor substrate 20. As a result, in the polishing step S110, the oxidation step S111 and the removal step S112 can be performed continuously and alternately. That is, the oxidation step S111 can be performed while the first region 11 is in contact with the polished surface 14 of the conductive semiconductor substrate 20, and the removal step S112 can be performed while the second region 12 is in contact with the polished surface 14 of the conductive semiconductor substrate 20. In this specification, when a portion of the polished surface 14 is in contact with the first region 11 (for example, when the polished surface 14 is in contact with both the first region 11 and the second region 12), it is determined that the first region 11 is in contact with the polished surface 14 of the conductive semiconductor substrate 20.

[0134] 14 is a graph showing a schematic diagram of a current flowing through the polishing pad 10B in the polishing step S110 of this embodiment. As shown in FIG. 14, in the polishing step S110 of this embodiment, even when a voltage is continuously applied, a current flows intermittently through the polishing pad 10B, as in the first and second embodiments. Because the first region 11 is impregnated with Nafion, which exhibits electrical conductivity, a predetermined current flows through the polishing pad 10B when the first region 11 is in contact with the polishing surface 14 of the conductive semiconductor substrate 20 (oxidation step S111). On the other hand, because the second region 12 is not impregnated with a conductive material such as Nafion, no current flows through the polishing pad 10B when the second region 12 is in contact with the polishing surface 14 of the conductive semiconductor substrate 20 (removal step S112).

[0135] 14, in the oxidation step S111 of this embodiment, the value of the current flowing through the polishing pad 10B varies depending on the area of ​​contact between the polished surface 14 and the first region 11. From the viewpoint of controlling the current value to a constant value and uniformly oxidizing the polished surface 14, it is preferable that the entire surface of the polishing surface 13 be impregnated with Nafion, as in the second embodiment described above.

[0136] (4) Effects of this embodiment According to this embodiment, one or more of the following effects can be achieved.

[0137] (a) The polishing pad 10B of this embodiment has, on the polishing surface 13, a first region 11 that generates OH radicals and oxidizes the polished surface 14 of the conductive semiconductor substrate 20 with the OH radicals, and a second region 12 that removes the oxides 31. Therefore, as in the first and second embodiments, a single polishing pad 10B can be used to oxidize and remove the oxides 31 from the polished surface 14 of the conductive semiconductor substrate 20. As a result, polishing can be performed while suppressing damage to the polished surface 14 of the conductive semiconductor substrate 20.

[0138] (b) In the polishing pad 10B of this embodiment, the first region 11 and the second region 12 are arranged so as to alternately come into contact with the polished surface 14 of the conductive semiconductor substrate 20 due to relative movement between the polishing pad 10B and the conductive semiconductor substrate 20. This allows the oxidation step S111 and the removal step S112 to be performed continuously and alternately.

[0139] (c) In the polishing step S110 of this embodiment, the region where the oxidation step S111 is performed (first region 11) and the region where the removal step S112 is performed (second region 12) are separated within the polishing surface 13 of the polishing pad 10B. Therefore, for example, in the oxidation step S111, the abrasive grains 32 do not come into contact with the polished surface 14 of the conductive semiconductor substrate 20. This makes it possible to prevent the abrasive grains 32 from interfering with the oxidation of the polished surface 14 of the conductive semiconductor substrate 20 in the oxidation step S111.

[0140] <Other Embodiments of the Present Invention> Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the present invention.

[0141] For example, in the third embodiment described above, a case where one sheet of nonwoven fabric is used to manufacture polishing pad 10B has been described, but two or more sheets of nonwoven fabric may be used to manufacture polishing pad 10B. For example, polishing pad 10B having first region 11 and second region 12 on polishing surface 13 may be manufactured by fixing Nafion to one nonwoven fabric and cerium oxide to the other nonwoven fabric, and then bonding the nonwoven fabrics together.

[0142] In the above-described embodiment, the conductive semiconductor substrate 20 is described as being a GaN substrate made of a single crystal of GaN or a SiC substrate made of a single crystal of SiC. However, the conductive semiconductor substrate 20 may be a group III nitride substrate made of a group III nitride other than GaN, such as InAlGaN, or a silicon substrate made of a single crystal of silicon. The conductive semiconductor substrate 20 may also be a template substrate in which a group III nitride is heteroepitaxially grown on an insulating substrate, such as a sapphire substrate. In this case, the entire substrate surface can be polished by, for example, contacting the side of the template substrate and applying a voltage. Among various conductive semiconductor substrates 20, it is extremely difficult to polish a GaN substrate at a practical polishing rate (e.g., 100 nm / h or higher). Therefore, the present invention is particularly effective when polishing a GaN substrate.

[0143] Furthermore, for example, in the above-described first and second embodiments, the case of polishing the Si face of a SiC substrate or the +c face of a GaN substrate has been described, but the present invention is also applicable to polishing other faces of the conductive semiconductor substrate 20.

[0144] Furthermore, for example, in the first embodiment described above, a pulse voltage is applied to the polishing pad 10, but a voltage may be applied to the polishing pad 10 continuously.

[0145] Furthermore, for example, in the above embodiment, the case where OH radicals are generated and the polishing surface 14 is oxidized has been described, but radicals other than OH radicals, atomic oxygen, etc. may be generated to oxidize the polishing surface 14. For example, peroxodisulfate ions (SO 8 2- ), an aqueous solution containing peroxodisulfate ions (e.g., an aqueous potassium peroxodisulfate solution) is supplied to the polishing surface 13, and the peroxodisulfate ions are heated and / or irradiated with light to generate sulfate ion radicals (SO4 - By generating sulfate ion radicals, it becomes possible to oxidize the polished surface 14, as in the above-described embodiment.

[0146] Furthermore, for example, in the second embodiment described above, the case where pure water is supplied in a spray form using a pure water supply unit has been described, but the manner in which pure water is supplied to the polishing surface 13 is not limited to the above embodiment. For example, gauze or the like soaked in pure water may be brought into contact with the polishing surface 13, and the pure water may be supplied to the polishing surface 13 by capillary action. In this case, it is easy to maintain a constant humidity level on the polishing surface 13. [Example]

[0147] Next, examples of the present invention will be described. These examples are merely examples of the present invention, and the present invention is not limited to these examples.

[0148] Example 1 (1) Preparation of GaN substrate First, a plurality of GaN substrates (2 inches in diameter) before polishing the surface 14 (+c-plane) were prepared as the conductive semiconductor substrate 20, and these were designated as Samples 1 to 3. The carrier concentration of Sample 1 was 1.6×10 17 cm -3 The carrier concentration of Sample 2 and Sample 3 was 2.56 × 10 18 cm-3 It was.

[0149] (2) GaN substrate polishing Using the polishing pad 10B described in the third embodiment of the present invention, the surface 14 to be polished of the sample 1 was polished while a voltage was continuously applied. The polishing conditions were as follows. Voltage (voltage applied by power supply 23): 100V Polishing pressure (pressure to press the polished surface 14 against the polishing surface 13): 18.3 kPa Rotation speed of the surface plate (rotation speed of the surface plate 21): 60 rpm Substrate rotation speed (rotation speed of the substrate holder 22): 60 rpm Polishing time (time to perform polishing process S110): 30 minutes (10 minutes x 3 times)

[0150] Furthermore, the polishing pad 10A described in the second embodiment of the present invention was used to polish the surface 14 to be polished of the sample 2 while applying a pulse voltage. The polishing conditions were as follows. Voltage (voltage applied by power supply 23): 100V Duty ratio D: 5% Pulse period T: 40 seconds Polishing pressure (pressure to press the polished surface 14 against the polishing surface 13): 18.3 kPa Rotation speed of the surface plate (rotation speed of the surface plate 21): 120 rpm Substrate rotation speed (rotation speed of the substrate holder 22): 120 rpm Polishing time (time to perform polishing process S110): 30 minutes (10 minutes x 3 times)

[0151] For comparison, the polishing surface 14 of the sample 3 was polished using a polishing pad in which only cerium oxide was dispersed in a nonwoven fabric without applying a voltage. The polishing conditions were as follows: Polishing pressure (pressure to press the polished surface 14 against the polishing surface 13): 18.3 kPa Rotation speed of the surface plate (rotation speed of the surface plate 21): 120 rpm Substrate rotation speed (rotation speed of the substrate holder 22): 120 rpm Polishing time (time to perform polishing process S110): 30 minutes (10 minutes x 3 times)

[0152] (3) Evaluation of polishing rate The polishing rate was calculated by measuring the weight and thickness of the GaN substrate before and after polishing. The polishing rate of sample 1 polished using polishing pad 10B was 132 nm / h. From the above, it was confirmed that the polishing rate can be increased to 100 nm / h or more by polishing surface 14 of the GaN substrate using polishing pad 10B.

[0153] 15 shows the polishing amounts (thickness removed by polishing) of Sample 2 and Sample 3. Sample 2, which was polished using polishing pad 10A, had a larger polishing amount than Sample 3, which was polished using a polishing pad containing only cerium oxide. From the above, it was confirmed that the polishing rate can be improved by using polishing pad 10A to polish surface 14 (+c-plane) of a GaN substrate.

[0154] (4) Evaluation of surface roughness FIG. 16 shows the results of measuring the arithmetic mean roughness Ra of sample 1 before and after polishing using an optical surface texture measuring instrument (Zygo NewView 7300). The arithmetic mean roughness Ra before polishing was 1.39 nm. The arithmetic mean roughness Ra after 10 minutes of polishing was 1.06 nm. The arithmetic mean roughness Ra after 20 minutes of polishing was 0.840 nm. The arithmetic mean roughness Ra after 30 minutes of polishing was 0.687 nm. From the above, it was confirmed that by using polishing pad 10B to polish surface 14 of a GaN substrate, a GaN substrate having an arithmetic mean roughness Ra of 0.7 nm or less can be manufactured.

[0155] <Example 2> (1) Preparation of polishing pad 10A First, the polishing pad 10A described in the second embodiment of the present invention was produced by the following procedure.

[0156] Nonwoven fabric with a diameter of 200 mm and an apparent thickness of 1 mm (apparent volume: 31.4 cm 3The mass of the nonwoven fabric was 2.80 g.

[0157] The nonwoven fabric was impregnated with a cerium oxide dispersion liquid to which a small amount of sodium alginate had been added. The nonwoven fabric was then placed in a calcium chloride aqueous solution, and after removing excess liquid from the nonwoven fabric using a squeezer, it was dried at 70°C for 30 minutes using a constant temperature dryer. The mass of the nonwoven fabric after drying was 23.88 g. The mass increase was 20.58 g, and since 40 mass% of the increase was cerium oxide (the remaining 60 mass% was sodium alginate), the density of the abrasive grains 32 was 0.26 g / cm 3 It was.

[0158] Next, the nonwoven fabric was impregnated with the Nafion dispersion, and after removing excess liquid from the nonwoven fabric using a squeezer, it was dried at 70°C for 30 minutes using a constant temperature dryer. The mass of the nonwoven fabric after drying was 23.53g. The mass increase was 0.15g, and the density of Nafion was 4.8mg / cm. 3 It was.

[0159] (2) Polishing of GaN and SiC substrates GaN substrates and SiC substrates were polished using the polishing pad 10A prepared in (1). The GaN substrates were prepared as follows: a 2-inch diameter, n-type, with a +c-plane surface 14 to be polished. The SiC substrates were prepared as follows: 4H—SiC, a 2-inch diameter, n-type, with a Si-plane surface 14 to be polished.

[0160] The polishing conditions were as follows: Voltage (voltage applied by power supply 23): 40V Current value: 100~150mA Duty ratio D: 90% Pulse period T: 120 seconds Polishing pressure (pressure to press the polished surface 14 against the polishing surface 13): 12 kPa Rotation speed of the surface plate (rotation speed of the surface plate 21): 60 rpm Substrate rotation speed (rotation speed of the substrate holder 22): 60 rpm Water supply amount: 0.4mL / min Temperature:RT Polishing time (time to perform polishing step S110): 10 minutes

[0161] (3) Evaluation of polishing rate The polishing rate was calculated by measuring the weight and thickness of the GaN substrate and SiC substrate before and after polishing. The polishing rate of the GaN substrate was 1 μm / h. In other words, it was confirmed that the polishing rate when polishing the GaN substrate using polishing pad 10A under the above polishing conditions was 1 μm / h or more.

[0162] The polishing rate of the SiC substrate was 4.5 μm / h. In other words, it was confirmed that the polishing rate when polishing a SiC substrate using polishing pad 10A under the above polishing conditions was 4.5 μm / h or more.

[0163] Example 3 (1) Preparation of the polishing pad 10 The polishing pad 10 described in the first embodiment of the present invention was produced by the following procedure.

[0164] PDMS was poured into an aluminum mold bearing a honeycomb pattern and thermally cured at 100°C. The cured PDMS was peeled off from the mold, and a Nafion dispersion (Sigma-Aldrich, product number 510211) was cast onto the surface with the transferred honeycomb pattern and allowed to dry at room temperature. After drying, the SPE membrane 15 was peeled off from the PDMS to obtain an SPE membrane 15 with a transferred honeycomb pattern. The arithmetic mean roughness Ra of the surface of the SPE membrane 15 with the transferred honeycomb pattern (with a textured structure) was measured using a confocal laser microscope (measured over an area of ​​1.8 mm x 1.8 mm; the same applies below) and found to be 12.6 μm.

[0165] The arithmetic mean roughness Ra of the surface of a commercially available Nafion membrane (Sigma-Aldrich, Nafion 117) was measured using a confocal laser microscope and found to be 1.3 μm. Next, sandpaper was rubbed against the surface of the commercially available Nafion membrane to obtain an SPE membrane 15 with a textured structure. The arithmetic mean roughness Ra of the surface of the SPE membrane 15 with a textured structure was measured using a confocal laser microscope and found to be 12.6 μm.

[0166] From the above, it was confirmed that by forming a texture structure on the surface of SPE membrane 15 using the various methods described above, the arithmetic mean roughness Ra of the surface of SPE membrane 15 can be made larger than that of commercially available Nafion membranes (for example, 5 μm or more).

[0167] The SPE film 15 with the textured structure formed by sandpaper was cut into 18 mm x 18 mm pieces and attached to a stainless steel plate in a grid pattern using conductive double-sided tape. The cut SPE film 15 was attached so that the grooves 33 were 2 mm wide, 1 mm deep, and 20 mm pitch. Thus, a polishing pad 10 was obtained.

[0168] (2) Polishing the conductive semiconductor substrate 20 A SiC substrate was polished using the polishing pad 10 prepared in (1). The SiC substrate was 4H—SiC, had a diameter of 2 inches, was n-type, and had a Si surface (off angle of 4 degrees) as the polishing surface 14.

[0169] The basic conditions for polishing were as follows: Current value: 50~450mA Duty ratio D: 90% Period T: 60 seconds Polishing pressure: 12.2kPa Platen rotation speed, substrate rotation speed: 60 rpm Slurry: Cerium oxide suspension (average particle size (D50) 1.3 μm, 3 wt%) Water supply amount: 30mL / min Polishing time: 5 minutes x 3 times

[0170] Figure 17(a) shows the polishing rate (MRR) and current efficiency (current efficiency) with varying current values. The polishing rate was calculated by measuring the weight and thickness of the SiC substrate before and after polishing. As shown in Figure 17(a), we confirmed that the polishing rate increased with increasing current value. We also confirmed that the slope of the polishing rate versus current value differed between region Z1, where the current value was 150 mA or less, and region Z2, where the current value was 200 mA or more. Region Z1, where the oxide 31 removal rate v2 was greater than the oxide 31 generation rate v1, also confirmed that the current efficiency was high. On the other hand, region Z2, where the current value was 200 mA or more, confirmed that the rate v1 was greater than the rate v2, and confirmed that the current efficiency was lower than region Z1. Therefore, we confirmed that energy loss could be reduced by polishing under the conditions of region Z1. However, if higher speed polishing is desired in the initial stage of polishing, polishing under the conditions of region Z2 may be performed.

[0171] FIG. 17(b) shows the change in voltage when polishing was performed with a current value of 250 mA, a duty ratio D of 50%, and a period T of 20 seconds. As shown in FIG. 17(b), it was confirmed that the voltage increased slightly over time while the voltage was being applied. This is thought to be due to the formation of oxide 31 on the surface of the SiC substrate. Furthermore, since the voltage was approximately 30 V at the start of voltage application for each duty cycle, it was confirmed that the oxide 31 formed during one cycle of the oxidation step S111 was completely removed during the section where no voltage was applied.

[0172] Figures 18(a) and 18(b) show the results of measurements of the polished SiC substrate surface using a phase-shifting interference microscope (Zygo NewView 7300) at a current of 250 mA. Figures 18(a) and 18(b) show the results of polishing with applied voltage (ECMP) and, for comparison, polishing without applied voltage (CMP). As shown in Figures 18(a) and 18(b), the surface shape remains almost unchanged when polishing without applied voltage, whereas when polishing with applied voltage, most scratches and cracks on the surface are removed. Furthermore, we confirmed that the arithmetic mean roughness (Ra) of the SiC substrate surface was significantly improved from approximately 50 μm to approximately 1 nm after 10 minutes of polishing.

[0173] The surface roughness distribution of the SiC substrate after 15 minutes of polishing is shown in Figures 19(a) and 19(b). As shown in Figures 19(a) and 19(b), the arithmetic mean roughness Ra was less than 1 nm at all measurement points, confirming that the entire surface of the SiC substrate was polished uniformly.

[0174] Furthermore, the arithmetic mean roughness Ra of the surface of the SPE film 15 after 15 minutes of polishing was measured using a confocal laser microscope and found to be 7.4 μm. It was confirmed that the arithmetic mean roughness Ra of the surface of the SPE film 15 after polishing was smaller than the arithmetic mean roughness Ra of the surface of the SPE film 15 before polishing. Therefore, it was confirmed that the life of the polishing pad 10 can be improved by performing the dressing treatment step S120 as necessary.

[0175] <Preferred embodiment of the present invention> Preferred embodiments of the present invention will be described below.

[0176] (Appendix 1) According to one aspect of the present invention, A polishing pad used for polishing a surface to be polished of a conductive semiconductor substrate, A polishing pad is provided, which has a film containing a solid polymer electrolyte on at least a portion of the polishing surface that contacts the surface to be polished.

[0177] (Appendix 2) 10. The polishing pad of claim 1, The polishing surface has a circular shape with a diameter of 500 mm or more. Preferably, the polishing surface has a circular shape with a diameter of 500 mm or more and 2000 mm or less. Preferably, the polishing pad has a thickness of 0.1 mm or more and 10 mm or less.

[0178] (Appendix 3) 1. The polishing pad according to claim 1 or 2, A textured structure is provided on the surface of the solid polymer electrolyte-containing film on the polished surface. Preferably, the textured structure has irregularities with a maximum height Rz of 20 μm or more and 200 μm or less. Preferably, the textured structure has random concaves and convexes. Preferably, the maximum height Rz of the textured structure is greater than the average grain size of the abrasive grains supplied to the polishing surface.

[0179] (Appendix 4) A polishing pad according to any one of claims 1 to 3, The arithmetic mean roughness Ra of the surface of the solid polymer electrolyte-containing film on the polished surface is 5 μm or more and 50 μm or less. Preferably, the arithmetic mean roughness Ra is 10 μm or more and 20 μm or less.

[0180] (Appendix 5) 5. The polishing pad according to claim 1, The thickness of the membrane containing the solid polymer electrolyte is 0.1 mm or more and 1 mm or less.

[0181] (Appendix 6) 6. The polishing pad according to claim 1, The polished surface has grooves with a width of 1 mm or more and a depth of 0.1 mm or more. Preferably, the width of the groove is 1 mm or more and 5 mm or less, the depth of the groove is 0.1 mm or more and 1 mm or less, and the pitch of the grooves is 10 mm or more and 50 mm or less.

[0182] (Appendix 7) 7. The polishing pad according to claim 1, The membrane containing the solid polymer electrolyte is provided on a conductive substrate.

[0183] (Appendix 8) 10. The polishing pad according to claim 1, With water molecules in contact with the solid polymer electrolyte, electrical conduction is established between the polished surface and the back surface opposite to the polished surface.

[0184] (Appendix 9) 10. The polishing pad according to claim 1, The solid polymer electrolyte is a polymer having a fluorocarbon skeleton and a fluorocarbon ether side chain having a sulfonic acid group at its end.

[0185] (Appendix 10) 10. The polishing pad according to any one of claims 1 to 9, Polishing is performed by supplying a slurry containing abrasive grains and water to the polishing surface.

[0186] (Appendix 11) 11. The polishing pad of claim 10, The water, which is the dispersion medium for the abrasive grains, is configured to supply water molecules to the solid polymer electrolyte.

[0187] (Appendix 12) According to another aspect of the present invention, preparing a polishing pad having a film containing a solid polymer electrolyte on at least a portion of a polishing surface that contacts a surface to be polished of a conductive semiconductor substrate; a step of bringing the polishing surface of the polishing pad into contact with the surface to be polished of the conductive semiconductor substrate under pressure while water molecules are in contact with the solid polymer electrolyte, and polishing the surface to be polished by moving the polishing pad and the conductive semiconductor substrate relative to each other while applying a voltage between the polishing pad and the conductive semiconductor substrate; A method for manufacturing a conductive semiconductor substrate is provided, comprising:

[0188] (Appendix 13) A method for producing a conductive semiconductor substrate according to claim 12, comprising: In the step of preparing the polishing pad, a polishing pad is prepared in which the polishing surface is circular and has a diameter of 500 mm or more.

[0189] (Appendix 14) A method for producing a conductive semiconductor substrate according to Supplementary Note 12 or Supplementary Note 13, comprising: In the step of preparing the polishing pad, a polishing pad is prepared in which a textured structure is provided on the surface of the film containing the solid polymer electrolyte on the polishing surface.

[0190] (Appendix 15) A method for producing a conductive semiconductor substrate according to any one of Supplementary Note 12 to Supplementary Note 14, At the start of the polishing step, the arithmetic mean roughness Ra of the surface of the solid polymer electrolyte-containing film on the polished surface is 5 μm or more and 50 μm or less.

[0191] (Appendix 16) A method for producing a conductive semiconductor substrate according to any one of Supplementary Note 12 to Supplementary Note 15, In the step of preparing the polishing pad, a polishing pad is prepared in which the thickness of the film containing the solid polymer electrolyte is 0.1 mm or more and 1 mm or less.

[0192] (Appendix 17) A method for producing a conductive semiconductor substrate according to any one of Supplementary Note 12 to Supplementary Note 16, comprising: In the step of preparing the polishing pad, a polishing pad is prepared in which grooves having a width of 1 mm or more and a depth of 0.1 mm or more are formed on the polishing surface.

[0193] (Appendix 18) A method for producing a conductive semiconductor substrate according to any one of Supplementary Note 12 to Supplementary Note 17, In the step of preparing the polishing pad, a polishing pad is prepared in which a film containing the solid polymer electrolyte is provided on a conductive substrate.

[0194] (Appendix 19) A method for producing a conductive semiconductor substrate according to any one of Supplementary Note 12 to Supplementary Note 18, comprising: In the step of preparing the polishing pad, a polishing pad is prepared using a polymer having a fluorocarbon skeleton and a fluorocarbon ether side chain having a sulfonic acid group at its terminal as the solid polymer electrolyte.

[0195] (Appendix 20) A method for producing a conductive semiconductor substrate according to any one of Supplementary Note 12 to Supplementary Note 19, In the polishing step, the surface to be polished is oxidized while the voltage is being applied, to generate an oxide.

[0196] (Appendix 21) A method for producing a conductive semiconductor substrate according to any one of Supplementary Note 12 to Supplementary Note 20, comprising: In the polishing step, the voltage is applied intermittently.

[0197] (Appendix 22) A method for producing a conductive semiconductor substrate according to any one of Supplementary Note 12 to Supplementary Note 21, In the polishing step, a slurry containing abrasive grains and water is supplied to the polishing surface. Preferably, the amount of water supplied is 10 mL / min or more and 50 mL / min or less.

[0198] (Appendix 23) A method for producing a conductive semiconductor substrate according to any one of Supplementary Note 12 to Supplementary Note 22, In the polishing step, the voltage is applied so that the current flowing between the polishing pad and the conductive semiconductor substrate gradually decreases.

[0199] (Appendix 24) A method for producing a conductive semiconductor substrate according to any one of Supplementary Note 12 to Supplementary Note 23, In the polishing step, the polishing pad and the conductive semiconductor substrate are moved relative to each other for a predetermined time without applying a voltage between the polishing pad and the conductive semiconductor substrate, and then the polishing step is completed.

[0200] (Appendix 25) A method for producing a conductive semiconductor substrate according to any one of Supplementary Note 12 to Supplementary Note 24, comprising: The method further includes a step of roughening the surface of the membrane containing the solid polymer electrolyte.

[0201] (Appendix 26) 21. A method for producing a conductive semiconductor substrate according to claim 20, comprising: In the polishing step, the rate v1 of generating the oxide is controlled by the value of the current flowing between the polishing pad and the conductive semiconductor substrate, and the rate v2 of removing the oxide is controlled by changing at least one of the amount of abrasive grains supplied to the polishing surface, the pressure applied between the polishing surface and the surface to be polished, or the relative speed between the polishing pad and the conductive semiconductor substrate.

[0202] (Appendix 27) 27. A method for producing a conductive semiconductor substrate according to claim 26, comprising: In the polishing step, the speed v1 and the speed v2 are controlled so as to satisfy the relationship v1≦v2.

[0203] (Appendix 28) 27. A method for producing a conductive semiconductor substrate according to claim 26, comprising: In the initial stage of the polishing process, the relationship v1>v2 is controlled to be satisfied, and in the final polishing of the polishing process, the relationship v1≦v2 is controlled to be satisfied.

[0204] (Appendix 29) According to another aspect of the present invention, preparing a polishing pad having a film containing a solid polymer electrolyte on at least a portion of a polishing surface that contacts a surface to be polished of a conductive semiconductor substrate; a step of bringing the polishing surface of the polishing pad into contact with the surface to be polished of the conductive semiconductor substrate under pressure while water molecules are in contact with the solid polymer electrolyte, and polishing the surface to be polished by moving the polishing pad and the conductive semiconductor substrate relative to each other while applying a voltage between the polishing pad and the conductive semiconductor substrate; A method for polishing a conductive semiconductor substrate is provided, comprising:

[0205] (Appendix 30) According to one aspect of the present invention, A polishing pad used for polishing a surface to be polished of a conductive semiconductor substrate, There is provided a polishing pad, the polishing surface of which comes into contact with the surface to be polished being impregnated with at least a solid polymer electrolyte.

[0206] (Appendix 31) 31. The polishing pad of claim 30, The solid polymer electrolyte is also impregnated in the thickness direction of the polishing pad.

[0207] (Appendix 32) 32. The polishing pad according to claim 30 or 31, The solid polymer electrolyte is 3 mg / cm 3 More than 20mg / cm 3 It is impregnated with the following densities:

[0208] (Appendix 33) 33. The polishing pad according to any one of claims 30 to 32, With water molecules in contact with the solid polymer electrolyte, electrical conduction is established between the polished surface and the back surface opposite to the polished surface.

[0209] (Appendix 34) 34. The polishing pad of claim 30, The polishing pad comprises a nonwoven fabric, The solid polymer electrolyte is attached to the surface of the fibers of the nonwoven fabric.

[0210] (Appendix 35) 35. The polishing pad of any one of claims 30 to 34, The solid polymer electrolyte is a polymer (Nafion) having a fluorocarbon skeleton and a fluorocarbon ether side chain having a sulfonic acid group at its end.

[0211] (Appendix 36) 36. The polishing pad of any one of claims 30 to 35, A conductive adhesive is applied to the back surface opposite the polished surface.

[0212] (Appendix 37) 37. The polishing pad of any one of claims 30 to 36, Abrasive grains are dispersed on the polishing surface. Preferably, the abrasive grains have a hardness lower than that of the semiconductor crystals that make up the surface to be polished.

[0213] (Appendix 38) 38. The polishing pad of claim 37, the abrasive grains include cerium oxide; The abrasive grains have a density of 0.1 g / cm 3 More than 0.5g / cm 3 It is distributed at the following density:

[0214] (Appendix 39) 39. The polishing pad according to claim 37 or 38, The solid polymer electrolyte is attached to the surface of the abrasive grain.

[0215] (Appendix 40) 39. The polishing pad according to claim 37, When a gallium nitride substrate made of a single crystal of gallium nitride is polished while a voltage of 40 V is intermittently applied between the polishing pad and the gallium nitride substrate, the polishing rate is 1 μm / h or more. Preferably, the value of the current flowing through the gallium nitride substrate is 100 mA or more and 150 mA or less. Preferably, the duty ratio D is 90%. Preferably, the period T of the pulses is 120 seconds. Preferably, the pressure with which the polishing surface is pressed against the surface to be polished is 12 kPa. Preferably, the rotation speed of the polishing pad and the gallium nitride substrate is 60 rpm. Preferably, the amount of water supplied to the polishing surface is 0.4 mL / min.

[0216] (Appendix 41) 41. The polishing pad of any one of claims 37 to 40, When a silicon carbide substrate made of single crystal silicon carbide is polished while a voltage of 40 V is intermittently applied between the polishing pad and the silicon carbide, the polishing rate is 4.5 μm / h or more. Preferably, the value of the current flowing through the silicon carbide substrate is 100 mA or more and 150 mA or less. Preferably, the duty ratio D is 90%. Preferably, the period T of the pulses is 120 seconds. Preferably, the pressure with which the polishing surface is pressed against the surface to be polished is 12 kPa. Preferably, the rotation speed of the polishing pad and the silicon carbide substrate is 60 rpm. Preferably, the amount of water supplied to the polishing surface is 0.4 mL / min.

[0217] (Appendix 42) According to another aspect of the present invention, A step of preparing a polishing pad, the polishing surface of which contacts the surface to be polished of the conductive semiconductor substrate being impregnated with at least a solid polymer electrolyte; a step of bringing the polishing surface of the polishing pad into contact with the surface to be polished of the conductive semiconductor substrate under pressure while water molecules are in contact with the solid polymer electrolyte, and polishing the surface to be polished by moving the polishing pad and the conductive semiconductor substrate relative to each other while applying a voltage between the polishing pad and the conductive semiconductor substrate; A method for manufacturing a conductive semiconductor substrate is provided, comprising:

[0218] (Appendix 43) 43. A method for producing a conductive semiconductor substrate according to claim 42, comprising: In the polishing step, the surface to be polished is oxidized while the voltage is being applied.

[0219] (Appendix 44) A method for producing a conductive semiconductor substrate according to claim 42 or 43, comprising: In the polishing step, the voltage is applied intermittently.

[0220] (Appendix 45) 45. A method for producing a conductive semiconductor substrate according to any one of claims 42 to 44, comprising: In the polishing step, a slurry containing abrasive grains is supplied to the polishing surface.

[0221] (Appendix 46) 46. ​​A method for producing a conductive semiconductor substrate according to any one of claims 42 to 45, comprising: In the polishing step, a porous structure is formed on the surface to be polished of the conductive semiconductor substrate, and then the porous structure is removed. Preferably, the conductive semiconductor substrate is a gallium nitride substrate made of a single crystal of gallium nitride.

[0222] (Appendix 47) 47. A method for producing a conductive semiconductor substrate according to any one of claims 42 to 46, comprising: In the polishing step, the voltage V applied between the polishing pad and the conductive semiconductor substrate is controlled so as not to exceed the voltage Vm at which the polishing rate of the conductive semiconductor substrate becomes maximum. Preferably, the conductive semiconductor substrate is a silicon carbide substrate made of a single crystal of silicon carbide.

[0223] (Appendix 48) 48. A method for producing a conductive semiconductor substrate according to any one of claims 42 to 47, comprising: In the polishing step, the polishing pad and the conductive semiconductor substrate are moved relative to each other for a predetermined time without applying a voltage between the polishing pad and the conductive semiconductor substrate, and then the polishing step is completed.

[0224] (Appendix 49) According to another aspect of the present invention, A polishing pad used for polishing a surface of a conductive semiconductor substrate, On a surface in contact with the surface of the conductive semiconductor substrate, a first region in which radicals are generated and the semiconductor crystals constituting the surface of the conductive semiconductor substrate are oxidized by the radicals; and a second region that removes oxides produced by oxidation of the semiconductor crystal by the radicals. Preferably, the polishing pad has water retention properties. Preferably, the surface of the polishing pad that comes into contact with the surface of the conductive semiconductor substrate has slidability relative to the surface of the conductive semiconductor substrate. Preferably, the polishing pad has a conductive adhesive on the back surface.

[0225] (Appendix 50) 49. The polishing pad of claim 49, The radical is an OH radical.

[0226] (Appendix 51) 51. The polishing pad according to claim 49 or 50, The first region is impregnated with a solid polymer electrolyte that generates the radicals (from water when a voltage is applied). Preferably, the solid polymer electrolyte is impregnated throughout the polishing pad in the thickness direction. Preferably, the voltage is 20V or more and 300V or less.

[0227] (Appendix 52) 52. The polishing pad according to any one of claims 49 to 51, Abrasive grains for removing the oxides are dispersed in the second region. Preferably, the abrasive grains have a hardness lower than that of the semiconductor crystals.

[0228] (Appendix 53) 53. The polishing pad of any one of claims 49 to 52, The first region and the second region are arranged so as to alternately come into contact with the conductive semiconductor substrate due to relative movement between the polishing pad and the conductive semiconductor substrate.

[0229] (Appendix 54) According to another aspect of the present invention, A polishing pad used for polishing a surface of a conductive semiconductor substrate, It contains dispersed abrasive grains that are less hard than gallium nitride. A polishing pad is provided that has a polishing rate of 100 nm / h or more and 10,000 nm / h or less when polishing (the +c plane of) a gallium nitride substrate made of a single crystal of gallium nitride in a neutral region. Preferably, OH radicals are generated from water by applying a voltage, and the gallium nitride is oxidized by the OH radicals. Preferably, gallium oxide produced by oxidizing the gallium nitride is removed. Preferably, the voltage is 20V or more and 300V or less. Preferably, the carrier concentration at the surface of the gallium nitride substrate is 1.0×10 16 cm -3 Over 1.0 x 10 20 cm -3 The following is the result.

[0230] (Appendix 55) According to another aspect of the present invention, A method for manufacturing a conductive semiconductor substrate, comprising: generating radicals and oxidizing semiconductor crystals constituting the surface of the conductive semiconductor substrate with the radicals; and removing oxides produced by oxidizing the semiconductor crystal with the radicals, There is provided a method for manufacturing a conductive semiconductor substrate, in which the oxidizing step and the removing step are carried out by relatively moving a polishing pad that polishes the surface of the conductive semiconductor substrate and the conductive semiconductor substrate. Preferably, the oxidizing step and the removing step are carried out simultaneously or alternately. [Explanation of symbols]

[0231] 10, 10A, 10B Polishing Pads 11 First area 12 Second area 13 Polished surface 14 Surface to be polished 15 SPE membrane 16 Fiber 17 Bubbles 18 Porous layer 19 Conductive substrate 20 Conductive semiconductor substrate 21 Surface Plate 22 Substrate holder 23 Power supply 24 Slurry supply section 30 Conductive semiconductors 31 Oxides 32 abrasive grains 33 Groove S100 Preparation process S110 Polishing process S111 Oxidation process S112 Removal process S120 Dressing process

Claims

1. preparing a polishing pad having a film containing a solid polymer electrolyte on at least a portion of a polishing surface that contacts a surface to be polished of a conductive semiconductor substrate; a step of bringing the polishing surface of the polishing pad into contact with the surface to be polished of the conductive semiconductor substrate under pressure while water molecules are in contact with the solid polymer electrolyte, and polishing the surface to be polished by moving the polishing pad and the conductive semiconductor substrate relative to each other while applying a voltage between the polishing pad and the conductive semiconductor substrate; and In the step of preparing the polishing pad, a polishing pad is prepared in which a textured structure is provided on the surface of the film containing the solid polymer electrolyte on the polishing surface, a step of performing a surface roughening treatment on the surface of the film containing the solid polymer electrolyte to form the textured structure again when a load generated when the polishing pad or the conductive semiconductor substrate is moved relative to the polishing pad exceeds a predetermined value.

2. 2. The method for producing a conductive semiconductor substrate according to claim 1, wherein in the step of preparing a polishing pad, a polishing pad is prepared, the polishing surface of which is circular and has a diameter of 500 mm or more.

3. 3. The method for producing a conductive semiconductor substrate according to claim 1, wherein the arithmetic mean roughness Ra of the surface of the film containing the solid polymer electrolyte on the polished surface is 5 μm or more at the start of the polishing step.

4. 4. The method for manufacturing a conductive semiconductor substrate according to claim 1, wherein in the step of preparing a polishing pad, a polishing pad having a film containing the solid polymer electrolyte having a thickness of 0.1 mm or more is prepared.

5. 5. The method for manufacturing a conductive semiconductor substrate according to claim 1, wherein in the step of preparing the polishing pad, a polishing pad is prepared in which a groove having a width of 1 mm or more and a depth of 0.1 mm or more is provided on the polishing surface.

6. 6. The method for manufacturing a conductive semiconductor substrate according to claim 1, wherein the step of preparing a polishing pad includes preparing a polishing pad having a conductive base material and a film containing the solid polymer electrolyte provided on the base material.

7. 7. The method for producing a conductive semiconductor substrate according to claim 1, wherein in the step of preparing the polishing pad, a polishing pad is prepared using a polymer having a fluorocarbon skeleton and a fluorocarbon ether side chain having a sulfonic acid group at its terminal as the solid polymer electrolyte.

8. The method for producing a conductive semiconductor substrate according to claim 1 , wherein in the polishing step, the surface to be polished is oxidized while the voltage is being applied to generate an oxide.

9. The method for manufacturing a conductive semiconductor substrate according to claim 1 , wherein the voltage is applied intermittently in the polishing step.

10. The method for manufacturing a conductive semiconductor substrate according to claim 1 , wherein in the polishing step, a slurry containing abrasive grains and water is supplied to the polishing surface.

11. 11. The method for manufacturing a conductive semiconductor substrate according to claim 1, wherein in the polishing step, the voltage is applied so that a current flowing between the polishing pad and the conductive semiconductor substrate gradually decreases.

12. 12. The method for manufacturing a conductive semiconductor substrate according to claim 1, wherein in the polishing step, the polishing pad and the conductive semiconductor substrate are moved relative to each other for a predetermined time in a state where no voltage is applied between the polishing pad and the conductive semiconductor substrate, and then the polishing step is terminated.

13. 9. The method for producing a conductive semiconductor substrate according to claim 8, wherein in the polishing step, a rate v1 of generating the oxide is controlled by a current value flowing between the polishing pad and the conductive semiconductor substrate, and a rate v2 of removing the oxide is controlled by changing at least one of an amount of abrasive grains supplied to the polishing surface, a pressure applied between the polishing surface and the surface to be polished, or a relative speed between the polishing pad and the conductive semiconductor substrate.

14. The method for producing a conductive semiconductor substrate according to claim 13 , wherein in the polishing step, the speed v1 and the speed v2 are controlled so as to satisfy the relationship v1≦v2.

15. preparing a polishing pad having a film containing a solid polymer electrolyte on at least a portion of a polishing surface that contacts a surface to be polished of a conductive semiconductor substrate; a step of bringing the polishing surface of the polishing pad into contact with the surface to be polished of the conductive semiconductor substrate under pressure while water molecules are in contact with the solid polymer electrolyte, and polishing the surface to be polished by moving the polishing pad and the conductive semiconductor substrate relative to each other while applying a voltage between the polishing pad and the conductive semiconductor substrate; and In the step of preparing the polishing pad, a polishing pad is prepared in which a textured structure is provided on the surface of the film containing the solid polymer electrolyte on the polishing surface, The method for polishing a conductive semiconductor substrate further comprises a step of performing a roughening treatment on the surface of the film containing the solid polymer electrolyte to form the textured structure again when a load generated when the polishing pad or the conductive semiconductor substrate is moved relative to one another exceeds a predetermined value.

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