Nanosheet semiconductor devices with N / P boundary structures

Abstract

A method for fabricating a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, each of the nanosheet stacks including alternating layers of a first-type sacrificial layer and an active semiconductor layer. The method includes forming a first-type sacrificial layer on a sidewall of the nanosheet stack, then forming a dielectric pillar between sidewall portions of the first-type sacrificial layer of adjacent nanosheet stacks, and then removing the first-type sacrificial layer. The method also includes forming a PWFM layer in a space formed by removing the first-type sacrificial layer for a first nanosheet stack of the nanosheet stacks, and forming a NWFM layer in a space formed by removing the first-type sacrificial layer for an adjacent second nanosheet stack of the nanosheet stacks.

Description

[Technical Field]

[0001] The present disclosure relates to fabrication methods and resulting structures for semiconductor devices. More particularly, the present disclosure relates to fabrication methods and resulting structures for nanosheet field effect transistors (FETs). [Background technology]

[0002] In certain semiconductor device fabrication processes, numerous semiconductor devices, such as n-type field-effect transistors (nFETs) and p-type field-effect transistors (pFETs), are fabricated on a single wafer. Non-planar transistor device architectures (e.g., fin-type field-effect transistors (FinFETs) and nanosheet FETs) can offer higher device density and higher performance than planar transistors. As semiconductor integrated circuits (ICs) and / or chips become smaller, stacked nanosheets are increasingly being implemented into semiconductor devices.

[0003] Nanosheets generally refer to two-dimensional nanostructures with thicknesses ranging on the order of about 1 nanometer (nm) to about 100 nm, which can facilitate the fabrication of non-planar semiconductor devices with reduced footprints compared to conventional planar semiconductor devices.

[0004] For example, in contrast to conventional planar FETs, nanosheet transistors contain a gate stack that surrounds the entire periphery of multiple stacked nanosheet channel regions to reduce the device footprint and improve control of the channel current. Nanosheet transistors also enable full depletion of the nanosheet channel region, reducing short-channel effects. Therefore, nanosheets and nanowires are considered viable options for reducing the footprint of semiconductor transistor devices to 7 nanometers or less. Summary of the Invention

[0005] Embodiments of the present disclosure relate to a method for fabricating a nanosheet field effect transistor (FET) device. In particular, certain embodiments include forming a plurality of nanosheet stacks on a substrate, each including alternating layers of a first-type sacrificial layer and an active semiconductor layer. The method includes forming a first-type sacrificial layer on a sidewall of the nanosheet stack, then forming a dielectric pillar between sidewall portions of the first-type sacrificial layer of adjacent nanosheet stacks, and then removing the first-type sacrificial layer. The method also includes forming a PWFM layer in a space formed by removing the first-type sacrificial layer for a first nanosheet stack of the nanosheet stacks, and forming an NWFM layer in a space formed by removing the first-type sacrificial layer for an adjacent second nanosheet stack of the nanosheet stacks.

[0006] Another embodiment relates to a nanosheet FET device. The nanosheet FET device includes a substrate and a plurality of nanosheet stacks formed on the substrate. A first nanosheet stack of the nanosheet stacks includes alternating layers of PWFM layers and active semiconductor layers. An adjacent second nanosheet stack of the nanosheet stacks includes alternating layers of NWFM layers and active semiconductor layers. PWFM layers and NWFM layers are also formed on the sidewalls of each nanosheet stack. The nanosheet FET device also includes a dielectric pillar formed between a sidewall portion of the PWFM layer and a sidewall portion of the NWFM layer of an adjacent nanosheet stack, the dielectric pillar extending from the substrate to a level above the top surface of the nanosheet stacks.

[0007] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

[0008] The drawings included in this application are incorporated into and form a part of this specification. These drawings illustrate embodiments of the present disclosure and, together with the description, explain the principles of the disclosure. The drawings are merely illustrative of particular embodiments and are not intended to limit the disclosure. [Brief explanation of the drawings]

[0009] [Figure 1A] 1A-1C are top views of a semiconductor nanosheet device at intermediate stages in a semiconductor fabrication process flow, according to an embodiment. [Figure 1B] 1B is a cross-sectional view of the semiconductor nanosheet device of FIG. 1A taken along line Y in FIG. 1A according to an embodiment. [Figure 1C] 1B is a cross-sectional view of the semiconductor nanosheet device of FIG. 1B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 1D] 1C is a cross-sectional view of the semiconductor nanosheet device of FIG. 1C taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 2A] 1D taken along line X in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 2B] 1D taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 2C] 1D taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 3A] 2B is a cross-sectional view of the semiconductor nanosheet device of FIG. 2A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 3B] 2B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 3C] 2C is a cross-sectional view of the semiconductor nanosheet device of FIG. 2C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 4A] 3B is a cross-sectional view of the semiconductor nanosheet device of FIG. 3A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 4B]3B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 4C] 3C is a cross-sectional view of the semiconductor nanosheet device of FIG. 3C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 5A] 4B is a cross-sectional view of the semiconductor nanosheet device of FIG. 4A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 5B] 4B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 5C] 4C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 6A] 5B is a cross-sectional view of the semiconductor nanosheet device of FIG. 5A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 6B] 5B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 6C] 5C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 7A] 6B is a cross-sectional view of the semiconductor nanosheet device of FIG. 6A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 7B] 6B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 7C] 6C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 8A] 7B is a cross-sectional view of the semiconductor nanosheet device of FIG. 7A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 8B]7B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 8C] 7D is a cross-sectional view of the semiconductor nanosheet device of FIG. 7C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 9A] 8B is a cross-sectional view of the semiconductor nanosheet device of FIG. 8A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 9B] 8B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 9C] 8C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 10A] 9B is a cross-sectional view of the semiconductor nanosheet device of FIG. 9A taken along line X in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 10B] 9B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 10C] 9C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 11A] 10B is a cross-sectional view of the semiconductor nanosheet device of FIG. 10A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 11B] 10B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 11C] 10C is a cross-sectional view of the semiconductor nanosheet device of FIG. 10C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 12A] 11B is a cross-sectional view of the semiconductor nanosheet device of FIG. 11A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 12B]11B is a cross-sectional view of the semiconductor nanosheet device of FIG. 11B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 12C] 11C is a cross-sectional view of the semiconductor nanosheet device of FIG. 11C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 13A] 12B is a cross-sectional view of the semiconductor nanosheet device of FIG. 12A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 13B] 12B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 13C] 12C is a cross-sectional view of the semiconductor nanosheet device of FIG. 12C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 14A] 13B is a cross-sectional view of the semiconductor nanosheet device of FIG. 13A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 14B] 13B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 14C] 13C is a cross-sectional view of the semiconductor nanosheet device of FIG. 13C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 15A] 14B is a cross-sectional view of the semiconductor nanosheet device of FIG. 14A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 15B] 14B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 15C] 14C is a cross-sectional view of the semiconductor nanosheet device of FIG. 14C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 16A] 15B is a cross-sectional view of the semiconductor nanosheet device of FIG. 15A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 16B] 15B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 16C] 15C is a cross-sectional view of the semiconductor nanosheet device of FIG. 15C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 17A] 15B is a cross-sectional view of the semiconductor nanosheet device of FIG. 15A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 17B] 15B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 17C] 15C is a cross-sectional view of the semiconductor nanosheet device of FIG. 15C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 18A] 17B is a cross-sectional view of the semiconductor nanosheet device of FIG. 17A taken along line X of FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 18B] 17B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. [Figure 18C] 17D is a cross-sectional view of the semiconductor nanosheet device of FIG. 17C taken along line Z in FIG. 1A after an additional fabrication operation, according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] This disclosure describes horizontally stacked gate-all-around (GAA) nanosheet structures (e.g., nanosheet field-effect transistor (FET) devices) and methods for fabricating the nanosheet structures. In particular, this disclosure describes nanosheet FET devices with improved negative FET (NFET) and positive FET (PFET) (i.e., N-2-P) interface.

[0011] Various embodiments of the present disclosure are described herein with reference to the associated drawings. Alternate embodiments may be devised without departing from the scope of the present disclosure. Note that in the following description and drawings, various connections and relationships (e.g., above, below, adjacent, etc.) between elements are described. These connections and / or relationships may be direct or indirect unless otherwise specified, and the present disclosure is not intended to be limited in this respect. Thus, coupling of entities may refer to either direct or indirect coupling, and relationship between entities may be direct or indirect. As an example of an indirect relationship, a reference herein to forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," as long as the relevant properties and functionality of layer "A" and layer "B" are not substantially altered by the intermediate layer(s).

[0012] The following definitions and abbreviations are used for interpreting the claims and this specification. As used herein, the terms "comprise," "comprising," "include," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements and can include other elements not expressly listed or inherent in such composition, mixture, process, method, article, or device.

[0013] For purposes of the following description, the terms "above," "below," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives refer to the structures and methods described as oriented in the drawings. The terms "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, resides on a second element, such as a second structure, and that an intervening element, such as an interfacial structure, may reside between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface between the two elements. Note that the term "selective to," as in, for example, "a first element selective to a second element," means that the first element can be etched and the second element can act as an etch stop.

[0014] For the sake of brevity, conventional techniques related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Moreover, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned herein or are omitted entirely without providing details of the well-known processes.

[0015] The various processes used to form microchips that are packaged into ICs generally fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD), among others. Removal / etching is any process that removes material from a wafer. Examples include etching processes (either wet or dry) and chemical mechanical planarization (CMP). Semiconductor doping is the modification of electrical properties, for example, by doping the source and drain of a transistor, typically by diffusion or ion implantation or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and separate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the substrate's conductivity to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate and the subsequent transfer of that pattern into the substrate. In semiconductor lithography, the pattern is formed with a light-sensitive polymer called a photoresist. The lithography and etching pattern transfer steps are repeated multiple times to build the intricate structures that make up the transistors and the numerous wires that connect the circuit's millions of transistors.Each pattern printed on the wafer is aligned to a previously formed pattern, gradually building up conductors, insulators and selectively doped regions to form the final device.

[0016] Turning now to an overview of the technology more specifically related to embodiments of the present disclosure, semiconductor nanosheet devices typically include one or more suspended nanosheets that function as channels. An epitaxial process is typically performed to grow source / drain epitaxy structures from the surface of the wafer and contact both ends of the nanosheets. Metal source / drain contacts are then typically formed on the top surface of the source / drain epitaxy structure to provide the final source / drain contacts for the device. As manufacturing trends continue to move toward smaller semiconductor device footprints, the total contact area between the top surface of the source / drain epitaxy structure and the bottom surface of the metal source / drain contacts is reduced.

[0017] The flow charts and cross-sectional views in the figures illustrate methods of fabricating nanosheet FET devices according to various embodiments. In some alternative implementations, the fabrication steps may occur in a different order than depicted in the figures, and certain additional fabrication steps may be performed between the steps depicted in the figures. Furthermore, any of the layered structures depicted in the figures may include multiple sublayers.

[0018] Referring now to the drawings, in which like numerals represent the same or similar elements, and first to FIG. 1A, a top view of a semiconductor nanosheet device 100 at an intermediate stage of the fabrication process is shown. As shown in FIG. 1A, several cut lines X, Y, and Z are illustrated, which are used herein to describe cross-sectional views of the semiconductor nanosheet device 100 at several stages of the fabrication process from different perspectives. The semiconductor nanosheet device 100 includes a silicon-based substrate (see FIG. 1B, element 102) that includes a p-type semiconductor field-effect transistor (PFET) region and an n-type semiconductor field-effect transistor (NFET) region. Accordingly, in certain embodiments, the silicon-based substrate 102 is doped with different materials in different regions to form the PFET and NFET regions. The device includes a nanosheet stack 150 (see FIG. 2A), which will be described in further detail with reference to FIG. 1B. The semiconductor nanosheet device 100 shown in FIG. 1A also includes a dummy gate 202. This dummy gate 202 is later removed as further described below with reference to Figures 8A and 8B.

[0019] Referring now to FIG. 1B, this figure shows a cross-sectional view taken along line Y of the semiconductor nanosheet device 100 of FIG. 1A at an intermediate stage of the fabrication process. As described above with respect to FIG. 1A, the semiconductor nanosheet device 100 includes a silicon-based substrate 102 having a PFET region and an NFET region. In a specific embodiment, a multilayer nanosheet stack 150 (see also FIG. 2A) including a first-type sacrificial layer 106 is formed, followed by the formation of alternating layers of a second-type sacrificial layer 108 and an active semiconductor layer 110, followed by the formation of another first-type sacrificial layer 106. The first-type sacrificial layer 106 is formed directly on the top surface of the substrate 102. In one example, the first-type sacrificial layer 106 is composed of 65% silicon germanium (SiGe65). A second-type sacrificial layer 108 is then formed on top of the first-type sacrificial layer 106. In one example, the second-type sacrificial layer 108 is composed of 30% silicon-germanium (SiGe30). Next, an active semiconductor layer 110 is formed on top of the second-type sacrificial layer 108. In one example, the active semiconductor layer 110 is composed of silicon. Several additional layers of the second-type sacrificial layers 108 and the active semiconductor layers 110 are formed alternately. In the example shown in FIG. 1B, there are a total of four second-type sacrificial layers 108 and three active semiconductor layers 110 formed alternately. However, it should be understood that any suitable number of alternating layers may be formed. Another first-type sacrificial layer 106 is formed on top of the top second-type sacrificial layer 108.

[0020] The first-type sacrificial layer 106 is composed of a first semiconductor material, the second-type sacrificial layer 108 is composed of a second semiconductor material, and the active semiconductor layer 110 is composed of a third semiconductor material, where the first, second, and third semiconductor materials are different from one another. For example, the first-type sacrificial layer 106 is composed of 65% silicon-germanium (SiGe65), the second-type sacrificial layer 108 is composed of 30% silicon-germanium (SiGe30), and the active semiconductor layer 110 is composed of silicon (Si). While the silicon-germanium concentrations described in the above example are 30% and 65%, it should be understood that these concentrations may be other amounts as long as there is a sufficient difference to allow selective removal of the first-type sacrificial layer 106 without (i.e., selectively) removing the second-type sacrificial layer 108, as described in further detail below with respect to Figures 3A, 3B, and 3C.

[0021] In certain embodiments, the first-type sacrificial layer 106 and the second-type sacrificial layer 108 have vertical thicknesses ranging from, for example, about 3 nm to about 20 nm. In certain embodiments, the active semiconductor layer 110 has a vertical thickness ranging from, for example, about 3 nm to about 10 nm. While a total of nine layers are shown, it should be understood that the nanosheet stack 150 can include any suitable number of layers. While the 3-20 nm range is provided as an exemplary thickness range, other thicknesses for these layers may also be used.

[0022] In certain embodiments, it may be desirable to reduce the vertical spacing (VSP) between adjacent nanosheet layers in a nanosheet stack to reduce parasitic capacitance associated with HNS-FETs and improve circuit speed. For example, the VSP (the distance between the bottom surface of a first nanosheet layer and the top surface of an adjacent second nanosheet layer) may range from 5 nm to 15 nm. However, the VSP must be sufficient to accommodate the subsequently formed gate stack. The gate stack generally includes a work function metal (WFM) that sets the device threshold voltage (Vt), a high-κ gate dielectric material that separates the WFM from the nanosheets, and other metals that may be desired to further tune the effective work function (eWF) or achieve a desired resistance associated with current flow parallel to the plane of the nanosheets through the gate stack, or both.

[0023] In FIG. 1B, multiple epitaxial growth processes can be performed to form the first-type sacrificial layer 106, the second-type sacrificial layer 108, and the active semiconductor layer 110. To achieve the SiGe 65 first-type sacrificial layer 106 directly on the top surface of the substrate 102, for example, a SiGe 65 layer can be first epitaxially grown on the top surface of a Si substrate or on an initial silicon-on-insulator (SOI) layer (not shown), followed by SiGe precipitation. In this manner, a single initial SiGe 65 first-type sacrificial layer 106 is formed on the top surface of the substrate 102, as shown in FIG. 1B. After forming the initial SiGe 65 first-type sacrificial layer 106, a SiGe 30 second-type sacrificial layer 108 is formed on the top surface of the initial SiGe 65 first-type sacrificial layer 106. The first active semiconductor layer 110 is then epitaxially grown on the top surface of the initial second-type sacrificial layer 108. Additional epitaxial growth processes can then be performed to form a multilayer structure as a nanosheet stack 150 (see FIG. 2A) including an initial first-type sacrificial layer 106, followed by an alternating series of second-type sacrificial layers 108 and active semiconductor layers 110, followed by a final first-type sacrificial layer 106, as shown in FIG. 1B.

[0024] Referring again to FIG. 1B , following the formation of the nanosheet stack 150 (e.g., all of layers 106, 108, and 110), a hard mask cap 112 is formed for nanosheet patterning. The hard mask cap 112 can be composed of various nitride materials, including, but not limited to, silicon nitride (SiN). The semiconductor nanosheet device 100 is then subjected to a fin etching process to expose a portion of the substrate 102. The fin etching process can be accomplished, for example, using a lithography patterning process followed by a directional reactive ion etching (RIE) process, which can remove portions of the first-type sacrificial layer 106, the second-type sacrificial layer 108, and the active semiconductor layer 110 that are not covered by the hard mask cap 112. The RIE may use, for example, boron-based or chlorine-based chemistries to selectively recess exposed portions of the first-type sacrificial layer 106, the second-type sacrificial layer 108, and the active semiconductor layer 110 without attacking the substrate.

[0025] Following the nanosheet patterning process described above, the semiconductor nanosheet device 100 is subjected to shallow trench isolation (STI), also known as the box isolation technique. Generally, STI is an integrated circuit feature that prevents current leakage between adjacent semiconductor device components. STI is commonly used in CMOS process technology nodes of 250 nanometers and below. Generally, the STI process involves etching a pattern of trenches into a silicon substrate 102 and then depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches and form STI regions 104.

[0026] Referring now to FIG. 1C, this figure shows a cross-sectional view of the semiconductor nanosheet device 100 of FIG. 1B taken along line Y in FIG. 1A after an additional fabrication operation, according to an embodiment. As shown in FIG. 1C, an additional layer of second-type sacrificial layer 108 (e.g., SiGe 30) is conformally deposited along the sidewalls of the previously formed second-type sacrificial layer 108, the active semiconductor layer 110, and the final (i.e., top) first-type sacrificial layer 106. In a specific embodiment, the additional material of the second-type sacrificial layer 108 covers a portion of the top surface of the STI region 104. In a specific embodiment, anisotropic reactive ion etching (RIE) is performed to remove layer 108 from horizontal surfaces.

[0027] Referring now to Figure 1D, this figure shows a cross-sectional view of the semiconductor nanosheet device 100 of Figure 1C taken along line Y in Figure 1A after additional fabrication operations according to an embodiment. In particular, in Figure 1D, the hard mask cap 112 has been removed by any suitable method known to those skilled in the art. For example, a first directional RIE process or an isotropic wet etch such as hot phosphorus can be performed to remove the hard mask cap 112 and expose the underlying nanosheet stack 150.

[0028] 2A and 2B, these figures show cross-sectional views of the semiconductor nanosheet device 100 of FIG. 1D taken along lines X and Y, respectively, of FIG. 1A after additional fabrication operations according to an embodiment. In FIG. 2A, a dummy gate 202 is formed by any suitable deposition technique known to those skilled in the art. In one example, the dummy gate 202 is formed by depositing a thin SiO 2 layer followed by a layer of amorphous Si (a-Si). The dummy gate 202 is also shown in the top view of FIG. 1A. Following the deposition of the dummy gate 202, a hard mask layer 204 is formed. After forming the hard mask layer 204 pattern, lithographic patterning and etching are performed to remove the portion of the dummy gate 202 not covered by the hard mask layer 204. The removal of the dummy gate 202 is apparent in the cross-sectional view of FIG. 2A but not in FIG. 2B. The removal of portions of dummy gate 202 can also be seen in the top view of Figure 1A, where the X cut lines pass through three portions of dummy gate 202 and the Y cut lines show no portions of the dummy gate that were removed by the etching process, which will be removed later as discussed in more detail below.

[0029] 2C, which shows a cross-sectional view of the semiconductor nanosheet device of FIG. 1B taken along line Z in FIG. 1A after additional fabrication operations, according to an embodiment. In FIG. 2C, portions of the STI regions 104 have been recessed to expose sidewall portions of the underlying first-type sacrificial layer 106 (e.g., SiGe 65). Because a portion of the thickness of the STI regions 104 has been removed, underlying portions of the second-type sacrificial layer 108 (e.g., SiGe 30) are also exposed.

[0030] 3A, which shows a cross-sectional view of the semiconductor nanosheet device of FIG. 2A taken along line X in FIG. 1A after additional fabrication operations according to an embodiment. In particular, at this stage in the fabrication process, the first-type sacrificial layer 106 has been removed. Thus, as shown in FIG. 3A, a void space exists between the substrate 102 and the bottom second-type sacrificial layer 108, and a void also exists between the top second-type sacrificial layer 108 and the dummy gate 202.

[0031] 3B, which shows a cross-sectional view of the semiconductor nanosheet device 100 along line Y in FIG. 1A at the same fabrication stage as FIG. 3A. In this figure, after the first-type sacrificial layer 106 has been removed, there is also an air gap between the substrate 102 and the bottom second-type sacrificial layer 108, and there is also an air gap between the top second-type sacrificial layer 108 and the dummy gate 202. It should be understood that after the removal of the first-type sacrificial layer 106, the multilayer nanosheet stack 150 (see also FIG. 3A) is physically supported by the STI region 104 and the dummy gate 202 (i.e., despite the air gap created by the removal of the first-type sacrificial layer 106).

[0032] Referring now to Figure 3C, this figure shows a cross-sectional view of the semiconductor nanosheet device 100 along line Z in Figure 1A at the same fabrication stage as Figures 3A and 3B. As mentioned above, at this stage in the fabrication process, the first-type sacrificial layer 106 has been removed. Thus, as shown in Figure 3C, an air gap exists between the substrate 102 and the bottom second-type sacrificial layer 108, as well as between adjacent nanosheet stacks 150 (see also Figure 2A).

[0033] 4A, 4B, and 4C, which show cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 3A, 3B, and 3C taken along section lines X, Y, and Z in FIG. 1A, respectively, after additional fabrication operations according to an embodiment. In particular, spacers 402 have been formed (see also FIG. 1A). The spacers 402 have dual functions. In certain locations, the spacers 402 simply function as spacers to enable subsequent semiconductor processing steps. In other locations, the spacer 402 layer also functions as an insulating layer to prevent electrical contact between the semiconductor material of the second-type sacrificial layer 108 and the silicon material of the substrate 102. Before removing the first-type sacrificial layer 106, there was a problem in that the semiconductor material of the first-type sacrificial layer 106 directly contacted both the semiconductor material of the substrate 102 and the semiconductor material of the second-type sacrificial layer 108. The spacers 402 fill the previously created voids caused by the removal of the first-type sacrificial layer 106, thus preventing electrical contact between the gate electrode and nanosheet stack 150 and the substrate 102 by replacing the semiconductor material of the first-type sacrificial layer 106 with an insulating material (i.e., a dielectric material). In certain embodiments, the material of the spacers 402 is a dielectric material such as SiN, SiO, SiBCN, SiOCN, or SiCO. After conformal deposition of the spacer 402 liner, an anisotropic etch is performed to remove the spacers from the exposed horizontal surfaces.

[0034] 5A, 5B, and 5C, which show cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 4A, 4B, and 4C taken along section lines X, Y, and Z, respectively, in FIG. 1A after additional fabrication operations according to an embodiment. First, as shown in FIG. 5A, portions of the nanosheet stack 150 between the spacers 402 are etched away (i.e., recessed) to expose sidewalls of the nanosheet stack 150 that originally corresponded to the sidewalls of the spacers 402.

[0035] In a subsequent fabrication step, a portion of the second-type sacrificial layer 108 is selectively etched back, as shown in FIGS. 5A and 5C. In FIG. 5C, all of the second-type sacrificial layer 108 material has been removed at this location. In FIG. 5B, none of the second-type sacrificial layer 108 material has been removed at this location. However, as shown in FIG. 5A, only a portion of the second-type sacrificial layer 108 material has been removed, leaving an indentation in the second-type sacrificial layer 108. Therefore, as shown in FIG. 5A, the width of the second-type sacrificial layer 108 is smaller than the width of the active semiconductor layer 110. Therefore, a selective etch is performed to remove a portion of the SiGe 30 material of the second-type sacrificial layer 108 while preventing or minimizing removal of the Si material of the active semiconductor layer 110 shown in FIG. 5A and the amorphous Si (a-Si) of the dummy gate 202 shown in FIG. 5B. In one example, the selective etch is performed using HCl.

[0036] Referring now to FIGS. 6A, 6B, and 6C, these figures illustrate cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 5A, 5B, and 5C taken along section lines X, Y, and Z, respectively, of FIG. 1A after additional fabrication operations, according to an embodiment. In a first fabrication step, inner spacers 602 are formed to fill the recesses formed during the removal of the SiGe 30 material of the second-type sacrificial layer 108, as described above with respect to FIG. 5A. The inner spacers 602 are formed of a suitable dielectric material. In FIG. 6C, it can also be seen that the inner spacers 602 are formed to completely surround the active semiconductor layer 110. FIG. 6B remains unchanged with respect to FIG. 5B. In a particular embodiment, an isotropic etching process is performed on the sidewalls of the newly formed inner spacers 602 to remove the inner spacer liner everywhere except in the recessed region.

[0037] In a further manufacturing step, the semiconductor nanosheet device 100 is shown after an epitaxy process, as shown in FIG. 6A. Various well-known epitaxy processes can be used to grow highly conductive materials, such as Si, SiGe, or germanium (Ge), from the sides of the active semiconductor layer 110, the top surface of the spacer 402, and the sides of the inner spacer 602. The epitaxy process used to grow the S / D epitaxial structure 604 can be performed using various epitaxy techniques, including, but not limited to, vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or liquid phase epitaxy (LPE) using a gas or liquid precursor, such as silicon tetrachloride. The S / D epitaxial structure 604 can also be doped. For example, when fabricating a p-type semiconductor device (e.g., a PFET), the epitaxially grown material can be composed of a SiGe material doped with boron (B). When fabricating n-type semiconductor devices (eg, NFETs), the epitaxially grown material can consist of Si material doped with phosphorus (P) or arsenic (As).

[0038] 6A, the epitaxy process may be performed such that the top surface of the S / D epitaxial structure 604 is flush (i.e., coplanar) with the interface between the bottom surface of the dummy gate 202 and the spacer 402. In other embodiments, the top surface of the S / D epitaxial structure 604 may extend beyond the interface between the bottom surface of the dummy gate 202 and the spacer 402. In one or more embodiments, an annealing process may be performed to activate any dopants implanted in the S / D epitaxial structure 604.

[0039] 7A, 7B, and 7C, which illustrate cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 6A, 6B, and 6C taken along section lines X, Y, and Z, respectively, of FIG. 1A after additional fabrication operations according to an embodiment. As shown in FIG. 7A, an interlayer dielectric (ILD) layer 702 is deposited between the spacers 402 and on the S / D epitaxial structures 604. Following the formation of the ILD layer 702, poly-open chemical-mechanical polishing (POC) is utilized to planarize the semiconductor nanosheet device 100 and remove layers of specific materials. The POC removes all layers down to the level of the top surface of the dummy gate 202. In particular, as shown in FIGS. 7A and 7B, the hard mask 204 formed in FIG. 2A is removed by the POC process. As shown in FIGS. 7A and 7C, the POC process also removes the top of the spacers 402 down to the level of the top surface of the dummy gate 202.

[0040] 8A, 8B, and 8C, which show cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 7A, 7B, and 7C taken along section lines X, Y, and Z, respectively, of FIG. 1A after additional fabrication operations according to an embodiment. Specifically, FIGS. 8A and 8B show semiconductor nanosheet structures obtained by removing portions of the remaining dummy gate 202 from the semiconductor nanosheet device 100 shown in FIGS. 7A and 7B. In one embodiment, selective etching is performed to remove the dummy gate 202. For example, a wet chemical etchant highly selective for removing the dummy gate relative to other surrounding materials can be a hot ammonia or tetramethylammonium hydroxide (TMAH) wet etching process.

[0041] 9A, 9B, and 9C, which show cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 8A, 8B, and 8C taken along cut lines X, Y, and Z, respectively, in FIG. 1A after additional fabrication operations according to an embodiment. In these figures, an organic planarization layer (OPL) 902 is formed on top of the semiconductor nanosheet device 100. Following the formation of the organic planarization layer 902, a self-aligned gate cut patterning process is performed to remove the OPL material between adjacent nanosheet stacks 150, as shown in FIG. 9B. The OPL material is removed all the way down to the STI region 104. The OPL etching process is selective to other surrounding materials, such as SiN, SiGe, and SiO. Therefore, the opening between the PFET and NFET regions is defined purely by the initial separation between the two regions and is not dependent on the alignment or critical dimensions of the cut opening shown in FIG. 9B. Therefore, the gate cut position between the NFET and PFET is self-aligned and unaffected by lithography process variations. While FIG. 9B shows a slight angle at the cut portion of the OPL layer 902, it should be understood that this may be a vertical surface rather than an angled surface. In the example where the cut portion of the OPL layer 902 is angled, the cut portion has a larger circular diameter (CD) region at the top and a smaller CD region at the bottom. In certain embodiments, the CD region at the top may be misaligned, but the CD region at the bottom is always perfectly aligned and centered between the nanosheet stacks 150.

[0042] 10A, 10B, and 10C, which illustrate cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 9A, 9B, and 9C taken along cut lines X, Y, and Z, respectively, in FIG. 1A after additional fabrication operations according to an embodiment. As shown in FIG. 10B, a dielectric fill layer 1002 has been formed in the previously cut space between adjacent nanosheet stacks 150. This dielectric fill layer 1002 (i.e., a dielectric pillar) serves as a separation layer that enables the subsequent formation of separate PFET work function metal (PWFM) and NFET work function metal (NWFM) structures on the right and left sides of the pillar, as described in further detail below. As shown in FIG. 10B, the dielectric fill layer 1002 has a portion that extends to the top side of the spacer 402 (near the left PFET-side nanosheet stack), which is formed on the second-type sacrificial layer 108. This is due to slight misalignment during the cutting process described above with respect to Figures 10A, 10B, and 10C.

[0043] 11A, 11B, and 11C, which show cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 10A, 10B, and 10C taken along section lines X, Y, and Z, respectively, in FIG. 1A after additional fabrication operations according to an embodiment. As shown in FIGS. 11A, 11B, and 11C, the OPL layer 902 is an organic layer and can be removed, for example, by an ashing process using CO2. Next, the SiGe 30 material of the second-type sacrificial layer 108 is removed, for example, by a wet etching technique using HCl. Thus, all of the SiGe 30 material has been removed at this stage of the fabrication process. As shown in FIG. 11B, the left center corner of the dielectric fill layer 1002 contacts (or slightly overlaps) the upper corner of the spacer 402 on the PFET side of the semiconductor nanosheet device 100. 11B, there is a space between the dielectric fill layer 1002 and the active semiconductor layer 110 on the right and left sides of the lower portion of the dielectric fill layer 1002. There is also a space between the dielectric fill layer 1002 and the spacers 402 on the right and left sides of the lower portion of the dielectric fill layer 1002. This is because the sidewalls of the second type sacrificial layer 108 were previously formed, as shown and described with respect to FIG.

[0044] 12A, 12B, and 12C, which show cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 11A, 11B, and 11C taken along section lines X, Y, and Z, respectively, in FIG. 1A after additional fabrication operations according to an embodiment. First, a conformal high-κ dielectric layer 1202 is deposited around all exposed surfaces of the active semiconductor material layer 110, all exposed surfaces of the interior spacers 602, all exposed surfaces of the spacers 402, and the exposed surfaces of the STI regions 104. This is shown as a thick black line on these surfaces, as shown in FIGS. 12A and 12B. The conformal high-κ dielectric layer 1202 comprises a high-κ gate dielectric material. The term high-κ generally refers to a material with a high dielectric constant (κ, kappa) compared to silicon dioxide. High-κ dielectrics are used in semiconductor fabrication processes, typically to replace a silicon dioxide gate dielectric or another dielectric layer in a device. Thus, the term high-κ, as used herein, refers to materials with a dielectric constant, κ, that is much higher than that of silicon dioxide (e.g., hafnium oxide (HfO2) has a dielectric constant, κ, of 25, as opposed to 4 for silicon dioxide). Examples of suitable high-κ gate dielectric materials include, but are not limited to, HfO2 and / or lanthanum oxide (La2O3).

[0045] Second, as also shown in FIGS. 12A and 12B, a PFET work function metal 1204 (PWFM) is formed on the conformal high-κ dielectric layer 1202. In a specific embodiment, the deposition of the WFM layer may be performed by utilizing atomic layer deposition (ALD). Specifically, the PWFM layer 1204 is formed vertically in the interior space between the spacer 402 and the active semiconductor layer 110 and horizontally in the interior space between the interior spacers 602. Also, as shown in FIG. 12A, the PWFM layer 1204 is formed between the upper sidewalls of the spacer 402 above the active semiconductor layer 110. As shown in FIG. 12B, the PWFM layer 1204 is formed all around the surfaces of the active semiconductor layer 110 and the spacer 402. The PWFM layer 1204 is formed on both the PFET side and the NFET side of the semiconductor nanosheet device 100, but the PWFM on the NFET side is later removed to make way for the NWFM material.

[0046] For an n-channel field effect transistor (nFET), the WFM layer can include one or more WFM layers for nFETs, such as TiAlC, TiC, TiN / TiAlC, etc. For a p-channel field effect transistor (pFET), the WFM layer can include TiN, TaN, TiN / TiAlC, or any other suitable transition metal that allows for adjusting the Vt by varying the thickness of the WFM layer.

[0047] In a specific embodiment, the PWFM layer is recessed by a process known as WFM chamfering (or more generally, chamfering). As shown in FIG. 12A , the top of the PWFM layer 1204 formed between the spacers 402 is only formed to partially fill the space between the spacers. However, in the initial WFM chamfering process, the PWFM layer 1204 is formed on all of the sidewalls of the high-κ dielectric layer 1202 all the way to the top of the semiconductor nanosheet device 100 (not shown in FIG. 12A ). A sacrificial material, an organic planarization layer 1206 (OPL), is then formed (also not shown in FIG. 12A ) to fill all of the space between the high-κ dielectric layers 1202 all the way to the top of the semiconductor nanosheet device 100. The OPL layer 1206 is then recessed to the level shown in FIGS. 12A and 12B , leaving the PWFM layer 1204 still formed on all of the sidewalls all the way to the top of the semiconductor nanosheet device 100 (also not shown in FIG. 12A ). Finally, as shown in FIG. 12A, a portion of the PWFM layer 1204 is removed down to the level of the recessed OPL layer 1206 so that the top of the PWFM layer 1204 is approximately level with the top surface of the OPL layer 1206. The same WFM chamfering process is used on the PWFM layer 1204 and the OPL layer 1206 to result in the layering shown in FIG. 12B, where the top surfaces of the PWFM layer 1204 and the OPL layer 1206 partially overlie the sides of the high-κ dielectric layer 1202 and the dielectric fill layer 1002. The cross-sectional view of FIG. 12C is unchanged with respect to FIG. 11C.

[0048] 13A, 13B, and 13C, these figures show cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 12A, 12B, and 12C taken along section lines X, Y, and Z, respectively, of FIG. 1A after additional fabrication operations according to an embodiment. First, as shown in FIGS. 13A and 13B, the previous OPL used for WFM chamfering is removed, and additional OPL material 1206 is deposited to a level above the top surfaces of the high-κ dielectric layer 1202, the interlayer dielectric layer 702, and the spacers 402. Second, as shown in FIG. 13B, a portion of the OPL layer 1206 is subjected to WFM patterning and reactive ion etching (RIE) to remove the portion of the OPL layer 1206 on the NFET side of the semiconductor nanosheet device 100. Removal of these portions of the OPL layer 1206 exposes the PWFM layer 1204 on the NFET side of the device, as well as the right-hand and top portions of the dielectric fill layer 1002 pillars and the high-κ dielectric layer 1202 covering the dielectric fill layer 1002. The temporary remaining OPL layer 1206 protects the PWFM layer 1204 on the PFET side of the semiconductor nanosheet device from removal in subsequent processing steps, while simultaneously allowing the PWFM layer 1204 on the NFET side of the device 100 to be removed. The pillars of the dielectric fill layer 1002 also protect the PWFM layer 1204 on the PFET side of the semiconductor nanosheet device 100 from removal in subsequent processing steps, as described in further detail below. The cross-sectional view of FIG. 13C is unchanged with respect to FIG. 12C.

[0049] 14A, 14B, and 14C, which show cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 13A, 13B, and 13C taken along section lines X, Y, and Z, respectively, of FIG. 1A after additional fabrication operations according to embodiments. First, as shown in FIG. 14B, the PWFM layer 1204 is removed from the NFET side (i.e., the right side of FIG. 14B) of the semiconductor nanosheet device 100 by an isotropic etching process. In these embodiments, the presence of the dielectric fill layer 1002 pillars ensures that any portion of the PWFM layer 1204 on the PFET side of the semiconductor nanosheet device 100 is not undercut by the etching process. In other words, without the dielectric fill layer 1002, there is a possibility of undercutting (i.e., removal) of the lateral edge portions of the PWFM layer 1204 that would otherwise be exposed on the PFET side of the device. Thus, the dielectric fill layer 1002 protects the PFET-side PWFM layer 1204 during this stage of the device's fabrication. Figures 14A and 14C are unchanged with respect to Figures 13A and 13C.

[0050] 15A, 15B, and 15C, which show cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 14A, 14B, and 14C taken along section lines X, Y, and Z, respectively, of FIG. 1A after additional fabrication operations according to an embodiment. Although not shown in FIGS. 15A and 15B, the previously formed PWFM layer 1204 is first peeled off to allow for the formation of a negative work function metal (NWFM) layer 1508, described below. As shown in FIG. 15B, the NWFM layer 1508 is formed on the conformal high-κ dielectric layer 1202 on the NFET side of the semiconductor nanosheet device 100. Specifically, the NWFM layer 1508 is formed vertically in the interior space between the spacer 402 and the active semiconductor layer 110, and horizontally in the interior space between the interior spacers 602. Thus, the NWFM layer 1508 is formed on the NFET side of the semiconductor nanosheet device 100 in a manner similar to how the PWFM layer 1204 was previously formed on this same side of the device. However, the PWFM layer 1204 on the PFET side of the device is unaffected by the formation of this NWFM layer 1508 due to the presence of the dielectric fill layer 1002. As shown in FIG. 15B, the NWFM layer 1508 is formed all around the surfaces of the active semiconductor layer 110 and the spacer 402. Also, as shown in FIG. 15A, the NWFM layer 1508 is formed between the sidewalls of the top of the spacer 402 above the active semiconductor layer 110.

[0051] In a specific embodiment, the NWFM layer 1508 is formed by WFM chamfering, similar to the formation of the PWFM layer 1204 described above. As shown in FIG. 15A , the top of the NWFM layer 1508 formed between the spacers 402 is formed so as to only partially fill the space between the spacers. However, in the initial WFM chamfering process, the NWFM layer 1508 is formed on all of the sidewalls of the high-κ dielectric layer 1202 all the way to the top of the semiconductor nanosheet device 100 (not shown in FIG. 15A ). A sacrificial material, an organic planarization layer 1510 (OPL), is then formed (also not shown in FIG. 15A ) to fill all of the space between the high-κ dielectric layers 1202 all the way to the top of the semiconductor nanosheet device 100. The OPL layer 1510 is then recessed to the level shown in FIGS. 15A and 15B , leaving the NWFM layer 1508 still formed on all of the sidewalls all the way to the top of the semiconductor nanosheet device 100 (also not shown in FIG. 15A ). Finally, as shown in Figures 15A and 15B, a portion of NWFM layer 1508 is removed down to the level of recessed OPL layer 1510, so that the top of NWFM layer 1508 is approximately level with the top surface of OPL layer 1510. Using this WFM chamfering process on NWFM layer 1508 and OPL layer 1510 results in the layered structure shown in Figures 15A and 15B. In Figure 15B, the top surfaces of NWFM layer 1508 and OPL layer 1510 partially overlie the sides of high-κ dielectric layer 1202 and dielectric fill layer 1002. The cross-sectional view in Figure 15C is unchanged with respect to Figure 14C.

[0052] 16A, 16B, and 16C, which show cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 15A, 15B, and 15C taken along section lines X, Y, and Z in FIG. 1A, respectively, after additional fabrication operations according to an embodiment. First, the OPL layer 1510 formed in FIGS. 15A and 15B is removed. Then, a metal layer 1602 is deposited. In a specific example, the metal layer 1602 is composed of tungsten (W). However, it should be understood that other suitable metals or metal alloys may be used for the metal layer 1602. Although not shown in FIGS. 16A and 16B, the metal layer 1602 is first deposited at or above the level of the top surface of the interlayer dielectric (ILD) layer 702. The semiconductor nanosheet device 100 is then subjected to a CMP process to remove the upper portion of the metal layer 1602 down to the level of the top surface of the interlayer dielectric (ILD) layer 702 (this intermediate step is also not shown in FIGS. 16A and 16B ). The metal layer 1602 is then recessed to a level below the top surface of the interlayer dielectric (ILD) layer 702, as shown in FIGS. 16A and 16B . In the same process, or at a later stage, the upper portion of the high-κ dielectric layer 1202 is also removed down to the same level as the top surface of the metal layer 1602, as shown in FIG. 16A . Finally, a self-aligned contact (SAC) cap layer (shown as an extension of the spacer 402) is formed over the metal layer 1602 and the existing spacer 402. In certain embodiments, the SAC cap layer is composed of the same material as the spacer layer 402 and can simply be considered an extension of that layer. For example, this SAC cap layer may be composed of SiN, the same material described above with respect to Figures 4A, 4B, and 4C and the formation of spacers 402. This SAC cap is useful for protecting the gate when ILD layer 702 is later removed in subsequent processing steps.

[0053] As explained in detail above, there are several structural features shown in FIG. 16B that enable an improved interface between the NFET and PFET (N-2-P) of the semiconductor nanosheet device 100. For example, as shown in FIG. 16B, the PWFM layer 1204 not only includes material between the active semiconductor layers 110, but also includes material on the sidewalls of the active semiconductor layers 110. This also applies to the NWFM layer 1508, as shown in FIG. 16B. In another example, as shown in FIG. 16B, a dielectric fill layer 1002 (i.e., a dielectric pillar) is formed between the sidewalls of the PWFM layer 1204 and the sidewalls of the NWFM layer 1508, which helps to create a blocking feature between the PWFM layer 1204 and the NWFM layer 1508 during device formation. This dielectric fill layer 1002 has a smaller bottom CD at the bottom and is formed in a self-aligned manner so that it is always perfectly aligned in the center between the nanosheet stacks 150. Another structural feature is that the inner spacers 602 are formed to completely surround the active semiconductor layer 110, as described above with respect to FIG. 6C.

[0054] In another embodiment, referring now to Figures 17A, 17B, and 17C, these figures show cross-sectional views of the semiconductor nanosheet device 100 of Figures 15A, 15B, and 15C taken along section lines X, Y, and Z of Figure 1A, respectively, after additional fabrication operations according to embodiments. In these embodiments, the processing steps are generally the same as those described above with respect to Figures 1A-15C, except for different processing steps with respect to the formation of the dielectric fill layer 1002 and the metal layer 1802 (see Figure 18B). Notably, in certain of these embodiments, as shown in Figure 17B, the dielectric fill layer 1002 pillars are recessed prior to the formation of the metal layer 1802 (see Figure 18B). Figures 17A and 17C are unchanged from Figures 15A and 15C.

[0055] 18A, 18B, and 18C, which show cross-sectional views of the semiconductor nanosheet device 100 of FIGS. 17A, 17B, and 17C taken along section lines X, Y, and Z, respectively, of FIG. 1A after additional fabrication operations according to an embodiment. In particular, as shown in FIG. 18B, due to the previously recessed dielectric fill layer 1002 pillars, a metal layer 1802 is formed across from the PFET side of the semiconductor nanosheet device 100 to the NFET side of the device, within the previously formed recess in the dielectric fill layer 1002. This metal layer 1802 enables a shared gate structure through the top and bottom of the gate, which can assist in the patterning of the PWFM layer 1204 and the NWFM layer 1508. Thus, the metal layer 1802 is a shared gate structure that allows for gate sharing at the device level rather than the contact level. The shared metal layer 1802 can also have the effect of reducing parasitic capacitance between the gate and the rest of the device compared to the embodiment described above with respect to Figures 15A-15C.

[0056] The description of various embodiments is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method for forming a nanosheet field effect transistor (FET) device, comprising: forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of a first type of sacrificial layer and an active semiconductor layer; forming a sidewall portion of the first type sacrificial layer on a sidewall of the nanosheet stack; forming dielectric pillars between the sidewall portions of the first type sacrificial layer of adjacent nanosheet stacks; removing the first type sacrificial layer; forming a p-type work function PWFM layer in a space formed by the removal of the first type sacrificial layer for a first one of the nanosheet stacks; forming an n-type work function NWFM layer in a space formed by the removal of the first type sacrificial layer for an adjacent second one of the nanosheet stacks; the dielectric pillars prevent the material of the NWFM layer from contacting the material of the PWFM layer during formation of the NWFM layer; method.

2. 2. The method of claim 1, further comprising forming a lower second-type sacrificial layer between the substrate and a lower surface of the nanosheet stack, and forming an upper second-type sacrificial layer on an upper surface of the nanosheet stack, wherein the sidewall portions of the first-type sacrificial layer are also formed on the sidewalls of the upper second-type sacrificial layer.

3. removing the upper and lower second-type sacrificial layers after forming the sidewall portions of the first-type sacrificial layer; forming a dielectric spacer layer in the space formed by said removal of said second type sacrificial layer; The method of claim 2 further comprising:

4. forming an organic planarization layer (OPL) on the nanosheet stack; removing portions of the OPL between adjacent nanosheet stacks to expose vertical sides of the sidewall portions of the first type sacrificial layer; forming the dielectric pillar in a space formed by the removal of the portion of the OPL; The method of claim 1 further comprising:

5. 5. The method of claim 4, wherein removing the portion of the OPL also exposes the top surfaces of the sidewall portions of the first type sacrificial layer of a first nanosheet stack of the nanosheet stacks, and the dielectric pillars are formed to also cover the top surfaces of the sidewall portions of the first type sacrificial layer.

6. the PWFM layer is first formed in the space formed by the removal of the second type sacrificial layer for both the first and second nanosheet stacks; forming an organic planarization layer (OPL) on a portion of the top surface of the first nanosheet stack and the dielectric pillar; removing the PWFM layer from the second nanosheet stack to reopen the space formed by the removal of the second type of sacrificial layer; forming the NWFM layer in the space formed by the removal of the second type sacrificial layer and by subsequent removal of the PWFM layer of the second nanosheet stack; The method of claim 1 further comprising:

7. 7. The method of claim 6, wherein the dielectric pillars are barriers to prevent undercutting of the PWFM layer from the first nanosheet stack during removal of the PWFM layer from the second nanosheet stack.

8. The method of claim 1 , further comprising forming a metal layer on the PWFM layer and the NWFM layer.

9. The method of claim 8 , further comprising forming a self-aligned contact (SAC) cap on the metal layer.

10. 3. The method of claim 2, wherein the first type sacrificial layer is comprised of a first percentage of SiGe material and the second type sacrificial layer is comprised of a second percentage of SiGe material, the second percentage being higher than the first percentage.

11. A substrate; a plurality of nanosheet stacks formed on the substrate, wherein a first one of the nanosheet stacks comprises alternating layers of PWFM layers and active semiconductor layers with a p-type work function, and an adjacent second one of the nanosheet stacks comprises alternating layers of NWFM layers and the active semiconductor layers with an n-type work function, and sidewall portions of the PWFM layers and sidewall portions of the NWFM layers are formed on sidewalls of each of the nanosheet stacks; a dielectric pillar formed between the sidewall portion of the PWFM layer and the sidewall portion of the NWFM layer of the adjacent nanosheet stack, the dielectric pillar extending from the substrate to a level above a top surface of the nanosheet stack; a portion of the dielectric pillar formed on an upper surface of the sidewall portion of the PWFM layer.

12. The nanosheet FET device of claim 11 , further comprising a first dielectric spacer layer formed between the substrate and the PWFM layer of the first nanosheet stack and also formed between the substrate and the NWFM layer of the second nanosheet stack.

13. 13. The nanosheet FET device of claim 12, further comprising a second dielectric spacer layer formed above the top active semiconductor layer of the first nanosheet stack and the top active semiconductor layer of the second nanosheet stack.

14. 14. The nanosheet FET device of claim 13, wherein a portion of the dielectric pillar directly contacts a portion of the second dielectric spacer layer of the first nanosheet stack.

15. 15. The nanosheet FET device of claim 14, further comprising a high-κ layer formed between outer surfaces of the layers of the first and second nanosheet stacks.

16. 12. The nanosheet FET device of claim 11, further comprising a metal layer formed on the PWFM layer and the NWFM layer.

17. 17. The nanosheet FET device of claim 16, further comprising a self-aligned contact (SAC) cap formed on said metal layer.

18. The nanosheet FET device of claim 11 , wherein the dielectric pillar has a larger diameter at the top than at the bottom.

19. A computer program comprising program code adapted to perform the method according to any one of claims 1 to 10 when the computer program is run on a computer.

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