Method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device with less variation in transistor characteristics.SOLUTION: A transistor 200 includes: an insulator 216 on an insulator 214; a conductor 205 arranged so as to be embedded in the insulator 214 or the insulator 216; an insulator 222 on the insulator 216 and the conductor 205; an insulator 224 on the insulator 222; an oxide 230a on the insulator 224; an oxide 230b on the oxide 230a; oxides 241 (an oxide 241a and an oxide 241b) and an oxide 230c on the oxide 230b; an oxide 230d on the oxide 230c; a conductor 240a on the oxide 241a; an insulator 271a on the conductor 240a: a conductor 240b on the oxide 241b; an insulator 271b on the conductor 240b; an insulator 250 on the oxide 230d; and a conductor 260 located on the insulator 250 and overlapping with parts of the oxide 230c and the oxide 230d.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] 1. Field of the Invention

[0003] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] Technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0005] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0006] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention involves forming a first insulator, forming an island-shaped stack by sequentially stacking a first oxide, a second oxide, and a first conductor on the first insulator, forming a second insulator on the first insulator and the stack, forming an opening in the second insulator to expose the stack, removing the area exposed in the opening of the first conductor to expose the top surface of the second oxide, and forming a second conductor and a third conductor disposed on the second oxide, and then performing a cleaning process to remove the side surface of the first oxide exposed in the opening and the A first oxide film is formed in contact with the upper and side surfaces of the second oxide and the fourth conductor, and oxygen is added near the interface between the second oxide and the first oxide film through the first oxide film. After that, a heat treatment is performed to form a first insulating film and a first conductive film on the first oxide film. After that, a chemical polishing treatment is performed to remove a portion of the first conductive film, the first insulating film, the first oxide film, and the second insulator, thereby exposing the second insulator, and a fourth conductor, a third insulator, and a third oxide are formed in the opening provided in the second insulator.

[0011] One embodiment of the present invention is a method for forming a first insulator, forming an island-shaped stack by sequentially stacking a first oxide, a second oxide, and a first conductor on the first insulator, forming a second insulator on the first insulator and the stack, forming an opening in the second insulator to expose the stack, removing the region exposed in the opening of the first conductor to expose the top surface of the second oxide, and forming a second conductor and a third conductor disposed on the second oxide, and then performing a cleaning process to remove contacts with the side surfaces of the first oxide exposed in the opening and the top and side surfaces of the second oxide. Then, a first oxide film is formed, a process of adding oxygen through the first oxide film to the vicinity of the interface between the second oxide film and the first oxide film is performed, a second oxide film is formed on the first oxide film, a heat treatment is performed, a first insulating film and a first conductive film are formed on the second oxide film, and then a chemical polishing process is performed to remove a portion of the first conductive film, the second oxide film, the first insulating film, the first oxide film and the second insulator, thereby exposing the second insulator, and a fourth conductor, a third insulator, a third oxide and a fourth oxide are formed in the opening provided in the second insulator.

[0012] In the above, the oxygen addition treatment is preferably performed by ion implantation.

[0013] In the above, in claim 1 or claim 2, it is preferable that in the ion implantation method, oxygen ions are incident in the short side direction of the second oxide at an angle θ (45°<θ<135°) with respect to a tangent to the upper surface of the second oxide.

[0014] In the above, the heat treatment is preferably carried out at a temperature of 350°C or higher and 400°C or lower.

[0015] In the above, the heat treatment is preferably carried out in an atmosphere containing 1% or more, or 10% or more, of an oxidizing gas.

[0016] In the above, the first oxide and the third oxide preferably suppress oxygen diffusion more than the second oxide. [Effects of the Invention]

[0017] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0019] [Figure 1] 1A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 1B and 1C are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 2] 2A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 2B and 2C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 3] 3A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 3B and 3C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] 4A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 4B and 4C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5]5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 5B and 5C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 6B and 6C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 7B and 7C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B and 8C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 9B and 9C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B and 10C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B and 11C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A, 12B, and 12C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B and 13C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14]Figure 14A is a diagram explaining the classification of IGZO crystal structures. Figure 14B is a diagram explaining the XRD spectrum of silica glass. Figure 14C is a diagram explaining the XRD spectrum of crystalline IGZO. Figure 14D is a diagram explaining the micro-electron diffraction pattern of crystalline IGZO. [Figure 15] 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B and 15C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A and 16B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 17B and 17C are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 18] 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 18B and 18C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 19B and 19C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 20B and 20C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 21B and 21C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] 22A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 22B and 22C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] 23A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 23B and 23C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] 24A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 24B and 24C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 25] 25A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 25B and 25C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 26] 26A, 26B, and 26C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 27] 27A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 27B and 27C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 28] 28A and 28B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 30] FIG. 30 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 31] FIG. 31 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 32] FIG. 32 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 33] FIG. 33 is a top view illustrating an apparatus for manufacturing a semiconductor device of one embodiment of the present invention. [Figure 34] 34A and 34B are a block diagram and a perspective view illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 35] 35A to 35H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 36] FIG. 36 is a diagram showing various storage devices by hierarchy. [Figure 37] 37A and 37B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 38] 38A and 38B are diagrams illustrating an example of an electronic component. [Figure 39] 39A to 39E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 40] 40A to 40H are diagrams showing electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0021] In addition, in the drawings, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are merely a schematic representation of one embodiment of the present invention and are not limited to the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may be unintentionally thinned by etching or other processes, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals may be used in common between different drawings for identical parts or parts having similar functions, and repeated explanations may be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0022] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0023] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0024] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0025] For example, if it is explicitly stated in this specification that X and Y are connected, it is assumed that the specification also discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is assumed that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0026] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0027] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0028] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0029] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width refers to any one value, maximum value, minimum value, or average value in the channel formation region.

[0030] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0031] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0032] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0033] Note that impurities in semiconductors refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. O :oxygen vacancy) may be formed.

[0034] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0035] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0036] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0037] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0038] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0039] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0040] <Configuration Example 1 of Semiconductor Device> The structure of a semiconductor device including a transistor 200 will be described with reference to FIG. 1. FIGS. 1A to 1C are top views and cross-sectional views of a semiconductor device including a transistor 200. FIG. 1A is a top view of the semiconductor device. FIGS. 1B to 1C are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0041] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, and an insulator 283 over the insulator 282. The insulators 212, 214, 280, 282, and 283 function as interlayer films.

[0042] The transistor 200 also includes a conductor 246 (conductor 246a and conductor 246b) that is electrically connected to the transistor 200 and functions as a plug. Note that an insulator 276 (insulator 276a and insulator 276b) is provided in contact with the side surface of the conductor 246 that functions as a plug. Further, a conductor 248 (conductor 248a and conductor 248b) that is electrically connected to the conductor 246 and functions as a wiring is provided on the insulator 283 and the conductor 246. Further, an insulator 286 is provided on the conductor 248 and the insulator 283.

[0043] Specifically, insulator 276a is provided in contact with the inner walls of the openings of insulators 280, 282, and 283, a first conductor of conductor 246a is provided in contact with the side surface of insulator 276a, and a second conductor of conductor 246a is provided further inward. Also, insulator 276b is provided in contact with the inner walls of the openings of insulators 280, 282, and 283, a first conductor of conductor 246b is provided in contact with the side surface of insulator 276b, and a second conductor of conductor 246b is provided further inward.

[0044] 1B, the height of the top surface of the conductor 246 can be made approximately the same as the height of the top surface of the insulator 283 in the region overlapping with the conductor 248. Note that, although the transistor 200 shows a structure in which the first conductor of the conductor 246 and the second conductor of the conductor 246 are stacked, the present invention is not limited to this. For example, the conductor 246 may be configured as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, ordinal numbers may be assigned to indicate the order of formation to distinguish them.

[0045] [Transistor 200] As shown in FIGS. 1A to 1C, the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide 230b on the oxide 230b. The oxide 230c includes oxides 241a and 241b, a conductor 240a on the oxide 241a, an insulator 271a on the conductor 240a, a conductor 240b on the oxide 241b, an insulator 271b on the conductor 240b, an insulator 250 on the oxide 230c, and a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping with a part of the oxide 230c. The oxide 230c is in contact with the side surfaces of the oxide 241a, the oxide 241b, the conductors 240a and 240b, the insulators 271a and 271b, respectively.

[0046] 1B and 1C, the upper surface of the conductor 260 is disposed so as to be substantially coincident with the upper surface of the insulator 250 and the upper surface of the oxide 230c. The insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, the oxide 230c, and the insulator 280.

[0047] In the following description, the insulators 271a and 271b may be collectively referred to as the insulator 271.

[0048] An opening reaching the oxide 230b is provided in the insulator 280. The oxide 230c, the insulator 250, and the conductor 260 are disposed in the opening. In addition, in the channel length direction of the transistor 200, the conductor 260, the insulator 250, and the oxide 230c are provided between the conductor 240a and the oxide 241a and between the conductor 240b and the oxide 241b. The insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. In addition, in the region overlapping with the oxide 230b, the oxide 230c has a region in contact with the oxide 230b, a region overlapping with the side surface of the conductor 260 with the insulator 250 interposed therebetween, and a region overlapping with the bottom surface of the conductor 260 with the insulator 250 interposed therebetween.

[0049] Preferably, oxide 230 comprises oxide 230a disposed on insulator 224, oxide 230b disposed on oxide 230a, and oxide 230c disposed on oxide 230b and at least partially in contact with oxide 230b.

[0050] Note that in the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region.

[0051] A transistor using an oxide semiconductor for a channel formation region has extremely low leakage current in a non-conducting state, and therefore can provide a semiconductor device with low power consumption. On the other hand, the electrical characteristics of a transistor using an oxide semiconductor tend to change due to impurities and oxygen vacancies in the oxide semiconductor, and the transistor tends to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode).

[0052] Therefore, it is preferable to use a high-purity intrinsic oxide semiconductor in which impurities and oxygen vacancies are reduced as the oxide semiconductor used for the channel formation region of a transistor. Note that in this specification and the like, a high-purity intrinsic oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic oxide semiconductor or a substantially high-purity intrinsic oxide semiconductor.

[0053] However, in a transistor including an oxide semiconductor, oxygen in the oxide semiconductor is gradually absorbed by a conductor included in the transistor or a conductor used in a plug or a wiring connected to the transistor, and oxygen vacancies may occur as a type of change over time.

[0054] Therefore, after oxide 230b is made substantially intrinsic with high purity, it is preferable to cover the region of oxide 230b where the channel is to be formed with oxide 230a and oxide 230c, which suppress oxygen diffusion more than oxide 230b.

[0055] Specifically, as shown in the figure, by disposing the oxide 230a below the oxide 230b, it is possible to prevent oxygen from being extracted from the oxide 230b, and it is also possible to prevent oxygen and impurities from diffusing into the oxide 230b from structures formed below the oxide 230a.

[0056] Furthermore, by disposing the oxide 230c on the oxide 230b, it is possible to suppress the extraction of oxygen from the oxide 230b, and it is also possible to suppress the diffusion of impurities into the oxide 230b from structures formed above the oxide 230c.

[0057] Note that the metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0058] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0059] Here, it is preferable that the oxide 230 has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, it is preferable that the atomic ratio of In to the element M in the metal oxide used for the oxide 230b is larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a or the oxide 230c.

[0060] That is, in the metal oxides used for oxide 230a and oxide 230c, the atomic ratio of element M to other metal elements that are the main components is preferably greater than the atomic ratio of element M to other metal elements that are the main components in the metal oxide used for oxide 230b. Also, in the metal oxide used for oxide 230a, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Also, in the metal oxide used for oxide 230b, the atomic ratio of In to element M is preferably greater than the atomic ratio of In to element M in the metal oxides used for oxide 230a and oxide 230c.

[0061] The oxide 230a and the oxide 230c have a common element other than oxygen (as a main component), which reduces the defect state density at the interfaces between the oxide 230a, the oxide 230b, and the oxide 230c. In this case, the main carrier path is the oxide 230b or its vicinity, for example, the interface between the oxide 230b and the oxide 230c. Because the defect state density at the interface between the oxide 230b and the oxide 230c can be reduced, the effect of interface scattering on carrier conduction is reduced, resulting in a high on-current.

[0062] For example, as the oxide 230b, specifically, a metal oxide or indium oxide having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto, or In:M:Zn=10:1:3 [atomic ratio] or a composition close thereto may be used.

[0063] The oxide 230b preferably has crystallinity, and it is particularly preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) for the oxide 230b.

[0064] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0065] Nanocrystals are basically hexagonal, but not necessarily regular hexagons; they can also have non-regular hexagonal shapes. Furthermore, the lattice arrangement of CAAC-OS can be pentagonal, heptagonal, or other shapes due to distortion. It is difficult to identify clear grain boundaries in CAAC-OS, even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distance caused by substitution of metal elements.

[0066] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially reducing the on-state current or field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0067] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, it can also be expressed as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, it can also be expressed as an (In,M) layer.

[0068] As described above, the CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (such as oxygen vacancies V). In particular, after the formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure by being subjected to heat treatment at a temperature (e.g., 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0069] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0070] Furthermore, the region of the oxide 230b where the channel is formed may have a smaller cross-sectional area in the W width direction than the region of the oxide 230b that functions as the source region or drain region. That is, in the processing step of forming an opening in the insulator 280 or in a cleaning step after the processing step, a part of the surface of the oxide 230b exposed at the bottom of the opening may be removed, and a groove (hereinafter also referred to as a counterbore) may be formed in the oxide 230b.

[0071] In addition, it is preferable to fill the grooves of the oxide 230b with oxide 230c. At this time, the oxide 230c is arranged so as to cover the inner walls (side walls and bottom surface) of the grooves. The film thickness of the oxide 230c may be approximately the same as the depth of the grooves.

[0072] With this structure, even if a damaged region is formed on the surface of the oxide 230b at the bottom of the opening when forming the opening for burying the conductor 260 or the like, the damaged region can be compensated for, thereby suppressing poor electrical characteristics of the transistor 200 due to the damaged region.

[0073] 1B, the side of the opening into which the conductor 260 and the like are embedded, including the groove portion of the oxide 230b, is approximately perpendicular to the surface on which the oxide 230b is to be formed, but this embodiment is not limited to this. For example, the bottom of the opening may be U-shaped, with a gently curved surface. Also, for example, the side of the opening may be inclined relative to the surface on which the oxide 230b is to be formed.

[0074] 1C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0075] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 240, or smaller than half the length of the region of the oxide 230b that does not have the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. This shape improves the coverage of the groove with the insulator 250 and conductor 260 formed in a later process. Furthermore, it is possible to prevent a decrease in the length of the region that does not have the curved surface, thereby suppressing a decrease in the on-current and mobility of the transistor 200. Therefore, a semiconductor device with excellent electrical characteristics can be provided.

[0076] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulator 250 functions as a first gate insulator, and the insulator 224 functions as a second gate insulator. The conductor 240a functions as one of a source electrode and a drain electrode, and the conductor 240b functions as the other of the source electrode and the drain electrode. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0077] Note that the conductor 260 and the insulator 250 may be shared between adjacent transistors 200. That is, the conductor 260 of one transistor 200 has a region provided continuously with the conductor 260 of another transistor 200 adjacent to the transistor 200. Furthermore, the insulator 250 of one transistor 200 has a region provided continuously with the insulator 250 of another transistor 200 adjacent to the transistor 200.

[0078] It is preferable that insulators 212, 214, 271, insulator 282, insulator 283, and insulator 286 function as barrier insulating films that prevent impurities such as water and hydrogen from diffusing into transistor 200 from the substrate side or from above transistor 200.

[0079] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0080] Therefore, it is preferable that the insulators 212, 214, 271, 282, 283, and 286 be made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. (the impurities are less likely to permeate through them). Alternatively, it is preferable that the insulators 212, 214, 271, 282, 283, and 286 be made of an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate through them).

[0081] For example, it is preferable to use silicon nitride or the like for the insulators 212, 283, and 286, and aluminum oxide or the like for the insulators 214, 271, and 282. This can prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 through the insulators 212 and 214. Alternatively, it can prevent oxygen contained in the insulator 224 or the like from diffusing to the substrate side through the insulators 212 and 214. It can also prevent impurities such as water and hydrogen from diffusing from the insulator 280, the conductor 248, or the like to the oxide 230. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 282, and 283, which have the function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0082] It may also be preferable to reduce the resistivity of the insulators 212, 283, and 286. For example, it may be preferable to reduce the resistivity of the insulators 212, 283, and 286 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulator 212, the insulator 283, and the insulator 286 may be able to reduce charge-up of the conductor 205, the conductor 240, the conductor 260, or the conductor 248 during treatment using plasma or the like in the semiconductor device manufacturing process. The resistivity of the insulator 212, the insulator 283, and the insulator 286 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0083] Furthermore, the insulators 216 and 280 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 216 and 280 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0084] The insulators 212, 214, and 216 are preferably formed by sputtering. The insulators 212, 214, and 216 formed by sputtering preferably have a low hydrogen concentration. The insulators 212, 214, and 216 are preferably formed successively without exposure to the atmospheric environment. Forming the insulators 212, 214, and 216 without exposure to the atmospheric environment is preferable because it prevents impurities or moisture from the atmospheric environment from adhering to the insulators 212, 214, and 216, and therefore the interface and the vicinity of the interface between the insulators 212 and 214, and the interface and the vicinity of the interface between the insulators 214 and 216 can be kept clean.

[0085] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to not applying a negative potential to the conductor 205.

[0086] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 214 or the insulator 216.

[0087] As shown in FIG. 1A, the conductor 205 is preferably larger than the area of ​​the oxide 230a and the oxide 230b that does not overlap with the conductor 240a and the conductor 240b. In particular, as shown in FIG. 1C, the conductor 205 preferably extends to areas outside the ends of the oxide 230a and the oxide 230b that intersect with the channel width direction. That is, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator outside the side surfaces of the oxide 230a and the oxide 230b in the channel width direction. This structure allows the channel formation region of the oxide 230 to be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0088] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0089] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0090] Note that, in the transistor 200, the conductor 205 has a stacked structure of the conductor 205a and the conductor 205b, but the present invention is not limited to this. For example, the conductor 205 may have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, it may be distinguished by assigning an ordinal number to the order of formation.

[0091] Here, the conductor 205a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0092] By using a conductive material capable of suppressing oxygen diffusion for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials capable of suppressing oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be a multilayer of tantalum, tantalum nitride, ruthenium, or ruthenium oxide with titanium or titanium nitride.

[0093] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 205b is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the conductive material.

[0094] Insulator 222 and insulator 224 function as gate insulators.

[0095] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0096] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 or the oxygen contained in the oxide 230.

[0097] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0098] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate voltage during transistor operation while maintaining the physical film thickness.

[0099] The insulator 224 preferably has a lower dielectric constant than the insulator 222. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as the insulator 216 and the insulator 280 as appropriate.

[0100] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structures are not limited to those made of the same material, and may be those made of different materials.

[0101] Oxide 241 (oxide 241a and oxide 241b) may be provided on oxide 230b.

[0102] The oxide 241 (oxide 241a and oxide 241b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 241, which has a function of suppressing oxygen permeation, between the conductor 240, which functions as a source electrode or a drain electrode, and the oxide 230b, the electrical resistance between the conductor 240 and the oxide 230b is reduced, which is preferable. This structure can improve the electrical characteristics and reliability of the transistor 200. Note that if the electrical resistance between the conductor 240 and the oxide 230b can be sufficiently reduced, the oxide 241 may not be provided.

[0103] The oxide 241 may be a metal oxide containing the element M. In particular, the element M may be aluminum, gallium, yttrium, or tin. The oxide 241 preferably has a higher concentration of the element M than the oxide 230b. Gallium oxide may be used as the oxide 241. A metal oxide such as an In-M-Zn oxide may be used as the oxide 241. Specifically, the atomic ratio of the element M to In in the metal oxide used for the oxide 241 is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. The thickness of the oxide 241 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. The oxide 241 preferably has crystallinity. When the oxide 241 has crystallinity, oxygen release from the oxide 230 can be effectively suppressed. For example, if the oxide 241 has a hexagonal or other crystal structure, oxygen release from the oxide 230 may be effectively suppressed.

[0104] It is preferable to form the oxide film that becomes oxide 230a, the oxide film that becomes oxide 230b, and the oxide film that becomes oxide 241 successively without exposing them to the atmospheric environment. Forming the films without exposing them to the atmosphere is preferable because it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film that becomes oxide 230a, the oxide film that becomes oxide 230b, and the oxide film that becomes oxide 241, and to keep clean the interface and the vicinity of the interface between the oxide film that becomes oxide 230a and the oxide film that becomes oxide 230b, and the interface and the vicinity of the interface between the oxide film that becomes oxide 230b and the oxide film that becomes oxide 241. An apparatus that can perform successive film formation will be described later.

[0105] The conductor 240a is provided over the oxide 241a, and the conductor 240b is provided over the oxide 241b. The conductor 240a and the conductor 240b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0106] As the conductor 240 (conductor 240a and conductor 240b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when they absorb oxygen.

[0107] If the oxide 241 is not provided, contact between the conductor 240 and the oxide 230b or the oxide 230c may cause oxygen in the oxide 230b or the oxide 230c to diffuse into the conductor 240, resulting in oxidation of the conductor 240. The oxidation of the conductor 240 is likely to result in a decrease in the conductivity of the conductor 240. The diffusion of oxygen in the oxide 230b or the oxide 230c into the conductor 240 can be rephrased as the conductor 240 absorbing the oxygen in the oxide 230b or the oxide 230c.

[0108] Furthermore, oxygen in the oxide 230b or the oxide 230c diffuses into the conductor 240a and the conductor 240b, and layers may be formed between the conductor 240a and the oxide 230b, between the conductor 240b and the oxide 230b, or between the conductor 240a and the oxide 230c, and between the conductor 240b and the oxide 230c. Because these layers contain more oxygen than the conductor 240a or the conductor 240b, they are presumed to have insulating properties. In this case, the three-layer structure of the conductor 240a or the conductor 240b, the layer, and the oxide 230b or the oxide 230c can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and can be regarded as a metal-insulator-semiconductor (MIS) structure or a diode junction structure primarily based on the MIS structure.

[0109] Note that hydrogen contained in the oxide 230b, the oxide 230c, and the like may diffuse into the conductor 240a or the conductor 240b. In particular, by using a nitride containing tantalum for the conductor 240a and the conductor 240b, hydrogen contained in the oxide 230b, the oxide 230c, and the like is likely to diffuse into the conductor 240a or the conductor 240b, and the diffused hydrogen may bond with nitrogen contained in the conductor 240a or the conductor 240b. In other words, hydrogen contained in the oxide 230b, the oxide 230c, and the like may be absorbed by the conductor 240a or the conductor 240b.

[0110] Furthermore, there may be a curved surface between the side surface of the conductor 240 and the top surface of the conductor 240. In other words, the end of the side surface and the end of the top surface may be curved. The curved surface has a radius of curvature of, for example, 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the conductor 240. The lack of corners at the end improves film coverage in the subsequent film formation process.

[0111] The insulator 271 is provided in contact with the upper surface of the conductor 240 and preferably functions as a barrier insulating film against at least oxygen. Therefore, the insulator 271 also preferably has a function of suppressing oxygen diffusion. For example, the insulator 271 preferably has a function of suppressing oxygen diffusion more than the insulator 280. As the insulator 271, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Alternatively, as the insulator 271, for example, an insulator containing silicon nitride may be used.

[0112] Furthermore, an insulator may be provided to cover the side surfaces of the oxide 230a, the oxide 230b, the oxide 241, the conductor 240, and the insulator 271. The insulator preferably functions as a barrier insulating film against at least oxygen. That is, the insulator preferably has a function of suppressing oxygen diffusion. For example, the insulator preferably has a function of suppressing oxygen diffusion more than the insulator 280. As the insulator, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed.

[0113] In particular, it is preferable to form the insulator 271 by sputtering aluminum oxide or hafnium oxide in an atmosphere containing oxygen. Sputtering does not involve a hydrogen atmosphere, so it is possible to suppress the inclusion of hydrogen as an impurity.

[0114] By providing the insulator 271, the oxide 230a, the oxide 230b, the oxide 241, and the conductor 240 can be separated from the insulator 280. This makes it possible to suppress the direct diffusion of oxygen from the insulator 280 to the oxide 230a, the oxide 230b, the oxide 241, and the conductor 240. This makes it possible to prevent excessive oxygen from being supplied to the source and drain regions of the oxide 230, which would reduce the carrier density in the source and drain regions. It also makes it possible to suppress the conductor 240 from being excessively oxidized, which would increase the resistivity and reduce the on-current.

[0115] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0116] The insulator 250 is preferably formed using an insulator that releases oxygen upon heating, similar to the insulator 224. By providing the insulator that releases oxygen upon heating as the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b, thereby reducing oxygen vacancies in the channel formation region of the oxide 230b. Therefore, a transistor with suppressed fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided. Furthermore, similar to the insulator 224, the concentrations of impurities such as water and hydrogen in the insulator 250 are preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0117] Although the insulator 250 is illustrated as a single layer in FIGS. 1B and 1C, it may have a laminated structure of two or more layers. When the insulator 250 has a laminated structure of two layers, it is preferable that the lower layer of the insulator 250 is formed using an insulator that releases oxygen when heated, and the upper layer of the insulator 250 is formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the lower layer of the insulator 250 into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 can be formed using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be formed using a material similar to that of the insulator 222.

[0118] When silicon oxide or silicon oxynitride is used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator into a laminated structure consisting of the lower layer of the insulator 250 and the upper layer of the insulator 250, a laminated structure that is stable against heat and has a high dielectric constant can be achieved. This makes it possible to reduce the gate voltage applied during transistor operation while maintaining the physical thickness of the gate insulator. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0119] Specifically, the upper layer of the insulator 250 can be made of a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0120] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0121] It is preferable that the metal oxide functions as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 can be used as the metal oxide. In this case, by forming the conductor 260a by a sputtering method, the electrical resistance value of the metal oxide can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0122] The inclusion of the metal oxide can improve the on-state current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Furthermore, the physical thickness of the insulator 250 and the metal oxide can maintain a distance between the conductor 260 and the oxide 230, thereby suppressing leakage current between the conductor 260 and the oxide 230. Furthermore, the provision of a stacked structure of the insulator 250 and the metal oxide can easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0123] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIGS. 1B and 1C, the top surface of the conductor 260 is substantially flush with the top surfaces of the insulator 250 and the oxide 230c. Although the conductor 260 is shown in FIGS. 1B and 1C as having a two-layer structure of the conductor 260a and the conductor 260b, it may have a single-layer structure or a stacked structure of three or more layers.

[0124] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0125] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0126] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity for the conductor 260b. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0127] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductor 240a and the conductor 240b without alignment.

[0128] 1C , in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap, relative to the bottom surface of the insulator 222, is preferably equal to or lower than the height of the bottom surface of the oxide 230b. The conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, making it easier for the electric field of the conductor 260 to act on the entire channel formation region of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0129] The insulator 280 is provided on the insulator 224, the oxide 230, the conductor 240, and the insulator 271. The top surface of the insulator 280 may be planarized.

[0130] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce the parasitic capacitance that occurs between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is released by heating.

[0131] It is also preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. The insulator 280 may have a structure in which the above-mentioned materials are stacked, for example, a stack structure of silicon oxide formed by sputtering and silicon oxynitride formed by chemical vapor deposition (CVD) on top of that. Silicon nitride may also be stacked on top of that.

[0132] The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 282 and the insulator 283 may be made of, for example, aluminum oxide, silicon nitride, or silicon nitride oxide. For example, the insulator 282 may be made of aluminum oxide, which has a high blocking property against oxygen, and the insulator 283 may be made of silicon nitride, which has a high blocking property against hydrogen.

[0133] The conductors 246a and 246b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 246a and 246b may have a layered structure.

[0134] Furthermore, when the conductor 246 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductors in contact with the insulators 284, 283, 282, 280, and 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 284 from mixing into the oxide 230 through the conductors 246a and 246b.

[0135] The insulators 276a and 276b may be made of, for example, silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 276a and 276b are provided in contact with the insulator 271a, and therefore can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductors 246a and 246b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductors 246a and 246b.

[0136] Conductors 248 (conductors 248a and 248b) may be disposed in contact with the upper surfaces of the conductors 246a and 246b, functioning as wiring. Conductor 248 is preferably made of a conductive material containing tungsten, copper, or aluminum as its main component. The conductor may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0137] The insulator 286 is provided on the conductor 248 and on the insulator 283. As a result, the upper surface and side surfaces of the conductor 248 are in contact with the insulator 286, and the lower surface of the conductor 248 is in contact with the insulator 283. In other words, the conductor 248 can be configured to be surrounded by the insulators 283 and 286. This configuration can suppress the permeation of oxygen from the outside and prevent oxidation of the conductor 248. This is also preferable because it can prevent impurities such as water and hydrogen from diffusing from the conductor 248 to the outside.

[0138] <<Metal oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as the oxide 230. Metal oxides that can be used as the oxide 230 according to the present invention will be described below.

[0139] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0140] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0141] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0142] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0143] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0144] In-Ga-Zn oxide (hereinafter referred to as IGZO), a type of metal oxide containing indium, gallium, and zinc, can sometimes have a stable structure when made into the above-mentioned nanocrystals. In particular, since IGZO tends to have difficulty growing crystals in the atmosphere, it may be structurally more stable to make it into smaller crystals (for example, the above-mentioned nanocrystals) than larger crystals (here, crystals of a few millimeters or a few centimeters).

[0145] The a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0146] Oxide semiconductors (metal oxides) have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0147] In addition to the oxide semiconductor, a cloud-aligned composite (CAC)-OS may be used.

[0148] CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and the material as a whole functions as a semiconductor. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is a function of allowing electrons (or holes) to flow as carriers, and the insulating function is a function of preventing the flow of electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0149] Furthermore, CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the above-mentioned conductive function, and the insulating regions have the above-mentioned insulating function. In addition, the conductive regions and the insulating regions may be separated at the nanoparticle level in the material. In addition, the conductive regions and the insulating regions may be unevenly distributed in the material. In addition, the conductive regions may be observed as connected in a cloud-like shape with the periphery blurred.

[0150] In addition, in CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may be dispersed in the material with sizes of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0151] Furthermore, a CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, a CAC-OS or CAC-metal oxide is composed of a component with a wide gap due to an insulating region and a component with a narrow gap due to a conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow gap. Furthermore, the component with the narrow gap acts complementarily with the component with the wide gap, and carriers also flow in the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in a channel formation region of a transistor, the transistor can achieve high current driving power in the on state, i.e., a large on-state current, and high field-effect mobility.

[0152] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0153] Furthermore, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of the crystal structure of oxide semiconductors will be explained using FIG. 14A. FIG. 14A is a diagram explaining the classification of the crystal structure of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0154] As shown in Figure 14A, IGZO is broadly classified into Amorphous, Crystalline, and Crystal. Amorphous includes completely amorphous. Crystalline includes c-axis aligned crystalline (CAAC), nanocrystalline (nc), and Cloud-Aligned Composite (CAC). Crystalline excludes single crystal, polycrystal, and completely amorphous. Crystal includes single crystal and polycrystal.

[0155] The structure within the bold frame in Figure 14A is an intermediate state between amorphous and crystal, and is a structure belonging to a new boundary region (new crystalline phase). This structure is in the boundary region between amorphous and crystal. In other words, this structure can be described as a structure that is completely different from the energetically unstable amorphous and crystal.

[0156] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) images. Figures 14B and 14C show the XRD spectra of silica glass and IGZO (also called crystalline IGZO), which has a crystal structure classified as Crystalline. Figure 14B shows the XRD spectrum of silica glass, while Figure 14C shows the XRD spectrum of crystalline IGZO. The composition of the crystalline IGZO shown in Figure 14C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the crystalline IGZO shown in Figure 14C is 500 nm.

[0157] As shown by the arrows in Figure 14B, the peak shape of the XRD spectrum of silica glass is nearly symmetrical. On the other hand, as shown by the arrows in Figure 14C, the peak shape of the XRD spectrum of crystalline IGZO is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals. In other words, if the peak shape of the XRD spectrum is not symmetrical, it cannot be said to be amorphous. Note that Figure 14C clearly shows the crystalline phase (IGZO crystal phase) at or near 2θ = 31°. The asymmetrical peak shape of the XRD spectrum is presumed to be due to the crystalline phase (microcrystals).

[0158] Specifically, the XRD spectrum of crystalline IGZO shown in FIG. 14C has a peak at or near 2θ=34°. Microcrystals have a peak at or near 2θ=31°. When an oxide semiconductor film is evaluated using an X-ray diffraction image, the spectrum width on the lower angle side is broader than the peak at or near 2θ=34°, as shown in FIG. 14C. This suggests that the oxide semiconductor film contains microcrystals with a peak at or near 2θ=31°.

[0159] The crystalline structure of the film can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). Figure 14D shows the diffraction pattern of an IGZO film formed at room temperature. The IGZO film shown in Figure 14D was formed by sputtering using an oxide target with an In:Ga:Zn=1:1:1 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction was performed with a probe diameter of 1 nm.

[0160] As shown in Figure 14C, a spot-like pattern, not a halo, is observed in the diffraction pattern of the IGZO film deposited at room temperature. Therefore, it is presumed that the IGZO film deposited at room temperature is in an intermediate state, neither crystalline nor amorphous, and therefore it cannot be concluded that it is in an amorphous state.

[0161] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0162] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be reduced. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor is likely to have normally-on characteristics (a channel exists even when no voltage is applied to the gate electrode, and current flows through the transistor).

[0163] A transistor using a metal oxide tends to have a normally-on characteristic due to fluctuations in its electrical characteristics caused by impurities and oxygen vacancies in the metal oxide. Furthermore, when the transistor is operated in a state where the metal oxide contains excess oxygen exceeding the appropriate amount, the valence of the excess oxygen atoms changes, which causes fluctuations in the electrical characteristics of the transistor, and this can lead to reduced reliability.

[0164] Therefore, it is preferable to use a metal oxide with a low carrier concentration in the channel formation region of a transistor. When the carrier concentration of a metal oxide is to be low, the impurity concentration in the metal oxide is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that in this specification and the like, a metal oxide with a carrier concentration of 1×10 16 cm -3 The following cases are defined as substantially high purity and authentic:

[0165] The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is 1×10 or less. 16 cm -3 More preferably, it is 1×10 or less. 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0166] Impurities in metal oxides include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. In particular, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water, which can cause oxygen vacancies in the metal oxide. If oxygen vacancies are present in the channel formation region of the metal oxide, the transistor may exhibit normally-on characteristics. Furthermore, if hydrogen enters an oxygen vacancy in the metal oxide, the oxygen vacancy and hydrogen bond to form a V O H may be formed. A defect where hydrogen enters an oxygen vacancy (V O Hydrogen atoms (H) function as donors, generating electrons as carriers. Some hydrogen atoms may also bond with oxygen atoms that bond with metal atoms, generating electrons as carriers. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to exhibit normally-on characteristics. Furthermore, since hydrogen atoms in metal oxides are easily moved by stresses such as heat and electric fields, the presence of a large amount of hydrogen in metal oxides can reduce the reliability of transistors.

[0167] In one embodiment of the present invention, V in the oxide 230 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. OTo obtain metal oxides with sufficiently reduced H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment), and to supply oxygen to the metal oxide to compensate for oxygen deficiencies (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be achieved.

[0168] A defect where hydrogen has entered an oxygen vacancy (V O H) can function as a donor in metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, metal oxides are sometimes evaluated by carrier concentration rather than donor concentration. Therefore, in this specification and the like, as a parameter of metal oxides, carrier concentration assuming a state in which no electric field is applied may be used rather than donor concentration. In other words, the "carrier concentration" described in this specification and the like can sometimes be rephrased as "donor concentration." Furthermore, the "carrier concentration" described in this specification and the like can sometimes be rephrased as "carrier density."

[0169] Therefore, it is preferable that the hydrogen content in the metal oxide is reduced as much as possible. Specifically, the hydrogen concentration in the metal oxide obtained by secondary ion mass spectrometry (SIMS) is set to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0170] The defect levels may include trap levels. Charges trapped in the trap levels of metal oxides take a long time to disappear and may behave like fixed charges. Therefore, a transistor having a channel formation region made of a metal oxide with a high density of trap levels may have unstable electrical characteristics.

[0171] Furthermore, the presence of impurities in the channel formation region of the oxide semiconductor may reduce the crystallinity of the channel formation region or the crystallinity of an oxide provided in contact with the channel formation region. The low crystallinity of the channel formation region tends to reduce the stability or reliability of the transistor. Furthermore, the low crystallinity of the oxide provided in contact with the channel formation region may form an interface state, which may reduce the stability or reliability of the transistor.

[0172] Therefore, in order to improve the stability or reliability of a transistor, it is effective to reduce the concentration of impurities in the channel formation region of the oxide semiconductor and its vicinity. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0173] Specifically, the concentration of the impurities obtained by SIMS in the channel formation region of the oxide semiconductor and its vicinity is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 or less. Alternatively, the concentration of the impurity in the channel formation region of the oxide semiconductor and its vicinity, as determined by elemental analysis using EDX, is set to 1.0 atomic % or less. Note that when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurity to element M in the channel formation region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the concentration ratio may be the concentration in the same region as the region where the concentration of the impurity is calculated, or may be the concentration in the oxide semiconductor.

[0174] Furthermore, metal oxides with reduced impurity concentrations have a low defect state density, and therefore may also have a low trap state density.

[0175] Furthermore, when impurities and oxygen vacancies exist in a channel formation region of a transistor including an oxide semiconductor, the resistance of the oxide semiconductor may be reduced, and the electrical characteristics may be easily changed, resulting in reduced reliability.

[0176] For example, silicon has a higher bond energy with oxygen than indium and zinc. For example, when an In-M-Zn oxide is used as an oxide semiconductor, if silicon is mixed into the oxide semiconductor, oxygen contained in the oxide semiconductor may be taken by the silicon, resulting in oxygen vacancies being formed near the indium or zinc.

[0177] In a transistor using an oxide semiconductor for its channel formation region, if a low-resistance region is formed in the channel formation region, a leakage current (parasitic channel) between the source and drain electrodes of the transistor is likely to occur in the low-resistance region. Furthermore, the parasitic channel is likely to cause defects in transistor characteristics, such as normally-on transistors, increased leakage current, and threshold voltage shift due to stress application. Furthermore, if the processing precision of a transistor is low, the parasitic channel varies from transistor to transistor, resulting in variations in transistor characteristics.

[0178] Therefore, it is preferable to reduce the impurities and oxygen vacancies as much as possible in the channel formation region of the oxide semiconductor and its vicinity.

[0179] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device shown in FIGS. 1A to 1C, which is one embodiment of the present invention, will be described with reference to FIGS. 2A to 11A, 2B to 11B, 2C to 11C, and 12A to 12C.

[0180] 2A to 11A are top views. FIGS. 2B to 11B are cross-sectional views corresponding to the portion indicated by the dashed dotted line A1-A2 in FIGS. 2A to 11A, and are also cross-sectional views in the channel length direction of the transistor 200. FIGS. 2C to 11C are cross-sectional views corresponding to the portion indicated by the dashed dotted line A3-A4 in FIGS. 2A to 11A, and are also cross-sectional views in the channel width direction of the transistor 200. Note that some elements are omitted from the top views in FIGS. 2A to 11A for clarity.

[0181] First, a substrate (not shown) is prepared, and then a film of the insulator 212 is formed on the substrate. The insulator 212 can be formed by a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0182] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0183] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0184] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0185] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. The PEALD (Plasma Enhanced ALD) method utilizes plasma, which can be preferable because it allows film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain higher amounts of impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0186] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0187] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0188] In this embodiment, silicon nitride is deposited as the insulator 212 by sputtering.

[0189] In this way, by using an insulator such as silicon nitride that is impermeable to copper as insulator 212, even if a metal that easily diffuses, such as copper, is used in a conductor in a layer (not shown) below insulator 212, it is possible to prevent the metal from diffusing upward through insulator 212. Furthermore, by using an insulator such as silicon nitride that is impermeable to impurities such as water and hydrogen, it is possible to prevent the diffusion of impurities such as water and hydrogen contained in layers below insulator 212.

[0190] Next, the insulator 214 is deposited on the insulator 212. The insulator 214 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is deposited as the insulator 214 by a sputtering method.

[0191] The hydrogen concentration of the insulator 214 is preferably lower than that of the insulator 212. By forming a silicon nitride film by a sputtering method as the insulator 212, a silicon nitride film with a low hydrogen concentration can be formed. Furthermore, by using aluminum oxide as the insulator 214, the hydrogen concentration can be lower than that of the insulator 212.

[0192] In a subsequent process, the transistor 200 is formed on the insulator 214, and it is preferable that the film close to the transistor 200 has a relatively low hydrogen concentration, and it is preferable that the film with a relatively high hydrogen concentration be placed farther from the transistor 200.

[0193] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is deposited as the insulator 216 by a sputtering method.

[0194] Note that the insulators 212, 214, and 216 are preferably successively deposited under reduced pressure without exposure to the air environment. Deposition without exposure to the air environment is preferable because impurities or moisture from the air environment can be prevented from adhering to the insulators 212, 214, and 216, and the interface and vicinity of the interface between the insulators 212 and 214 and the interface and vicinity of the interface between the insulators 214 and 216 can be kept clean. For example, a multi-chamber deposition apparatus can be used for successive deposition. Successive deposition is preferable because it enables a reduction in the manufacturing process time of a semiconductor device.

[0195] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The region in which the opening is formed may also be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, it is preferable to use silicon nitride, aluminum oxide, or hafnium oxide for the insulator 214.

[0196] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high-density plasma source.

[0197] After the opening is formed, a conductive film that will become the conductor 205a is formed. The conductive film preferably contains a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0198] In this embodiment, the conductive film that becomes the conductor 205a has a multilayer structure. First, a tantalum nitride film is formed by sputtering, and then titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductor 205b, even if a metal that easily diffuses, such as copper, is used in the conductive film that becomes the conductor 205b (described later), the metal can be prevented from diffusing out of the conductor 205a.

[0199] Next, a conductive film that will become the conductor 205b is formed. The conductive film can be formed by plating, sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, a low-resistance conductive material such as copper is deposited as the conductive film that will become the conductor 205b.

[0200] Next, chemical mechanical polishing (CMP) is performed to remove the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216. As a result, the conductors 205a and 205b remain only in the openings. This allows the formation of a conductor 205 with a flat upper surface (see FIGS. 2A to 2C). Note that the CMP process may remove a portion of the insulator 216.

[0201] In the above description, the conductor 205 is formed so as to be embedded in the opening of the insulator 216, but this embodiment is not limited to this. For example, the conductor 205 may be formed on the insulator 214, the insulator 216 may be formed on the conductor 205, and a part of the insulator 216 may be removed by performing CMP treatment on the insulator 216, thereby exposing the surface of the conductor 205.

[0202] Next, the insulator 222 is formed over the insulator 216 and the conductor 205. As the insulator 222, an insulator containing one or both of an oxide of aluminum and hafnium is preferably formed. Note that as the insulator containing one or both of an oxide of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. An insulator containing one or both of an oxide of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water.

[0203] Because the insulator 222 has barrier properties against hydrogen and water, the hydrogen and water contained in the structures provided around the transistor 200 are prevented from diffusing into the inside of the transistor 200 through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0204] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0205] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0206] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the insulator 222 as much as possible.

[0207] In this embodiment, after the insulator 222 is formed, heat treatment is performed at 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4 slm:1 slm. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment can improve the crystallinity of the insulator 222. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0208] Next, the insulator 224 is deposited on the insulator 222. The insulator 224 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a silicon oxide or silicon oxynitride film is deposited as the insulator 224 by ALD. The insulator 224 is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulator 224 to be reduced. Since the insulator 224 will be the insulator 224 in contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0209] Alternatively, the insulator 224 may be subjected to plasma treatment containing oxygen under reduced pressure. By appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed.

[0210] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, CMP processing may be performed until the aluminum oxide reaches the insulator 224. By performing the CMP processing, the surface of the insulator 224 can be planarized and smoothed. By placing the aluminum oxide on the insulator 224 and performing the CMP processing, it becomes easier to detect the end point of the CMP processing. Furthermore, the CMP processing may polish a portion of the insulator 224, reducing the thickness of the insulator 224; however, the thickness can be adjusted during the formation of the insulator 224. By planarizing and smoothing the surface of the insulator 224, it may be possible to prevent a deterioration in the coverage of the oxide film to be formed later and prevent a decrease in the yield of the semiconductor device.

[0211] Next, an oxide film 230A and an oxide film 230B are formed in this order on the insulator 224 (see FIGS. 2A to 2C).

[0212] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0213] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. When the oxide film is formed by sputtering, the In-M-Zn oxide target can be used.

[0214] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. Oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film can be formed according to the desired characteristics of oxide 230a and oxide 230b by appropriately selecting the film formation conditions and atomic ratio.

[0215] Next, an oxide film 241A is formed on the oxide film 230B (see FIGS. 2A to 2C). The oxide film 241A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 241A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 241A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0216] It is preferable to form oxide films 230A, 230B, and 241A successively under reduced pressure without exposure to the atmospheric environment. Forming oxide films 230A, 230B, and 241A without exposure to the atmospheric environment prevents impurities or moisture from the atmospheric environment from adhering to oxide films 230A, 230B, and 241A, and thus maintains clean the interface and vicinity of the interface between oxide film 230A and oxide film 230B, and the interface and vicinity of the interface between oxide film 230B and oxide film 241A. For example, a multi-chamber film formation apparatus may be used. Successive film formation is preferable because it shortens the manufacturing process time for the semiconductor device.

[0217] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 241A do not polycrystallize, i.e., 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to replenish the desorbed oxygen.

[0218] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the moisture content of the gas used in the heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other substances from being absorbed into oxide film 230A, oxide film 230B, oxide film 241A, and the like as much as possible.

[0219] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 550°C for one hour, followed by another heat treatment in an oxygen atmosphere at 550°C for one hour. This heat treatment can remove impurities such as water and hydrogen from the oxide films 230A, 230B, and 241A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser, more compact structure. This reduces the diffusion of oxygen or impurities in the oxide film 230B.

[0220] Next, a conductive film 240A is formed on the oxide film 241A (see FIGS. 2A to 2C). The conductive film 240A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, tantalum nitride may be formed as the conductive film 240A by sputtering. Note that heat treatment may be performed before the formation of the conductive film 240A. The heat treatment may be performed under reduced pressure, and the conductive film 240A may be formed successively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 241A can be removed, and the moisture and hydrogen concentrations in the oxide film 230A, the oxide film 230B, and the oxide film 241A can be further reduced. The heat treatment temperature is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the heat treatment temperature is set to 200° C.

[0221] Next, an insulating film 271A is formed on the conductive film 240A (see FIGS. 2A to 2C). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271A is preferably an insulating film that has a function of suppressing oxygen permeation. For example, the insulating film 271A may be formed by a sputtering method or an ALD method using aluminum oxide, hafnium oxide, silicon nitride, or the like.

[0222] Next, a conductive film 291A is formed over the insulating film 271A (see FIGS. 2A to 2C). The conductive film 291A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film 291A may be, for example, a conductive film similar to the conductive film 240A.

[0223] In this embodiment, the conductive film 240A, the insulating film 271A, and the conductive film 291A are formed by sputtering using tantalum nitride for the conductive film 240A, aluminum oxide for the insulating film 271A, and tantalum nitride for the conductive film 291A.

[0224] Note that the conductive film 240A, the insulating film 271A, and the conductive film 291A are preferably successively formed under reduced pressure without exposure to the air environment. Forming the films without exposure to the air environment is preferable because impurities or moisture from the air environment can be prevented from adhering to the conductive film 240A, the insulating film 271A, and the conductive film 291A, and the interface and the vicinity of the interface between the conductive film 240A and the insulating film 271A, and the interface and the vicinity of the interface between the insulating film 271A and the conductive film 291A can be kept clean. For example, a multi-chamber film formation apparatus may be used. Successive film formation is preferable because it shortens the manufacturing process time of the semiconductor device.

[0225] Next, the oxide film 230A, the oxide film 230B, the oxide film 241A, the conductive film 240A, the insulating film 271A, and the conductive film 291A are processed into island shapes using lithography to form the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, the insulating layer 271B, and the conductive layer 291B (see FIGS. 3A to 3C). This processing can be performed using a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. The oxide film 230A, the oxide film 230B, the oxide film 241A, the conductive film 240A, the insulating film 271A, and the conductive film 291A may be processed under different conditions. Note that in this process, the thickness of the insulator 224 in a region not overlapping with the oxide 230a may be reduced.

[0226] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. A conductor, semiconductor, or insulator can then be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist to KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique can also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or an ion beam can also be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0227] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed on the conductive film 240A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film 240A and the like may be performed after removing the resist mask or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 240A and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask. In this embodiment, the insulating layer 271B and the conductive layer 291B are used as hard masks.

[0228] The oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, the insulating layer 271B, and the conductive layer 291B are formed so as to at least partially overlap with the conductor 205. Preferably, the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, the insulating layer 271B, and the conductive layer 291B are approximately perpendicular to the top surface of the insulator 222. When the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, the insulating layer 271B, and the conductive layer 291B are approximately perpendicular to the top surface of the insulator 222, a smaller area and higher density can be achieved when providing multiple transistors 200. Alternatively, the angle formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, the insulating layer 271B, and the conductive layer 291B and the upper surface of the insulator 222 may be low. In this case, the angle formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, the insulating layer 271B, and the conductive layer 291B and the upper surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, the coverage of the insulating film 280A and the like can be improved in subsequent processes, and defects such as voids can be reduced.

[0229] Next, the conductive layer 291B is removed by dry etching (see FIGS. 4A to 4C).

[0230] Next, an insulating film that will become the insulator 280 is formed on the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, and the insulating layer 271B. The insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0231] For example, the insulating film may be formed by depositing a silicon oxide film using a sputtering method and then depositing another silicon oxide film thereon using a PEALD method or a thermal ALD method. It is preferable to deposit the insulating film using a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration in the insulator 280. Heat treatment may be performed before the insulating film is deposited. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited successively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the insulator 224 and the surface of the substrate can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, the oxide layer 241B, and the insulator 224 can be reduced. The heat treatment conditions described above can be used for the heat treatment.

[0232] Next, the insulating film is subjected to CMP processing to form an insulator 280 with a flat upper surface (see FIGS. 5A to 5C). Note that, similar to the insulator 224, an aluminum oxide film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP processing may be performed until the aluminum oxide reaches the insulator 280.

[0233] Here, microwave treatment may be performed. The microwave treatment is preferably performed in an oxygen-containing atmosphere under reduced pressure. After the microwave treatment, heat treatment may be performed while maintaining the reduced pressure. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.

[0234] Furthermore, microwave treatment can modify the film quality of the insulator 280, thereby suppressing the diffusion of hydrogen, water, impurities, and the like from the insulator 280 to the oxide 230. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, and the like to the oxide 230 via the insulator 280 in post-processing steps after the formation of the insulator 280, or by heat treatment, etc. Note that, although the present embodiment illustrates a form in which microwave treatment is performed from above the insulator 280, this is not limiting. For example, in addition to microwave treatment, plasma treatment or microwave-excited plasma treatment may also be performed.

[0235] Next, a portion of the insulator 280, a portion of the insulating layer 271B, a portion of the conductive layer 240B, a portion of the oxide layer 241B, and a portion of the oxide 230b are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the insulator 271a, the insulator 271b, the conductor 240a, the conductor 240b, the oxide 241a, and the oxide 241b are formed (see FIGS. 6A to 6C).

[0236] Here, the upper part of the oxide 230b may be removed in the step of forming the opening. By removing a part of the oxide 230b, a groove is formed in the oxide 230b.

[0237] Note that a portion of the insulator 280, a portion of the insulating layer 271B, a portion of the conductive layer 240B, a portion of the oxide layer 241B, and a portion of the oxide 230b can be processed by dry etching or wet etching. Processing by dry etching is suitable for fine processing. The processing may be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulating layer 271B may be processed by wet etching, and a portion of the oxide layer 241B, a portion of the conductive layer 240B, and a portion of the oxide 230b may be processed by dry etching. Furthermore, the processing of a portion of the oxide layer 241B and a portion of the conductive layer 240B may be performed under different conditions from the processing of a portion of the oxide 230b.

[0238] When a part of the oxide 230b is removed by dry etching to form the groove, it is preferable to perform the process with a high bias power. For example, the power density of the bias power is set to 0.02 W / cm. 2 It should be more than 0.03W / cm 2 It is preferable to set it to 0.06W / cm or more. 2 The dry etching time may be appropriately set in accordance with the depth of the groove.

[0239] In this case, impurities may be generated inside the opening or damaged areas may be generated on the surface of the oxide 230b during the above-mentioned opening process. These impurities and damaged areas are preferably removed by a cleaning process.

[0240] The impurities include, for example, those originating from components contained in insulator 280, part of insulating layer 271B, and conductive layer 240B, components contained in members used in the device used to form the opening, components contained in the gas or liquid used in etching, etc. Specific examples of the impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0241] In particular, impurities such as aluminum or silicon may inhibit the oxide 230c formed in a later step from becoming a CAAC-OS.

[0242] In metal oxides, the region where impurities such as aluminum or silicon inhibit the formation of CAAC-OS and the region becomes an amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, so V O A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the non-CAAC regions of the oxide 230b and the oxide 230c are reduced or eliminated.

[0243] Therefore, it is preferable to reduce or remove impurity elements, such as aluminum or silicon, attached to the surfaces of the oxide 230a and the oxide 230b, which inhibit the formation of CAAC-OS. For example, the concentration of aluminum atoms at the interface between the oxide 230b and the oxide 230c and its vicinity may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0244] Furthermore, the oxide 230b and the oxide 230c preferably have a layered CAAC structure. In particular, it is preferable that the CAAC structure be formed up to the bottom end of the drain of the oxide 230b and the oxide 230c. Here, in the transistor 200, the conductor 240a or the conductor 240b and its vicinity function as the drain. That is, it is preferable that either or both of the oxide 230b and the oxide 230c near the bottom end of the conductor 240a (conductor 240b) have a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed, and by having a CAAC structure, fluctuations in the electrical characteristics of the transistor 200 can be further suppressed. Furthermore, the reliability of the transistor 200 can be improved.

[0245] The cleaning process may be a wet cleaning process using a cleaning solution, a plasma process using plasma, or a heat treatment process, and may be performed by combining the above cleaning processes as appropriate. Note that the cleaning process may deepen the grooves.

[0246] Wet cleaning may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, or pure water, or carbonated water. Ultrasonic cleaning may also be performed using these aqueous solutions, pure water, or carbonated water. These cleaning methods may also be used in combination.

[0247] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as "diluted hydrofluoric acid," and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be referred to as "diluted ammonia water." The concentration, temperature, and other parameters of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0248] It is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning, as this frequency can reduce damage to the oxide 230b and the like.

[0249] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0250] In this embodiment, the cleaning process involves wet cleaning using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. This cleaning process can remove impurities that have adhered to the surfaces of or diffused into the oxides 230a and 230b. Furthermore, it can improve the crystallinity of the oxide 230c formed on the oxide 230b.

[0251] Furthermore, due to the processing such as the dry etching or the cleaning process, the film thickness of the insulator 224 in the area that overlaps with the opening but does not overlap with the oxide 230b may become thinner than the film thickness of the insulator 224 in the area that overlaps with the oxide 230b.

[0252] Heat treatment may be performed after the etching or cleaning. The heat treatment may be performed at a temperature of 100°C to 450°C, preferably 350°C to 400°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0253] Next, the oxide film 230C is formed (see FIGS. 7A to 7C). Heat treatment may be performed before the formation of the oxide film 230C. The heat treatment is preferably performed under reduced pressure, and the oxide film 230C is formed immediately after the formation of the oxide film 230C without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 200°C.

[0254] Here, the oxide film 230C is preferably provided so as to contact at least the inner wall of the groove formed in the oxide 230b, part of the side surface of the oxide 241, part of the side surface of the conductor 240, part of the side surface of the insulator 271, and part of the side surface of the insulator 280. By being surrounded by the oxide 241, the insulator 271, and the oxide film 230C, the decrease in conductivity of the conductor 240 due to oxidation in the subsequent steps can be suppressed.

[0255] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230C may be formed by the same film formation method as that for the oxide film 230A. In this embodiment, the oxide film 230C is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0256] Here, in order to reduce the oxygen vacancies in the oxide 230b and the oxide film 230C and make the oxide 230b substantially high-purity and intrinsic, a process of adding oxygen to the oxide 230b and the oxide film 230C (hereinafter also referred to as an oxygen ion implantation process or an oxygen doping process) is performed (see Figures 8A to 8C and Figure 12A. Note that Figure 12A is an enlarged view of a portion of Figure 8C).

[0257] By performing oxygen addition treatment on the channel formation region of the oxide 230b through the oxide film 230C, it is possible to suppress the diffusion of impurities or the generation of damaged regions on the surface of the channel formation region. In particular, since the oxide film 230C is composed of the same elements as the oxide 230b, even if a part of the oxide film 230C diffuses into the oxide 230b due to the addition treatment, no problems caused by impurities will occur.

[0258] 8B, 8C, and 12A, oxygen implantation treatment forms oxygen-added regions 292 on the oxide film 230C, the surface of the oxide 230b, the surface of the insulator 280, and the surface of the insulator 224. In particular, it is preferable to provide the regions 292 near the interface between the oxide film 230C and the oxide 230b. By adding oxygen to the surface of the oxide 230b, oxygen vacancies in the oxide 230b can be efficiently reduced in a subsequent heat treatment.

[0259] Specifically, oxygen can be added to the oxide film 230C and the oxide 230b by using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like as the oxygen implantation process. 16 O2 or 18Examples of the gas include oxygen gas such as O2, and gases containing oxygen such as nitrous oxide gas, ozone gas, etc. The process of adding oxygen may be performed while heating the substrate.

[0260] For example, the acceleration voltage in the ion doping process is 0.5 kV to 100 kV, preferably 1 kV to 50 kV, more preferably 1 kV to 30 kV, and even more preferably 1 kV to 10 kV. The ion implantation concentration is 1×10 15 atoms / cm 2 or more, preferably 2 x 10 15 atoms / cm 2 More preferably, 5 × 10 15 atoms / cm 2 or more, more preferably 1×10 16 atoms / cm 2 More preferably, 2×10 16 atoms / cm 2 That's all.

[0261] The ion doping process may be performed approximately perpendicular to the sample surface, or may be performed at an angle to the sample surface.

[0262] 8B and 8C, an arrow 290 schematically indicates the direction of travel of oxygen ions. As indicated by the arrow 290, in the channel width direction of the oxide 230b, it is preferable that one ion is incident at an angle θ (45°<θ<135°) with respect to a tangent to the top surface of the oxide 230b. In addition, in the L length direction of the oxide 230b, it is preferable that one ion is incident approximately perpendicularly to the top surface of the oxide 230b. By appropriately adjusting the angle θ, oxygen can be added to the side surface of the oxide 230b and the oxide film 230C formed on the side surface of the oxide 230b.

[0263] Note that a process of adding oxygen may be performed before forming oxide film 230C. When oxygen is added before forming oxide film 230C, it is preferable that oxide layer 241B remains in the opening, as shown in Fig. 13. Note that when oxide layer 241B remains on the bottom surface of the opening, it is preferable that oxide layer 241B and oxide film 230C are made of the same material and have the same atomic ratio.

[0264] By performing oxygen addition treatment on the channel formation region of the oxide 230b through the oxide layer 241B, it is possible to suppress the diffusion of impurities or the generation of damaged regions on the surface of the channel formation region. In particular, since the oxide layer 241B is composed of the same elements as the oxide 230b, even if a part of the oxide layer 241B diffuses into the oxide 230b due to the addition treatment, problems caused by impurities do not occur.

[0265] Next, a heat treatment is carried out (see FIGS. 9A to 9C, 12B, and 12C. Note that FIGS. 12B and 12C are enlarged views of a part of FIG. 9C).

[0266] The heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230b, thereby reducing oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0267] Specifically, the heat treatment is preferably performed at a temperature of 100° C. to 450° C., preferably 350° C. to 400° C. Note that the heat treatment is preferably performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.

[0268] The effect of the heat treatment will be described with reference to FIG. 12. As shown in FIG. 12B, the oxygen added to the region 292 by the oxygen implantation process diffuses into the oxide 230b, the insulator 224, and the insulator 280. At the same time, as shown in FIG. 12C, the diffused oxygen is supplied to the oxygen vacancies Vo in the oxide film 230C and the oxide 230b by the heat treatment, filling the oxygen vacancies and becoming part of the oxide film 230C and the oxide 230b. Meanwhile, the oxygen diffused into the insulators 224 and 280 remains in the insulators 224 and 280 as excess oxygen.

[0269] By reducing the defect level or oxygen vacancy in the channel formation region, a highly reliable transistor with little fluctuation in electrical characteristics can be provided, and a normally-off transistor can also be provided.

[0270] On the other hand, when the transistor is operated in a state where the metal oxide contains excess oxygen that exceeds the appropriate amount, the valence of the excess oxygen atoms changes, and the electrical characteristics of the transistor fluctuate, which may result in reduced reliability.

[0271] Therefore, by covering the channel formation region of the oxide 230b with the oxide 230a having barrier properties and the oxide 230c having barrier properties, it is possible to prevent excess oxygen contained in the insulator 224 from being excessively supplied to the oxide 230b.

[0272] Next, the insulating film 250A is formed (see FIGS. 10A to 10C). Heat treatment may be performed before forming the insulating film 250A. After the heat treatment under reduced pressure, it is preferable to continuously form the insulating film 250A without exposing it to the atmosphere. The heat treatment is also preferably performed in an oxygen-containing atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the oxide film 230C can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0273] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration in the insulating film 250A. The insulating film 250A will become the insulator 250 that will be in contact with the oxide 230c in a later process, so it is preferable that the hydrogen concentration be reduced in this way.

[0274] When the insulator 250 has a two-layer laminated structure, it is preferable to successively deposit the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 without exposing them to the atmospheric environment. Depositing the films without exposing them to the atmospheric environment can prevent impurities or moisture from the atmospheric environment from adhering to the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250, and can keep the vicinity of the interface between the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 clean.

[0275] Here, after forming the insulating film 250A, microwave treatment may be performed in an oxygen-containing atmosphere under reduced pressure. Heat treatment may also be performed after the microwave treatment while maintaining the reduced pressure. By performing microwave treatment, the film quality of the insulating film 250A and other films can be improved, thereby suppressing the diffusion of hydrogen, water, impurities, and the like. Therefore, post-processing such as film formation of a conductive film that becomes the conductor 260 or post-treatment such as heat treatment can suppress the diffusion of hydrogen, water, impurities, and the like through the insulator 250 into the oxide 230b, the oxide 230a, and the like.

[0276] Next, a conductive film 260A and a conductive film 260B are formed in this order (see FIGS. 10A to 10C). The conductive films 260A and 260B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed using an ALD method, and then the conductive film 260B is formed successively using a CVD method under reduced pressure without exposure to the atmosphere.

[0277] Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see Figures 11A to 11C).

[0278] The CMP process may remove a portion of the insulator 280, including the region 292. By removing this region, the amount of excess oxygen contained in the insulator 280 can be reduced.

[0279] By the above processing, the oxide 230c is arranged so as to cover the opening that reaches the oxide 230b and the inner walls (side walls and bottom surface) of the groove of the oxide 230b. The insulator 250 is arranged so as to cover the opening and the inner walls of the groove via the oxide 230c. The conductor 260 is arranged so as to fill the opening and the groove via the oxide 230c and the insulator 250.

[0280] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0281] Next, the insulator 282 is formed over the oxide 230b, the oxide 230c, the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, the insulator 282 is preferably formed by sputtering aluminum oxide. It is also preferable to form the insulator 282 while heating the substrate. It is also preferable to form the insulator 282 in contact with the top surface of the conductor 260, because this can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 260 during subsequent heat treatment.

[0282] Next, the insulator 283 is formed over the insulator 282. The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon nitride film is formed by a sputtering method.

[0283] Next, openings are formed in the insulators 271, 280, 282, and 283, reaching the conductor 240. The openings may be formed using lithography. Note that although the shape of the openings is circular in top view in FIG. 1A, the shape is not limited to this. For example, the openings may have a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners in top view.

[0284] Next, an insulating film that will become the insulator 276 is formed, and the insulating film is anisotropically etched to form the insulator 276 (insulator 276a and insulator 276b). The insulating film that will become the insulator 276 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film that will become the insulator 276, it is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, it is preferable to form a film of aluminum oxide using the ALD method. Alternatively, it is preferable to form a film of silicon nitride using the PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0285] Furthermore, dry etching, for example, may be used for anisotropic etching of the insulating film that will become the insulator 276. By providing the insulator 276 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductors 246a and 246b that will be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 246a and 246b.

[0286] Next, a conductive film that will become the conductor 246a and the conductor 246b is formed. The conductive film that will become the conductor 246a and the conductor 246b preferably has a layered structure including a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that will become the conductor 246 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0287] Next, CMP processing is performed to remove portions of the conductive film that will become the conductors 246a and 246b, exposing the upper surfaces of the insulators 283 and 276. As a result, the conductive film remains only in the openings, thereby forming the conductors 246a and 246b with flat upper surfaces. Note that the CMP processing may remove portions of the upper surfaces of the insulators 283 and 276.

[0288] Next, a conductive film is formed to become the conductor 248. The conductive film to become the conductor 248 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0289] Next, the conductive film that will become the conductor 248 is processed by lithography to form the conductor 248a that contacts the upper surface of the conductor 246a and the conductor 248b that contacts the upper surface of the conductor 246b. At this time, although not shown, part of the insulator 283 may be removed in a region where the conductor 248a and the conductor 248b do not overlap with the insulator 283.

[0290] Next, an insulator 286 is formed on the conductor 248 and the insulator 283 (see FIGS. 1A to 1C). The insulator 286 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 286 may also be a multilayer structure. For example, a silicon nitride film may be formed by a sputtering method, and then another silicon nitride film may be formed on the silicon nitride by a CVD method.

[0291] Through the above steps, a semiconductor device including the transistor 200 shown in FIGS. 1A to 1C can be manufactured.

[0292] <Semiconductor Device Modification 1> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 15A to 15C.

[0293] Fig. 15A shows a top view of the semiconductor device. Fig. 15B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 15A. Fig. 15C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 15A. Some elements have been omitted from the top view of Fig. 15A for clarity.

[0294] 15A to 15C, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Example 1 of Semiconductor Device>. Also in this section, the materials described in detail in <Configuration Example 1 of Semiconductor Device> can be used as the materials constituting the semiconductor device.

[0295] The semiconductor device shown in Figures 15A to 15C is a modified example of the semiconductor device shown in Figures 1A to 1C. The semiconductor device shown in Figures 15A to 15C differs from the semiconductor device shown in Figures 1A to 1C in the shapes of insulators 214, 282, and 283. Also, it differs in that it has insulator 284.

[0296] In the semiconductor device shown in FIGS. 15A to 15C , the insulators 214, 216, 222, 224, 280, and 282 are patterned. The insulator 283 covers the insulators 214, 216, 222, 224, 280, and 282. That is, the insulator 283 contacts the top and side surfaces of the insulator 282 and the top surface of the insulator 212. As a result, the insulators 214, 216, 222, 224, 280, and 282, including the oxide 230, are isolated from the outside by the insulators 283 and 212. In other words, the transistor 200 is disposed within a region sealed by the insulators 283 and 212.

[0297] For example, it is preferable to form the insulators 214 and 282 using a material that can capture and fix hydrogen, and to form the insulators 212 and 283 using a material that can suppress the diffusion of hydrogen and oxygen. Typically, aluminum oxide can be used for the insulators 214 and 282. Typically, silicon nitride can be used for the insulators 212 and 283.

[0298] With this configuration, it is possible to prevent hydrogen contained outside the sealed region from being mixed into the sealed region.

[0299] 15A to 15C show a structure in which the insulator 212 and the insulator 283 are provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 212 and the insulator 283 may have a stacked structure of two or more layers.

[0300] The insulator 284 functions as an interlayer film. The insulator 284 preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator 284 can be formed using, for example, a material similar to that of the insulator 280.

[0301] <Semiconductor device application example 1> 16A and 16B , an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from those described in the above <Structural Example 1 of Semiconductor Device> and the above <Variation Example 1 of Semiconductor Device>, will be described. In the semiconductor device illustrated in FIGS. 16A and 16B , structures having the same functions as those of the semiconductor device illustrated in <Variation Example 1 of Semiconductor Device> (see FIGS. 1A to 1C ) are denoted by the same reference numerals. In this section, the transistor 200 can be made of the materials described in detail in <Structural Example 1 of Semiconductor Device> and <Variation Example 1 of Semiconductor Device>.

[0302] 16A and 16B show a configuration in which a plurality of transistors 200_1 to 200_n are encapsulated by an insulator 283 and an insulator 212. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 16A and 16B, this is not a limitation. The transistors 200_1 to 200_n may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, the transistors 200_1 to 200_n may be arranged without any regularity depending on the design.

[0303] 16A, a portion where the insulator 283 and the insulator 212 contact each other (hereinafter, may be referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With this structure, the plurality of transistors 200_1 to 200_n can be enclosed by the insulator 283 and the insulator 212. Therefore, a plurality of transistors surrounded by the sealing portion 265 are provided on the substrate.

[0304] Also, dicing lines (sometimes called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. Since the substrate is divided along the dicing lines, a group of transistors surrounded by the sealing portion 265 is extracted as one chip.

[0305] 16A shows an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, but the present invention is not limited to this. As shown in FIG. 16B, the plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In FIG. 16B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0306] In this manner, by using a structure in which the plurality of transistors 200_1 to 200_n are surrounded by a plurality of sealing portions, the contact area between the insulator 283 and the insulator 212 increases, thereby further improving the adhesion between the insulator 283 and the insulator 212. This makes it possible to more reliably seal the plurality of transistors 200_1 to 200_n.

[0307] In this case, a dicing line may be provided overlapping the sealing portion 265a or the sealing portion 265b, or may be provided between the sealing portion 265a and the sealing portion 265b.

[0308] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0309] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0310] (Embodiment 2) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0311] Note that the same reference numerals are assigned to structures having the same functions as those of the semiconductor devices described in the previous embodiments. Therefore, the previous embodiments can be referred to for structures having the same reference numerals.

[0312] <Configuration Example 2 of Semiconductor Device> The structure of a semiconductor device including a transistor 200 will be described with reference to FIG. 17. FIGS. 17A to 17C are top views and cross-sectional views of a semiconductor device including a transistor 200. FIG. 17A is a top view of the semiconductor device. FIGS. 17B to 17C are cross-sectional views of the semiconductor device. FIG. 17B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 17A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 17C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 17A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted from the top view of FIG. 17A for clarity.

[0313] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 274 over the transistor 200, an insulator 280 over the insulator 274, an insulator 282 over the insulator 280, and an insulator 283 over the insulator 282. The insulators 212, 214, 274, 280, 282, and 283 function as interlayer films.

[0314] The transistor 200 also includes a conductor 246 (conductor 246a and conductor 246b) that is electrically connected to the transistor 200 and functions as a plug. Note that an insulator 276 (insulator 276a and insulator 276b) is provided in contact with the side surface of the conductor 246 that functions as a plug. Further, a conductor 248 (conductor 248a and conductor 248b) that is electrically connected to the conductor 246 and functions as a wiring is provided on the insulator 283 and the conductor 246. Further, an insulator 286 is provided on the conductor 248 and the insulator 284.

[0315] Specifically, insulator 276a is provided in contact with the inner walls of the openings of insulators 274, 280, 282, and 283, a first conductor of conductor 246a is provided in contact with the side surface of insulator 276a, and a second conductor of conductor 246a is provided further inward. Also, insulator 276b is provided in contact with the inner walls of the openings of insulators 280, 282, and 283, a first conductor of conductor 246b is provided in contact with the side surface of insulator 276b, and a second conductor of conductor 246b is provided further inward.

[0316] 17B, ​​the height of the top surface of the conductor 246 and the height of the top surface of the insulator 283 in the region overlapping with the conductor 248 can be made approximately the same. Note that, although the transistor 200 shows a structure in which the first conductor of the conductor 246 and the second conductor of the conductor 246 are stacked, the present invention is not limited to this. For example, the conductor 246 may be configured as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, ordinal numbers may be assigned to indicate the order of formation to distinguish them.

[0317] [Transistor 200] As shown in FIGS. 17A to 17C, the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) disposed so as to be embedded in the insulator 214 or the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide 241 (oxide 242) on the oxide 230b. The oxide 230c has an oxide 230d on the oxide 230c, a conductor 240a on the oxide 241a, an insulator 271a on the conductor 240a, a conductor 240b on the oxide 241b, an insulator 271b on the conductor 240b, an insulator 250 on the oxide 230d, and a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping with part of the oxide 230c and the oxide 230d. The oxide 230c is in contact with the side of the oxide 241a, the side of the oxide 241b, the side of the conductor 240a, the side of the conductor 240b, the side of the insulator 271a, and the side of the insulator 271b.

[0318] 17B and 17C, the upper surface of the conductor 260 is disposed so as to substantially coincide with the upper surface of the insulator 250, the oxide 230c, and the upper surfaces of the oxide 230d. The insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, the oxide 230c, the oxide 230d, and the insulator 280.

[0319] In the following description, the insulators 271a and 271b may be collectively referred to as the insulator 271.

[0320] An opening is provided in the insulator 280, reaching the oxide 230b. The oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 are arranged in the opening. In addition, in the channel length direction of the transistor 200, the conductor 260, the insulator 250, the oxide 230d, and the oxide 230c are provided between the conductor 240a and the oxide 241a and between the conductor 240b and the oxide 241b. The insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. The oxide 230d is provided between the oxide 230c and the insulator 250. In addition, in the region overlapping with oxide 230b, oxide 230c has a region in contact with oxide 230b, a region overlapping with oxide 230d and the side of conductor 260 via insulator 250, and a region overlapping with the bottom surface of conductor 260 via insulator 250.

[0321] Oxide 230 preferably includes oxide 230a disposed on insulator 224, oxide 230b disposed on oxide 230a, oxide 230c disposed on oxide 230b and at least partially in contact with oxide 230b, and oxide 230d disposed on oxide 230c.

[0322] Note that in the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d) including the channel formation region.

[0323] A transistor using an oxide semiconductor for a channel formation region has extremely low leakage current in a non-conducting state, and therefore can provide a semiconductor device with low power consumption. On the other hand, the electrical characteristics of a transistor using an oxide semiconductor tend to change due to impurities and oxygen vacancies in the oxide semiconductor, and the transistor tends to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode).

[0324] Therefore, it is preferable to use a high-purity intrinsic oxide semiconductor in which impurities and oxygen vacancies are reduced as the oxide semiconductor used for the channel formation region of a transistor. Note that in this specification and the like, a high-purity intrinsic oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic oxide semiconductor or a substantially high-purity intrinsic oxide semiconductor.

[0325] However, in a transistor including an oxide semiconductor, oxygen in the oxide semiconductor is gradually absorbed by a conductor included in the transistor or a conductor used in a plug or a wiring connected to the transistor, and oxygen vacancies may occur as a type of change over time.

[0326] Therefore, it is preferable to make the oxide 230b substantially high-purity and intrinsic. To make the oxide 230b high-purity and intrinsic, it is preferable to perform a process of adding oxygen to the oxide 230b (hereinafter also referred to as oxygen implantation process or oxygen doping process). Specifically, the oxygen implantation process can be performed by ion implantation, ion doping, plasma immersion ion implantation, or the like.

[0327] On the other hand, when performing a process of adding oxygen using an ion implantation method or the like, physical damage may occur to the surface of the oxide 230b. Therefore, it is preferable to perform a process of adding oxygen to the oxide 230b via the oxide film 230C. Therefore, it is preferable to use the same material for the oxide film 230C as for the oxide 230b.

[0328] By performing an oxygen addition process on the channel formation region of the oxide 230b through the oxide 230c, it is possible to prevent impurities from diffusing into the surface of the channel formation region or the generation of damaged regions. Furthermore, since the same material is used for the oxide 230b and the oxide 230c, even if a part of the oxide film 230C diffuses into the oxide 230b due to the oxygen addition process, problems caused by impurities do not occur.

[0329] Furthermore, after oxide 230b is made substantially intrinsic with high purity, it is preferable to cover the region of oxide 230b where the channel is to be formed with oxide 230a and oxide 230d, which suppress oxygen diffusion more than oxide 230b.

[0330] Specifically, as shown in the figure, by disposing the oxide 230a below the oxide 230b, it is possible to prevent oxygen from being extracted from the oxide 230b, and it is also possible to prevent oxygen and impurities from diffusing into the oxide 230b from structures formed below the oxide 230a.

[0331] Furthermore, by disposing the oxide 230d on the oxide 230b and the oxide 230c, it is possible to suppress the extraction of oxygen from the oxide 230b and the oxide 230c, and it is also possible to suppress the diffusion of impurities into the oxide 230b from structures formed above the oxide 230d.

[0332] Note that the metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0333] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0334] Here, it is preferable that the oxide 230 has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, it is preferable that the atomic ratio of In to M in the metal oxide used for the oxide 230b is larger than the atomic ratio of In to M in the metal oxide used for the oxide 230a or the oxide 230d.

[0335] That is, in the metal oxides used for oxide 230a and oxide 230d, the atomic ratio of element M to the main component metal element is preferably greater than the atomic ratio of element M to the main component metal element in the metal oxide used for oxide 230b. Also, in the metal oxide used for oxide 230a, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Also, in the metal oxide used for oxide 230b, the atomic ratio of In to element M is preferably greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a and oxide 230d.

[0336] The oxide 230a and the oxide 230d have a common element other than oxygen (as a main component), which reduces the defect state density at the interfaces between the oxide 230a, the oxide 230b, and the oxide 230d. In this case, the main carrier path is the oxide 230b or its vicinity, for example, the interface between the oxide 230b and the oxide 230c. Because the defect state density at the interface between the oxide 230b and the oxide 230c can be reduced, the effect of interface scattering on carrier conduction is reduced, resulting in a high on-current.

[0337] For example, as oxide 230b and oxide 230c, specifically, metal oxides, indium oxides, etc., having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto, or In:M:Zn=10:1:3 [atomic ratio] or a composition close thereto may be used.

[0338] The oxide 230b and the oxide 230c preferably have crystallinity. In particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) for the oxide 230b.

[0339] In one embodiment of the present invention, for example, it is preferable to use silicon nitride or the like for the insulators 212, 282, 283, 274, and 286, and aluminum oxide or the like for the insulators 214 and 271. This can prevent impurities such as water and hydrogen from diffusing from the substrate to the transistor 200 through the insulators 212 and 214. Alternatively, it can prevent oxygen contained in the insulator 224 or the like from diffusing to the substrate through the insulators 212 and 214. It can also prevent impurities such as water and hydrogen from diffusing from the insulator 280, the conductor 248, or the like to the oxide 230. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 274, 282, and 283, which have the function of preventing the diffusion of impurities such as water and hydrogen and oxygen.

[0340] For example, an insulator 274 is provided to cover the side surfaces of the oxide 230a, the oxide 230b, the oxide 241, the conductor 240, and the insulator 271. The insulator 274 preferably functions as a barrier insulating film at least against oxygen, more so than the insulator 280. That is, the insulator preferably has a function of suppressing oxygen diffusion. For example, the insulator 274 preferably has a function of suppressing oxygen diffusion more so than the insulator 280.

[0341] Furthermore, the insulator 274 is preferably formed in an oxygen-free atmosphere, particularly an inert atmosphere. When the insulator 274 is formed in an oxygen-containing atmosphere, oxygen may be added to the surface where the insulator 274 is to be formed. When oxygen is added to the insulator 224, the oxygen is likely to diffuse into the channel formation region through the oxide 230c. Excess oxygen diffusion into the channel formation region may cause degradation of the electrical characteristics of the transistor. Therefore, the insulator 274 may be formed using, for example, a nitride such as silicon nitride.

[0342] In particular, it is preferable to form the insulator 274 by a sputtering method, since the sputtering method does not use a hydrogen atmosphere, it is possible to suppress the inclusion of hydrogen as an impurity.

[0343] By providing the insulators 271 and 274, the oxide 230a, the oxide 230b, the oxide 241, and the conductor 240 can be separated from the insulator 280. This makes it possible to suppress the direct diffusion of oxygen from the insulator 280 to the oxide 230a, the oxide 230b, the oxide 241, and the conductor 240. This makes it possible to prevent excessive oxygen from being supplied to the source and drain regions of the oxide 230, which would reduce the carrier density in the source and drain regions. It is also possible to suppress the conductor 240 from being excessively oxidized, which would increase the resistivity and reduce the on-current.

[0344] Furthermore, when the conductor 246 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductors in contact with the insulators 284, 283, 282, 280, and 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 284 from mixing into the oxide 230 through the conductors 246a and 246b.

[0345] In particular, like the insulator 274, the insulator 282 is preferably formed in an oxygen-free atmosphere or an inert atmosphere. When the insulator 282 is formed in an oxygen-containing atmosphere, oxygen may be added to the deposition surface. When oxygen is added to the insulator 280, the oxygen is likely to diffuse into the channel formation region through the oxide 230c. Excess oxygen diffusion into the channel formation region may cause deterioration of the electrical characteristics of the transistor. Therefore, the insulator 282 may be formed using, for example, a nitride such as silicon nitride.

[0346] Note that when an oxide film with high barrier properties, such as aluminum oxide, is to be used for the insulator 282, the film may be formed under conditions in which oxygen is not injected into the surface on which the film is to be formed.

[0347] The insulator 282 is preferably formed by a sputtering method, which does not involve a hydrogen atmosphere and can therefore prevent hydrogen from being mixed in as an impurity.

[0348] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device shown in FIGS. 17A to 17C, which is one embodiment of the present invention, will be described with reference to FIGS. 18A to 25A, 18B to 25B, 18C to 25C, and 26A to 26C.

[0349] 18A to 25A are top views. Also, FIGS. 18B to 25B are cross-sectional views corresponding to the portion indicated by the dashed dotted line A1-A2 in FIGS. 18A to 25A, and are also cross-sectional views in the channel length direction of the transistor 200. Also, FIGS. 18C to 25C are cross-sectional views corresponding to the portion indicated by the dashed dotted line A3-A4 in FIGS. 18A to 25A, and are also cross-sectional views in the channel width direction of the transistor 200. Note that some elements are omitted from the top views in FIGS. 18A to 25A for clarity.

[0350] First, in this embodiment, the manufacturing method described with reference to FIGS. 2 to 4 in the previous embodiment can be referred to.

[0351] Next, the insulator 274 is deposited on the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, and the insulating layer 271B.

[0352] The insulator 274 is preferably formed in an atmosphere that does not contain at least oxygen. For example, the insulator 274 is preferably formed in an inert atmosphere containing a rare gas, nitrogen, or the like. Specifically, the insulator 274 is preferably formed using a nitride such as silicon nitride.

[0353] When a film is formed in an oxygen-containing atmosphere, oxygen may be added to the film formation surface. When oxygen is added to the insulator 224, the oxygen is likely to diffuse into the channel formation region through the oxide 230c. Excess oxygen diffusion into the channel formation region may cause degradation of the electrical characteristics of the transistor.

[0354] Subsequently, an insulating film that will become the insulator 280 is formed on the insulator 274. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0355] Next, the insulating film is subjected to CMP processing to form an insulator 280 with a flat upper surface (see FIGS. 18A to 18C). Note that, similar to the insulator 224, an aluminum oxide film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP processing may be performed until the aluminum oxide reaches the insulator 280.

[0356] Here, microwave treatment may be performed. The microwave treatment is preferably performed in an oxygen-containing atmosphere under reduced pressure. After the microwave treatment, heat treatment may be performed while maintaining the reduced pressure. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.

[0357] Furthermore, microwave treatment can modify the film quality of the insulator 280, thereby suppressing the diffusion of hydrogen, water, impurities, and the like. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, and the like into the oxide 230 through the insulator 280 in post-processing steps after the formation of the insulator 280, or by heat treatment, and the like. Note that, although the present embodiment illustrates a form in which microwave treatment is performed from above the insulator 280, this is not limiting. For example, in addition to microwave treatment, plasma treatment or microwave-excited plasma treatment may also be performed.

[0358] Next, a portion of the insulator 280, a portion of the insulator 274, a portion of the insulating layer 271B, a portion of the conductive layer 240B, a portion of the oxide layer 241B, and a portion of the oxide 230b are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the insulator 271a, the insulator 271b, the conductor 240a, the conductor 240b, the oxide 241a, and the oxide 241b are formed (see FIGS. 19A to 19C).

[0359] Here, the upper part of the oxide 230b may be removed in the step of forming the opening. By removing a part of the oxide 230b, a groove is formed in the oxide 230b.

[0360] Note that a portion of the insulator 280, a portion of the insulator 274, a portion of the insulating layer 271B, a portion of the conductive layer 240B, a portion of the oxide layer 241B, and a portion of the oxide 230b can be processed by dry etching or wet etching. Dry etching is suitable for fine processing. The processing may be performed under different conditions. For example, a portion of the insulator 280 and a portion of the insulator 274 may be processed by dry etching, a portion of the insulating layer 271B may be processed by wet etching, and a portion of the oxide layer 241B, a portion of the conductive layer 240B, and a portion of the oxide 230b may be processed by dry etching. The processing of a portion of the oxide layer 241B and a portion of the conductive layer 240B may be performed under different conditions from the processing of a portion of the oxide 230b.

[0361] When a part of the oxide 230b is removed by dry etching to form a groove, it is preferable to perform the process by increasing the bias power. For example, the power density of the bias power is set to 0.02 W / cm. 2 It should be more than 0.03W / cm 2 It is preferable to set it to 0.06W / cm or more. 2 The dry etching time may be appropriately set in accordance with the depth of the groove.

[0362] In this case, impurities may be generated inside the opening or damaged areas may be generated on the surface of the oxide 230b during the above-mentioned opening process. These impurities and damaged areas are preferably removed by a cleaning process.

[0363] Next, the oxide film 230C is formed (see FIGS. 20A to 20C). Heat treatment may be performed before the formation of the oxide film 230C. The heat treatment is preferably performed under reduced pressure, and the oxide film 230C is formed immediately after the formation of the oxide film 230C without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 200°C.

[0364] Here, the oxide film 230C is preferably provided so as to contact at least the inner wall of the groove formed in the oxide 230b, part of the side surface of the oxide 241, part of the side surface of the conductor 240, part of the side surface of the insulator 271, and part of the side surface of the insulator 280. By being surrounded by the oxide 241, the insulator 271, and the oxide film 230C, the decrease in conductivity of the conductor 240 due to oxidation in the subsequent steps can be suppressed.

[0365] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230C may be formed by the same film formation method as that for the oxide film 230A. In this embodiment, the oxide film 230C is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0366] Here, in order to reduce the oxygen vacancies in the oxide 230b and the oxide film 230C and make the oxide 230b substantially high-purity and intrinsic, a process of adding oxygen to the oxide 230b and the oxide film 230C (hereinafter also referred to as oxygen implantation process or oxygen doping process) is performed (see Figures 21A to 21C and Figure 26A. Note that Figure 26A is an enlarged view of a portion of Figure 21C).

[0367] By performing oxygen addition treatment on the channel formation region of the oxide 230b through the oxide film 230C, it is possible to suppress the diffusion of impurities or the generation of damaged regions on the surface of the channel formation region. In particular, since the oxide film 230C is made of the same material as the oxide 230b, even if a part of the oxide film 230C diffuses into the oxide 230b due to the oxygen addition treatment, problems caused by impurities do not occur.

[0368] 21B, 21C, and 26A, oxygen implantation treatment forms oxygen-added regions 292 on the oxide film 230C, the surface of the oxide 230b, the surface of the insulator 280, and the surface of the insulator 224. In particular, it is preferable to provide the regions 292 near the interface between the oxide film 230C and the oxide 230b. By adding oxygen to the surface of the oxide 230b, oxygen vacancies in the oxide 230b can be efficiently reduced in a subsequent heat treatment.

[0369] Specifically, oxygen can be added to the oxide film 230C and the oxide 230b by using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like as the oxygen implantation process. 16 O2 or 18 Examples of the gas include oxygen gas such as O2, and gases containing oxygen such as nitrous oxide gas, ozone gas, etc. The process of adding oxygen may be performed while heating the substrate.

[0370] For example, the acceleration voltage in the ion doping process is 0.5 kV to 100 kV, preferably 1 kV to 50 kV, more preferably 1 kV to 30 kV, and even more preferably 1 kV to 10 kV. The ion implantation concentration is 1×10 15 atoms / cm 2 or more, preferably 2 x 10 15 atoms / cm 2 More preferably, 5 × 10 15 atoms / cm 2 or more, more preferably 1×10 16 atoms / cm 2 More preferably, 2×10 16 atoms / cm 2 That's all.

[0371] The ion doping process may be performed approximately perpendicular to the sample surface, or may be performed at an angle to the sample surface.

[0372] 21B and 21C, an arrow 290 schematically indicates the direction of travel of oxygen ions. As indicated by the arrow 290, in the channel width direction of the oxide 230b, it is preferable that one ion is incident at an angle θ (45°<θ<135°) with respect to a tangent to the top surface of the oxide 230b. In addition, in the L length direction of the oxide 230b, it is preferable that one ion is incident approximately perpendicularly to the top surface of the oxide 230b. By appropriately adjusting the angle θ, oxygen can be added to the side surface of the oxide 230b and the oxide film 230C formed on the side surface of the oxide 230b.

[0373] Next, an oxide film 230D is formed on the oxide film 230C (see FIGS. 22A to 22C). The oxide film 230D preferably has a better barrier property against oxygen and impurities than the oxide 230b and the oxide film 230C.

[0374] By disposing the oxide film 230D on the oxide 230b and the oxide film 230C, it is possible to suppress the extraction of oxygen from the oxide 230b and the oxide film 230C. It is also possible to suppress the diffusion of impurities into the oxide 230b from structures formed above the oxide film 230D.

[0375] Next, a heat treatment is carried out (see FIGS. 23A to 23C, 26B, and 26C. Note that FIGS. 26B and 26C are enlarged views of a part of FIG. 23C).

[0376] The heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230b, thereby reducing oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0377] Specifically, the heat treatment is preferably performed at a temperature of 100° C. to 450° C., preferably 350° C. to 400° C. Note that the heat treatment is preferably performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.

[0378] The effect of the heat treatment will be described with reference to FIG. 26. As shown in FIG. 26B, the oxygen added to the region 292 by the oxygen implantation process diffuses into the oxide 230b, the insulator 224, and the insulator 280 due to the heating. At the same time, as shown in FIG. 26C, the diffused oxygen is supplied to the oxygen vacancies Vo in the oxide film 230C and the oxide 230b due to the heating, and fills the oxygen vacancies, thereby becoming part of the oxide film 230C and the oxide 230b. Meanwhile, the oxygen diffused into the insulators 224 and 280 remains in the insulators 224 and 280 as excess oxygen.

[0379] By reducing the defect levels or oxygen vacancies in the channel formation region, a highly reliable transistor with little fluctuation in electrical characteristics can be provided.Furthermore, a normally-off transistor can be provided.

[0380] On the other hand, when the transistor is operated in a state where the metal oxide contains excess oxygen that exceeds the appropriate amount, the valence of the excess oxygen atoms changes, and the electrical characteristics of the transistor fluctuate, which may result in reduced reliability.

[0381] Therefore, by covering the channel formation region of the oxide 230b with the oxide 230a having barrier properties and the oxide 230d having barrier properties, it is possible to prevent excess oxygen contained in the insulator 224 from being excessively supplied to the oxide 230b.

[0382] Next, the insulating film 250A is formed (see FIGS. 24A to 24C). A heat treatment may be performed before the formation of the insulating film 250A. After the heat treatment is performed under reduced pressure, it is preferable to continuously form the insulating film 250A without exposing it to the atmosphere. The heat treatment is also preferably performed in an oxygen-containing atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230D can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the oxide film 230D can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0383] Next, a conductive film 260A and a conductive film 260B are formed in this order (see FIGS. 24A to 24C). The conductive film 260A and the conductive film 260B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed using an ALD method, and then the conductive film 260B is formed successively using a CVD method under reduced pressure without exposure to the atmosphere.

[0384] Next, the oxide film 230C, the oxide film 230D, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see Figures 25A to 25C).

[0385] The CMP process may remove a portion of the insulator 280, including the region 292. By removing this region, the amount of excess oxygen contained in the insulator 280 can be reduced.

[0386] By the above processing, the oxide 230c is arranged so as to cover the opening that reaches the oxide 230b and the inner walls (side walls and bottom surface) of the groove of the oxide 230b. The insulator 250 is arranged so as to cover the opening and the inner walls of the groove via the oxide 230c. The conductor 260 is arranged so as to fill the opening and the groove via the oxide 230c and the insulator 250.

[0387] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0388] Next, an insulator 282 is formed on the oxide 230d, the oxide 230c, the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0389] The insulator 282 is preferably formed in an atmosphere that does not contain at least oxygen. For example, the insulator 282 is preferably formed in an inert atmosphere containing a rare gas, nitrogen, or the like. Specifically, the insulator 282 is preferably formed using a nitride such as silicon nitride.

[0390] When a film is formed in an oxygen-containing atmosphere, oxygen may be added to the film formation surface. When oxygen is added to the insulator 280, the oxygen is likely to diffuse into the channel formation region through the oxide 230c. Excess oxygen diffusion into the channel formation region may cause degradation of the electrical characteristics of the transistor.

[0391] Next, the insulator 283 is formed on the insulator 282 .

[0392] Next, openings are formed in the insulators 271, 280, 282, and 283 to reach the conductor 240.

[0393] Next, an insulating film that will become the insulator 276 is formed, and the insulating film is anisotropically etched to form the insulator 276 (insulator 276a and insulator 276b).

[0394] Next, a conductive film to become the conductor 246a and the conductor 246b is formed. The conductive film to become the conductor 246a and the conductor 246b preferably has a layered structure including a conductor that has a function of suppressing permeation of impurities such as water and hydrogen.

[0395] Next, CMP processing is performed to remove portions of the conductive film that will become the conductors 246a and 246b, exposing the upper surfaces of the insulators 283 and 276. As a result, the conductive film remains only in the openings, thereby forming the conductors 246a and 246b with flat upper surfaces. Note that the CMP processing may remove portions of the upper surfaces of the insulators 283 and 276.

[0396] Next, a conductive film that will become the conductor 248 is formed.

[0397] Next, the conductive film that will become the conductor 248 is processed by lithography to form the conductor 248a in contact with the top surface of the conductor 246a and the conductor 248b in contact with the top surface of the conductor 246b.

[0398] Next, an insulator 286 is formed over the conductor 248 and the insulator 283 (see FIGS. 17A to 17C).

[0399] Through the above steps, a semiconductor device including the transistor 200 shown in FIGS. 17A to 17C can be manufactured.

[0400] <Modification 2 of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 27A to 27C.

[0401] Fig. 27A shows a top view of the semiconductor device. Fig. 27B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 27A. Fig. 27C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 27A. Some elements have been omitted from the top view of Fig. 27A for clarity.

[0402] 27A to 27C, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Example 2 of Semiconductor Device>. Also in this section, the materials described in detail in <Configuration Example 2 of Semiconductor Device> can be used as the constituent materials of the semiconductor device.

[0403] The semiconductor device shown in Figures 27A to 27C is a modified example of the semiconductor device shown in Figures 17A to 17C. The semiconductor device shown in Figures 27A to 27C differs from the semiconductor device shown in Figures 17A to 17C in the shapes of insulators 214, 282, and 283. Also, it differs in that it has insulator 284.

[0404] In the semiconductor device shown in FIGS. 27A to 27C , the insulators 214, 216, 222, 224, 280, and 282 are patterned. The insulator 283 covers the insulators 214, 216, 222, 224, 280, and 282. That is, the insulator 283 contacts the top and side surfaces of the insulator 282 and the top surface of the insulator 212. As a result, the insulators 214, 216, 222, 224, 280, and 282, including the oxide 230, are isolated from the outside by the insulators 283 and 212. In other words, the transistor 200 is disposed within a region sealed by the insulators 283 and 212.

[0405] For example, it is preferable to form the insulator 214 using a material that can capture and fix hydrogen, and to form the insulators 212, 282, and 283 using a material that can suppress the diffusion of hydrogen and oxygen. Typically, aluminum oxide can be used as the insulator 214. Typically, silicon nitride can be used as the insulators 212, 282, and 283.

[0406] With this configuration, it is possible to prevent hydrogen contained outside the sealed region from being mixed into the sealed region.

[0407] 27A to 27C show a structure in which the insulator 212 and the insulator 283 are provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 212 and the insulator 283 may have a stacked structure of two or more layers.

[0408] The insulator 284 functions as an interlayer film. The insulator 284 preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator 284 can be formed using, for example, a material similar to that of the insulator 280.

[0409] <Semiconductor device application example 2> 28A and 28B , an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from those described in the above <Structural Example 2 of Semiconductor Device> and the above <Variation 2 of Semiconductor Device>, will be described. In the semiconductor device shown in FIGS. 28A and 28B , structures having the same functions as those of the semiconductor device described in <Variation 2 of Semiconductor Device> (see FIGS. 17A to 17C ) are denoted by the same reference numerals. In this section, the transistor 200 can be made of the materials described in detail in <Structural Example 2 of Semiconductor Device> and <Variation 2 of Semiconductor Device>.

[0410] 28A and 28B show a configuration in which a plurality of transistors 200_1 to 200_n are encapsulated by an insulator 283 and an insulator 212. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 28A and 28B, this is not a limitation. The transistors 200_1 to 200_n may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, the transistors 200_1 to 200_n may be arranged without any regularity depending on the design.

[0411] 28A, a portion where the insulator 283 and the insulator 212 contact each other (hereinafter, may be referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With this structure, the plurality of transistors 200_1 to 200_n can be enclosed by the insulator 283 and the insulator 212. Therefore, a plurality of transistors surrounded by the sealing portion 265 are provided on the substrate.

[0412] Also, dicing lines (sometimes called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. Since the substrate is divided along the dicing lines, a group of transistors surrounded by the sealing portion 265 is extracted as one chip.

[0413] 28A shows an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, but the present invention is not limited to this. As shown in Fig. 28B, the plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In Fig. 28B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0414] In this manner, by using a structure in which the plurality of transistors 200_1 to 200_n are surrounded by a plurality of sealing portions, the contact area between the insulator 283 and the insulator 212 increases, thereby further improving the adhesion between the insulator 283 and the insulator 212. This makes it possible to more reliably seal the plurality of transistors 200_1 to 200_n.

[0415] In this case, a dicing line may be provided overlapping the sealing portion 265a or the sealing portion 265b, or may be provided between the sealing portion 265a and the sealing portion 265b.

[0416] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0417] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0418] (Embodiment 3) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0419] [Storage device 1] 29 and 30 illustrate an example of a semiconductor device (memory device) according to one embodiment of the present invention. The semiconductor device according to one embodiment of the present invention includes a transistor 200, a transistor 300, and a capacitor 100. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0420] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced.

[0421] 29 and 30 , a wiring 1001 is electrically connected to the source of a transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0422] Moreover, the memory devices shown in FIGS. 29 and 30 can be arranged in a matrix to form a memory cell array.

[0423] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel type or an n-channel type.

[0424] Here, in the transistor 300 shown in FIGS. 29 and 30, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. An insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0425] Note that the transistor 300 shown in FIGS. 29 and 30 is just an example, and the structure is not limited thereto, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0426] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric. Here, the insulator 130 is preferably the same as the insulator 286 described in the above embodiment.

[0427] For example, the conductor 112 over the conductor 246 and the conductor 110 can be formed simultaneously. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0428] 29 and 30 show the conductor 112 and the conductor 110 as having a single layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0429] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be formed as a stacked layer or a single layer.

[0430] For example, it is preferable to use a layered structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitor 100 can improve its dielectric strength by having an insulator with high dielectric strength, thereby preventing electrostatic breakdown of the capacitor 100.

[0431] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0432] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide or resin with pores, etc.

[0433] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0434] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0435] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0436] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIGS. 29 and 30, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0437] Similarly, a conductor 218 and a conductor (conductor 205) constituting the transistor 200 are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0438] Here, similar to the insulator 271 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 211, 212, 214, and 216. That is, the insulator 217 is provided between the conductor 218 and the insulators 210, 211, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0439] The insulator 217 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 is provided in contact with the insulators 211, 212, 214, and 222, and therefore can prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, the insulator 217 can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0440] The insulator 217 can be formed by a method similar to that of the insulator 271. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0441] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0442] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0443] For example, insulators 150, 210, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, or resin. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0444] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen. Therefore, the insulators 214, 212, and 350 can be formed using insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0445] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0446] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0447] For example, the conductors 328, 330, 356, conductor 218, and conductor 112 can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed using low-resistance conductive materials such as aluminum and copper. Using a low-resistance conductive material can reduce wiring resistance.

[0448] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0449] 29 and 30, an insulator 271 may be provided between the insulator 224 and the insulator 280 containing excess oxygen and the conductor 246. By providing the insulator 271 in contact with the insulator 222, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0450] That is, the insulator 271 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 246. Furthermore, the insulator 271 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 246.

[0451] The insulator 271 may be made of an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. Silicon nitride is particularly preferable because of its high blocking properties against hydrogen. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide.

[0452] As in the above embodiment, the transistor 200 is preferably sealed with the insulators 212, 214, 282, and 283. This structure can reduce the intrusion of hydrogen contained in the insulators 284, 150, and the like into the insulator 280 and the like.

[0453] Here, the conductor 246 penetrates the insulators 283 and 282, and the conductor 218 penetrates the insulators 214, 212, and 211. As described above, the insulator 271 is provided in contact with the conductor 246, and the insulator 217 is provided in contact with the conductor 218. This reduces hydrogen that gets mixed into the insulators 212, 214, 282, and 283 through the conductors 246 and 218. In this way, the transistor 200 can be more reliably sealed with the insulators 212, 214, 282, 283, 271, and 217, reducing the amount of impurities, such as hydrogen, contained in the insulator 284, etc., that get mixed in from the outside.

[0454] Furthermore, as described in the previous embodiment, the insulators 216, 224, 280, 250, and 284 are preferably formed by a deposition method using a gas in which hydrogen atoms are reduced or removed, thereby reducing the hydrogen concentrations in the insulators 216, 224, 280, 250, and 284.

[0455] In this way, the hydrogen concentration in the silicon-based insulating film near the transistor 200 can be reduced, and the hydrogen concentration in the oxide 230 can be reduced.

[0456] <Dicing line> The following describes dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the multiple semiconductor devices.

[0457] 29 and 30, for example, it is preferable to design the insulator 282, the insulator 280, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 so that the area where the insulator 283 and the insulator 212 contact each other overlaps with the dicing line. That is, openings are provided in the insulators 282, 280, 224, 222, 216, and 214 near the area that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0458] That is, the insulator 212 and the insulator 283 are in contact with each other through the openings formed in the insulators 282, 280, 224, 222, 216, and 214. Adhesion can be improved by providing the insulators 212 and 283 using the same material and method. For example, silicon nitride is preferably used.

[0459] With this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. At least one of the insulators 212, 214, 282, and 283 has a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, even when the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side surface of the divided substrate and diffusing into the transistor 200.

[0460] Furthermore, this structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. This allows the oxide in which a channel is formed in the transistor 200 to be an oxide semiconductor with a low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0461] 29 and 30, the shape of the capacitor 100 is a planar type, but the memory device described in this embodiment is not limited to this. For example, as shown in FIGS. 31 and 32, the shape of the capacitor 100 may be a cylindrical type. The memory device shown in FIG. 32 has the same configuration below the insulator 150 as the semiconductor device shown in FIG. 31.

[0462] 31 and 32 includes an insulator 150 on an insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the openings formed in the insulator 150 and the insulator 142.

[0463] The conductor 115 functions as the lower electrode of the capacitor 100, the conductor 125 functions as the upper electrode of the capacitor 100, and the insulator 145 functions as the dielectric of the capacitor 100. The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surfaces of the openings in the insulators 150 and 142, allowing for a larger capacitance per unit area. Therefore, the deeper the openings, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0464] The insulator 152 may be an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be an insulator that can be used for the insulator 214.

[0465] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be rectangular, a polygonal shape other than a rectangular, a polygonal shape with curved corners, or a circular shape including an ellipse. Here, it is preferable that the area over which the openings and the transistor 200 overlap in the top view is large. With such a configuration, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0466] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The upper surface of the conductor 115 preferably substantially coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening in the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0467] The insulator 145 is disposed to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. For example, the insulator 145 can be an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order.

[0468] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a high dielectric constant (high-k) material may be used.

[0469] Examples of high-dielectric-constant (high-k) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Using such high-k materials ensures sufficient capacitance of the capacitor 100 even when the insulator 145 is thick. By thickening the insulator 145, leakage current between the conductor 115 and the conductor 125 can be suppressed.

[0470] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN) formed using the ALD method is x ), silicon oxide (SiO x ), silicon nitride (SiN x ) can be used. By using such an insulator with high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0471] The conductor 125 is arranged to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0472] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0473] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0474] (Fourth embodiment) In this embodiment, an apparatus that can be used for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0475] When manufacturing a semiconductor device according to one embodiment of the present invention, it is preferable to use a so-called multi-chamber apparatus having multiple treatment chambers in which different types of films can be successively formed. Each treatment chamber can perform a film formation process such as sputtering, CVD, or ALD. For example, when one treatment chamber is used as a sputtering chamber, the sputtering chamber can be connected to a gas supply system, a gas purifier connected to the gas supply system, a vacuum pump, a target, and the like.

[0476] In addition, each treatment chamber may perform a substrate cleaning treatment, a plasma treatment, a reverse sputtering treatment, an etching treatment, an ashing treatment, a heating treatment, etc. By appropriately performing different treatments in each treatment chamber, an insulator, a conductor, and a semiconductor film can be formed without exposure to the atmosphere.

[0477] A typical example of a semiconductor film used in one embodiment of the present invention is an oxide semiconductor film. In particular, an oxide semiconductor film having a low impurity concentration and a low density of defect states (few oxygen vacancies) enables the manufacture of a transistor with excellent electrical characteristics. Here, a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic film or a substantially highly purified intrinsic film.

[0478] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film can have a low carrier density because of a small number of carrier generation sources. Therefore, a transistor in which a channel formation region is formed in the oxide semiconductor film rarely has electrical characteristics in which the threshold voltage is negative (also referred to as normally-on). Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film may also have a low density of trap states because of a low density of defect states. Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely small off-state current and a channel width of 1×10 6 Even if the device has a channel length L of 10 μm and a source electrode voltage (drain voltage) of 1 V to 10 V, the off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1 × 10-13 It can achieve a characteristic of A or below.

[0479] Typical examples of impurities in an oxide semiconductor film include water and hydrogen. In this specification and the like, reducing or removing water and hydrogen from an oxide semiconductor film may be referred to as dehydration or dehydrogenation. Adding oxygen to an oxide semiconductor film may be referred to as oxygen addition, and a state in which oxygen is added and the oxide semiconductor film has more oxygen than the stoichiometric composition may be referred to as an excess oxygen state.

[0480] Here, by successively depositing different types of films, including an oxide semiconductor, an insulator or conductor located below the oxide semiconductor, and an insulator or conductor located above the oxide semiconductor, without exposure to the atmosphere, it is possible to form a substantially high-purity intrinsic oxide semiconductor film in which the concentration of impurities (particularly, hydrogen and water) is reduced.

[0481] First, a structural example of an apparatus that can be used to manufacture a semiconductor device of one embodiment of the present invention will be described in detail with reference to Figure 33. By using the apparatus shown in Figure 33, a semiconductor film, an insulator or conductor located below the semiconductor film, and an insulator or conductor located above the semiconductor film can be successively formed. Therefore, impurities (particularly hydrogen and water) that may enter the semiconductor film can be suppressed.

[0482] FIG. 33 is a schematic top view of a single-wafer multi-chamber apparatus 4000.

[0483] The apparatus 4000 has an atmosphere-side substrate supply chamber 4010, an atmosphere-side substrate transfer chamber 4012 for transferring substrates from the atmosphere-side substrate supply chamber 4010, a load lock chamber 4020a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 4020b for unloading substrates and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 4029 and a transfer chamber 4039 for transferring substrates in a vacuum, transfer chambers 4030a and 4030b connecting the transfer chamber 4029 and the transfer chamber 4039, and processing chambers 4024a, 4024b, 4034a, 4034b, 4034c, 4034d, and 4034e for performing film formation or heating.

[0484] The multiple processing chambers can each perform different processes in parallel. This makes it easy to fabricate a stacked structure of different film types. Parallel processing can be performed up to the number of processing chambers. For example, the apparatus 4000 shown in FIG. 33 has seven processing chambers. Therefore, using one apparatus (also referred to as in-situ in this specification), seven film formation processes can be performed consecutively without being exposed to the atmosphere.

[0485] On the other hand, in a laminated structure, the number of layers that can be fabricated without exposure to the atmosphere does not necessarily equal the number of processing chambers. For example, if the desired laminated structure has multiple layers of the same material, the layers can be formed in a single processing chamber, so that a laminated structure with a greater number of layers than the number of processing chambers installed can be fabricated.

[0486] The atmosphere-side substrate supply chamber 4010 also includes a cassette port 4014 for accommodating substrates, and an alignment port 4016 for aligning the substrates. Note that the configuration may include multiple cassette ports 4014 (for example, three in FIG. 33).

[0487] The atmosphere-side substrate transfer chamber 4012 is connected to the load lock chamber 4020a and the unload lock chamber 4020b. The transfer chamber 4029 is connected to the load lock chamber 4020a, the unload lock chamber 4020b, the transfer chamber 4030a, the transfer chamber 4030b, the processing chamber 4024a, and the processing chamber 4024b. The transfer chamber 4030a and the transfer chamber 4030b are connected to the transfer chamber 4029 and the transfer chamber 4039. The transfer chamber 4039 is connected to the transfer chamber 4030a, the transfer chamber 4030b, the processing chamber 4034a, the processing chamber 4034b, the processing chamber 4034c, the processing chamber 4034d, and the processing chamber 4034e.

[0488] A gate valve 4028 or a gate valve 4038 is provided at the connection between each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmosphere-side substrate supply chamber 4010 and the atmosphere-side substrate transfer chamber 4012. The atmosphere-side substrate transfer chamber 4012 has a transfer robot 4018. The transfer chamber 4029 has a transfer robot 4026, and the transfer chamber 4039 has a transfer robot 4036. The transfer robot 4018, the transfer robot 4026, and the transfer robot 4036 have multiple movable parts and arms that hold substrates, and can transfer substrates to each chamber.

[0489] The number of transfer chambers, processing chambers, load lock chambers, unload lock chambers and transport chambers is not limited to the above, and an optimum number can be provided as appropriate in accordance with the installation space and process conditions.

[0490] In particular, when there are multiple transfer chambers, it is preferable to have two or more transfer chambers between one transfer chamber and another. For example, as shown in Figure 33, when there are transfer chambers 4029 and 4039, it is preferable to arrange transfer chambers 4030a and 4030b in parallel between transfer chambers 4029 and 4039.

[0491] By arranging the transfer chambers 4030a and 4030b in parallel, for example, a step in which the transfer robot 4026 loads a substrate into the transfer chamber 4030a and a step in which the transfer robot 4036 loads a substrate into the transfer chamber 4030b can be performed simultaneously. Also, a step in which the transfer robot 4026 unloads a substrate from the transfer chamber 4030b and a step in which the transfer robot 4036 unloads a substrate from the transfer chamber 4030a can be performed simultaneously. In other words, by driving multiple transfer robots simultaneously, production efficiency is improved.

[0492] 33 shows an example in which one transfer chamber has one transfer robot and is connected to multiple processes, but this is not limited to this structure. One transfer chamber may have multiple transfer robots.

[0493] In addition, one or both of the transfer chamber 4029 and the transfer chamber 4039 are connected to a vacuum pump and a cryopump via valves. Therefore, the transfer chamber 4029 and the transfer chamber 4039 are evacuated from atmospheric pressure to a low or medium vacuum (several hundred Pa to about 0.1 Pa) using a vacuum pump, and then the valve is switched and the cryopump is used to evacuate from the medium vacuum to a high or ultra-high vacuum (0.1 Pa to 1×10 -7 It is possible to evacuate to a pressure of approximately 100 Pa.

[0494] Furthermore, for example, two or more cryopumps may be connected in parallel to one transfer chamber. By having multiple cryopumps, even if one cryopump is regenerating, it is possible to use the other cryopumps to pump air. Regeneration is the process of releasing molecules (or atoms) that have accumulated inside a cryopump. If a cryopump accumulates too many molecules (or atoms), its pumping capacity will decrease, so it is a good idea to regenerate it periodically.

[0495] The processing chambers 4024a, 4024b, 4034a, 4034b, 4034c, 4034d, and 4034e can each perform different processes in parallel. That is, each processing chamber can perform a film formation process using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like, a heat treatment, or a plasma treatment on a substrate placed therein. Furthermore, a film formation process may be performed in a processing chamber after a heat treatment or a plasma treatment.

[0496] The apparatus 4000 has multiple processing chambers, which allows substrates to be transported between processing steps without being exposed to the atmosphere, thereby preventing impurities from being adsorbed onto the substrate. Furthermore, each processing chamber can perform a different type of film formation process, heat treatment, or plasma treatment, allowing for flexible configuration of the order of film formation, heat treatment, etc.

[0497] Each processing chamber may be connected to a vacuum pump via a valve, such as a dry pump or a mechanical booster pump.

[0498] Each processing chamber may be connected to a power source capable of generating plasma. The power source may be a DC power source, an AC power source, or a high-frequency (RF, microwave, etc.) power source. A pulse generator may be connected to the DC power source.

[0499] The processing chamber may be connected to a gas purification device via a gas supply device. The number of gas supply devices and gas purification devices provided may be equal to the number of gas types.

[0500] For example, when a film formation process by sputtering is performed in a process chamber, the process chamber may include a target, a backing plate connected to the target, a cathode arranged opposite the target via the backing plate, an adhesion prevention plate, a substrate stage, etc. Furthermore, for example, the substrate stage may include a substrate holding mechanism that holds the substrate, a backside heater that heats the substrate from the backside, etc.

[0501] The substrate stage is held in a generally perpendicular position relative to the floor during film formation, and is held in a generally horizontal position relative to the floor during substrate transfer. By holding the substrate stage generally perpendicular to the floor, the probability of dust or particles, which may be mixed in during film formation, adhering to the substrate can be reduced compared to holding the substrate in a horizontal position. However, since holding the substrate stage perpendicular (90°) to the floor may cause the substrate to fall, it is preferable that the angle of the substrate stage relative to the floor be between 80° and 90°.

[0502] The configuration of the substrate stage is not limited to the above. For example, the substrate stage may be configured to be approximately horizontal with respect to the floor. In this configuration, the target may be placed below the substrate stage, and the substrate may be placed between the target and the substrate stage. The substrate stage may also be equipped with a jig or mechanism for fixing the substrate so that the substrate does not fall.

[0503] Furthermore, by providing a shielding plate in the processing chamber, it is possible to prevent particles sputtered from the target from accumulating in unwanted areas. It is also desirable to process the shielding plate so that accumulated sputtering particles do not peel off. For example, blasting treatment may be performed to increase the surface roughness, or the surface of the shielding plate may be provided with irregularities.

[0504] The backing plate has a function of holding the target, and the cathode has a function of applying a voltage (for example, a negative voltage) to the target.

[0505] The target can be a conductor, an insulator, or a semiconductor. For example, when the target is an oxide semiconductor such as a metal oxide, an oxide semiconductor film can be formed in the treatment chamber. Even when the target is a metal oxide, an oxynitride semiconductor film can be formed by using nitrogen gas as a deposition gas.

[0506] Each processing chamber may be connected to a gas supply device via a gas heating mechanism. The gas heating mechanism is connected to a gas purification device via the gas supply device. The gas introduced into the processing chamber may have a dew point of -80°C or less, preferably -100°C or less, and more preferably -120°C or less. For example, oxygen gas, nitrogen gas, and rare gases (such as argon gas) may be used. The gas heating mechanism may heat the gas introduced into the processing chamber to 40°C or more and 400°C or less, preferably 50°C or more and 200°C or less. It is preferable to provide as many gas heating mechanisms, gas supply devices, and gas purification devices as there are gas types.

[0507] Each processing chamber may be connected to a turbomolecular pump and a vacuum pump via a valve, and each processing chamber may be provided with a cryotrap.

[0508] A cryotrap is a mechanism capable of adsorbing molecules (or atoms) with a relatively high melting point, such as water. Turbomolecular pumps are highly productive because they can stably pump large molecules (or atoms) and require little maintenance, but they have low pumping capacity for hydrogen and water. Therefore, cryotraps can be used to improve their pumping capacity for water and other gases. The temperature of the cryotrap's refrigerator is set to 100 K or less, preferably 80 K or less. Furthermore, if a cryotrap has multiple refrigerators, it is preferable to set each refrigerator to a different temperature, as this allows for more efficient pumping. For example, the temperature of the first-stage refrigerator can be set to 100 K or less, and the temperature of the second-stage refrigerator to 20 K or less.

[0509] The exhaust method for the processing chamber is not limited to this, and may be the same as the exhaust method for the connected transfer chamber (exhaust method using a cryopump and a vacuum pump).The exhaust method for the transfer chamber may be the same as the exhaust method for the processing chamber (exhaust method using a turbomolecular pump and a vacuum pump).

[0510] In particular, a vacuum pump and a cryotrap may be combined to evacuate the treatment chamber for forming the oxide semiconductor film. The evacuating device provided in the treatment chamber for forming the oxide semiconductor film preferably has a function of adsorbing at least water molecules.

[0511] In addition, the partial pressure of hydrogen molecules in the treatment chamber for forming the oxide semiconductor film is 1×10 -2 Pa or less, and the partial pressure of water molecules is 1×10 -4 In addition, the pressure in the treatment chamber in which the oxide semiconductor film is formed in a standby state is preferably 8.0×10 Pa or less. -5 Pa or less, preferably 5.0 x 10 -5 Pa or less, more preferably 1.0 × 10 -5 The partial pressure of hydrogen molecules and the partial pressure of water molecules are values ​​when the processing chamber in which sputtering is performed is in a standby state and when the chamber is in a film forming state (plasma is in a discharging state).

[0512] The total pressure and partial pressure of the processing chamber can be measured using a mass spectrometer, such as a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc.

[0513] When the partial pressure of hydrogen molecules, the partial pressure of water molecules, and the pressure in the standby state in the treatment chamber are set within the above ranges, the concentration of impurities in the oxide semiconductor film to be formed can be low.

[0514] In particular, by using each treatment chamber for film formation by sputtering, part of the structure of the transistor 200 described in the above embodiment can be manufactured to have a stacked structure in which films are successively formed in situ.

[0515] In a method for manufacturing the transistor 200, the insulator 212, the insulator 214, and the insulator 216 are successively formed using an apparatus 4000. The oxide film 230A, the oxide film 230B, and the oxide film 243A are successively formed using the apparatus 4000. The conductive film 242A, the insulating film 271A, and the conductive film 248A are successively formed using the apparatus 4000.

[0516] That is, the insulators 212, 214, and 216 can be formed successively without being exposed to the atmosphere. Also, the oxide films 230A, 230B, and 243A can be formed successively without being exposed to the atmosphere. Also, the conductive film 242A, the insulating film 271A, and the conductive film 248A can be formed successively without being exposed to the atmosphere.

[0517] The above-described structure makes it possible to form a laminated film from which impurities (typically, water, hydrogen, etc.) are thoroughly eliminated. Furthermore, since the interfaces of the laminated film are not exposed to the atmosphere, the impurity concentration is reduced.

[0518] Furthermore, for example, when heat treatment is performed in a treatment chamber, the treatment chamber may be equipped with a plurality of heating stages capable of storing substrates. The heating stages may have a multi-stage configuration. Increasing the number of heating stages allows multiple substrates to be heat-treated simultaneously, thereby improving productivity.

[0519] The heating mechanism that can be used in the processing chamber may be, for example, a heating mechanism that uses a resistance heating element or the like for heating. Alternatively, a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas may be used. For example, RTAs (Rapid Thermal Anneals) such as GRTAs (Gas Rapid Thermal Anneals) and LRTAs (Lamp Rapid Thermal Anneals) can be used. LRTAs heat the workpiece by radiating light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. GRTAs perform heat treatment using high-temperature gases. The gas used is an inert gas.

[0520] The load lock chamber 4020a may be equipped with a substrate transfer stage, a backside heater for heating the substrate from the backside, etc. The load lock chamber 4020a increases its pressure from a reduced pressure state to atmospheric pressure, and when the pressure in the load lock chamber 4020a reaches atmospheric pressure, the substrate transfer stage receives the substrate from the transfer robot 4018 provided in the atmosphere-side substrate transfer chamber 4012. Thereafter, the load lock chamber 4020a is evacuated to a reduced pressure state, and then the transfer robot 4026 provided in the transfer chamber 4029 receives the substrate from the substrate transfer stage.

[0521] The load lock chamber 4020a is connected to a vacuum pump and a cryopump via a valve. The unload lock chamber 4020b may have the same configuration as the load lock chamber 4020a.

[0522] The atmosphere-side substrate transfer chamber 4012 has a transfer robot 4018, which allows substrates to be transferred between the cassette port 4014 and the load lock chamber 4020a. A mechanism for preventing the intrusion of dust or particles, such as a HEPA filter (High Efficiency Particulate Air Filter), may be provided above the atmosphere-side substrate transfer chamber 4012 and the atmosphere-side substrate supply chamber 4010. The cassette port 4014 can store multiple substrates.

[0523] By using the above-described apparatus 4000 to successively form an insulating film, a semiconductor film, and a conductive film without exposing the film to the atmosphere, it is possible to suitably prevent impurities from entering the semiconductor film.

[0524] As described above, by using the apparatus of one embodiment of the present invention, a stacked structure including a semiconductor film can be manufactured by successive film formation. Therefore, impurities such as hydrogen and water that are taken into the semiconductor film can be suppressed, and a semiconductor film with a low density of defect states can be manufactured.

[0525] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0526] (Embodiment 5) In this embodiment, a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a memory device including a capacitor (hereinafter also referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to FIGS. 34A, 34B, and 35A to 35H. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. The off-state current of the OS transistor is extremely small, so the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0527] <Storage device configuration example> 34A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0528] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to a memory cell in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, etc., and can select a row to access.

[0529] The memory device 1400 is supplied with a low power supply voltage (VSS) from the outside as power supply voltages, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0530] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0531] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0532] 34A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 34B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0533] 35A to 35H will be used to explain examples of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0534] [DOSRAM] 35A to 35C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 35A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0535] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, the back gate of the transistor M1 is connected to the wiring BGL, and the second terminal of the capacitance element CA is connected to the wiring CAL.

[0536] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0537] Furthermore, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 35B. Furthermore, for example, the memory cell MC may be configured as a memory cell including a single-gate transistor, that is, a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 35C.

[0538] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Furthermore, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is very small, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0539] Furthermore, in the DOSRAM, if the sense amplifier is configured to overlap under the memory cell array 1470 as described above, the bit line can be shortened, which reduces the bit line capacitance and the storage capacitance of the memory cell.

[0540] [NOSRAM] 35D to 35G show circuit configuration examples of a gain cell type memory cell with two transistors and one capacitor. The memory cell 1474 shown in FIG. 35D includes a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and elsewhere, a memory device having a gain cell type memory cell in which the transistor M2 is an OS transistor may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0541] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0542] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0543] 35D corresponds to the memory device shown in Fig. 37. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, the wiring CAL corresponds to the wiring 1005, the wiring RBL corresponds to the wiring 1002, and the wiring SL corresponds to the wiring 1001.

[0544] Furthermore, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 35E. Furthermore, for example, the memory cell MC may be configured as a memory cell having a single gate structure, that is, a memory cell including a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 35F. Furthermore, for example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 35G.

[0545] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be significantly reduced. This allows written data to be held by the transistor M2 for a long time, thereby reducing the frequency of refreshing the memory cell. Furthermore, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0546] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be either an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. Furthermore, by using a Si transistor as the transistor M3, the transistor M2 can be stacked on top of the transistor M3, thereby reducing the area occupied by the memory cell and achieving higher integration of the memory device.

[0547] Furthermore, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0548] FIG. 35H shows an example of a gain cell type memory cell with three transistors and one capacitor. The memory cell 1478 shown in FIG. 35H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The GNDL wiring is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of wiring BIL.

[0549] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have a back gate.

[0550] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured using only n-channel transistors.

[0551] When the semiconductor device described in the above embodiment is used in the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely small.

[0552] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

[0553] Generally, various storage devices (memories) are used in semiconductor devices such as computers depending on the application. Figure 36 shows various storage devices by layer. The higher the layer, the faster the access speed required, while the lower the layer, the larger the storage capacity and recording density required. Figure 36 shows, from the top layer, memories embedded as registers in arithmetic processing units such as CPUs, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0554] The memory embedded as a register in a CPU or other processing unit is frequently accessed by the processing unit because it is used to temporarily store the results of calculations. Therefore, a faster operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0555] SRAM is used, for example, in caches. Caches have the function of storing a copy of the information stored in main memory. By storing copies of frequently used data in the cache, access speed to the data can be increased.

[0556] DRAM is used, for example, as main memory. Main memory has the function of storing programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0557] 3D NAND memory is used, for example, in storage. Storage has the function of storing data that requires long-term storage and various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0558] A storage device according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. The storage device according to one embodiment of the present invention can be suitably used as a storage device located in a boundary area 901 that includes both a tier where a cache is located and a tier where a main memory is located. The storage device according to one embodiment of the present invention can also be suitably used as a storage device located in a boundary area 902 that includes both a tier where a main memory is located and a tier where a storage is located.

[0559] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or examples.

[0560] (Sixth embodiment) In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown using Figures 37A and 37B. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0561] As shown in FIG. 37A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0562] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201, as shown in Fig. 37B. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of PCB 1201, which is connected to a motherboard 1203.

[0563] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the previous embodiment may be used as the DRAM 1221. Also, for example, the NOSRAM described in the previous embodiment may be used as the flash memory 1222.

[0564] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the NOSRAM or DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing and multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0565] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

[0566] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0567] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0568] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0569] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0570] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0571] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0572] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0573] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or examples.

[0574] (Embodiment 7) This embodiment mode will describe examples of electronic components and electronic devices in which the memory device or the like described in the above embodiment mode is incorporated.

[0575] <Electronic components> First, an example of an electronic component incorporating memory device 720 will be described with reference to FIGS. 38A and 38B.

[0576] FIG. 38A shows a perspective view of electronic component 700 and a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 38A has memory device 720 inside mold 711. Parts of FIG. 38A are omitted to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to memory device 720 by wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0577] The memory device 720 includes a driver circuit layer 721 and a memory circuit layer 722 .

[0578] 38B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 720 provided on interposer 731.

[0579] In the electronic component 730, an example is shown in which the storage device 720 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0580] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The interposer 731 may be a silicon interposer, a resin interposer, etc.

[0581] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, with a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0582] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require the provision of active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0583] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0584] Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

[0585] A heat sink (heat dissipation plate) may be provided over the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 720 and the height of the semiconductor device 735.

[0586] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 38B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0587] The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0588] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes or examples.

[0589] (Embodiment 8) In this embodiment, an application example of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.). Note that the term "computer" here refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). FIGS. 39A to 39E schematically show several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memories.

[0590] 39A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 or the like.

[0591] FIG. 39B is a schematic diagram of the appearance of an SD card, and FIG. 39C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. Furthermore, a wireless chip with a wireless communication function may be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 or the like.

[0592] FIG. 39D is a schematic diagram of the appearance of an SSD, and FIG. 39E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be a DOSRAM chip, for example. By providing memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into memory chip 1154 or the like.

[0593] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes or examples.

[0594] (Embodiment 9) A semiconductor device according to one embodiment of the present invention can be used in a processor such as a CPU or a GPU, or a chip. Specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention are shown in FIGS.

[0595] <Electronic devices and systems> A GPU or chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of such electronic devices include electronic devices with relatively large screens, such as televisions, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an electronic device with a GPU or chip according to one embodiment of the present invention, it is possible to equip the electronic device with artificial intelligence.

[0596] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0597] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0598] An electronic device of one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. Examples of electronic devices are shown in FIGS. 40A to 40H.

[0599] [Information terminal] 40A shows a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.

[0600] By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display portion 5102, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display portion 5102 and displays them on the display portion 5102, and an application that performs biometric authentication such as fingerprint or voiceprint authentication.

[0601] 40B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0602] The notebook information terminal 5200 can execute applications using artificial intelligence by applying a chip of one embodiment of the present invention, similar to the information terminal 5100 described above. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, new artificial intelligence can be developed by using the notebook information terminal 5200.

[0603] 40A and 40B, respectively, are taken as examples of electronic devices, but information terminals other than smartphones and notebook information terminals can also be applied. Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0604] [Game consoles] FIG. 40C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection unit 5305 of the housing 5301 to another housing (not shown), the video displayed on the display unit 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play a game simultaneously. The chips described in the above embodiments can be incorporated into the substrates of the housings 5301, 5302, and 5303.

[0605] 40D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wired connection.

[0606] A game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0607] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can have artificial intelligence.

[0608] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game console 5300, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0609] Furthermore, when playing a game requiring multiple players on the portable game console 5300, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0610] 40C and 40D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0611] [Mainframe Computer] The GPU or chip according to one embodiment of the present invention can be applied to a mainframe computer.

[0612] 40E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 40F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0613] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the GPU or chip described in the above embodiment can be mounted on the boards.

[0614] The supercomputer 5500 is a large-scale computer primarily used for scientific and technological calculations. Scientific and technological calculations require high-speed processing of enormous amounts of calculations, resulting in high power consumption and large amounts of heat generated by the chip. By applying a GPU or chip according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from circuits, thereby reducing the impact of heat generation on the circuits themselves, peripheral circuits, and modules.

[0615] 40E and 40F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied include a computer (server) that provides services, a large general-purpose computer (mainframe), etc.

[0616] [Moving object] The GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0617] Fig. 40G is a diagram showing the area around the windshield inside the interior of an automobile, which is an example of a moving body, showing display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0618] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioning settings, etc. The display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, allowing for improved design. The display panels 5701 to 5703 can also be used as lighting devices.

[0619] The display panel 5704 can complement the view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0620] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for automobiles. The chip can also be used in a system that provides road guidance, hazard prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0621] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and the chip of one embodiment of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0622] [electric appliances] 40H shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0623] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0624] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0625] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0626] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes or examples. [Explanation of symbols]

[0627] 100: Capacitive element, 110: Conductor, 112: Conductor, 115: Conductor, 120: Conductor, 125: Conductor, 130: Insulator, 140: Conductor, 142: Insulator, 145: Insulator, 150: Insulator, 152: Insulator, 153: Conductor, 154: Insulator, 156: Insulator, 200: Transistor, 200_n: Transistor, 200_1: Transistor, 205: Conductor, 205a: Conductor, 205b: Conductor, 210: Insulator, 211: Insulator, 212: Insulator, 214: Insulator, 216 : insulator, 217: insulator, 218: conductor, 222: insulator, 224: insulator, 230: oxide, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230c: oxide, 230C: oxide film, 240: conductor, 240a: conductor, 240A: conductive film, 240b: conductor, 240B: conductive layer, 241: oxide, 241a: oxide, 241A: oxide film, 241b: oxide, 241B: oxide layer, 242A: conductive film, 243A: oxide film, 246: conductor, 246a: Conductor, 246b: Conductor, 248: Conductor, 248a: Conductor, 248A: Conductiv...

Claims

1. depositing a first insulator; forming an island-shaped laminate on the first insulator by sequentially laminating a first oxide, a second oxide, and a first conductor; forming a first insulating layer in which a second insulator and a third insulator are laminated in this order on the first insulator and the laminate; forming an opening in the first insulating layer to expose the stack; removing a region of the first conductor exposed in the opening to expose an upper surface of the second oxide and forming a second conductor and a third conductor disposed on the second oxide, and then performing a cleaning process; forming a first oxide film in contact with the upper surface and side surfaces of the second oxide exposed in the opening; adding oxygen to the vicinity of the interface between the second oxide and the first oxide film through the first oxide film, and then performing a heat treatment; a fourth conductor, a fourth insulator, and a third oxide are formed in the opening of the first insulating layer by chemical polishing treatment after forming a first insulating film and a first conductive film on the first oxide film and then removing a portion of the first conductive film, the first insulating film, the first oxide film, and the first insulating layer.

2. depositing a first insulator; forming an island-shaped laminate on the first insulator by sequentially laminating a first oxide, a second oxide, and a first conductor; forming a first insulating layer in which a second insulator and a third insulator are laminated in this order on the first insulator and the laminate; forming an opening in the first insulating layer to expose the stack; removing a region of the first conductor exposed in the opening to expose an upper surface of the second oxide and forming a second conductor and a third conductor disposed on the second oxide, and then performing a cleaning process; forming a first oxide film in contact with the upper surface and side surfaces of the second oxide exposed in the opening; adding oxygen to the vicinity of the interface between the second oxide and the first oxide film through the first oxide film, and then performing a heat treatment; forming a first insulating film and a first conductive film on the first oxide film, and then removing a portion of the first conductive film, the first insulating film, the first oxide film, and the first insulating layer by chemical polishing to expose the first insulating layer, and forming a fourth conductor, a fourth insulator, and a third oxide in the opening provided in the first insulating layer; The method for manufacturing a semiconductor device, wherein the first oxide is indium oxide.

3. In claim 1 or claim 2, The oxygen addition process is a method for manufacturing a semiconductor device using an ion implantation method.

4. In claim 3, In the ion implantation method, oxygen ions are incident in the short side direction of the second oxide at an angle θ (45°<θ<135°) with respect to a tangent to an upper surface of the second oxide.

5. In any one of claims 1 to 4, The method for manufacturing a semiconductor device, wherein the heat treatment is performed at a temperature of 350° C. or higher and 400° C. or lower.

6. In any one of claims 1 to 5, The method for manufacturing a semiconductor device, wherein the heat treatment is performed in an atmosphere containing an oxidizing gas at 1% or more, or 10% or more.

7. In any one of claims 1 to 6, The method for manufacturing a semiconductor device, wherein the first oxide and the third oxide suppress oxygen diffusion more effectively than the second oxide.

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