A lithography model that considers probability theory for mask synthesis.

Abstract

In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process to print a pattern on a wafer. The mask pattern is applied as an input to a deterministic model of the lithography process to predict features of the printed pattern. While the deterministic model is deterministic, it accounts for local stochastic variations of features in the printed pattern.

Description

Technical Field

[0001] Related Applications This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 63 / 112,733, filed Nov. 12, 2020, entitled “Stochastic-Aware Lithographic Models For Mask Synthesis,” and U.S. Patent Application No. 17 / 522,574, filed Nov. 9, 2021, entitled “Stochastic-Aware Lithographic Models For Mask Synthesis.” The entire subject matter of the foregoing is hereby incorporated by reference in its entirety.

[0002] The present disclosure relates to lithography modeling and mask synthesis, including masks for extreme ultraviolet (EUV).

Background Art

[0003] One step in the manufacture of semiconductor wafers involves lithography. In a typical lithography process, a light source generates light that is collected and directed by a condenser / illumination optical system to illuminate a lithography mask. A projection optical system relays the pattern generated onto the wafer by the illuminated mask and exposes the resist on the wafer according to the illumination pattern. The patterned resist is then used in the process to fabricate structures on the wafer.

[0004] Various technologies are being developed to improve lithography processes, including the design of lithography masks. In many of these technologies, the lithography mask design is used as input to several process models, which predict the outcomes of several processes. These results can then be used to modify the lithography mask design. In many cases, the process model can be subjected to regression analysis against data from actual manufacturing processes. Different lithography mask patterns, including test patterns, are executed by the lithography process. The resulting structures are measured and used to calibrate the process model.

[0005] Current process models typically do not directly address the variability that can arise from probabilistic variability in the lithography process itself. Rather, lithography mask patterns are used as input to models that model the lithography process as a completely deterministic process. However, as lithography moves to shorter wavelength ranges around 13.3–13.7 nm (e.g., extreme ultraviolet (EUV)) and smaller geometries (e.g., 10 nm, 7 nm, and smaller technology nodes with respect to approximately 20 nm, 14 nm, and smaller minimum feature sizes), probabilistic variability within relatively small areas (local probabilistic variability) becomes more significant, resulting in suboptimal mask designs with conventional methods. [Overview of the project]

[0006] In some embodiments, a mask pattern is accessed. The mask pattern is intended for use in a lithography process that prints a pattern onto a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict the features of the printed pattern. The deterministic model is deterministic (not, for example, a Monte Carlo simulation), but it takes into account the local probabilistic variability of features in the printed pattern.

[0007] In some embodiments, the deterministic model is a compact model that predicts hotspots in a printed pattern as a function of the mask pattern and further as a function of exposure, focus, and probabilistic model properties, where the probabilistic model properties correlate with the local probabilistic variability of the predicted features. Examples of probabilistic model properties may include diffuse aerial image signal, acid concentration or density, quencher concentration or density, inhibitor concentration or density, gradient of the optical image, acid, quencher, or inhibitor signal, mask pattern density, secondary electron concentration, ligand concentration, and resist surface tension. The compact model is regression-analyzed against empirical data containing the local probabilistic variability of the predicted features. Examples of empirical data may include line edge roughness with respect to CD below or above a certain criterion, variability in critical dimension (CD), worst-case CD, and the number of empirical measurements.

[0008] Other embodiments include components, devices, systems, improvements, methods, processes, applications, computer-readable media, and other technologies related to any of the above.

[0009] This disclosure will be better understood from the detailed description and accompanying drawings of embodiments of this disclosure provided below. The drawings are used to provide knowledge and understanding of embodiments of this disclosure and do not limit the scope of this disclosure to these specific embodiments. Furthermore, the drawings are not necessarily to scale. [Brief explanation of the drawing]

[0010] [Figure 1] This figure shows an EUV lithography process suitable for use with the embodiments of this disclosure. [Figure 2A] This diagram shows a flowchart for simulating the lithography process. [Figure 2B]This figure shows a flowchart for simulating a lithography process using a compact model that takes into account local probabilistic variability. [Figure 3] This diagram shows a flowchart for adding probabilistic model properties to a compact model that does not consider local probabilistic variability. [Figure 4A] This is a diagram showing a simulation of the lithography process. [Figure 4B] This is a diagram showing a simulation of the lithography process. [Figure 5] This figure shows the process window axis diagram and the image simulated from the process in Figure 3. [Figure 6] This figure shows flowcharts of various processes used during the design and manufacture of integrated circuits according to some embodiments of this disclosure. [Figure 7] This is a schematic diagram of an exemplary computer system in which embodiments of the present disclosure may operate. [Modes for carrying out the invention]

[0011] Aspects of this disclosure relate to “probability-aware” lithography models for mask synthesis. In particular, at shorter wavelengths and higher photon energies, local probabilistic influences in the lithography process itself become more significant. Local probabilistic variability is variability arising from a process that has some randomness at a local level. For example, higher photon energies at EUV wavelengths mean that fewer photons are needed to achieve a given energy exposure compared to longer wavelengths. Photon events have some randomness (i.e., probability distribution), which becomes more pronounced when the total number of photons is small. As a result, variability in the number of photons at any particular location on the wafer can result in probabilistic defect mechanisms that were previously negligible or nonexistent as the number of photons increases. Other components of a lithography process that may have local probabilistic variability include photon distribution, secondary electron distribution, photoacid generator (PAG) distribution, quencher distribution, and inhibitor distribution. These probabilistic effects are localized, meaning they can occur over relatively small areas, for example, within an area of ​​10 μm × 10 μm or less of the printed pattern.

[0012] In various embodiments of this disclosure, a deterministic model of a lithography process takes into account these local probabilistic variability in the lithography process. In one method, the model is a compact model that may be used for mask synthesis. A compact model is a parameterized model. The parameters may be called model properties. The values ​​of the model properties may be determined by regression on empirical data. The model properties include at least one probabilistic model property that correlates with the local probabilistic variability in the lithography process. Examples of possible probabilistic model properties include photon density, pattern density, optical signal intensity, optical signal gradient, secondary electron density, secondary electron gradient, photoacid concentration, resist quencher concentration, resist inhibitor concentration, resist inhibitor gradient, metal resist ligand concentration, etc. Although the model takes into account probabilistic variability, the model itself is deterministic. That is, for any given input, the output predicted by the model is always the same (there is no probabilistic variability in the model's output), but the output is adjusted to account for the probabilistic variability in the lithography process.

[0013] The advantages of this disclosure include, but are not limited to, the following: Local probabilistic variability leads to more accurate predictions because probabilistic effects are not ignored. In addition, doing so using a deterministic model can reduce the model's execution time. In other methods, probabilistic variability can be modeled by a probabilistic model in which the same simulation is run many times using statistically fluctuating conditions (e.g., Monte Carlo simulation). However, that method requires many runs to obtain results based on different predictions from different runs, whereas a deterministic model yields the predicted result in a single run. Regression of a parameterized model on empirical data also yields more accurate predictions. It also allows some flexibility in the model's form. Since the accuracy of the model can be achieved by calibrating it against empirical data, the constants and parameters used in this model do not need to be computed with precision, nor do the physical processes being performed need to be modeled with precision.

[0014] Figure 1 shows an EUV lithography process suitable for use with embodiments of the present disclosure. In this system, a light source 110 generates EUV light that is collected and directed by a focusing / illumination optical system 120 to illuminate a mask 130. A projection optical system 140 relays the pattern generated on the wafer 150 by the illuminated mask, exposing the resist on the wafer according to the illumination pattern. The exposed resist is then developed to produce a patterned resist on the wafer. This printed pattern is used to manufacture a structure on the wafer, for example, by deposition, doping, etching, or other processes.

[0015] In Figure 1, the light is within the EUV wavelength range, approximately 13.5 nm, or 13.3–13.7 nm. At these wavelengths, the components are typically reflective rather than transmissive. Mask 130 is a reflective mask, and optics 120, 140 are also reflective and off-axis. This is just one example. Other types of lithography systems can also be used, including the use of transmissive masks and / or optics at other wavelengths, and the use of positive or negative resists.

[0016] Figure 2A shows a simulation of the lithography process. Illumination model 222 models the light source 110 and illumination optics 120 in Figure 1. These are used to predict the light pattern 225 that illuminates the mask. Model 242 takes into account the effects of the lithography mask 130 and projection optics 140 to predict the illumination 245 that exposes the resist. This is sometimes called the optical image 245. The resist model 252 may include the effects of exposure of the resist from the optical image, secondary electron generation, chemical reactions, and subsequent removal, whether by chemical development, etching, or other processes. The removal of the resist leaves a layer of patterned resist 254 covering the wafer, also called the printed pattern. The wafer fab model 256 then models subsequent processes, such as etching, deposition, doping, injection, etc., resulting in a device structure 258 on the wafer.

[0017] For convenience, separate boxes corresponding to physical components or processes are shown in Figure 2A, but the model does not have to be implemented in this manner. For example, all of these effects may be combined into a single compact model that can be used for full-chip evaluation, as shown in Figure 2B. Such a model predicts a uniform optical image (referred to as printed pattern 234 in Figure 2B) from the resulting patterned resist, or mask pattern 230. Such a single model includes the effects from the light source, optics, and resist, and in embodiments described herein, also takes into account local probabilistic variability in the lithography process. The compact model 232 may be designed to process the mask pattern over the entire die in a rapid manner. To complete the full-chip correction on a device such as a microprocessor, 10 18 More than one simulation may be necessary.

[0018] The compact model 232 can be a parameterized deterministic model that predicts the features of the printed pattern 234 and / or the printed pattern as a function of model parameters, also called model properties. For example, the compact model can predict hotspots (defects in the printed pattern), or failure rates in the pattern, as a function of the mask pattern 230, exposure, and focus of the lithography system, and also as a function of certain model properties that correlate with local probabilistic variability. These model properties are called probabilistic model properties.

[0019] The compact model can be regression-analyzed against empirical data. Measured data are collected for various mask patterns. The patterns obtained as a result of manufacturing on the wafer are measured. These are typically measurements of the photoresist and / or Critical Dimension Scanning Electron Microscopy (CDSEM) for measuring the length of each structure. Other measurements such as Atomic Force Microscopy (AFM) can also be used.

[0020] One measure of the quality of the patterned resist 234 is the Critical Dimension (CD). The CD is the dimension of an important feature in the patterned resist or the dimension of an important spacing between features in the patterned resist. Typically, the minimum CD is the minimum line width or space width printed in the resist. Thus, it is a measure of the resolution of the resist and the lithography process. Referring again to FIGS. 2A and 2B, the simulation results 254, 234 in these figures may include predictions of the CD. Another common output is the predicted optical image or a contour of a certain intensity of the optical image.

[0021] The compact model can be used for mask synthesis or mask correction. Mask correction includes optical proximity effect correction, sub-resolution assist features, phase shift masks, inverse lithography techniques, and other types of resolution enhancement techniques. In optical proximity effect correction (OPC), the geometric shape of the mask pattern is perturbed based on the predicted results. In sub-resolution assist features, sub-wavelength features are added to or removed from the mask pattern to introduce beneficial diffraction and scattering. In phase shift masks, different mask shapes introduce different amounts of phase shift to introduce beneficial interference in the resulting illumination pattern.

[0022] Figure 3 shows a flowchart for adding probabilistic model properties to a compact model that does not consider local probabilistic variations. This flow is explained using the examples shown in FIGS. 4 and 5. The compact model 310 predicts the location of hot spots (e.g., defects) on the wafer but does not consider the increase in failure rate due to local probabilistic variations. For example, this "probability-unaware" compact model 310 can predict the patterned resist CD as a function of exposure, focus, and mask pattern. It can also predict the failure rate or identify hot spots for a process window (PW) defined by the range of these parameters. The compact model 310 may be a parameterized model that is regression-analyzed against empirical data.

[0023] The compact model 310 may include scanner parameters in an observable PW mask or model such as exposure, focus, and mask bias. These are set to correspond to physically measurable quantities set during experimental lithography exposure. The compact model 310 can also include non-physical model parameters such as chemical blur, inhibitor concentration, or mechanical stress, etc., or parameters in a model that are not observable on the mask or scanner. These cannot be varied in a directly observable manner during lithography exposure, and their parameter coefficients and weights are fitted to the average of observed wafer measurements for different resists or etched patterns.

[0024] Figures 4A and 4B show a simulation of a lithography process using such a compact model 310. In Figure 4A, the linear shape is the mask pattern, and the curves show the resulting printed resist shape on the wafer at different exposures and focus levels, as indicated by the elliptical process window diagram on the right side of Figure 4A. In this example, the process window is a focus blur of + / - 50 nm and an exposure of + / - 3%. The curves in Figure 4A correspond to the points in the PW diagram.

[0025] Model 310 can be regression-analyzed against empirical data as shown in Figure 4B. Figure 4B shows two different cases. The case on the left is for optimal process window conditions, with no change in focus or exposure from the ideal. The left side of Figure 4B shows an actual printed structure on a wafer with no defects. The case on the right is for conditions on the edge of the process window. In this case, the actual printed structure has defects where a fracture exists in the printed line. The results predicted by Model 310 can be improved by comparing the measured results.

[0026] Model 310 in Figure 4 considers exposure and focus variations but does not consider local probabilistic variations. Returning to Figure 3, this probabilistic-ignorant model is modified to consider local probabilistic variations 320, 330, 340. Several model forms or parameters, collectively called probabilistic model properties (SMPs), are added to the compact model 320. Empirical data that reflects the effects of local probabilistic variations are collected 330. The SMPs are regressiond against the empirical data with local probabilistic variations 340. Some kind of statistical local variation on the wafer is used for regression 340. This could be the worst-case CD, a CD variation index, or line edge roughness or features of defect locations.

[0027] Model 310, which does not consider probability theory, defines several observable process parameters, such as scanner exposure, focus, or feature CD on the mask. Model 310 can account for variations in these observable process parameters, such as the scanner exposure being slightly higher or lower than nominal, or there being a slight blur, or the feature CD being slightly larger or smaller than nominal. A compact model 310, which does not consider probability theory, can account for these types of variations.

[0028] In Figure 3, the non-probability-aware model 310 is modified to account for probabilistic variability occurring locally, for example, within a view of a single CDSEM image. The compact model 310 is modified to include these local probabilistic variability, which is done by adjusting these additional SMPs. This adjusts the model morphology so that the new "probability-aware" model 350 morphology predicts not only deterministic variability but also local probabilistic variability. Examples include CDs variating across lines within a local area of ​​a wafer, or CDs variing across multiple repeating patterns.

[0029] The probability-aware Model 350 can incorporate "probability-aware" lithographically non-physical model parameters, or parameters in the model that cannot be observed by the mask or scanner, such as secondary electron density, range of chemical interactions, inhibitor yield, additional chemical blurring, and additional mechanical stress, which cannot be changed during lithography exposure, but whose parameter coefficients and weights are fitted to the statistical variability observed in repeated local wafer measurements for each of several different individual resists or etched patterns.

[0030] For example, Model 310, which does not consider probability theory, can predict the position of a line edge on a wafer. However, due to local probabilistic variability, a probability distribution function actually exists for the position of the line edge. Presumably, the distribution is a Gaussian with an expected position and some standard deviation from this expected position. Model 310, which does not consider probability theory, can predict the expected position but ignores the probability distribution. Model 350, which considers probability theory, takes into account the existence of a probability distribution. It cannot explicitly predict that a distribution exists, but it takes into account the effect of the distribution. For example, it can predict the position of a line edge based on one standard deviation that deviates from the expected position.

[0031] It should be noted that Model 350, while "probability-conscious," does not necessarily have to be probabilistic itself. It can be a deterministic model that always produces the same prediction for the same input, rather than a prediction with some random elements, but the prediction takes into account local probabilistic influences. In this example, Model 350 considers a Gaussian distribution by always predicting line edge positions based on the standard deviation of the probability distribution.

[0032] These variations are localized, occurring over very localized areas such as within the field of view of a CDSEM image, typically having dimensions between 0.5 and 10 μm per side. In some cases, visible variations may exist over 10 × 10 pattern arrays, 20 × 20 pattern arrays, or even 1 × 40 one-dimensional pattern arrays. As a counterexample, exposure and focus blur can also vary, but these are not localized variations because these variations affect a much larger area, for example, 1000 μm per side, or even the entire exposure field on the wafer.

[0033] In other words, “probabilistic” hotspots can be defined as patterns observed on wafers that fail considerably more frequently than would be predicted by traditional “probability-aware” hotspot detection methods. Probabilistic model properties (SMPs) are model properties that correlate with or predict the failure of probabilistic hotspots.

[0034] Figure 5 illustrates the process of Figure 3 using predicted signal intensity images. These signal intensity images may be optical images or represent chemical properties in the resist, such as photoacid concentration. In this example, the left column 510 represents a compact model 310 that is not aware of probability theory, the middle column 540 represents a correction for local probabilistic variability, and the right column 550 represents the resulting probabilistic model 350. The bottom row shows the predicted signal intensity images, and the ellipses in the top row represent the parameters considered within the process window.

[0035] In 510, the compact model 310 is developed with respect to the process window, including exposure and focus variations, but does not consider local probabilistic variations. In 540, SMP (probabilistic param1 in the figure in the row above) is added to the model to account for local probabilistic process variations. They add correction factors to the signal. The resulting signal image is shown in 550. In this example, Corrected image signal = Original image signal + Coefficient * Photoacid gradient signal (1) The photoacid gradient is the gradient of photoacid concentration in the resist after exposure, and the coefficient is a negative or positive parameter determined based on comparison with empirical data. Another example is the use of nonlinear coupling of the original image signal and SMP to produce a modified image signal.

[0036] In this example, the photoacid gradient is an SMP. Other SMPs can also be used. For example, • Photon density or diffuse optical image signal • Nonlinear filtered optical image signal • Acid concentration or acid density • Light-quenching agent concentration or light-quenching agent density • Inhibitor concentration or inhibitor density • Secondary electron concentration or density • Ligand concentration or density • Gradient signal of the optical image • Acid, quencher, or inhibitor signal gradient Log of the gradient of the optical image, acid, quencher, or inhibitor signal. • The square of the gradient of the optical image, acid, quencher, or inhibitor signal. • Mask pattern density • Resist surface tension It may include.

[0037] Figure 6 shows an exemplary set of processes 600 used during the design, verification, and manufacture of products such as integrated circuits to translate and verify design data and instructions representing the integrated circuit. Each of these processes can be structured and made available as multiple modules or operations. The term "EDA" stands for "Electronic Design Automation." These processes begin with the generation of a product idea 610 using information provided by the designer, which is then translated to produce the product using a set of EDA processes 612. When the design is complete, it is tapeped out 634, when the artwork (e.g., geometric patterns) for the integrated circuit is sent to a manufacturing facility to produce a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor dies are manufactured 636, and packaging and assembly processes 638 are performed to produce the finished integrated circuit 640.

[0038] Specifications for a circuit or electronic structure can range from low-level transistor material layouts to high-level description languages. High-level abstractions can be used to design circuits and systems using hardware description languages ​​("HDL") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be converted to logic-level register transfer-level ("RTL") descriptions, gate-level descriptions, layout-level descriptions, or mask-level descriptions. Each low-abstract level, being a less abstract description, adds more useful details to the design description, e.g., more details about the module containing the description. Low-abstract levels, being less abstract descriptions, can be generated by a computer, extracted from a design library, or generated by another design automation process. An example of a specification language in a low-abstract level language that specifies a more detailed description is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each abstraction level is made available for use by the corresponding tool at the layer (e.g., a formal verification tool). The design process can use the sequence shown in Figure 6. The described process is made available by the EDA product (or tool).

[0039] In system design 614, the functionality of the integrated circuit to be manufactured is defined. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or code lines), and cost reduction. Dividing the design into different types of modules or components may be done at this stage.

[0040] During logic design and functional verification 616, modules or components in a circuit are specified in one or more descriptive languages, and the specifications are checked for functional accuracy. For example, components of a circuit may be verified to produce outputs that meet the specifications of the circuit or system being designed. Functional verification can be performed using simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, a special system of components called an "emulator" or "prototyping system" is used to speed up functional verification.

[0041] During synthesis and design for testing (618), the HDL code is converted into a netlist. In some embodiments, the netlist may be a graph structure, where the edges of the graph structure represent the components of the circuit, and the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical products that can be used by EDA products to verify that the integrated circuit performs according to a specific design during manufacturing. The netlist can be optimized for the target semiconductor manufacturing technology. Furthermore, the finished integrated circuit can be tested to verify that the integrated circuit satisfies the requirements of the specification.

[0042] During netlist verification 620, the netlist is checked for compliance with timing constraints and correspondence with the HDL code. During design planning 622, an overall floor plan for the integrated circuit is constructed and timing and top-level routing are analyzed.

[0043] During layout or physical implementation 624, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of circuit components with multiple wires) may be performed, and cells may be selected from a library to enable specific logic functions. As used herein, the term 'cell' can refer to a set of transistors, other components, and interconnects that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or memory functions (e.g., flip-flops or latches). As used herein, a circuit 'block' can refer to two or more cells. Both cells and circuit blocks may be referred to as modules or components, and both are made available as physical structures and in simulation. Parameters such as size are specified for selected cells (based on 'standard cells') and made accessible in a database for use by EDA products.

[0044] During analysis and extraction 626, circuit functionality is verified at the layout level, thereby enabling refinement of the layout design. During physical verification 628, the layout design is checked to ensure that manufacturing constraints such as DRC constraints, electrical constraints, and lithography constraints are correct, and that the circuit functionality conforms to the HDL design specifications. During resolution enhancement 630, the layout geometry is transformed to improve how the circuit design is manufactured.

[0045] During tape-out, the data is generated to be used for the production of lithography masks (after lithography enhancements are applied, if necessary). During mask data preparation 632, the 'tape-out' data is used to produce lithography masks, which are then used to produce the finished integrated circuits.

[0046] The storage subsystem of the computer system (such as the computer system 700 in Figure 7) may be used to store programs and data structures used by some or all of the EDA products described herein, as well as products used for the development of cells for libraries and for the physical and logical designs that use these libraries.

[0047] Figure 7 shows an exemplary machine of computer system 700 in which a set of instructions causing the machine to perform one or more of the methodologies described herein may be executed. In alternative implementations, the machine may be connected to (e.g., network-connected) other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine within the capacity of a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0048] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, server, network router, switch or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify the actions to be taken by that machine. Furthermore, although a single machine is shown, the term “machine” may also be interpreted to include any group of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methodologies described herein.

[0049] An exemplary computer system 700 includes a processing device 702, main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage devices 718, which communicate with each other via a bus 730.

[0050] The processing device 702 represents one or more processors, such as a microprocessor or a central processing unit. More specifically, the processing device may be a composite instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 702 may also be one or more purpose-specific processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), or a network processor. The processing device 702 may be configured to execute instructions 726 that perform the operations and steps described herein.

[0051] The computer system 700 may further include a network interface device 708 that communicates via a network 720. The computer system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD) or cathode ray tube (CRT)), a character / number input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), a graphics processing unit 722, a signal generation device 716 (e.g., a speaker), a graphics processing unit 722, a video processing unit 728, and an audio processing unit 732.

[0052] The data storage device 718 may include a machine-readable storage medium 724 (also called a non-temporary computer-readable medium) in which one or more instruction sets 726 or software are stored that embody one or more of the methodologies or functions described herein. The instructions 726 may also reside entirely or at least partially in the main memory 704 and / or in the processing device 702, which also constitute the computer system 700, the main memory 704, and the machine-readable storage medium.

[0053] In some implementations, Instruction 726 includes an instruction to perform a function corresponding to the Disclosure. Although the machine-readable storage medium 724 is shown in exemplary implementations to be a single medium, the term “machine-readable storage medium” should be understood to include a single or multiple mediums that store one or more instruction sets (e.g., a centralized or distributed database, and / or associated caches and servers). The term “machine-readable storage medium” should also be understood to include any medium that can store or encode instruction sets for machine execution and cause a machine and processing device 702 to perform one or more of the methodologies of the Disclosure. Accordingly, “machine-readable storage medium” should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0054] Some parts of the detailed description above are presented in terms of algorithms and symbolic representations of operations on data bits in computer memory. These descriptions and representations of algorithms are the methods used by those skilled in data processing to most efficiently convey the content of their research to others skilled in the art. An algorithm can be a sequence of operations that produce a desired result. Operations require the physical manipulation of physical quantities. Such quantities can take the form of electrical or magnetic signals that can be stored, synthesized, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, terms, digits, and so on.

[0055] However, it should be noted that all these and similar terms should be in relation to appropriate physical quantities and are merely convenient labels applied to those quantities. As will be apparent from this disclosure, unless otherwise specifically stated, throughout this description certain terms will be understood to refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data, represented as physical (electronic) quantities in the registers and memory of a computer system, to other data, similarly represented as physical quantities in the memory or registers or other such information storage devices of a computer system.

[0056] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for the intended purpose, or it may include a computer that is selectively started or reconfigured by a computer program stored in the computer. Such a computer program may be stored on a computer-readable storage medium, for example, any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each connected to a computer system bus, for example.

[0057] The algorithms and representations presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the program in accordance with the teachings herein, or it may prove that they are convenient for constructing more specialized devices to perform this method. Furthermore, this disclosure does not describe any particular programming language. It will be understood that various programming languages ​​may be used to carry out the teachings of this disclosure as described herein.

[0058] This disclosure may be provided as a computer program product or software which may include a machine-readable medium storing instructions thereon that can be used to program a computer system (or other electronic device) to perform the processes described herein. The machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). For example, machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer) storage media such as read-only memory ("ROM"), random-access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0059] In the aforementioned disclosures, the implementation of the disclosure has been described with reference to specific exemplary implementations of the disclosure. It will be apparent that various modifications may be made therein without departing from the broader intent and scope of the implementation of the disclosure as described in the following claims. Where the disclosure refers to a subset of elements in the singular, two or more elements may be shown in the figures, and the same elements will be named by the same number. Therefore, the disclosure and drawings should be considered illustrative rather than restrictive.

Claims

1. A step of accessing a mask pattern for use in a lithography process to print a pattern onto a wafer, The process involves a processor applying the mask pattern to a deterministic model of the lithography process in order to predict the features of the printed pattern, A method comprising the steps to be applied, Applying the mask pattern to a compact model that predicts the features of the printed pattern, This includes applying a correction to the predicted features from the compact model, wherein the correction takes into account the local probabilistic variability of the features in the printed pattern. A method wherein the compact model is subjected to regression analysis on first empirical data, and the correction is subjected to regression analysis on second empirical data, which includes local probabilistic variability of the predicted features.

2. The method according to claim 1, wherein the compact model does not take into account local probabilistic variability of the features.

3. The method according to claim 1, wherein applying the correction to the predicted features from the compact model comprises (a) a linear combination of the predicted features from the compact model and (b) the correction, the correction being a function of a probabilistic model property that correlates with the local probabilistic variability of the predicted features.

4. The method according to claim 1, wherein applying the correction to the predicted features from the compact model includes a nonlinear coupling of (a) the predicted features from the compact model and (b) the correction, the correction being a function of a probabilistic model property that correlates with the local probabilistic variability of the predicted features.

5. The method according to claim 1, wherein the compact model predicts the features of the printed pattern as a function of exposure, focus, and the mask pattern.

6. Memory for storing instructions, A system comprising a processor coupled to the memory and executing the instruction, wherein the instruction, when executed, Accessing mask patterns for use in lithography processes that print patterns onto wafers, The method involves applying the mask pattern to a deterministic model of the lithography process to predict the features of the printed pattern, wherein the deterministic model considers the local probabilistic variability of the features in the printed pattern, and the deterministic model includes a compact model that predicts the features of the printed pattern as a function of exposure, focus, the mask pattern, and probabilistic model properties, wherein the probabilistic model properties correlate with the local probabilistic variability of the predicted features. A system that causes the processor to perform an operation including: performing a regression analysis of the compact model on empirical data that does not include measurements of the probabilistic model properties.

7. The system according to claim 6, wherein the predicted features of the printed pattern are used for mask synthesis and / or mask correction.

8. The system according to claim 7, wherein the mask pattern includes a mask pattern for the entire die.

9. The system according to claim 6, wherein the local probabilistic variability includes the probabilistic variability within a 10 μm × 10 μm area of ​​the printed pattern.

10. At least one of the aforementioned probabilistic model properties is one of the following: diffuse optical image signal, acid concentration or acid density, quenching agent concentration or quenching agent density, inhibitor concentration or inhibitor density, gradient of optical image, acid, quenching agent, or inhibitor signal, mask pattern density, secondary electron concentration, ligand concentration, and resist surface tension. The compact model predicts hotspots in the printed pattern as a function of the mask pattern. The system according to claim 6.

11. A non-temporary computer-readable medium containing stored instructions, wherein the stored instructions, when executed by a processor, Accessing mask patterns for use in lithography processes that print patterns onto wafers, A non-temporary computer-readable medium, wherein the processor is instructed to perform an operation including applying a deterministic model of the lithography process to the mask pattern in order to predict the features of the printed pattern, wherein the deterministic model predicts the features of the printed pattern as a function of a model property which includes at least one probabilistic model property that correlates with the local probabilistic variability of the predicted features, and the deterministic model is regression-analyzed against empirical data which includes the local probabilistic variability of the predicted features.

12. The non-transient computer-readable medium according to claim 11, wherein the at least one probabilistic model property is one of the following: diffuse optical image signal, acid concentration or acid density, quenching agent concentration or quenching agent density, inhibitor concentration or inhibitor density, gradient of optical image, acid, quenching agent, or inhibitor signal, mask pattern density, secondary electron concentration, ligand concentration, and resist surface tension.

13. The non-transient computer-readable medium according to claim 11, wherein the empirical data includes one of line edge roughness, limit dimension (CD) variation, and worst-case CD.

14. The non-temporary computer-readable medium according to claim 11, wherein the deterministic model predicts hotspots in the printed pattern as a function of the mask pattern.

15. The non-temporary computer-readable medium according to claim 11, wherein the deterministic model predicts the failure rate in the printed pattern as a function of the mask pattern.

16. The non-temporary computer-readable medium according to claim 11, wherein the deterministic model includes a compact model that predicts the features of the printed pattern as a function of exposure, focus, the mask pattern, and the probabilistic model properties.

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