Semiconductor and electronic equipment

Abstract

To provide a semiconductor device for performing a signal transmission based on a pair of valid pulses via a transformer that includes a primary and a secondary winding.SOLUTION: The present invention comprises: a transformer (T1) having a primary and a secondary winding; a drive circuit connected to the primary winding, for applying drive signals (SG1, SG2) to the primary winding; a pulse edge detection circuit connected to the secondary winding, for detecting pulse edges (CPs_out, CPr_out) having occurred in the secondary winding; and a signal generation circuit (3) for outputting one of a set signal (SET) and a reset signal (RESET) in accordance with the polarity of each of a pair of valid pulse edges, the signal generation circuit (3) being characterized in that the polarities of two pulses, in the pair of valid pulse edges, are opposite, and the time interval is within a prescribed time range. Thus, it is possible to reliably output the set and reset signals, as well as effectively eliminate the influences of noise signals.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of electronic circuits, and in particular to signal transmission technology.

Background Art

[0002] A positive or negative pulse received by the primary winding of a transformer can be transmitted to the secondary winding to generate a set signal (SET) or a reset signal (RESET). Patent Document 1 (US6720816 B2) discloses a circuit having the above-described principle. FIG. 1 is a schematic diagram of the circuit configuration of Patent Document 1, and FIG. 2 is a timing diagram of each signal in Patent Document 1. In FIGS. 1 and 2, Us represents the voltage of the secondary winding of the transformer Trf, and Up represents the voltage of the primary winding. The circuit AST generates a drive signal, which is a positive or negative pulse, and the pulse widths are both T, and the pulse period is Tr. K1 and K2 are comparators, and the reference voltages +Uref and -Uref are input thereto, respectively. G2 and G3 are NAND circuits. ZG1 and ZG2 are delay circuits, and a delay τ occurs in both. Also, the output terminals of ZG1 and ZG2 are connected to the S terminal and the R terminal of the RS flip-flop (RS-FF), respectively, and a signal Uout is output from the Q terminal of the RS flip-flop. The signal Uout is a reset signal (i.e., the signal Uout is at a low level) or a set signal (i.e., the signal Uout is at a high level). In Patent Document 1, as shown in FIG. 2, the set signal is triggered based on the rising edge of Us, and the reset signal is triggered based on the falling edge of Us. Thereby, the input signal Uin can be transmitted to the Q terminal of the RS flip-flop with a single winding.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] However, in Patent Document 1, the set signal is triggered based on only one rising edge of Us, and the reset signal is triggered based on only one falling edge of Us. This presents a problem in that it is prone to malfunctions, such as the set signal or reset signal being triggered incorrectly when a rising edge or falling edge is generated by noise.

[0005] This invention was made in view of the above-mentioned problems, and aims to provide a semiconductor device that can solve these problems, effectively eliminate the influence of noise signals, and reliably output set signals and reset signals. [Means for solving the problem]

[0006] According to one embodiment of the present invention, the semiconductor device includes a transformer having a primary winding and a secondary winding, a drive circuit connected to the primary winding and applying a drive signal to the primary winding, a pulse edge detection circuit connected to the secondary winding and detecting pulse edges generated in the secondary winding, and a circuit that outputs one of a set signal and a reset signal according to the polarity of each pulse edge of a pair of effective pulse edges. do Includes a signal generation circuit The signal generation circuit is the The polarity of two of the effective pulse edges is reversed. The two pulse edges The time interval is within a predetermined time range. In this case, one of the set signal and the reset signal is output. It is characterized by the following: [Effects of the Invention]

[0007] According to the present invention, a set signal or a reset signal is output on the secondary winding side of the transformer according to the polarity of each pulse in a pair of effective pulses, so that a set signal or a reset signal can be reliably output and the influence of noise signals can be effectively eliminated. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic diagram of the circuit configuration described in Patent Document 1. [Figure 2] Figure 2 is a timing chart of each signal in Patent Document 1. [Figure 3] Figure 3 is a schematic diagram of the semiconductor device according to Embodiment 1 of the present invention. [Figure 4] Figure 4 is a schematic diagram of the signal generation circuit 3 of the present invention. [Figure 5] Figure 5 shows the timing chart of the signals in each part of the semiconductor device 100 of the present invention. [Modes for carrying out the invention]

[0009] Referring to the drawings, the aforementioned and other features of this application will become clear from the following description. While the specification and drawings specifically disclose certain embodiments of this application, and this application shows some embodiments to which the principles of this application can be applied, it should be understood that this specification is not limited to the embodiments described herein, but rather includes all modifications, variations, and equivalents that fall within the scope of the appended rights. The embodiments of the present invention will be described in detail below with reference to the figures.

[0010] (First Embodiment) Figure 3 is a schematic diagram of the semiconductor device of this embodiment. As shown in Figure 3, the semiconductor device 100 comprises a transformer T1, a drive circuit 1, a pulse waveform detection circuit 2, and a signal generation circuit 3. The transformer T1 has a primary winding P and a secondary winding S. The drive circuit 1 is connected to the primary winding P, and a drive signal is applied to the primary winding P. The drive signal is generated, for example, based on a first input signal SG1 or a second input signal SG2. The pulse edge detection circuit 2 is connected to the secondary winding S and detects the pulse edge generated in the secondary winding S. For example, the pulse edge detection circuit 2 can output a detection result, CPs_out or CPr_out, where CPs_out is a pulse edge indicating that a falling edge has been detected, and CPr_out represents a pulse edge that has detected a rising edge.

[0011] In the present application, although a pulse edge can be generated in the secondary winding S by the drive signal output from the drive circuit 1, there is a possibility that a pulse edge is generated in the secondary winding S due to a noise signal mixed in the primary winding P or the secondary winding S. The signal generation circuit 3 outputs one of a set signal (SET) and a reset signal (RESET) according to the polarity of each pulse edge in a pair of valid pulse edges. Here, two pulse edges among the pair of valid pulse edges satisfy two conditions. Condition 1: The polarities of the two pulse edges are opposite. For example, one pulse edge is a rising pulse edge and the other pulse edge is a falling pulse edge. Condition 2: The time interval T0 between the two pulses is within a predetermined time range [DL1, DL3]. For example, DL1 < T0 ≦ DL3. Further, when the time interval between the two pulse edges is outside the predetermined time range [DL1, DL3], for example, T0 < DL1 or DL3 < T0, the two pulse edges are not a pair of valid pulse edges. In the first embodiment of the present application, since the set signal or the reset signal is determined from two pulse edges with opposite polarities, the determination result is more reliable than when determined from only one rising pulse edge or one falling pulse edge. Further, in the present application, if the interval between pulse edges due to a short noise signal or a long noise signal is outside the predetermined time range, the influence of the noise signal can be effectively removed.

[0012] In this embodiment, as shown in Figure 3, the drive circuit 1 includes a first drive circuit 11 and a second drive circuit 12. The first drive circuit 11 is connected to one end of the primary winding P of the transformer T1, and a first drive signal is input to the primary winding P. The second drive circuit 12 is connected to the other end of the primary winding P, and a second drive signal is input to the primary winding P. The first drive signal and the second drive signal may be pulse signals in the same direction; for example, they may both be forward pulse signals, or they may both be negative pulse signals. As a result, the first drive signal and the second drive signal can form a reverse current in the primary winding P. The first drive signal is generated based on the first input signal SG1, which is generated in accordance with the rising edge of the input signal Vsg, the forward pulse duration of the first input signal SG1 is Tsg1, and the duration of the first drive signal is Tsg1. The second drive signal is generated based on the second input signal SG2, which is generated in accordance with the falling edge of the input signal Vsg, the forward pulse duration of the second input signal SG2 is Tsg2, and the duration of the second drive signal is Tsg2. In this embodiment, Tsg1 and Tsg2 may or may not be equal. The input signal Vsg can be generated by an external circuit of the semiconductor device 100, and a method for generating the first input signals SG1 and SG2 based on the input signal Vsg can be found in related technologies. In this embodiment, as shown in Figure 3, the first drive circuit 11 includes transistors Q1 and Q3, which can form a complementary metal oxide semiconductor (CMOS) structure, the first input signal SG1 can be input to the input terminal of this CMOS structure, and the first drive signal can be output from the output terminal of this CMOS structure. The second drive circuit 12 may include transistors Q2 and Q4, which can form a complementary metal oxide semiconductor (CMOS) structure, the second input signal SG2 can be input to the input terminal of this CMOS structure, and the second drive signal can be output from the output terminal of this CMOS structure. Note that the configurations of the first drive circuit 11 and the second drive circuit 12 are not limited to these.

[0013] The pulse edge detection circuit 2 can include a first comparator CPs and a second comparator CPr. Resistors R1 and R2 are respectively connected to both ends of the secondary winding S, and the connection point of resistor R1 and the secondary winding S is connected to the "-" end of the first comparator CPs and the "+" end of the second comparator CPr. Thereby, the voltage generated in the secondary winding S can be introduced to the "-" end of the first comparator CPs and the "+" end of the second comparator CPr. Also, resistor R2 may be connected in parallel with capacitor C1. Resistors R3, R4, and R5 are connected in series. One end of resistor R3 is connected to one end of resistor R1 and is connected to the positive voltage of a control power supply (not shown). One end of resistor R5 is connected to one end of resistor R2 and is connected to the negative voltage of a control power supply (not shown). The connection point of resistors R3 and R4 is connected to the "-" end of the second comparator CPr, and the connection point of resistors R4 and R5 is connected to the "+" end of the first comparator CPs. Thereby, a first reference voltage Ref_L can be input to the "+" end of the first comparator CPs, and a second reference voltage Ref_H can be input to the "-" end of the second comparator CPr. When the falling pulse voltage generated in the secondary winding S is smaller than Ref_L, the output end of the first comparator CPs outputs a high-level signal. When the rising pulse voltage generated in the secondary winding S is larger than Ref_H, the output end of the second comparator CPr outputs a high-level signal. When the voltage along the pulse generated in the secondary winding S is between the second reference voltage Ref_H and the first reference voltage Ref_L, the output ends of both the first comparator CPs and the second comparator CPr output low-level signals. Thereby, a pulse edge with a small voltage (for example, due to the generation of a noise signal) does not cause the first comparator CPs and the second comparator CPr to output a high-level signal.

[0014] FIG. 4 is a schematic diagram of the signal generation circuit 3. As shown in FIG. 4, the signal generation circuit 3 includes a first signal latch section 31, a first time delay section DELAY1, a second signal latch section 32, a second time delay section DELAY2, a third signal latch section 33, a third time delay section DELAY3, a fourth signal latch section 34, a fourth time delay section DELAY4, and a fifth signal latch section FF5. The first signal latch unit 31 generates a first latch signal, for example, signal FFs2_Q, in response to a falling pulse edge in the secondary winding S. The first time delay unit DELAY1 delays the first latch signal FFs2_Q in response to a falling pulse edge in the secondary winding S, and generates a first delay signal for the first signal latch unit 31 with a time length DL1 smaller than the time length (e.g., the time length Tsg1 of the first drive signal SG1) of the drive signal. The second signal latch unit 32 generates a second latch signal, for example, signal FFr2_Q, in response to a rising pulse edge in the secondary winding S. The second time delay unit DELAY2 delays the second latch signal FFr2_Q in response to a rising pulse edge in the secondary winding S, and generates a second delay signal for the second signal latch unit 32 with a time length DL2 smaller than the time length (e.g., the time length Tsg2 of the second drive signal SG2) of the drive signal. The third signal latch unit 33 generates a third latch signal, for example, FFs4_Q, in response to the first latch signal, the second delay signal, and the third delay signal. The third time delay unit DELAY3 generates a time length DL3 larger than the time length (e.g., the time length Tsg1 of the first drive signal SG1) of the drive signal in response to a rising pulse edge in the secondary winding S. The fourth signal latch unit 34 generates a fourth latch signal, for example, FFr4_Q, in response to the second latch signal, the first delay signal, and the fourth delay signal. The fourth time delay unit DELAY4 generates a time length DL4 larger than the time length (e.g., the time length Tsg2 of the second drive signal SG2) of the drive signal in response to a falling pulse edge in the secondary winding S. The fifth signal latch unit FF5 outputs a set signal (SET) or the reset signal (RESET) based on the third latch signal and the fourth latch signal. For example, the fifth signal latch unit FF5 is an RS flip-flop, the set terminal S of the fifth signal latch unit FF5 receives the third latch signal, and the reset terminal R of the fifth signal latch unit FF5 receives the fourth latch signal.

[0015] As shown in Figure 4, the first signal latch unit 31 includes a first RS flip-flop FFs1 and a first D flip-flop FFs2. The first time delay unit DELAY1 delays the signal output from the Q terminal of the first RS flip-flop FFs1 and inputs it to the R terminal of the first RS flip-flop FFs1, causing the first delayed signal to be output from the Q terminal of the first RS flip-flop FFs1. The second signal latch section 32 includes a second RS flip-flop FFr1 and a second D flip-flop FFr2. The second time delay section DELAY2 delays the signal output from the Q terminal of the second RS flip-flop FFr1 and inputs it to the R terminal of the second RS flip-flop FFr1, causing the second delayed signal to be output from the Q terminal of the second RS flip-flop FFr1. The third signal latch section 33 includes a first AND circuit AND1, a third D flip-flop FFs3, and a third RS flip-flop FFs4. The first AND gate AND1 receives the second delay signal FFr1_Q and the first latch signal FFs2_Q, and the output terminal of the first AND gate AND1 is connected to the clock input terminal ck of the third D flip-flop FFs3. For example, the Q terminal of the 3D flip-flop FFs3 and the S terminal of the 3RS flip-flop FFs4 are directly connected to each other. The fourth signal latch section 34 includes a second AND circuit AND2, a fourth D flip-flop FFr3, and a fourth RS flip-flop FFr4. The second AND gate AND2 receives the first delay signal FFs1_Q and the second latch signal FFr2_Q, and the output terminal of the second AND gate AND2 is connected to the clock input terminal ck of the fourth D flip-flop FFr3. The Q terminal of the 4th D flip-flop FFr3 and the S terminal of the 4th RS flip-flop FFr4 are connected, and for example, they are connected via the 4th knot circuit NOT4. The Q terminal of the 4th D flip-flop FFr3 is connected to the input terminal of the 3rd time delay section DELAY3 and the input terminal of the 1st knot circuit NOT1. The output terminal of the 3rd time delay section DELAY3 and the output terminal of the 1st knot circuit NOT1 are connected to the input terminals of the 1st OR circuit OR1, respectively. The output terminal of the 1st OR circuit OR1 is connected to the R terminal of the 3rd RS flip-flop FFs4. The Q terminal of the 3D flip-flop FFs3 is connected to the input terminal of the 2nd knot circuit NOT2. The output terminal of the 2nd knot circuit NOT2 is connected to the input terminal of the 4th time delay section DELAY4 and the input terminal of the 3rd knot circuit NOT3. The output terminal of the 4th time delay section DELAY4 and the output terminal of the 3rd knot circuit NOT3 are each connected to the two input terminals of the 2nd OR circuit OR2. The output terminal of the 2nd OR circuit OR2 is connected to the R terminal of the 4th RS flip-flop FFr4.

[0016] Figure 5 shows the timing chart of the signals in each part of the semiconductor device 100 of the present invention. Next, the operating principle of the semiconductor device 100 according to an embodiment of the present invention will be explained according to the timing chart shown in Figure 5. As shown in Figure 5, when the input signal Vsg changes from a low level to a high level at time t1, a rising pulse edge is generated, triggering the first input signal SG1, which is then input to the gates of transistors Q1 and Q3, i.e., Qg1 and Qg3. The duration of the first input signal SG1 is Tsg1. The rising edge of the first input signal SG1 is generated as a falling pulse edge in the secondary winding S of the transformer T1, i.e., as shown in T1(S) in Figure 5. Since the voltage generated by this falling pulse is greater in the negative direction than the first reference voltage Ref_L (as shown in "Cpr,CPs input" in Figure 5), the output terminal of the first comparator CPs outputs a forward pulse (as shown in CPs_out in Figure 5). The output CPs_out of the first comparator CPs is input to the set terminal S of the first RS flip-flop FFs1. As shown in the signal FFs1_Q in Figure 5, the output signal of the Q terminal of the first RS flip-flop FFs1 becomes high level. This high-level signal is input to the clock input terminal ck of the first D flip-flop FFs2. As shown in the FFs2_Q in Figure 5, the output signal FFs2_Q of the Q terminal of the first D flip-flop FFs2 changes from low level to high level. Furthermore, the signal FFs1_Q passes through the first time delay section DELAY1, and after a delay time DL1 has elapsed, it enters the reset terminal R of the first RS flip-flop FFs1, causing FFs1_Q to become low level. Therefore, the duration of the high level of signal FFs1_Q is DL1, meaning that signal FFs1_Q becomes the first delayed signal. The signal FFs1_Q is input to one input terminal of the second AND circuit AND2, and the signal FFr2_Q output from the Q terminal of the second D flip-flop FFr2 is input to the other input terminal of the second AND circuit AND2. Since the signal FFr2_Q still maintains a high level, the signal output by the second AND circuit AND2 is also high level, and this high level has a time length of DL1 from time t1. The high level of the AND2 output causes the output signal FFr3_Q at the Q terminal of the fourth D flip-flop FFr3 to change from a low level to a high level. This high-level signal passes through the first knot circuit NOT1, the third time delay section DELAY3, and the first OR circuit OR1, causing the signal at the reset terminal R of the RS flip-flop FFs4 to become low level. This low-level signal is present from time t1 and has a duration of DL3.

[0017] As shown in Figure 5, at time t2, the falling edge of the first input signal SG1 becomes the rising pulse edge in the secondary winding S of transformer T1 shown at T1(S). Since the voltage generated by this rising pulse is greater than the second reference voltage Ref_H (shown as "Cpr,CPs_input" in Figure 5), the output terminal of the second comparator CPr outputs a forward pulse (shown as CPr_out in Figure 5). The output signal CPr_out of the second comparator is triggered when the output signal of the Q terminal of the second RS flip-flop FFr1 (shown as FFr1_Q in Figure 5) becomes high level from time t2. This high-level signal is input to the clock input terminal ck of the second D flip-flop FFr2, causing the output signal of the Q terminal of the second D flip-flop FFr2 (shown as FFr2_Q in Figure 5) to change from high level to low level. The signal FFr1_Q passes through the second time delay section DELAY2, and after a delay time DL2, it enters the reset terminal R of the second RS flip-flop FFr1. As a result, the signal FFr1_Q becomes low level, and the duration of the high level of the signal FFr1_Q is DL2, meaning that the signal FFr1_Q becomes a second delayed signal. Furthermore, the signal FFr1_Q is input to one input terminal of the first AND gate AND1, and the signal FFs2_Q output from the Q terminal of the first D flip-flop FFs2 is input to the other input terminal of the first AND gate AND1. Here, since the signal FFs2_Q still maintains a high level, the signal output from the first AND gate AND1 becomes high level, and this high level has a time length DL2 from time t2. The high level of the output of the first AND circuit AND1 causes the output signal FFs3_Q of the Q terminal of the third D flip-flop FFs3 to change from a low level to a high level. This high level is input to the set terminal S of the third RS flip-flop FFs4, and the signal FFs4_Q of the output terminal Q of the third RS flip-flop FFs4 changes from a low level to a high level at time t2. The signal FF5_Q of the terminal Q of the fifth signal latch FF5 changes from a low level to a high level at time t2, meaning that signal FF5_Q becomes the set signal output by the semiconductor device 100 in Figure 3. Signal FF5_Q may also be output to the driver DRV to form a high-level gate voltage.

[0018] If the time interval between time t2 and t1, when the secondary winding S of transformer T1 generates a forward pulse, is greater than DL3, the reset terminal signal FFs4_R of the third RS flip-flop FFs4 returns to a high level, causing the signal FFs4_Q to remain at a low level. In this case, this forward pulse is considered to be due to a noise signal. Therefore, the delay time DL3 of the third time delay unit DELAY3 can shield a pair of pulse edges with a long interval due to a noise signal. Also, the delay time DL1 of the first time delay unit DELAY1 can shield a pair of pulse edges with a short time interval (i.e., a time interval of less than DL1) due to a noise signal. As a result, by providing the first time delay unit and the third time delay unit, a pair of effective pulse edges with a time interval within a predetermined time range (for example, the predetermined time range is [DL1, DL3]) can be identified, and it can be determined that the input signal is SG1.

[0019] As shown in Figure 5, at time t3, the input signal Vsg changes from a high level to a low level, triggering the second input signal SG2, which is then input to the gates of transistors Q2 and Q4, i.e., Qg2 and Qg4. Here, the time duration of the second input signal SG2 is Tsg2. At time t3, the secondary winding S of transformer T1 generates a rising pulse edge; however, for explanations of each signal thereafter, please refer to the related explanation at time t2. As shown in Figure 5, at the falling edge of the second input signal SG2 at time t4, a falling pulse edge occurs in the secondary winding S of transformer T1, i.e., as shown in T1(S). For explanations of each signal thereafter, please refer to the explanation for time t1.

[0020] At time t4, terminal Q of the fourth RS flip-flop FFr4 is output to a high level, and the signal FF5_Q of terminal Q of the fifth signal latch FF5 changes from a high level to a low level. In other words, signal FF5_Q becomes the reset signal output by the semiconductor device 100 in Figure 3. Signal FF5_Q is output to the driver to form a low-level gate voltage. Similar to the first input signal SG1, by providing a second time delay section DELAY2 and a fourth time delay section DELAY4, it is possible to identify a pair of effective pulse edges with a time interval within a predetermined time range (for example, a predetermined time range of [DL2, DL4]), and determine that the input signal is SG2. In this way, pulse edges caused by noise signals with short time intervals (for example, time intervals less than DL2) or long time intervals (for example, time intervals greater than DL4) can be shielded.

[0021] In Embodiment 1 of the present invention, on the secondary winding side of a transformer, a set signal or a reset signal is output based on the polarity of each pulse in a pair of effective pulse edges. Since the two pulses in this pair of effective pulse edges have opposite polarities and the time interval is within a predetermined time range, the set signal or reset signal is determined based on the two pulse edges with opposite polarities. Therefore, the determination result of the present invention is more reliable than determination based on only one rising edge or one falling edge, and the influence of noise signals can be effectively eliminated because the interval between pulse edges due to short-duration noise or long-duration noise signals is outside the predetermined time range.

[0022] (Second Embodiment) Embodiment 2 of the present invention provides an electronic device that includes the semiconductor device 100 of Embodiment 1 and integrates it. The electronic device may further include an input circuit for generating an input signal Vsg. The electronic device may also include a backend circuit that supplies a gate voltage generated based on a set signal or reset signal output from the semiconductor device 100 to the backend circuit, thereby controlling the on or off state of a transistor in the backend circuit. According to Embodiment 2 of the present invention, the influence of noise signals can be effectively eliminated, the accuracy of reset signals and set signals can be improved, and the reliability of electronic equipment can be enhanced.

[0023] While the present application has been described above in relation to specific embodiments, those skilled in the art should recognize that these descriptions are illustrative and do not limit the scope of protection of the present application. Those skilled in the art can make various modifications and alterations to the present application based on its spirit and principles, and these modifications and alterations also fall within the scope of the present application. [Explanation of Symbols]

[0024] 1. Drive circuit 2. Pulse edge detection circuit 3. Signal generation circuit 11. First drive circuit 12. Second drive circuit 31 First signal latch section 32 Second signal latch section 33 Third signal latch section 34. Fourth signal latch section FF5 Fifth Signal Latch Unit 100 Semiconductor Equipment C1 Capacitor CPr, CPs comparator AND1~2 AND circuit DELAY1~4 Time Delay Section FFr1, FFr4, FFs1, FFs4 RS flip-flops FFr2~3, FFs2~3 D flip-flops NOT1-4 Knot Circuit OR1~2 OR circuit Q1-4 Transistors R1~R5 Resistors T1 Transformer

Claims

1. A transformer equipped with a primary winding and a secondary winding, A drive circuit connected to the primary winding and applying a drive signal to the primary winding, A pulse edge detection circuit connected to the secondary winding for detecting pulse edges generated in the secondary winding, Includes a signal generation circuit that outputs either a set signal or a reset signal depending on the polarity of each pulse edge of a pair of effective pulse edges, The signal generation circuit is a semiconductor device that outputs one of the set signal and the reset signal when the polarity of two of the effective pulse edges is reversed and the time interval between the two pulse edges is within a predetermined time range.

2. The aforementioned drive circuit includes a first drive circuit and a second drive circuit, The first drive circuit is connected to one end of the primary winding and inputs a first drive signal to the primary winding. The semiconductor device according to claim 1, wherein the second drive circuit is connected to the other end of the primary winding and inputs a second drive signal to the primary winding.

3. The aforementioned signal generation circuit is A first signal latch unit that generates a first latch signal in response to the falling edge of the pulse, A first time delay unit, which delays the first latch signal in response to the falling edge of the pulse edge and supplies it to the first signal latch unit, thereby causing the first signal latch unit to generate a first delayed signal having a time length shorter than the time length of the drive signal, A second signal latch unit generates a second latch signal in response to the rising edge of the pulse, A second time delay unit, which delays the second latch signal and supplies it to the second signal latch unit in response to the rising edge of the pulse, thereby causing the second signal latch unit to generate a second delayed signal having a time length shorter than the time length of the drive signal, A third signal latch unit that generates a third latch signal in response to the first latch signal, the second delay signal, and the third delay signal, A third time delay unit that generates the third delay signal having a time length longer than the time length of the drive signal in response to the rising edge of the pulse edge, A fourth signal latch unit that generates a fourth latch signal in response to the second latch signal, the first delay signal, and the fourth delay signal, A fourth time delay unit that generates the fourth delay signal having a time length longer than the time length of the drive signal in response to the falling edge of the pulse edge, The semiconductor device according to claim 1, further comprising: a fifth signal latch unit that outputs the set signal or the reset signal in response to the third latch signal and the fourth latch signal.

4. The fifth signal latch is an RS flip-flop, The set terminal of the fifth signal latch unit receives the third latch signal. The semiconductor device according to claim 3, wherein the reset terminal of the fifth signal latch unit receives the fourth latch signal.

5. The third signal latch section includes a first AND circuit, a third D flip-flop, and a third RS flip-flop. The first AND circuit receives the second delay signal and the first latch signal, and the output terminal of the first AND circuit is connected to the clock input terminal of the third D flip-flop. The semiconductor device according to claim 3, wherein the Q terminal of the third D flip-flop is connected to the S terminal of the third RS flip-flop.

6. The fourth signal latch section includes a second AND circuit, a fourth D flip-flop, and a fourth RS flip-flop. The second AND circuit receives the first delay signal and the second latch signal, and the output terminal of the second AND circuit is connected to the clock input terminal of the fourth D flip-flop. The semiconductor device according to claim 5, wherein the Q terminal of the fourth D flip-flop is connected to the S terminal of the fourth RS flip-flop.

7. The semiconductor device according to claim 6, wherein the Q terminal of the fourth D flip-flop is connected to the input terminal of the third time delay unit and the input terminal of the first NOT circuit, the output terminal of the third time delay unit and the output terminal of the first NOT circuit are connected to the input terminal of the first OR circuit, and the output terminal of the first OR circuit is connected to the R terminal of the third RS flip-flop.

8. The Q terminal of the third D flip-flop is connected to the input terminal of the second NOT circuit. The semiconductor device according to claim 6, wherein the output terminal of the second NOT circuit is connected to the input terminal of the fourth time delay unit and the input terminal of the third NOT circuit, the output terminal of the fourth time delay unit and the output terminal of the third NOT circuit are connected to the input terminal of the second OR circuit, and the output terminal of the second OR circuit is connected to the R terminal of the fourth RS flip-flop.

9. An electronic device comprising a semiconductor device according to any one of claims 1 to 8.

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