control system

Abstract

A control device (100) having a processing unit (91) equipped with a multicore processor having multiple cores (4), the control device (100) having a non-volatile memory (94) which is a storage unit that stores log information including at least information identifying each of the multiple cores (4) and the processing content by each of the multiple cores (4) each time each of the multiple cores (4) accesses a pre-configured memory (92), at each interrupt timing, or at each pre-configured period.

Description

Technical Field

[0001] This disclosure relates to , regulation a control system.

Background Art

[0002] In industrial machines such as machine tools equipped with numerical control devices and robots equipped with control devices, problems may occur during software processing. When a problem occurs, early recovery is necessary. However, due to the multifunctionality and high functionality of machine tools and industrial machines, the machines have become more complex, and the occurrence of problems that are difficult to identify the cause early is increasing.

[0003] In addition, the numerical control device itself has been highly functionalized so that multiple processes can be performed simultaneously, making it difficult to reproduce and investigate problems. In order to recover such problems early, it may be necessary to connect to the machine at the site where the problem occurred to investigate the cause. However, for example, since the development base and the site are physically separated, operators may not be able to respond flexibly. As a solution to this problem, there is a method of recording the processing data of the machine operating at the site in a set with preset recording conditions. According to this method, when a problem occurs, by utilizing the recorded processing data, even if the problem cannot be reproduced, it is possible to flexibly investigate the cause of the machine at the site.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, the method disclosed in Patent Document 1 does not take into account situations where a large number of tasks operate in a complex manner, for example, in a control device having multiple multi-core processors, each containing multiple cores. In such situations, when investigating the cause of a malfunction, it is not possible to quickly grasp, for example, the processing content before and after data processing and the timing of processing across multiple cores.

[0006] This disclosure is made in view of the above, and provides control that can quickly investigate the cause of a problem, taking into account the architecture of a multicore processor including multiple cores. system The objective is to obtain. [Means for solving the problem]

[0007] To solve the aforementioned problems and achieve the objectives, the control related to this disclosure system It features a multi-core processor with multiple cores. ,Ko The system has a storage unit that stores log information, which includes at least information identifying A and the processing details of the core, each time the core accesses a pre-configured memory, at each interrupt timing, or at each pre-configured period of time. The system comprises a control device and an external processing device connected to the control device. When the control system sets the conditions for recording log information and reads log information recorded in the storage unit from the external processing device, it performs user authentication and allows only authenticated users to read log information from the storage unit. . [Effects of the Invention]

[0008] Control related to this disclosure system This has the effect of enabling rapid root cause analysis, taking into account the architecture of multi-core processors that include multiple cores. [Brief explanation of the drawing]

[0009] [Figure 1] Diagram showing the configuration of the control device according to Embodiment 1 [Figure 2] A diagram showing an example of log information for the control device according to Embodiment 1. [Figure 3] A diagram showing an example of log information for the control device according to Embodiment 1. [Figure 4] This figure shows an example of debugging between cores in the processing unit of the control device according to Embodiment 1. [Figure 5] A diagram showing an example of log information recording for the control device according to Embodiment 1. [Figure 6] This figure shows an example of continuous data writing to memory in the control device according to Embodiment 1. [Figure 7] A diagram showing an example of the processing timing in the control device according to Embodiment 1. [Figure 8] This figure shows an example of parallel processing of the same process by multiple multicore processors in a control device according to a first modified example of Embodiment 1. [Figure 9] This figure shows an example of log information recording in a control device according to a second modified example of Embodiment 1. [Figure 10] Diagram showing the configuration of the control system according to Embodiment 2 [Figure 11] A diagram showing the configuration of a control system according to a modified example of Embodiment 2. [Figure 12] This figure shows an example of a debug screen displayed on an external processing unit of a control system according to a modified example of Embodiment 2. [Figure 13] Diagram showing the configuration of the control system according to Embodiment 3 [Modes for carrying out the invention]

[0010] The following describes embodiments The system I will explain your system in detail based on the diagrams.

[0011] Embodiment 1. FIG. 1 is a diagram showing the configuration of the control device according to Embodiment 1. FIG. 1 shows an example in the case where a processing circuit 93 included in a control device 100 according to Embodiment 1 is composed of a processing unit 91 and a memory 92. When the processing circuit 93 is composed of the processing unit 91 and the memory 92, each function of the processing circuit 93 is realized by software, firmware, or a combination of software and firmware. The software or firmware is described as a program and stored in the memory 92. In the processing circuit 93, the processing unit 91 reads and executes the program stored in the memory 92, thereby realizing each function. That is, the processing circuit 93 includes the memory 92 for storing a program in which the processing of the control device 100 is ultimately executed. Also, these programs can be said to cause a computer to execute the procedures and methods of the control device 100. The control device 100 includes a non-volatile memory 94, which is a storage unit that stores at least log information including information for identifying core 4 and the processing content by core 4 each time core 4 accesses a preset memory, at each interrupt timing, or at each preset period. The processing unit 91 includes a multi-core CPU (Central Processing Unit) 1 having four cores 4, a local memory 2 used as a work area by the multi-core CPU 1 during execution of processing, and a storage unit 3 in which instructions to be executed in the multi-core CPU 1 are stored. The processing is executed by the multi-core CPU 1 executing the instructions stored in the storage unit 3 using the local memory 2 as a work area. In the control device 100 according to Embodiment 1, the multi-core CPU 1 has four cores 4, and each core 4 accesses the memory 92 in which data is stored by the processing. Here, a configuration in which the multi-core CPU 1 has four cores 4 is taken as an example, but the number of cores 4 possessed by the multi-core CPU 1 is not limited to four.

[0012] Here, the processing unit 91 equipped with the multi-core CPU 1 is taken as an example. However, the processing unit 91 may be configured to include a processing device, an arithmetic device, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor), etc. Also, the memory 92 corresponds to, for example, non-volatile or volatile semiconductor memories such as RAM (Random Access Memory), flash memory, EPROM (Erasable Programmable ROM), and EEPROM (registered trademark) (Electrically EPROM). Further, for the non-volatile memory 94, for example, non-volatile semiconductor memories such as flash memory or writable disk-type storage media can be applied. For example, for the non-volatile memory 94, writable types among various disk-type storage media such as magnetic disks, flexible disks, optical disks, compact disks, mini-disks, or DVDs (Digital Versatile Discs) can be applied.

[0013] When the processing circuit 93 included in the control device 100 is configured with dedicated hardware, the processing circuit 93 corresponds to, for example, a single circuit, a composite circuit, a programmed processor, a parallel-programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination thereof. Each function of the control device 100 may be realized by the processing circuit 93 according to function types, or all functions may be realized together by the processing circuit 93. Note that for each function of the control device 100, a part may be realized by dedicated hardware and a part may be realized by software or firmware. Thus, the processing circuit 93 can realize each of the above functions by dedicated hardware, software, firmware, or a combination thereof.

[0014] Figures 2 and 3 show examples of log information for the control device according to Embodiment 1. Figure 2 shows an example of log information used for processing confirmation in each core 4, and Figure 3 shows an example of log information used when checking values.

[0015] Log information includes, for example, when a process that was previously handled sequentially is executed on multiple cores, information indicating when and which address each core accessed, as well as the value of the address accessed by that core. Furthermore, since there may be multiple addresses accessed within a specific task, the log information may also record, for example, the source code line or function.

[0016] Time 61 is the numerical control time at the start of execution of a pre-set process, and for example, the year, month, day, second, millisecond, and microsecond of the start of execution are recorded in the format yy.mm.dd.ss.mm.uu. Execution core identifier 62 records an identifier indicating core 4 that is executing the process. Task identifier 63 records the identifier of a task, such as interpolation processing. Task identifier 63 is recorded in the format "x_y" with a main identifier x and a sub-identifier y. The inclusion of the sub-identifier y in task identifier 63 makes it possible to confirm whether or not it is the task on the side that was split. Access address 64 is a value indicating the address accessed by the relevant function or process, and if the relevant function or process accesses multiple addresses, multiple values ​​indicating each of the multiple addresses are recorded. Value 65 records the numerical value recorded or read by accessing the address. Line 66 records a value indicating the line number where the process was performed in order to identify which process it is.

[0017] When recording log information, data is acquired using a data acquisition function for each pre-configured process for tasks that require detailed review, and the data is saved in a table. Then, a pre-configured data acquisition task acquires a specified, pre-configured address value and data at regular intervals. Alternatively, interrupts are generated at regular intervals to acquire the address, process value, and execution line of the process being executed by each execution core.

[0018] Figure 4 shows an example of inter-core debugging within the processing unit of the control device according to Embodiment 1. When an access occurs to specific data recorded in memory 92 in each core 4, or when a specific instruction program is executed in each core 4, an interrupt is generated for each core 4.

[0019] Figure 5 shows an example of log information recording by the control device according to Embodiment 1. As shown in Figure 5, the core 4 that receives an interrupt records log information such as information indicating which core 4 performed the access processing for specific data recorded in memory 92 or which core 4 executed the instruction program, the name or address of the data to be accessed, and the timing or time when the data was accessed. The log information data may be temporarily stored in memory 92 and then written to non-volatile memory 94 or external storage, or it may be written directly to non-volatile memory 94 or external storage. Figure 5 shows the state in which the log information data is temporarily stored in memory 92. By analyzing the recorded log information, it is possible to determine which core 4 accessed the data when it was accessed by multiple cores 4, and which core 4 executed the program instruction, making debugging and troubleshooting easier.

[0020] Figure 6 is a diagram illustrating an example of continuous data writing to memory in the control device according to Embodiment 1. Figure 6 shows a state in which core 4 continuously records data in memory 92. As shown in Figure 6, when data is continuously or periodically recorded in memory 92, if another core 4 overwrites data while a specific core 4 is writing data to be recorded, data inconsistency may occur. Therefore, when continuous data is recorded periodically, the timing of the log information recording process on each core 4 is synchronized, for example, before or immediately after the execution of analysis processing or interpolation processing, so that the data recorded by each core 4 does not overlap, thereby guaranteeing the state of the recorded data. In this way, when continuous data is recorded periodically, log information is stored in non-volatile memory 94 at predetermined intervals. The "×" mark in Figure 6 indicates that data overwriting by other core 4 is prohibited while a specific core 4 is continuously writing data. Figure 7 is a diagram illustrating an example of processing timing in the control device according to Embodiment 1. Figure 7 shows an example of recording log information before the execution of analysis processing or interpolation processing. By recording log information before executing analysis or interpolation processing, it is possible to prevent the log information from being overwritten by interrupts during machine tool control processing, screen display, and communication processing.

[0021] Figure 8 shows an example of parallel processing of the same process by multiple multicore processors in a control device according to a first modified example of Embodiment 1. Figure 8 shows a state in which data of information to be recorded in non-volatile memory 94 or external storage is temporarily stored in memory 92. In numerical control, functional safety is achieved by performing the same process across different CPUs and different operating systems and performing cross-checks. In Figure 8, one of the multicore CPUs 1 is executing data processing, and another multicore CPU 1 is being triggered, thereby executing the same process in parallel. As shown in Figure 8, even in a control device 100 with a system configuration such as a multi-CPU or multi-ASIC equipped with multiple multicore processors like the multicore CPU 1, by identifying which CPU or ASIC core 4 is being used and recording log information data such as address, execution time, and timing for the execution of a specific program instruction or access to specific data, debugging and fault analysis can be easily performed even in complex multiprocessor systems, such as a control system with a multicore processor containing multiple cores.

[0022] Figure 9 shows an example of log information recording in a control device according to a second modification of Embodiment 1. Figure 9 shows a state in which data for information to be recorded in non-volatile memory 94 or external storage is temporarily stored in memory 92. The control device 100 according to the second modification of Embodiment 1 has a cache 5 for each core 4. In the case of a control device that has common cache data between multi-core CPUs or between cores, inconsistencies in cache data do not occur. However, in the control device 100 according to the second modification of Embodiment 1, since each core 4 has cache data, if a specific core 4 processes the data area to be recorded, and then another core 4 has the same data cached, the content of the data processing is reflected in the cache data of the other core 4 after the data processing of the specific core 4, and log information data is recorded for debugging data or fault analysis. Furthermore, when performing fault analysis due to cache inconsistencies, the control device 100 according to the second modification of Embodiment 1 records the data cached by each core 4 along with which core 4's cache 5 the information was held by, without writing back the cache data. As a result, the control device 100 according to the second modification of Embodiment 1 can analyze data inconsistencies between the caches 5.

[0023] G-code analysis and interpolation processing, which analyzes G-code (code used to process the internal settings of numerically controlled machine tools), can be divided according to the number of systems and axes. However, the common processing loop requires processing timing across multiple cores because it involves checking the status of all systems and axes for each specific process. Alternatively, when separating the tasks of G-code analysis and interpolation processing, a single CPU typically performs sequential processing such as reading one line of G-code and executing the interpolation process. However, there are also processes that involve writing G-code with minute line segments or pre-reading to interpolate the shape, and if data consistency cannot be maintained between the pre-reading execution process and the interpolation process, the processing cannot be performed correctly. In the control device 100 according to Embodiment 1, each core 4 stores log information, which includes at least information identifying the core 4 and the processing content of the core 4, in the non-volatile memory 94, which is a storage unit. Therefore, the log information in the non-volatile memory 94 can be used when debugging core processing distribution in a specific process. Therefore, the control device 100 according to Embodiment 1 stores log information, which includes at least information identifying the core 4 and the processing content by the core 4, in the non-volatile memory 94, which is a storage unit, each time the core 4 accesses a pre-configured memory, at each interrupt timing, or at each pre-configured period, so that debugging can be performed taking into account the architecture of the multi-core CPU 1, which is a multi-core processor.

[0024] Embodiment 2. Figure 10 shows the configuration of the control system according to Embodiment 2. The control system 200 comprises a control device 100 and an external processing device 10 connected to the control device 100. In the control system 200 equipped with the control device 100 according to Embodiment 2, user authentication is performed when setting conditions for recording from the outside and when writing recorded data to the outside, and the control system 200 can only be executed when operated by an authenticated user. Therefore, in the control system 200 according to Embodiment 2, only authenticated users can record, output, and view information of the internal data of the control device 100 from the external processing device 10. Consequently, in the control system 200 according to Embodiment 2, confidential information held by the control device 100 and vulnerability information inherent in the control device 100 cannot be accessed by an unauthenticated user from the external processing device 10.

[0025] When performing user authentication, the user of the external processing unit 10 inputs authentication data 11 into the external processing unit 10. Here, the user authentication function may be executed within the external processing unit 10 or within the control unit 100. The control unit 100 and the external processing unit 10 are connected, and the information to be debugged or investigated for a malfunction and the recording conditions are set while the user is authenticated. After that, when writing the recorded information to the external storage area in the external processing unit 10, if the user authentication state is maintained, the writing is executed as is. If access is interrupted for a certain period of time or more for malfunction investigation, or if recording continues until the malfunction is reproduced after the user authentication state is released, and the recorded data is retrieved, user authentication is performed again, and after authentication is completed, the recorded data is written from the control unit 100 to the external processing unit 10. If a mechanism such as user authentication cannot be implemented, measures to conceal the data recorded in the control unit 100, such as password encryption, may be taken.

[0026] Figure 11 shows the configuration of a control system according to a modified example of Embodiment 2. In the control system 200 according to the modified example of Embodiment 2, the control device 100 and the external processing device 10 are connected via a network 300.

[0027] For phenomena that can only be reproduced with on-site installed machinery or in the specific environment, a rapid response is required for malfunctions and other issues, but it may not always be possible to immediately go to the site for investigation. As shown in Figure 11, the setting of recording conditions or data retrieval for debugging or malfunction analysis may be performed remotely via the network 300. Even via the network 300, data confidentiality can be protected by performing user authentication on the external processing unit 10 or the control unit 100. In addition, by using an encryption protocol for communication between the control unit 100 and the external processing unit 10, or by encrypting the data recorded on the control unit 100, data confidentiality can be protected even if the data is intercepted by a third party on the communication path between the control unit 100 and the external processing unit 10.

[0028] Figure 12 shows an example of a debug screen displayed on an external processing unit of a control system according to a modified example of Embodiment 2. The debug screen 50 includes a command input field 51 for inputting commands to be executed by the control device 100, and a response display field 52 for displaying response messages from the control device 100. While this screen operation user interface is not mandatory, remote debugging or fault analysis can be performed by inputting commands to be executed by the control device 100 from the debug screen 50 or displaying response messages on the debug screen 50.

[0029] Embodiment 3. Figure 13 shows the configuration of the control system according to Embodiment 3. The control system 200 according to Embodiment 3 differs from the control system 200 according to Embodiment 2 in that it includes an external computing device 101. The external computing device 101 may be a general-purpose industrial personal computer or a cloud system. The external computing device 101 is connected to the control device 100 via a network 300, and a portion of the processing performed by the control system 200 is shared and executed by the control device 100 and the external computing device 101. The external computing device 101 may execute a portion of the processing that should be performed by the multi-core CPU 1 in the control device 100, or it may acquire data from within the control device 100 or from other external devices or sensors, perform computationally intensive calculations, and feed the results back to the control device 100.

[0030] The control device 100 and the external arithmetic unit 101 perform time synchronization processing to synchronize processing. Data delays occur due to differences in the clocks of the control device 100 and the external arithmetic unit 101, and because the external arithmetic unit 101 is connected via the network 300. However, by performing time synchronization processing between the control device 100 and the external arithmetic unit 101, the time of the log information recorded by the control device 100 for debugging or fault analysis can be synchronized with the time of the external arithmetic unit log information recorded by the external arithmetic unit 101 for debugging or fault analysis.

[0031] The configurations shown in the above embodiments are merely examples of the content, and can be combined with other known technologies. It is also possible to omit or modify parts of the configuration without departing from the gist of the invention. [Explanation of symbols]

[0032] 1 Multicore CPU, 2 Local memory, 3 Storage unit, 4 Core, 5 Cache, 10 External processing unit, 11 Authentication data, 50 Debug screen, 51 Command input field, 52 Response display field, 61 Time, 62 Execution core identifier, 63 Task identifier, 64 Access address, 65 Value, 66 Line, 91 Processing unit, 92 Memory, 93 Processing circuit, 94 Non-volatile memory, 100 Control unit, 101 External processing unit, 200 Control system, 300 Network.

Claims

1. A control device comprising a multicore processor having multiple cores, and a storage unit that stores log information including at least information identifying the cores and the processing content of the cores each time the cores access a predetermined memory, at each interrupt timing, or at a predetermined interval, and an external processing device connected to the control device, A control system characterized in that, when setting the recording conditions for the log information and reading the log information recorded in the storage unit from the external processing unit, user authentication is performed, and only authenticated users are permitted to read the log information from the storage unit.

2. The control system according to claim 1, characterized in that, when writing data to the memory, the multiple cores lock the data to be written and prohibit other cores from writing data until the writing of data to the memory is complete.

3. Each of the multiple cores is provided with a cache memory for storing data. The control system according to claim 1, characterized in that when writing data to the memory, the data to be written is also written to the cache memory of another core that holds the same data as the data to be written, thereby ensuring consistency of the data in the cache memory of each of the multiple cores.

4. The control system according to claim 1, characterized in that the control device and the external processing device are connected via a network.

5. A control device comprising a multicore processor having a plurality of cores, and a storage unit that stores log information including at least information identifying the cores and the processing content by the cores each time the cores access a predetermined memory, at each interrupt timing, or at each predetermined period, and an external processing device connected to the control device, The control system is characterized in that the control device encrypts the log information and records it in the storage unit, and when the external processing unit requests to read the log information recorded in the storage unit, it outputs the encrypted log information to the external processing unit.

6. The control system according to claim 5, characterized in that when a plurality of cores write data to the memory, they lock the data to be written and prohibit other cores from writing data until the writing of data to the memory is complete.

7. Each of the multiple cores is provided with a cache memory for storing data, The control system according to claim 5, characterized in that when writing data to the memory, the data to be written is also written to the cache memory of another core that holds the same data as the data to be written, thereby ensuring consistency of the data in the cache memories of each of the multiple cores.

8. The control system according to claim 5, characterized in that the control device and the external processing device are connected via a network.

9. It includes an external computing device connected to the control device and which performs processing in cooperation with the control device, The control system according to any one of claims 1 to 8, characterized in that the control device and the external computing device perform time synchronization between the external computing device log information, which indicates the processing content of the external computing device, and the log information.

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