Virtual circuit generation device, virtual circuit generation program, and virtual circuit generation method

Abstract

To provide a virtual circuit generation device, a virtual circuit generation program, and a virtual circuit generation method for improving the diversity of a virtual circuit, and for achieving time reduction and labor saving in the generation of the virtual circuit.SOLUTION: When a device identifier which is an identifier for specifying a type of a semiconductor device is received from a user terminal, a variable setting process of setting a plurality of numerical variables related to numerical values in components constituting the semiconductor device of the type indicated by the device identifier, a variable selection process of randomly selecting a numerical variable of which a value is changeable from the plurality of numerical variables for a basic circuit associated with the semiconductor device, a variable changing process of randomly changing the value of the selected numerical variable, and a virtual circuit generation process of generating a virtual circuit based on the changed value are performed.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a virtual circuit generation device, a virtual circuit generation program, and a virtual circuit generation method for generating a plurality of virtual circuits having a circuit of a semiconductor device as a basic circuit based on predetermined design information, particularly design information of a semiconductor device provided as a PDK (Process Design Kit).

Background Art

[0002] Conventionally, when circuit design of a semiconductor device is performed, materials necessary for design called PDK (Process Design Kit) are provided from a foundry, which is an order destination for semiconductor manufacturing. And, a PDK designer of a semiconductor needs to verify the validity of the PDK.

[0003] A semiconductor device has a large number of parameters. And, when verifying the validity of the PDK, it is common for a PDK designer to manually set the value of each parameter one by one. In order to improve the accuracy of verification of the validity of the PDK, it is necessary to generate a large number of virtual circuit symbols (hereinafter referred to as "virtual circuits") while changing the values of each parameter variously. Therefore, an enormous amount of time is spent for verifying the validity of the PDK.

[0004] Regarding the above problem, the program described in Patent Document 1 automatically generates virtual circuits of a PDK library by a PDK designer setting types of some parameters and their values.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, inputting parameters is still required. Furthermore, the final virtual circuit type is a combination of the input parameter types and values. Therefore, simply setting some parameter values ​​as a PDK designer may not be sufficient to determine the type of virtual circuit.

[0007] This invention has been made in view of the above circumstances. Specifically, its objective is to provide a virtual circuit generation device, a virtual circuit generation method, and a virtual circuit generation program that can increase the diversity of virtual circuits, and reduce the time and effort required for generating virtual circuits. [Means for solving the problem]

[0008] To achieve the above objective, a virtual circuit generation device according to one aspect of the present invention has the following features.

[0009] One embodiment of the present invention, made to solve the above problems, (1) A virtual circuit generation device consisting of an information processing device, Upon receiving a device identifier, which is an identifier for identifying the type of semiconductor device, from the user terminal, a variable setting process is performed to set multiple numerical variables related to the numerical values ​​of the components constituting the semiconductor device of the type indicated by the device identifier. A variable selection process is performed to randomly select a numerical variable whose value can be changed from among the plurality of numerical variables set by the variable setting process for the basic circuit associated with the semiconductor device, A variable modification process is performed to randomly change the value of the numerical variable selected by the aforementioned variable selection process. A virtual circuit generation process that generates a virtual circuit based on the values ​​changed by the variable modification process, It is equipped with a control unit that performs the following. According to the embodiment described in (1) above, a numerical variable whose value can be changed is randomly selected from among a plurality of numerical variables for a basic circuit associated with a semiconductor device, the value of the selected numerical variable is randomly changed, and a virtual circuit is generated based on the changed value. This increases the diversity of the virtual circuit and reduces the time and effort required to generate the virtual circuit.

[0010] (2) In the virtual circuit generation device described in (1), The control unit further performs a maximum / minimum value setting process to set the maximum and minimum values ​​of the plurality of numerical variables set by the variable setting process, and in the variable change process, it may randomly change the value of the numerical variable selected by the variable selection process within the range between the minimum and maximum values ​​of the numerical variable. According to the embodiment described in (2) above, the value of the numerical variable is randomly changed within the range between the minimum and maximum values, thereby increasing the diversity of the virtual circuit. (3) In the virtual circuit generation device described in (1), In addition to numerical variables, the objects that can be set in the aforementioned variable setting process and selected in the aforementioned variable selection process include layout variables related to the circuit layout among the components constituting the semiconductor device. The layout variable may take at least one value: a first content corresponding to the basic circuit, and a second content different from the first content. If the control unit selects a layout variable in the variable selection process, it may decide on either the first or second content in the variable modification process. According to the embodiment described in (3) above, in addition to numerical variables, layout variables related to the circuit layout among the components constituting the semiconductor device are included as objects that can be set in the variable setting process and objects that can be selected in the variable selection process, thus further increasing the diversity of virtual circuits. (4) In the virtual circuit generation device described in (1), In addition to numerical variables, the objects that can be set in the variable setting process and selected in the variable selection process include a feasibility status variable, which is a state relating to whether a particular numerical variable can be changed. The feasibility status variable can have at least two values: an unchangeable state, which does not allow the change of the particular numerical variable, and a changeable state, which allows the change of the particular numerical variable. When the control unit selects the feasibility status variable in the variable selection process, it may determine it to be either the unchangeable state or the changeable state in the variable change process. If the feasibility status variable is in the changeable state, it may be possible to change the value of the particular numerical variable in the variable change process. According to the embodiment described in (4) above, in addition to numerical variables, there are feasibility status variables, which are the state of whether or not a particular numerical variable can be changed, as objects that can be set in the variable setting process and objects that can be selected in the variable selection process. Since the feasibility status variable can take on at least two values: an unchangeable state, which does not allow the change of a particular numerical variable, and a changeable state, which allows the change of a particular numerical variable, the randomness of the virtual circuit generation process is increased, and as a result, the diversity of the virtual circuit is further increased. (5) In a virtual circuit generation device described in any one of (1) to (4), If there are multiple targets for selection in the variable selection process, the control unit may select the targets in a random order for each virtual circuit in the variable selection process. According to the embodiment described in (5) above, since the selection targets are selected in a random order for each virtual circuit, the randomness in the virtual circuit generation process is increased, and as a result, the diversity of virtual circuits is further increased. (6) In a virtual circuit generation device described in any one of (1) to (4), If the number of variables that can be selected in the variable selection process is less than the number of variables set in the variable setting process, The control unit, in the variable selection process, randomly selects a target for each virtual circuit, The variable selected in the variable selection process relating to one virtual circuit may be different from the variable selected in the variable selection process relating to another virtual circuit. According to the embodiment described in (6) above, a selection target is randomly selected for each virtual circuit, and the variable selected in the variable selection process for one virtual circuit is different from the variable selected in the variable selection process for another virtual circuit. Therefore, under the condition that the number of variables that can be selected in the variable selection process is less than the number of variables set in the variable setting process, the randomness of the virtual circuit generation process is increased, and as a result, the diversity of virtual circuits is further increased.

[0011] Furthermore, in order to achieve the above objective, a virtual circuit generation program according to one aspect of the present invention has the following features. (7) The computer is made to function as a virtual circuit generation device as described in any one of (1) through (6).

[0012] Furthermore, in order to achieve the above objective, a virtual circuit generation method according to one aspect of the present invention has the following features. (8) When a device identifier, which is an identifier for identifying the type of semiconductor device, is received from the user terminal, the first step is to set multiple numerical variables related to the numerical values ​​of the components constituting the semiconductor device of the type indicated by the device identifier, A second step involves randomly selecting a numerical variable whose value can be changed from among the plurality of numerical variables set in the first step, with respect to the basic circuit associated with the semiconductor device, The third step involves randomly changing the values ​​of the numerical variables selected in the second step, A fourth step involves generating a virtual circuit based on the values ​​changed in the third step, It has. According to the aspect described in (8) above, for the basic circuit associated with the semiconductor device, a numerical variable that can change its value is randomly selected from among a plurality of numerical variables, and for the selected numerical variable, the value is randomly changed, and a virtual circuit based on the changed value is generated. Therefore, the diversity of the virtual circuit can be enhanced, and the time required for generating the virtual circuit can be shortened and the labor can be saved.

Advantages of the Invention

[0013] The virtual circuit generation apparatus, virtual circuit generation program, and virtual circuit generation method according to the present invention can enhance the diversity of the virtual circuit and can shorten the time required for generating the virtual circuit and save labor.

Brief Description of the Drawings

[0014] [Figure 1] It is a schematic diagram showing the overall configuration of the virtual circuit generation system according to the first embodiment of the present invention. [Figure 2] It is a block diagram showing the characteristic functional configuration of the management server. [Figure 3] It is an explanatory diagram of each database. [Figure 4] It is a table for explaining variables related to the N-channel MOSFET. [Figure 5] It is a flowchart showing the virtual circuit generation process. [Figure 6] It is a flowchart showing the initial setting process. [Figure 7] It is a flowchart showing the virtual circuit generation execution process. [Figure 8] It is a diagram showing an example of the circuit diagram generated by the virtual circuit generation process. [Figure 9] It is a distribution diagram of values with the gate length (variable 2) on the horizontal axis and the width per finger (variable 3) on the vertical axis. [Figure 10] It is a flowchart of the virtual circuit generation method.

Modes for Carrying Out the Invention

[0015] (First Embodiment) A first embodiment of the present invention will be described below. In this specification, "information" and "data" are synonymous and will not be distinguished from each other. Furthermore, when "information" or "data" is mentioned, the number and format are not limited. Moreover, data stored in a storage medium in a so-called table format is also referred to as "information" or "data" as herein.

[0016] (Overall configuration of virtual circuit generation system 1) Figure 1 is a schematic diagram showing the overall configuration of the virtual circuit generation system 1 according to this embodiment. The virtual circuit generation system 1 generates a large number of virtual circuits to verify the validity of a model of a single semiconductor device included in a certain PDK. Hereafter, the virtual circuit generation system 1 will be simply referred to as "System 1". The process of generating a large number of virtual circuits by the virtual circuit generation system 1 will be referred to as "testing".

[0017] As shown in Figure 1, System 1 comprises a management server 2 managed by the operator of System 1 and a user terminal 3 used by users. The management server 2 and the user terminal 3 are connected via a communication network 4, enabling them to send and receive information (data) to and from each other. The communication network 4 may consist of, for example, the Internet, LAN, telephone lines, mobile communication networks, Wi-Fi (Wireless Fidelity) (registered trademark), other communication lines, or a combination thereof, and may be wired or wireless.

[0018] Management Server 2 is composed of a general information processing device and, although not shown in the diagram, includes a CPU (Central Processing Unit) that controls the entire system, RAM (Random Access Memory) that functions as the CPU's workspace, ROM (Read Only Memory) that stores various programs, a storage device that stores various data, an input unit including a keyboard and mouse, a display unit that displays images, and a transmitting / receiving unit that communicates with external devices. However, Management Server 2 may consist of a single information processing device (a single physical computer), or it may be configured so that multiple information processing devices (multiple physical computers) work together to perform their functions (it may also be configured in a cloud environment). Details of Management Server 2 will be described later.

[0019] User terminal 3 is a general-purpose communication terminal and, although not shown in the diagram, includes a CPU that controls the entire system, RAM that functions as the CPU's workspace, ROM that stores various programs, a storage device that stores various data, an input unit including a keyboard and mouse, a display unit that displays images, and a transmitting / receiving unit that communicates with external devices. Specifically, user terminal 3 can be a desktop PC, a notebook PC, a PDA (Personal Digital Assistant), a tablet device, or a smartphone. In this embodiment, user terminal 3 is assumed to be a desktop PC.

[0020] As described later, the PDK designer for a semiconductor device inputs a device identifier to the user terminal 3 to identify the type of semiconductor device (semiconductor type). Upon receiving the device identifier, the user terminal 3 transmits it to the management server 2. When the management server 2 receives the device identifier transmitted from the user terminal 3, it generates a number of virtual circuits based on the circuit of the semiconductor device indicated by the device identifier. At this time, the management server 2 controls the system so that the PDK designer repeatedly changes the values ​​of the variables in the basic circuit to generate virtual circuits.

[0021] (Management Server 2) Next, we will describe the management server 2. Figure 2 is a block diagram showing the characteristic functional configuration of the management server 2. The management server 2 comprises a server communication unit 21, a server control unit 22, and a server storage unit 23.

[0022] The server communication unit 21 consists of an interface that communicates with the user terminal 3 and sends and receives data. The communication method between the server communication unit 21 and the user terminal 3 may be either wireless or wired.

[0023] The server storage unit 23 consists of a storage device such as memory or a disk drive, provided by the storage area of ​​a physical device consisting of a computer-readable recording medium. In other words, the server storage unit 23 stores various programs, including operating system programs and driver programs, and various data used during the execution of these programs.

[0024] The server storage unit 23 stores a management program 23a that is to be executed by the server control unit 22, which will be described later.

[0025] The server storage unit 23 includes a PDK storage area 23b for storing PDKs. The PDK storage area 23b stores PDKs provided by multiple foundries. In addition, new PDKs provided by foundries can be added to the PDK storage area 23b.

[0026] The PDK contains SPICE models (macro models) for various semiconductor devices, libraries of various semiconductor devices, and other information necessary for designing the basic circuits and layouts of each semiconductor device (basic design information). Therefore, the basic design information includes, for example, information such as the type of semiconductor device, the components included in each semiconductor device, the dimensions of each component, and information on the structure (circuit layout) of each semiconductor device.

[0027] Furthermore, the server storage unit 23 includes a database 23c that stores various data used during the execution of the management program 23a, or a database 23c that stores various data that can be edited during the execution of the management program 23a. The databases 23c include a semiconductor type database 23c1, a variable database 23c2, a maximum / minimum value database 23c3, and a test result database 23c4. Figure 3 is an explanatory diagram of each database.

[0028] The semiconductor type database 23c1, the variable database 23c2, and the maximum / minimum value database 23c3 all store various data, with the device identifier as the key, constituting one record. The device identifier is identification information used to identify a specific semiconductor device type (semiconductor type), in other words, identification information assigned to various semiconductor types.

[0029] The test results database 23c4 stores various data, each record consisting of a virtual circuit identifier as the key. The virtual circuit identifier is identification information used to identify a single virtual circuit that is assigned to each virtual circuit generated in the virtual circuit generation process described later.

[0030] The semiconductor type database 23c1 stores semiconductor type data, with each record consisting of a device identifier as the key. Each semiconductor type data entry associates multiple pieces of semiconductor type identification information, such as the foundry providing the PDK, the component type related to that foundry, the first classification, and the second classification, with the device identifier.

[0031] Device identification information includes information about the foundry providing the PDK, the component type, and the classification used to further subdivide the component type. The classifications include Category 1, Category 2 (lower than Category 1), Category 3 (lower than Category 2), and so on.

[0032] Examples of foundries that provide PDKs include companies A, B, and C. Examples of component types include diodes, transistors, light-emitting devices, light-receiving devices, and sensors. However, the types of components included in a PDK vary depending on the foundry.

[0033] An example of the first category is, for instance, if the component type is a transistor from company A, then, based on structure, it could be classified as a bipolar transistor or a MOS field-effect transistor (MOSFET). Furthermore, an example of the second category is, if the first category is a bipolar transistor, then it could be an NPN transistor or a PNP transistor. Another example of the second category is, if the first category is a MOS field-effect transistor, then it could be an N-channel MOSFET, a P-channel MOSFET, or a complementary MOSFET. However, the classifications included in a PDK may differ depending on the foundry.

[0034] Furthermore, the server control unit 22 is capable of obtaining basic design information for the semiconductor type corresponding to the device identifier from the PDK storage area 23b based on the device identifier.

[0035] The variable database 23c2 stores variable data, with each record consisting of a device identifier as the key. Each variable data entry contains information about multiple variables set for the semiconductor type associated with that device identifier. The values ​​of the variables can be changed by the server control unit 22 during the virtual circuit generation process.

[0036] Variables include numerical variables, layout variables, and status variables that represent the feasibility of specific matters. Each variable has an initial value. Specific examples of variables will be discussed later.

[0037] The maximum / minimum value database 23c3 stores maximum / minimum value data, with each record consisting of a device identifier as the key. Each maximum / minimum value data contains information about the maximum / minimum values ​​of numerical variables, such as the maximum / minimum values ​​of a specific part of a specific component within the semiconductor type associated with the device identifier, as described later. In other words, as described later, the server control unit 22 can change the dimensions of a specific part of the specific component in various ways within the range between the minimum and maximum values ​​indicated by the maximum / minimum value data.

[0038] For example, if the semiconductor device is an N-channel MOSFET, the maximum / minimum values ​​of the gate length, width per finger, drain diffusion area, source diffusion area, drain perimeter, and source perimeter are set as appropriate.

[0039] The test result database 23c4 stores test result data, each record consisting of a virtual circuit identifier as the key. Each test result data contains the values ​​of various variables set to the semiconductor type associated with the device identifier that is the target of the virtual circuit generation process. As will be described later, the server control unit 22 can generate a virtual circuit corresponding to the virtual circuit identifier of the test result data based on the test result data and the basic design information stored in the PDK storage area 23b.

[0040] The server memory unit 23 includes a circuit generation counter 23d1, a device identifier memory area 23d2, a variable memory area 23d3, a maximum / minimum value memory area 23d4, a test identifier memory area 23d5, a virtual circuit identifier memory area 23d6, and a selected variable memory area 23d7.

[0041] The circuit generation counter 23d1 counts the number of times a circuit is generated. The number of circuit generation times is the number of times a virtual circuit is generated in the virtual circuit generation execution process described later. The number of circuits generated in one virtual circuit generation execution process is predetermined. In the initial setup process described later, this predetermined number is set in the circuit generation counter 23d1. Then, each time a virtual circuit is generated in the virtual circuit generation execution process, the counter value of the circuit generation counter 23d1 is decremented by "1". In the following, the predetermined number of circuits generated in the virtual circuit generation execution process will be referred to as the "predetermined number of circuit generation times", and the current number of circuit generation times indicated by the counter value of the circuit generation counter 23d1 will be referred to as the "measured number of circuit generation times".

[0042] The device identifier storage area 23d2 stores the device identifier. The variable storage area 23d3 stores various variables associated with the semiconductor type indicated by the device identifier. The maximum / minimum value storage area 23d4 stores the maximum / minimum values ​​of various numerical variables among the various variables associated with the semiconductor type indicated by the device identifier, which will be described later.

[0043] The test identifier storage area 23d5 stores the test identifier. The test identifier is identification information used to identify a single test assigned to a test by the virtual circuit generation process. The virtual circuit identifier storage area 23d6 stores virtual circuit identifier data that indicates the virtual circuit identifier. The selected variable storage area 23d7 stores selected variable data that indicates the variables selected during the generation process of a single virtual circuit.

[0044] Furthermore, the server storage unit 23 has a circuit diagram file area 23e. The circuit diagram file area 23e stores circuit diagram files for displaying circuit diagrams that show each circuit generated by the virtual circuit generation process. A circuit diagram file is generated for each test related to one semiconductor type. The circuit diagrams include a circuit diagram of the basic circuit that is fundamental to the semiconductor type, and a circuit diagram of a virtual circuit that has been modified based on the basic circuit.

[0045] Next, the server control unit 22 will be described. The server control unit 22 is a processor, that is, a processing unit that is responsible for data calculation, processing and transfer, program execution and control of other devices, and consists of a CPU and various registers.

[0046] The server control unit 22 centrally controls the management server 2 by executing various programs stored in the server memory unit 23. Furthermore, by executing the management program 23a, the server control unit 22 implements a function to generate numerous virtual circuits, similar to how a PDK designer designs many new circuits (virtual circuits) by changing the components of a single basic circuit (basic circuit).

[0047] The functional blocks implemented by the server control unit 22 will now be described. As shown in Figure 2, the server control unit 22 includes a semiconductor type setting unit 22a, an initial setting unit 22b, and a virtual circuit generation unit 22c. Each unit 22a to 22c corresponds to a function that the server control unit 22 can implement. Note that the configuration of each unit 22a to 22c corresponding to the functions of the server control unit 22 is not limited to this, and these units 22a to 22c may be integrated as appropriate, and furthermore, each unit 22a to 22c may be subdivided as appropriate.

[0048] When accessed by a user terminal 3, the semiconductor type setting unit 22a displays a screen (semiconductor type input screen) on the user terminal 3's display unit to allow the user to identify the semiconductor type to be designed for the virtual circuit. Although not shown in the diagram, the semiconductor type input screen has an area for inputting a device identifier associated with the semiconductor type. When the device identifier is entered into this area through a predetermined operation on the user terminal 3 and sent to the management server 2, the semiconductor type setting unit 22a stores (stores) the device identifier in the device identifier storage area 23d2. In other words, the semiconductor type has been identified by the user. The method for identifying the semiconductor type is not particularly limited and may be changed as appropriate. For example, the semiconductor type setting unit 22a may display a list of semiconductor types with selection buttons on the user terminal 3's display unit, and when the user selects a semiconductor type, the device identifier associated with the selected semiconductor type is sent to the management server 2.

[0049] The initial setup unit 22b is capable of performing initial setup for generating a virtual circuit of the semiconductor type specified by the user. Specifically, the initial setup unit 22b performs the following: setting various variables associated with the semiconductor type specified by the user, setting the maximum / minimum values ​​of various numerical variables among the variables associated with the semiconductor type specified by the user, setting the specified number of circuit generation cycles, assigning a test identifier, and creating a circuit diagram file. Note that the initial setup by the initial setup unit 22b is performed immediately after the semiconductor type is identified by the semiconductor type setting unit 22a.

[0050] The virtual circuit generation unit 22c is capable of generating virtual circuits a specified number of times, in which some or all of the components of a basic circuit related to the semiconductor type specified by the user are modified. Specifically, the virtual circuit generation unit 22c first generates one virtual circuit by modifying some or all of the components of a basic circuit related to the semiconductor type specified by the user. Next, the virtual circuit generation unit 22c generates a second virtual circuit by modifying some or all of the components of the first virtual circuit. Thereafter, the virtual circuit generation unit 22c repeatedly generates new virtual circuits based on the previously generated virtual circuit until the circuit generation measurement count reaches the specified number of circuit generation counts.

[0051] Thus, when the management server 2 receives a device identifier from the user terminal 3, which is an identifier for identifying the type of semiconductor device, it sets multiple numerical variables related to the numerical values ​​of the components constituting the semiconductor device of the type indicated by the device identifier. For the basic circuit associated with the semiconductor device, it randomly selects numerical variables whose values ​​can be changed from the set multiple numerical variables, randomly changes the values ​​of the selected numerical variables, and generates a virtual circuit based on the changed values. In other words, the management server 2 constitutes the virtual circuit generation device of the present invention.

[0052] (Virtual circuit generation process) Next, the control related to virtual circuit generation by the server control unit 22 will be explained based on Figures 5 to 7. Figure 5 is a flowchart showing the virtual circuit generation process, which is the general process for generating virtual circuits a specified number of times, in other words, the virtual circuit generation process corresponding to one test. Figure 6 is a flowchart showing the initial setup process in the virtual circuit generation process, and Figure 7 is a flowchart showing the virtual circuit generation execution process in the virtual circuit generation process. Note that the flowcharts showing each process of the control related to virtual circuit generation described below are examples. Furthermore, the execution order of multiple processes in the flowchart can be changed as appropriate, or they can be executed in parallel, as long as there is no inconsistency in the processing content.

[0053] When accessed by a user terminal 3, the server control unit 22 performs virtual circuit generation processing. In the virtual circuit generation processing, the server control unit 22 sequentially performs semiconductor type setting processing (S1), initial setup processing (S2), and virtual circuit generation execution processing (S3).

[0054] In the semiconductor type setting process (S1), the server control unit 22 first displays the semiconductor type input screen on the display unit of the user terminal 3. As described above, the semiconductor type input screen has an area for inputting a device identifier. When the device identifier is transmitted to the management server 2 by a predetermined operation on the user terminal 3, the semiconductor type setting unit 22a stores (stores) the device identifier in the device identifier storage area 23d2. Here, assuming that a device identifier representing an N-channel MOSFET has been stored (stored) in the device identifier storage area 23d2, the following initial setup process (S2) and virtual circuit generation execution process (S3) will be described.

[0055] Next, before explaining the initial setup process (S2) and the virtual circuit generation execution process (S3), we will describe the variables and variable properties related to the N-channel MOSFET as an example. First, we will explain the variables.

[0056] Figure 4 is a table explaining the variables related to the N-channel MOSFET. As shown in Figure 4, the variables related to the N-channel MOSFET are set as follows: multiplier (variable 1), gate length (variable 2), width per finger (variable 3), presence or absence of maximum gate width (variable 4), number of gates (variable 5), applicability of maximum gate width change (variable 6), maximum gate width change (variable 7), S / D connection (variable 8), switch S / D (variable 9), pre-change state for specific variable change (variable 10), post-change state for specific variable change (variable 11), drain diffusion area (variable 12), source diffusion area (variable 13), drain circumference (variable 14), and source circumference (variable 15). In the following, the possible changes that these variables can take may be referred to as "change patterns".

[0057] The multiplier (variable 1) is the number of N-channel MOSFETs in question, and the change pattern can be within the range between the minimum and maximum values ​​of the multiplier. The multiplier value, minimum value, and maximum value are integers. Also, the minimum value is at least "1".

[0058] The gate length (variable 2) is the distance between the drain and source, and its variation pattern can be a range between the minimum and maximum values ​​of the gate length.

[0059] The width per finger (variable 3) is the so-called "gate width" for a single gate, and the possible modification patterns are within the range between the minimum and maximum values ​​of the gate width.

[0060] The presence or absence of a maximum gate width (variable 4) refers to the state related to the maximum value of the total number of gate widths. The possible change patterns are a state where no maximum value is set (no maximum value state) and a state where the maximum value of the total number of gate widths is set to the specified maximum value of 50 μm (maximum value specified state).

[0061] The gate count (variable 5) refers to the number of gates contained in a single N-channel MOSFET, and the change pattern can be within the range between the minimum and maximum values ​​of the gate count. The gate count value, minimum value, and maximum value are integers. Also, the minimum value is at least "1".

[0062] The state of whether or not the maximum gate width can be changed (variable 6) refers to whether or not a change value (changed maximum value) different from the specified maximum value is applied to the maximum total number of gate widths. The change patterns can be either a state where the change value is not applied (change value cannot be applied state) or a state where the change value is applied (change value can be applied state).

[0063] The maximum gate width change value (variable 7) is a maximum value (changeable maximum) that is different from the specified maximum total number of gate widths. The change pattern can take the range between the minimum and maximum values ​​of the maximum gate width change value. Note that the maximum gate width change value (variable 7) can be changed when the gate width change value applicability status (variable 6) is in the state where the change value can be applied.

[0064] The S / D connection (variable 8) refers to the state of whether or not a short connection is made, and the type of connection if a short connection is made. The possible change patterns are: no short connection (no connection state), connected to the source (source connection state), connected to the drain (drain connection state), and connected to both the source and the drain (both connection state).

[0065] The switch S / D (variable 9) refers to the state of the source and drain positions, and can take two forms: the normal state and a state where the source and drain positions are reversed (special state).

[0066] The state before the changeability of a specific variable (variable 10) refers to the state related to whether or not the changeability of the changeability of a specific variable (variable 11) is possible. The possible change patterns are a state in which the changeability of a specific variable cannot take place in the changeability of a specific variable (pre-stage changeability state) and a state in which the changeability of a specific variable can take place in the changeability of a specific variable (pre-stage changeability state).

[0067] The "Specific Variable Changeability Post-Stage State" (Variable 11) refers to the state of whether or not a specific variable can be changed. The possible change patterns are a state where the specific variable cannot be changed (Post-Stage Change Impossible State) and a state where the specific variable can be changed (Post-Stage Change Possible State). The specific variables are the drain diffusion area (Variable 12), source diffusion area (Variable 13), drain perimeter (Variable 14), and source perimeter (Variable 15). Furthermore, the "Specific Variable Changeability Post-Stage State" (Variable 11) can be changed when the "Specific Variable Changeability Pre-Stage State" (Variable 10) is in the "Pre-Stage Change Possible State."

[0068] The drain diffusion area (variable 12) is the total diffusion area of ​​the drain terminal, which is one of the terminals of the MOSFET. The variation pattern can be a range between the minimum and maximum values ​​of the drain diffusion area.

[0069] The source diffusion area (variable 13) is the total diffusion area of ​​the source terminal, which is one of the terminals of the MOSFET. The variation pattern can be a range between the minimum and maximum values ​​of the source diffusion area.

[0070] The drain perimeter (variable 14) refers to the perimeter of the drain terminal's diffusion, and its variation pattern can be within the range between the minimum and maximum values ​​of the drain perimeter.

[0071] Source perimeter (variable 15) refers to the perimeter of the source terminal diffusion, and the change pattern can be within the range between the minimum and maximum values ​​of the source perimeter.

[0072] Furthermore, the types of variables related to the N-channel MOSFET include numerical variables whose content consists of numerical values, layout variables whose content consists of components related to the circuit layout, and feasibility / state variables whose content consists of states related to the feasibility or non-feasibility of specific matters.

[0073] Numerical variables include multiplier (variable 1), gate length (variable 2), width per finger (variable 3), number of gates (variable 5), maximum gate width change (variable 7), drain diffusion area (variable 12), source diffusion area (variable 13), drain perimeter (variable 14), and source perimeter (variable 15). Layout variables include the presence / absence of the maximum gate width (variable 4), S / D connection (variable 8), and switch S / D (variable 9). Applicability status variables include the applicability of the maximum gate width change (variable 6), the pre-change status of a specific variable (variable 10), and the post-change status of a specific variable (variable 11).

[0074] As mentioned above, the maximum / minimum value database 23c3 stores the maximum / minimum values ​​of numerical variables associated with each semiconductor type. While specific numerical explanations are omitted, it is assumed that the maximum / minimum values ​​of numerical variables associated with each semiconductor type, including N-channel MOSFETs, are set appropriately.

[0075] Furthermore, each variable has an initial value set. The basic design information corresponding to the numerical variables and layout variables related to the semiconductor type constitutes the initial values ​​of the numerical variables and layout variables. In addition, for the feasibility status variables, the state related to negation is set as the initial value. That is, the initial value of the feasibility status of applying the maximum gate width change (variable 6) is the state where the change value cannot be applied, the initial value of the pre-stage state of feasibility of changing a specific variable (variable 10) is the pre-stage state where it cannot be changed, and the initial value of the post-stage state of feasibility of changing a specific variable (variable 11) is the post-stage state where it cannot be changed.

[0076] Here, we will explain the total number of gate widths. The total number of gate widths is calculated as the width per finger (variable 3) × the number of gates (variable 5). The maximum value of the total number of gate widths includes a predetermined maximum value related to the presence or absence of a maximum gate width (variable 4), and a changeable maximum value related to the maximum changeable gate width (variable 7).

[0077] When the change limit applicability status (variable 6) is in the change limit applicability status, the value of the change limit for gate width (variable 7) (change limit) is applied to the maximum total number of gate widths, regardless of the status of the gate width maximum value existence status (variable 4). When the change limit applicability status (variable 6) is in the change limit applicability status, the maximum total number of gate widths is set according to the status of the gate width maximum value existence status (variable 4). That is, when there is no maximum value, the maximum total number of gate widths is not set, and when there is a maximum value specified, the specified maximum value of "50 μm" is set as the maximum total number of gate widths.

[0078] Therefore, as will be described later, the maximum total number of gate widths reflected at any given time differs depending on the order in which the maximum gate width status (variable 4), the status of whether the maximum change value can be applied (variable 6), and the maximum change value of the gate width (variable 7) are selected. If the total number of gate widths calculated by width per finger (variable 3) × number of gates (variable 5) exceeds the maximum total number of gate widths reflected at that time, the width per finger or the number of gates is adjusted according to a predetermined process to keep it within the maximum gate width. This execution of a predetermined process when data is input is called a callback process.

[0079] Furthermore, as will be described later, in the virtual circuit generation unit processing, a change determination is performed to determine whether or not to change each variable. The server control unit 22 then randomly decides whether or not to change the value of the selected variable in the change determination. Here, "random" means that even for the same variable, the probability is not constant and varies each time a change determination is made. However, the server control unit 22 may also determine to change the value of the selected variable with a predetermined probability in the change determination. In this case, for example, the probability of determining to change the value of the selected variable (change determination probability) may be set in advance for each variable and stored in the maximum / minimum value database 23c3. In the change determination, the server control unit 22 performs a change determination for each variable so as to be the change determination probability for each variable. The change determination probability can be set as appropriate.

[0080] Next, let's discuss variable properties. Variable properties are attributes that determine whether or not variables 1 through 15 can be changed. They can be either mutable (meaning they can be changed) or immutable (meaning they cannot be changed). Variables can be further divided into those whose mutable state is maintained regardless of the contents of other variables (mutable-maintaining variables) and those whose variable properties change depending on the contents of other variables (mutable-variable variables).

[0081] The variable that can be changed is the constant variable, which includes the multiplier (variable 1), gate length (variable 2), width per finger (variable 3), presence or absence of the maximum gate width (variable 4), number of gates (variable 5), applicability of the maximum gate width change (variable 6), S / D connection (variable 8), switch S / D (variable 9), and the pre-change / changeability state (variable 10). On the other hand, the variable that can be changed is the maximum gate width change (variable 7), the post-change / changeability state (variable 11), drain diffusion area (variable 12), source diffusion area (variable 13), drain perimeter (variable 14), and source perimeter (variable 15).

[0082] The maximum gate width change value (variable 7) becomes changeable when the gate width change value application status (variable 6) is in a state where the change value can be applied, and is unchangeable when it is not in a state where the change value can be applied. The changeability of the subsequent stage status (variable 11) becomes changeable when the changeability of the preceding stage status (variable 10) is in a state where the preceding stage is possible, and is unchangeable when it is not in a state where the preceding stage is possible. The drain diffusion area (variable 12), source diffusion area (variable 13), drain perimeter (variable 14), and source perimeter (variable 15) become changeable when the changeability of the preceding stage status (variable 10) is in a state where the preceding stage is possible and the changeability of the subsequent stage status (variable 11) is in a state where the subsequent stage is possible, and are unchangeable when the changeability of the preceding stage status (variable 10) is in a state where the preceding stage is possible and the changeability of the subsequent stage status (variable 11) is not in a state where the subsequent stage is possible.

[0083] Note that when the virtual circuit generation execution process (S3) starts, the variable properties of each mutable variable are set appropriately in accordance with the semiconductor type. However, the variable properties of each mutable variable when the virtual circuit generation execution process (S3) starts may be arbitrarily set depending on the PDK library, cell type, and application.

[0084] Next, the initial setup process (S2) will be described. In the initial setup process (S2), the server control unit 22 first sets various variables (S201). As mentioned above, the various variables related to S201 are associated with device identifiers. Therefore, the server control unit 22 reads the variable data associated with the device identifiers stored in the device identifier storage area 23d2 in the semiconductor type setting process (S1) from the variable database 23c2 and stores it in the variable storage area 23d3.

[0085] In the initial setup process (S2), the server control unit 22 sets the maximum and minimum values ​​of various numerical variables after S201 (S202). As mentioned above, the maximum and minimum values ​​of the various numerical variables related to S202 are associated with device identifiers. Therefore, the server control unit 22 reads the maximum and minimum value data associated with the device identifier stored in the device identifier storage area 23d2 in the semiconductor type setting process (S1) from the maximum / minimum value database 23c3, associates the maximum and minimum values ​​of the various numerical variables with the numerical variables, and stores them in the maximum / minimum value storage area 23d4.

[0086] In the initial setup process (S2), after S202, the server control unit 22 sets the circuit generation counter to the specified number of circuit generation cycles (S203), assigns a test identifier (S204), creates a circuit diagram file (S205), and then completes the initial setup process.

[0087] In S203, the server control unit 22 sets the counter value of the circuit generation counter to the specified number of circuit generation cycles associated with the semiconductor type indicated by the device identifier. In the first embodiment, the specified number of circuit generation cycles for an N-channel MOSFET is set to 2000.

[0088] In S204, the server control unit 22 appropriately generates a test identifier corresponding to the virtual circuit generation that is about to be started, and stores the test identifier in the test identifier storage area 23d5.

[0089] In S205, the server control unit 22 appropriately generates a circuit diagram file for writing the circuit diagram of the virtual circuit to be generated, associating it with the test identifier, and saves it in the circuit diagram file area 23e.

[0090] Next, the virtual circuit generation execution process (S3) will be described. In the virtual circuit generation execution process (S3), the server control unit 22 first generates a basic circuit of the semiconductor type (in this case, an N-channel MOSFET) indicated by the device identifier stored in the device identifier storage area 23d2 (S301). In S301, the server control unit 22 generates a virtual circuit identifier indicating that it is the "0th" virtual circuit and stores it in the virtual circuit identifier storage area 23d6. Furthermore, in S301, the server control unit 22 stores variable data indicating the initial values ​​of various variables in the test result database 23c4, corresponding to the generated virtual circuit identifier, and writes the basic circuit, which will serve as the basis for subsequent changes, to the circuit diagram file.

[0091] Furthermore, when storing the variable data related to S301 in the test result database 23c4, the server control unit 22 reads the basic design information related to the numerical variables and layout variables of the semiconductor type (in this case, N-channel MOSFET) associated with the device identifier from the PDK storage area 23b, and stores the basic design information that will be used as the initial value for the numerical variables and layout variables in the test result database 23c4. In addition, the server control unit 22 stores the pre-set state as the initial value for each pass / fail status variable in the test result database 23c4.

[0092] After S301, the server control unit 22 prepares to generate a new virtual circuit. Specifically, the server control unit 22 updates the virtual circuit identifier stored in the virtual circuit identifier storage area 23d6 by adding "1". The server control unit 22 also stores the variable data related to the numerical variables, layout variables, and feasibility status variables associated with the previous virtual circuit identifier stored in the test result database 23c4, associating them with the newly updated virtual circuit identifier, in the test result database 23c4. From this point onward, a new virtual circuit will be generated by modifying the variable data newly stored in the test result database 23c4. Furthermore, in S302, the server control unit 22 clears the selected variable storage area 23d7.

[0093] Following S302, the server control unit 22 selects one variable (S303). Here, the server control unit 22 randomly selects one variable according to a predetermined algorithm. Randomness means that the order in which variables related to each virtual circuit generation process (S302-S314) are selected is irregular. Therefore, the order in which variables related to all virtual circuit generation processes in the virtual circuit generation process (S3) are selected may be different from each other, or the order in which variables related to the generation process of one virtual circuit may be selected to be the same as the order in which variables related to the generation process of another virtual circuit may be selected by chance. Furthermore, the server control unit 22 uses a predetermined algorithm to ensure that the same variable is not selected more than once in the generation process of a given virtual circuit. That is, the server control unit 22 uses a predetermined algorithm to ensure that a variable that has already been selected in the generation process of a given virtual circuit is not selected again. Therefore, in the generation process of a given virtual circuit, there may be variables that are not subject to the change determination described later.

[0094] After S303, the server control unit 22 subsequently stores the selected variable data, which indicates the variables selected in S303, in the selected variable storage area 23d7 (S304). By checking the selected variable storage area 23d7, the server control unit 22 can understand the variables selected during the virtual circuit generation process. Therefore, the server control unit 22 may, for example, check the selected variable storage area 23d7 to ensure that the same variable is not selected more than once during the generation of the virtual circuit.

[0095] After S304, the server control unit 22 then checks the variable properties of the variable selected in S303 (S305).

[0096] After S305, the server control unit 22 then determines whether the variable properties of the selected variables are in a changeable state (S306). As mentioned above, some variables cannot be changed depending on the content of other variables. For example, even if the drain diffusion area (variable 12), source diffusion area (variable 13), drain perimeter (variable 14), and source perimeter (variable 15) are selected, they will not be determined to be changeable unless the specific variable changeability status after the selection (variable 11) is in a changeable state after the selection. Furthermore, the specific variable changeability status after the selection (variable 11) will not be determined to be changeable unless the specific variable changeability status before the selection (variable 10) is in a changeable state before the selection. Also, the gate width change maximum value (variable 7) will not be determined to be changeable unless the gate width change maximum value applicability status (variable 6) is in a changeable state where the change maximum value can be applied. On the other hand, the multiplier (variable 1), gate length (variable 2), width per finger (variable 3), presence or absence of the maximum gate width (variable 4), number of gates (variable 5), applicability of the maximum gate width change (variable 6), S / D connection (variable 8), switch S / D (variable 9), and the pre-change state of specific variables (variable 10) are determined to be changeable in S306 if they are selected in S303.

[0097] If the server control unit 22 determines in S306 that the variable property is not in a modifiable state (NO in S306), it proceeds to S311. On the other hand, if it determines in S306 that the variable property is in a modifiable state (YES in S306), it proceeds to S307.

[0098] If the server control unit 22 determines in S306 that the variable property is in a modifiable state, it performs a change determination to decide whether or not to change the value of the selected variable (S307). As mentioned above, the probability of determining to "change the value of the selected variable" in the change determination is random.

[0099] The server control unit 22 then determines, after S307, whether the result of the change determination is to "change the value of the variable" (S308). If the server control unit 22 determines in S308 that the result of the change determination is not to "change the value of the variable" (NO in S308), it proceeds to S310. On the other hand, if the server control unit 22 determines in S308 that the result of the change determination is to "change the value of the variable" (YES in S308), it proceeds to S309.

[0100] When the server control unit 22 proceeds to S309, it changes the value of the variable (S309). Here, if the variable is a multiplier (variable 1), gate length (variable 2), width per finger (variable 3), number of gates (variable 5), maximum gate width change value (variable 7), drain diffusion area (variable 12), source diffusion area (variable 13), drain perimeter (variable 14), and source perimeter (variable 15), the server control unit 22 randomly generates a value between the minimum and maximum values ​​for the variable according to a predetermined algorithm. Furthermore, if the variable is a maximum gate width presence / absence state (variable 4), S / D connection (variable 8), or switch S / D (variable 9), the server control unit 22 randomly changes it to another state according to a predetermined algorithm. Moreover, if the variable is a maximum gate width change applicability state (variable 6), a pre-change state for specific variable changeability (variable 10), or a post-change state for specific variable changeability (variable 11), the server control unit 22 changes it to the other state. In addition, in S309, the server control unit 22 reflects the changed variable value in the variable data associated with the virtual circuit identifier stored in the test result database 23c4.

[0101] After S308 or S309, the server control unit 22 subsequently executes a callback to the virtual circuit based on the current variable data associated with the virtual circuit identifier (S310).

[0102] After S310, the server control unit 22 then checks the selected variable storage area 23d7 to determine whether all variables are stored, in other words, whether all variables were selected in S303 and the variable properties of all variables were confirmed in S305 during the virtual circuit generation process (S311). If the server control unit 22 determines in S311 that not all variables have been selected (NO in S311), it returns to S303. If it determines in S311 that all variables have been selected (YES in S311), it proceeds to S312.

[0103] When the server control unit 22 proceeds to S303, it repeats the processing from S303 to S311 until all variables have been selected in S303. Meanwhile, when the server control unit 22 proceeds to S312, it generates a virtual circuit based on the variable data associated with the virtual circuit identifier stored in the test result database 23c4, and adds the circuit diagram of the virtual circuit to the circuit diagram file. When adding the circuit diagram of the virtual circuit to the circuit diagram file, it is written to the right of the layout of the most recent circuit.

[0104] Following S312, the server control unit 22 then subtracts "1" from the counter value of the circuit generation counter 23d1 (S313).

[0105] After S313, the server control unit 22 then determines whether the counter value of the circuit generation counter 23d1 is 0, that is, whether the virtual circuit has been generated for the specified number of times (S314). If the server control unit 22 determines in S314 that the virtual circuit has not been generated for the specified number of times (NO in S314), it proceeds to S302. On the other hand, if the server control unit 22 determines in S314 that the virtual circuit has been generated for the specified number of times (YES in S314), it terminates the virtual circuit generation execution process.

[0106] When the server control unit 22 proceeds to S302, it repeats the processes from S302 to S313 until it determines in S314 that the virtual circuit has been generated the specified number of times. In the following, the process for generating one virtual circuit, consisting of S302 to S313, will be referred to as the "virtual circuit generation unit process".

[0107] Here, an example of a circuit diagram generated by the virtual circuit generation process is shown in Figure 8. As shown in Figure 8, in the first embodiment, the basic circuit is displayed on the far left, and then the virtual circuits are displayed to the right in the order of generation.

[0108] Next, a predetermined algorithm for generating numerical variable values ​​by the server control unit 22 will be described. This algorithm may be a known algorithm or a novel algorithm. Furthermore, the randomness of the numerical variable values ​​may be such that they are evenly distributed across the entire range between the minimum and maximum values, or they may be biased towards a specific range within that range. The specific range may be, for example, lower than the midpoint of the range between the minimum and maximum values, or midpoint of the range between the minimum and maximum values, or higher than the midpoint of the range between the minimum and maximum values. In other words, the randomness may be weighted.

[0109] Here, an example of the generated values ​​of numerical variables is shown in Figure 9. Figure 9 is a distribution graph of values ​​for gate length (variable 2) and width per finger (variable 3) for each virtual circuit identifier, with gate length (variable 2) on the horizontal axis and width per finger (variable 3) on the vertical axis. In Figure 9, both gate length (variable 2) and width per finger (variable 3) are generated with a bias towards the lower end of the middle. In this way, by weighting the randomness of the numerical variable values, it is possible to focus on verifying a desired range.

[0110] (Method for generating virtual circuits) Next, a virtual circuit generation method will be described, in which the management server 2 generates a virtual circuit by executing the management program 23a. Figure 10 is a flowchart of the virtual circuit generation method. The virtual circuit generation method includes a variable setting step S10 (first step), a variable selection step S20 (second step), a variable modification step S30 (third step), and a virtual circuit generation step S40 (fourth step).

[0111] In the variable setting step S10 (first step), when a device identifier, which is an identifier for identifying the type of semiconductor device, is received from the user terminal 3, multiple numerical variables related to the numerical values ​​of the components constituting the semiconductor device of the type indicated by the device identifier are set.

[0112] In the variable selection step S20 (second step), numerical variables whose values ​​can be changed are randomly selected from among the multiple numerical variables set in the variable setting step S10 (first step) for the basic circuit associated with the semiconductor device.

[0113] In the variable change process S30 (third process), the numerical variables selected in the variable selection process S20 (second process) are randomly changed in value.

[0114] In the virtual circuit generation process S40 (fourth process), a virtual circuit is generated based on the values ​​changed in the variable modification process S30 (third process).

[0115] As described above, according to the virtual circuit generation device of the first embodiment, when a device identifier, which is an identifier for identifying the type of semiconductor device, is received from the user terminal 3, a variable setting process (server control unit 22 performing S201: part of the initial setting unit 22b) is performed to set multiple numerical variables (multiplier (variable 1), gate length (variable 2), width per finger (variable 3), number of gates (variable 5), drain diffusion area (variable 12), source diffusion area (variable 13), drain perimeter (variable 14), and source perimeter (variable 15)) related to the numerical values ​​of the components constituting the semiconductor device of the type indicated by the device identifier, and The system includes a control unit (server control unit 22) that performs the following processes for a basic circuit associated with a conductive device: a variable selection process (S303 performed by the server control unit 22: part of the virtual circuit generation unit 22c) which randomly selects a numerical variable whose value can be changed from among multiple numerical variables set by a variable setting process; a variable change process (S309 performed by the server control unit 22: part of the virtual circuit generation unit 22c) which randomly changes the value of the numerical variable selected by the variable selection process; and a virtual circuit generation process (S312 performed by the server control unit 22: part of the virtual circuit generation unit 22c) which generates a virtual circuit based on the value changed by the variable change process.

[0116] Furthermore, according to the virtual circuit generation device 2 of the first embodiment, the control unit further performs a maximum / minimum value setting process (a server control unit 22 that performs S202: part of the initial setting unit 22b) to set the maximum and minimum values ​​of a plurality of numerical variables set by the variable setting process, and in the variable change process, the value of the numerical variable selected by the variable selection process is randomly changed within the range between the minimum and maximum values ​​of the numerical variable. Since the value is randomly changed within the range between the minimum and maximum values ​​of the numerical variable, the diversity of the virtual circuit is increased. Furthermore, according to the virtual circuit generation device 2 of the first embodiment, in addition to numerical variables, the objects that can be set in the variable setting process and selected in the variable selection process include layout variables related to the layout of circuits among the components that constitute the semiconductor device (the presence or absence of the maximum gate width (variable 4), S / D connection (variable 8), and switch S / D (variable 9)). The layout variables can take on at least a first content corresponding to the basic circuit and a second content different from the first content as their values. When the control unit selects a layout variable in the variable selection process, it may decide on either the first content or the second content in the variable change process. Since the objects that can be set in the variable setting process and selected in the variable selection process include layout variables related to the layout of circuits among the components that constitute the semiconductor device, in addition to numerical variables, the diversity of virtual circuits is further increased. Furthermore, according to the virtual circuit generation device 2 of the first embodiment, in addition to numerical variables, the objects that can be set in the variable setting process and selected in the variable selection process include, in addition to the numerical variables, a feasibility status variable (gate width change maximum value applicability status (variable 6), specific variable change feasibility pre-stage status (variable 10), specific variable change feasibility post-stage status (variable 11)) which is the state relating to whether or not specific numerical variables (gate width change maximum value applicability status (variable 7), drain diffusion area (variable 12), source diffusion area (variable 13), drain perimeter length (variable 14), and source perimeter length (variable 15)) can be changed. The feasibility status variable can take on at least two values: an unchangeable state which does not allow the change of a specific numerical variable, and a changeable state which allows the change of a specific numerical variable. When the control unit selects a changeability variable in the variable selection process, it may determine it to be in an unchangeable state or a changeable state in the variable change process. When the changeability variable is in a changeable state, it is possible to change the value of a specific numerical variable in the variable change process. In addition to numerical variables, there are also feasibility status variables, which are the states related to whether or not a particular numerical variable can be changed, and these feasibility status variables can take on at least two values: an immutable state, which does not allow the change of the particular numerical variable, and a changeable state, which allows the change of the particular numerical variable. As a result, the randomness in the virtual circuit generation process increases, and consequently, the diversity of virtual circuits increases even further. Furthermore, according to the virtual circuit generation device 2 of the first embodiment, if there are multiple selection targets in the variable selection process, the control unit selects the selection targets in a random order for each virtual circuit in the variable selection process. Since the selection targets are selected in a random order for each virtual circuit, the randomness of the virtual circuit generation process is increased, and as a result, the diversity of virtual circuits is further increased.

[0117] Furthermore, according to the virtual circuit generation method of the first embodiment, upon receiving a device identifier, which is an identifier for identifying the type of semiconductor device, from a user terminal 3, the method includes a first step of setting a plurality of numerical variables (multiplier (variable 1), gate length (variable 2), width per finger (variable 3), number of gates (variable 5), drain diffusion area (variable 12), source diffusion area (variable 13), drain perimeter (variable 14), and source perimeter (variable 15)) related to the numerical values ​​of the components constituting the semiconductor device of the type indicated by the device identifier; a second step of randomly selecting numerical variables whose values ​​can be changed from the plurality of numerical variables set in the first step for a basic circuit associated with a semiconductor device; a third step of randomly changing the values ​​of the numerical variables selected in the second step; and a fourth step of generating a virtual circuit based on the values ​​changed in the third step. For a basic circuit associated with a semiconductor device, a numerical variable whose value can be changed is randomly selected from among multiple numerical variables. The value of the selected numerical variable is then randomly changed, and a virtual circuit is generated based on the changed value. This increases the diversity of virtual circuits and reduces the time and effort required for generating them.

[0118] (modified version) The present invention has been described above based on the embodiments. These embodiments are illustrative, and it will be understood by those skilled in the art that various modifications are possible in the combination of these components, and that such modifications also fall within the scope of the present invention.

[0119] In the first embodiment, all variables are always selected in S303 during the generation process of a single virtual circuit and are subject to verification of variable properties in S305. However, the number and types of variables selected during the generation process of a single virtual circuit may be set as appropriate.

[0120] For example, the server control unit 22 may randomly select variables such that the number of variables selected in the generation process of one virtual circuit is the same as the number of variables selected in the generation process of another virtual circuit, but the types of variables selected in the generation process of one virtual circuit are different from the types of variables selected in the generation process of another virtual circuit. In this case, the randomness of the virtual circuit generation process increases, and as a result, the diversity of virtual circuits increases even further. Alternatively, the server control unit 22 may choose to have different numbers of variables selected in the generation process of one virtual circuit compared to the number of variables selected in the generation process of another virtual circuit.

[0121] Furthermore, in the first embodiment, the order in which variables related to the generation process of each virtual circuit (S302-S314) are selected is irregular, but the order may be regular. For example, there may be only one type of order, or there may be multiple types of orders, and the type of order may be selected in each virtual circuit generation process (S302-S314). Moreover, in the first embodiment, the same variable is not selected more than once in the generation process of a single virtual circuit, but it may be selected more than once. In this case, the condition for the termination of a single virtual circuit generation process may be the number of times variables were selected in S303 or the number of times a change judgment was made in S307. Furthermore, in addition to "all variables have been selected" as in the first embodiment, the condition for the termination of a single virtual circuit generation process may also be the number of times variables were selected in S303 or the number of times a change judgment was made in S307, and the termination condition may be set randomly for each virtual circuit generation process (S302-S314).

[0122] Furthermore, in the first embodiment, numerical variables, layout variables, and pass / fail status variables are set as the types of variables related to the virtual circuit, but there may also be cases where only numerical variables and layout variables are set, or where only numerical variables and pass / fail status variables are set.

[0123] Furthermore, in the first embodiment, the provided PDK is stored in the management server 2, but it may also be stored in a server other than the management server 2, and by accessing that other server, basic design information relating to the semiconductor device of the type indicated by the device identifier can be obtained.

[0124] Furthermore, in the above-described embodiment, the server control unit 22 implements various functions based on various programs and information stored in the server storage unit 23 of the management server 2. However, the various programs stored in the server storage unit 23 may be stored in a cloud-based system connected to the management server 2 via the communication network 4.

[0125] Furthermore, the processing disclosed in the above-described embodiments may be performed on a single CPU, multiple CPUs, hardware such as an ASIC, or a combination thereof. Also, the processing disclosed in the above-described embodiments can be implemented in various forms, such as a recording medium or method that stores a program for performing the processing.

[0126] Furthermore, by generating a layout based on a circuit diagram with the highly diverse virtual circuits generated in the first embodiment and then performing DRC (design rule check) and LVS (Layout versus schematic), the likelihood of error detection during DRC and LVS execution can be increased, thereby improving the quality of the PDK library.

[0127] Similarly, by running SPICE (Simulation Program with Integrated Circuit Emphasis) based on the circuit diagram generated in the first embodiment, SPICE results for highly diverse input data can be obtained. By running SPICE under various conditions, the validity of the obtained characteristic values ​​can be verified, thereby improving the quality of the PDK library.

[0128] In the circuit diagram generation process of the first embodiment, numerous variable changes are made. By analyzing this situation, it is possible to detect errors or abnormal conditions during virtual circuit generation and layout generation. The possibility of detecting these errors can be increased by generating a variety of virtual circuits. [Explanation of Symbols]

[0129] 1…Virtual circuit generation system 2…Management Server (Virtual Circuit Generator) 3…User terminal 4…Communication Networks 21…Server Communication Department 22…Server Control Unit 22a... Semiconductor type setting unit 22b…Initial setting section 22c...Virtual circuit generation unit 23…Server Storage Unit 23b…PDK storage area 23c1… Semiconductor Type Database 23c2...Variable Database 23c3…Maximum / Minimum Value Database 23c4…Test results database 23d1... Circuit generation counter 23e...File area for circuit diagrams

Claims

1. A virtual circuit generation device consisting of an information processing device, Upon receiving a device identifier, which is an identifier for identifying the type of semiconductor device, from the user terminal, a variable setting process is performed to set multiple numerical variables related to the numerical values ​​of the components constituting the semiconductor device of the type indicated by the device identifier. A variable selection process is performed to randomly select a numerical variable whose value can be changed from among the plurality of numerical variables set by the variable setting process for the basic circuit associated with the semiconductor device, A variable modification process is performed to randomly change the value of the numerical variable selected by the aforementioned variable selection process. A virtual circuit generation process that generates a virtual circuit based on the values ​​changed by the variable modification process, It includes a control unit that performs the following: In the variable selection process, the number of variables that can be selected is less than the number of variables that have been set in the variable setting process. The control unit, in the variable selection process, randomly selects a target for each virtual circuit, To make the variable selected in the variable selection process relating to one virtual circuit different from the variable selected in the variable selection process relating to another virtual circuit, A virtual circuit generation device.

2. A virtual circuit generation device according to claim 1, The control unit, Further, a maximum / minimum value setting process is performed to set the maximum and minimum values ​​of the plurality of numerical variables set by the variable setting process, In the aforementioned variable modification process, the numerical variable selected by the aforementioned variable selection process is randomly changed within a range between the minimum and maximum values ​​of the numerical variable. Virtual circuit generator.

3. A virtual circuit generation device according to claim 1, In addition to numerical variables, the objects that can be set in the aforementioned variable setting process and selected in the aforementioned variable selection process include layout variables related to the circuit layout among the components constituting the semiconductor device. The layout variable may take at least one value: a first value corresponding to the basic circuit, and a second value different from the first value. If the control unit selects a layout variable in the variable selection process, it may decide on either the first or second content in the variable modification process. Virtual circuit generator.

4. A virtual circuit generation device according to claim 1, In addition to numerical variables, the objects that can be set in the aforementioned variable setting process and selected in the aforementioned variable selection process include feasibility status variables, which represent the state of whether or not a particular numerical variable can be changed. The permission / impossibility state variable may have at least two values: an immutable state in which the specific numerical variable is not permitted to be changed, and a modifiable state in which the specific numerical variable is permitted to be changed. The control unit, If a variable that can be changed is selected in the variable selection process, the variable change process may determine that it is either in the state of being unchangeable or in the state of being changeable. When the changeable variable is in the changeable state, it is possible to change the value of the specific numerical variable in the variable change process. Virtual circuit generator.

5. A virtual circuit generation device according to any one of claims 1 to 4, If there are multiple targets for selection in the variable selection process, the control unit selects targets in a random order for each virtual circuit in the variable selection process. Virtual circuit generator.

6. A virtual circuit generation program for causing a computer to function as a virtual circuit generation device according to any one of claims 1 to 4.

7. The first step involves receiving a device identifier from a user terminal, which is an identifier for identifying the type of semiconductor device, and setting multiple numerical variables related to the numerical values ​​of the components constituting the semiconductor device of the type indicated by the device identifier. A second step involves randomly selecting a numerical variable whose value can be changed from among the plurality of numerical variables set in the first step, with respect to the basic circuit associated with the semiconductor device, A third step involves randomly changing the value of the numerical variable selected in the second step, A fourth step involves generating a virtual circuit based on the values ​​changed in the third step, It has, The number of variables that can be selected in the second step is less than the number of variables set in the first step. For each of the aforementioned virtual circuits, a target is randomly selected. To make the variable selected in the second step relating to one virtual circuit different from the variable selected in the second step relating to another virtual circuit, A method for generating virtual circuits.

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