Crystalline oxide thin film, method for producing same, thin film transistor, and method for producing same

Abstract

A crystalline oxide thin film having In as a main component, the crystalline oxide thin film being such that 50% or more of Fourier transform images obtained by processing each of a plurality of lattice images of image regions, which are extracted from a transition electron microscope (TEM) image of a cross-section of the crystalline oxide thin film, using respective two-dimensional Fourier transforms (FFT) exhibit any plane orientation selected from the (100), (110), (111), (211), (411), (125), (210), (310), and (320) planes.

Description

Crystalline oxide thin film and method for manufacturing the same, and thin film transistor and method for manufacturing the same

[0001] The present invention relates to a crystalline oxide thin film and a method for producing the same, and a thin film transistor and a method for producing the same.

[0002] Thin film transistors (TFTs) using a crystalline oxide thin film for the channel layer are known (see Patent Documents 1 and 2). For example, in Patent Document 1, an oxide semiconductor containing In as a main component is formed by sputtering while introducing water, and high mobility characteristics are obtained in a TFT using the oxide semiconductor. In addition, in Patent Document 2, a crystalline oxide thin film containing In as a main component is made to have a composition containing Sm as well as Ga, and good mobility is obtained in a TFT device without introducing water during thin film formation.

[0003] Patent No. 5491258 Patent No. 6853421

[0004] However, even with the techniques of Patent Documents 1 and 2, the improvement in TFT characteristics was not necessarily sufficient, and there was room for improvement. With the technique of Patent Document 1, the threshold voltage (Vth) was prone to fluctuate when a voltage was applied for a predetermined period of time, which sometimes caused problems in terms of reliability. Furthermore, with the techniques of Patent Documents 1 and 2, crystallization progressed in the oxide thin film before the annealing step, which hindered good crystal growth in the annealing step, and the effect of improving mobility was sometimes not fully achieved.

[0005] An object of the present invention is to provide a crystalline oxide thin film that exhibits good mobility and high reliability when applied to a TFT, and to provide a thin film transistor having the crystalline oxide thin film and a method for manufacturing the same.

[0006] According to the present invention, there is provided the following crystalline oxide thin film: 1. A crystalline oxide thin film containing In as a main component, wherein 50% or more of Fourier transform images obtained by subjecting lattice images of a plurality of image regions extracted from a transmission electron microscope (TEM) image of a cross section of the crystalline oxide thin film to two-dimensional Fourier transform (FFT) processing show any one of plane orientations selected from (100), (110), (111), (211), (411), (125), (210), (310), and (320). In each of the Fourier transform images obtained for the plurality of image regions and showing any one of plane orientations selected from (100), (110), (111), (211), (411), (125), (210), (310), and (320), the size of the frequency domain from the central coordinates of a reciprocal lattice point P1 selected from bright points located on a coordinate axis extending from the central coordinates of the Fourier transform image in a normal direction to the main surface of the crystalline oxide thin film is defined as a plane spacing in the normal direction d1, the size of the frequency domain from the central coordinates of a reciprocal lattice point P2 selected from bright points located on a coordinate axis extending from the central coordinates of the Fourier transform image in a direction parallel to the main surface of the crystalline oxide thin film is defined as a plane spacing in the planar direction d2, and the Miller indices of the reciprocal lattice point P1 are defined as (h １ , k １ , l １ ), and the Miller indices of the reciprocal lattice point P2 are (h ２ , k ２ , l ２ ) and the lattice constant a in the normal direction calculated by the following formula (1) and the lattice constant b in the planar direction calculated by the following formula (2), the average value ε of the lattice strain ε of each of the plurality of image regions is calculated by the following formula (3): ａｖｅｒ However, 1.0<ε ａｖｅｒ <1.1. The crystalline oxide thin film according to 1, wherein the lattice constant in the normal direction is a=√(h １ ２ +k １ ２ +h １ ２ ) × d1 ... (Equation (1)) Lattice constant b in the planar direction = √(h ２ ２ +k ２ ２ +h２ ２ ) × d2 … (Formula (2)) 3. The crystalline oxide thin film according to 1 or 2, having a film thickness of 3 nm or more and less than 50 nm. 4. The crystalline oxide thin film according to any one of 1 to 3, wherein the length of the short side of the crystalline oxide thin film is less than 50 μm. 5. The crystalline oxide thin film according to any one of 1 to 4, wherein the average spacing D between grain boundaries is 0.01 μm or more and 2 μm or less. 6. The crystalline oxide thin film according to any one of 1 to 5, containing 62 at % or more of In. 7. The crystalline oxide thin film according to any one of 1 to 6, further comprising one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, and Bi. 8. The method for producing a crystalline oxide thin film according to any one of 1 to 7, wherein the oxide thin film formed on the support is annealed in air at a temperature exceeding 300°C. 9. The method for producing a crystalline oxide thin film according to 8, wherein the oxide thin film subjected to the annealing treatment has a thickness of 3 nm or more and less than 50 nm. 10. The method for producing a crystalline oxide thin film according to 8 or 9, wherein the oxide thin film subjected to the annealing treatment has a short side of less than 50 μm. 11. A thin film transistor comprising the crystalline oxide thin film according to any one of 1 to 7. 12. The thin film transistor according to 11, comprising a buffer layer and a channel layer, the channel layer being the crystalline oxide thin film, and having a gate insulating film and a gate electrode, in this order from the channel layer side, on the opposite side of the channel layer from the buffer layer. 13. The method for producing a thin film transistor according to 11 or 12, comprising the steps of: forming an oxide thin film on a substrate; annealing the oxide thin film in an air atmosphere at a temperature exceeding 300° C. to form a crystalline oxide thin film; and forming a gate insulating film and a gate electrode, in this order, on the crystalline oxide thin film. 14. The method for producing a thin film transistor according to 13, wherein a buffer layer is formed on the substrate, and then the oxide thin film is formed on the buffer layer.15. The method for manufacturing a thin film transistor according to 11 or 12, comprising the steps of forming an oxide thin film on a substrate, annealing the oxide thin film in an air atmosphere at a temperature exceeding 300°C to form a crystalline oxide thin film, and forming an interlayer insulating film on the crystalline oxide thin film in this order. 16. The method for manufacturing a thin film transistor according to 15, wherein a gate electrode and a gate insulating film are formed on the substrate in this order, and then the oxide thin film is formed on the gate insulating film layer.

[0007] According to the present invention, it is possible to provide a crystalline oxide thin film that exhibits good mobility and high reliability when applied to a TFT, and also to provide a thin film transistor having the crystalline oxide thin film and a method for manufacturing the same.

[0008] 1 is a schematic cross-sectional view of a TFT according to an example of the present embodiment; FIG. 2 is a schematic cross-sectional view of a TFT according to another example of the present embodiment; FIG. 3 is a schematic cross-sectional view of a TFT according to another example of the present embodiment; ２ O ３ 1 is a diagram showing an FFT image of the bixbyite structure of In. FIG. 2 is a diagram for explaining a method for calculating the lattice constants a and b. ２ O ３ 1 is a diagram showing the results of a reciprocal lattice simulation of the bixbyite structure of FIG.

[0009] The ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion of components, and components that are specified numerically, i.e., components that do not have a description specifying whether they are singular or plural or a description specifying an order, are not limited numerically.

[0010] In this specification and the like, the terms "film" or "thin film" and "layer" can be used interchangeably in some cases.

[0011] In the sintered body and oxide thin film of this specification and the like, the terms "compound" and "crystalline phase" can be interchangeable in some cases.

[0012] In this specification, the “oxide sintered body” may be simply referred to as the “sintered body.” In this specification, the “sputtering target” may be simply referred to as the “target.”

[0013] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes, wiring, switching elements (such as transistors), resistive elements, inductors, capacitors, and other elements with various functions.

[0014] In this specification, the functions of the source and drain of a transistor may be interchanged when transistors of different polarities are used or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms source and drain may be used interchangeably.

[0015] In this specification, "x to y" represents a numerical range of "not less than x and not more than y." The upper and lower limits of the numerical ranges can be combined in any combination. In addition, a combination of two or more of the individual embodiments of the present invention described below is also an embodiment of the present invention.

[0016] In this specification, the term "main surface of a thin film" refers to the surface of a thin film that has the largest area.

[0017] In this specification, a specific plane of a crystal or a plane parallel to it is referred to as a crystal plane, and a direction perpendicular to the crystal plane is referred to as a plane orientation.

[0018] 1. Crystalline Oxide Thin Film The crystalline oxide thin film according to this embodiment is a crystalline oxide thin film containing In as its main component. Furthermore, lattice images of multiple image regions extracted from a cross-sectional transmission electron microscope image (hereinafter sometimes referred to as a cross-sectional TEM image) of the crystalline oxide thin film are subjected to two-dimensional Fourier transform (FFT) processing. More than 50% of the Fourier transform images (hereinafter referred to as FFT images) exhibit any one of the plane orientations selected from (100), (110), (111), (211), (411), (125), (210), (310), and (320). Note that, although the multiple image regions are 10 image regions in the following description, the number of image regions is not limited to 10 and may be greater than this. For example, 50 or more image regions may be extracted.

[0019] A crystalline oxide thin film having the above properties can be obtained not only by the method for producing a crystalline oxide thin film described later, but also by adjusting the crystalline state of the crystalline oxide thin film to a columnar shape.

[0020] The crystalline oxide thin film according to this embodiment is mainly composed of In element. Being the main component means that the composition ratio (atomic %: at%) of In relative to all metal elements in the crystalline oxide thin film is 50 at% or more. The composition ratio of In is preferably 62 at% or more, more preferably 70 at% or more, even more preferably 80 at% or more, and even more preferably 85 at% or more. If 50 at% or more of the total number of atoms of the metal elements constituting the crystalline oxide thin film are In element, crystallization easily proceeds in the formed amorphous film, and when the crystalline oxide thin film according to this embodiment is used in a TFT, sufficiently high mobility can be exhibited.

[0021] In addition to In, the crystalline oxide thin film may contain one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, and Bi.

[0022] In this embodiment, the crystalline oxide thin film may consist essentially of elements selected from In, Mg, Al, Si, Zn, Ga, Mo, Sn, Ln elements (lanthanoid elements), and O. Here, "substantially" means that the crystalline oxide thin film according to this embodiment may contain other components as long as the effects of the present invention resulting from the combination of In, Mg, Al, Si, Zn, Ga, Mo, Sn, Ln, and O are achieved.

[0023] In this embodiment, a more preferred first form of the crystalline oxide thin film is one in which the metal elements are composed of In and Ga, and the atomic ratio satisfies the following formula (11): [Ga] / ([In] + [Ga])<22 at% (11). Note that the metal elements may contain inevitable impurities, and may further contain F or H in addition to O. By setting the composition within the above range, the In ratio becomes large, and even with annealing at a low temperature such as 300°C, Ga can be substituted for the In site, allowing crystallization into a bixbyite structure. Furthermore, by adding Ga, which has a strong bond with oxygen, oxygen deficiency after annealing can be suppressed, and a stable film as a semiconductor can be formed.

[0024] In this embodiment, a more preferred second form of the crystalline oxide thin film comprises a metal element, In, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, where X is a metal element other than In, and satisfies the following atomic ratio: [X] / ([In] + [X])<15 at% (12). The metal element may contain unavoidable impurities, and may further contain F or H in addition to O. By setting the composition within the above range, the In ratio is increased, enabling crystallization into a bixbyite structure in which X substitutes for the In site, even with annealing at a low temperature such as 300°C. Furthermore, adding an element X, which has a strong bond with oxygen, suppresses oxygen deficiency after annealing, resulting in the formation of a stable film as a semiconductor.

[0025] In the present embodiment, a more preferred third form of the crystalline oxide thin film comprises metal elements In, Ga, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, and when a metal element other than In or Ga is designated as an additional element X, the atomic ratios satisfy the following formulas (13) and (14): [Ga] / ([In]+[Ga]+[X])<22.5 at% (13) [X] / ([In]+[Ga]+[X])<8.0 at% (14) The metal elements may contain inevitable impurities, and may further contain F or H in addition to O. By setting the composition in the above range, the In ratio becomes large, and crystallization into a bixbyite structure in which Ga substitutes for the In site can be achieved even by annealing at a low temperature such as 300° C. Furthermore, by adding an additional element X that has a strong bond with oxygen, oxygen deficiency after annealing can be further suppressed, and a stable film as a semiconductor can be formed.

[0026] In the present embodiment, a fourth more preferable form of the crystalline oxide thin film is composed of metal elements In, Sn, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, and when a metal element other than In and Sn is element X, the atomic ratios satisfy the following formulas (15) and (16): [Sn] / ([In]+[Sn]+[X])<20 at % (15) [X] / ([In]+[Sn]+[X])<8.0 at % (16) The metal elements may contain inevitable impurities, and may further contain F or H in addition to O. By setting the composition in this range, the In ratio becomes large, and even when annealed at a low temperature such as 300°C, crystallization can be achieved into a bixbyite structure in which Sn substitutes for the In site. Sn has a large ionic radius and a large overlap of its orbital with In, so high mobility can be maintained. Furthermore, by adding an additional element X that has a strong bond with oxygen, oxygen deficiency after annealing can be further suppressed, and a stable film can be formed as a semiconductor.

[0027] In the present embodiment, a more preferable fifth form of the crystalline oxide thin film is composed of metal elements In, Zn, and one or more elements X selected from B, Al, Sc, Mg, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, and when a metal element other than In and Zn is element X, the atomic ratios satisfy the following formulas (17) and (18): [Zn] / ([In]+[Zn]+[X])<12 at% (17) [X] / ([In]+[Zn]+[X])<8.0 at% (18) The metal elements may contain inevitable impurities, and may further contain F or H in addition to O. By setting the composition within the above range, the In ratio becomes large, and even when annealed at a low temperature such as 300°C, the film can be crystallized into a bixbyite structure in which Zn substitutes for the In site. By adding Zn, the film can be made amorphous immediately after deposition, and can be processed without leaving any residue when semiconductor patterning is performed with acid during TFT fabrication. Furthermore, by adding an additional element X that has a strong bond with oxygen, oxygen deficiency after annealing can be suppressed, and a stable film can be formed as a semiconductor.

[0028] The content (atomic ratio) of each metal element in the crystalline oxide thin film can be determined by measuring the amount of each element by ICP (Inductive Coupled Plasma) measurement or XRF (X-ray Fluorescence) measurement. For ICP measurement, an inductively coupled plasma optical emission spectrometer (ICP-OES, manufactured by Agilent) can be used. For XRF measurement, a thin film X-ray fluorescence spectrometer (AZX400, manufactured by Rigaku Corporation) can be used.

[0029] Furthermore, the content (atomic ratio) of each metal element in a crystalline oxide thin film can be analyzed with an error accuracy of 2 atomic percent or less by TEM-EDS measurement using an electron microscope, ICP measurement using an inductively coupled plasma optical emission spectrometer, and SIMS analysis using a sector-type dynamic secondary ion mass spectrometer. First, the metal elements in the crystalline oxide thin film are identified by cross-sectional TEM-EDS, and the composition ratio is identified within an error range of approximately 10 atomic percent by semi-quantitative analysis. Next, standard oxide thin films are prepared from the semi-quantitative analysis results, each consisting of 10 different composition ratios with known atomic ratios of metal elements within a 20 atomic percent range. For the standard oxide thin films, the values ​​measured using an inductively coupled plasma optical emission spectrometer or a thin-film X-ray fluorescence analyzer are used as absolute values ​​of the composition ratio. Furthermore, source and drain electrodes formed of the same material and with the same channel length as the TFT element are fabricated on the top surface of the standard oxide thin film, and using this as the standard material, the oxide semiconductor layer is analyzed using a sector-type dynamic secondary ion mass spectrometer SIMS (IMS 7f-Auto, manufactured by AMETEK Corporation) to obtain the mass spectral intensity of each element, and a calibration curve of known element concentrations and mass spectral intensities is prepared. Next, the oxide thin film portion of the actual TFT element removed from the panel is analyzed using the sector-type dynamic secondary ion mass spectrometer to obtain the spectral intensities. Using the above-mentioned calibration curve, the atomic ratio is calculated from the spectral intensities obtained by SIMS analysis using the sector-type dynamic secondary ion mass spectrometer. The calculated atomic ratio can be confirmed to an accuracy of within 2 atomic % of the atomic ratio of the oxide thin film measured separately using a thin film fluorescent X-ray analyzer or an inductively coupled plasma optical emission analyzer.

[0030] In the crystalline oxide thin film according to this embodiment, lattice images of a plurality of image regions extracted from a cross-sectional TEM image of the cross section of the crystalline oxide thin film are subjected to a two-dimensional Fourier transform (FFT) process, and 50% or more of the FFT images obtained show any one of plane orientations selected from (100), (110), (111), (211), (411), (125), (210), (310), and (320). (100), (110), (111), (211), (411), (125), (210), (310), and (320) are all In. ２ O ３The bixbyite structure of the crystalline planes is referred to as "exhibiting an FFT-specific plane orientation." When 50% or more of the FFT images obtained from the lattice image of each image region correspond to one of the plane orientations described above, the crystalline oxide thin film can be determined to have a favorable bixbyite crystal structure suitable for the FFT channel layer. This allows the crystalline oxide thin film to exhibit high mobility and minimal threshold voltage (Vth) fluctuations, resulting in excellent reliability when used in the TFT channel layer. The method for determining the FFT-specific plane orientation will be described in detail in the Examples.

[0031] Preferably, 60% or more, 70% or more, 80% or more, 90% or more, 95% or more, or 99% or more of the FFT images of lattice images of a plurality of image regions extracted from a cross-sectional TEM image of a cross section of the crystalline oxide thin film exhibit any one of plane orientations selected from (100), (110), (111), (211), (411), (125), (210), (310), and (320). More preferably, 100% of the FFT images of lattice images of a plurality of image regions exhibit any one of plane orientations selected from (100), (110), (111), (211), (411), (125), (210), (310), and (320).

[0032] The crystalline oxide thin film according to one embodiment has a lattice distortion ε calculated from the lattice constant a in the normal direction (hereinafter referred to as the normal direction) to the main surface of the crystalline oxide thin film and the lattice constant b in the direction parallel to the main surface of the crystalline oxide thin film (hereinafter referred to as the planar direction) for each of the Fourier transform images showing the FFT specific plane orientation by the following formula (3): １ , ... ε ｘ The arithmetic mean value ε ａｖｅｒ However, 1.0<ε ａｖｅｒ <1.1.

[0033] Lattice distortion ε indicates the degree of distortion of the crystal lattice. When the value of ε exceeds 1.0, the lattice constant b in the planar direction is larger than the lattice constant a in the normal direction, resulting in a state in which tensile stress is generated in the crystal lattice. As a result, the crystalline oxide thin film has reduced defects within the crystal grains, resulting in a crystalline state with few electron traps and good conductivity characteristics. Therefore, when the crystalline oxide thin film is used in the channel layer of a TFT, it can exhibit high mobility and has little fluctuation in threshold voltage (Vth), resulting in excellent reliability. Furthermore, when the value of ε is less than 1.1, peeling and cracking of the crystalline oxide thin film are suppressed, resulting in good film properties. ε ａｖｅｒ is preferably 1.01 to 1.09, and more preferably 1.02 to 1.08. The method for calculating the lattice constant a in the normal direction and the lattice constant b in the planar direction will be explained in detail in the Examples.

[0034] In one embodiment, the thickness of the crystalline oxide thin film is 3 nm or more and 130 nm or less. A thickness of 130 nm or less facilitates the formation of columnar single-layer crystals in the crystalline oxide thin film. This is because a thickness of 130 nm or less can suppress the progression of crystallization in the oxide thin film formed on the support before annealing, thereby preventing the presence of microcrystals from hindering crystal growth in the subsequent annealing process. Therefore, when the crystalline oxide thin film is used as a channel layer of a TFT, it can exhibit high mobility and excellent reliability. Furthermore, because microcrystallization in the oxide thin film can be suppressed, problems such as the inability to remove a film to be peeled due to residues generated during the patterning process can be suppressed, resulting in excellent film properties. The thickness of the crystalline oxide thin film is preferably less than 50 nm, more preferably 45 nm or less, and particularly preferably 40 nm or less. Meanwhile, the thickness of the crystalline oxide thin film may be, for example, 5 nm or more, or even 10 nm or more. By making the thickness of the crystalline oxide thin film 3 nm or more, the crystals of the crystalline oxide thin film are less susceptible to the influence of the underlayer, and it is easy to form high-quality columnar single-layer crystals. In this specification, the film thickness is measured based on a cross-sectional TEM image.

[0035] In one embodiment, the length of the short side of the crystalline oxide thin film is less than 50 μm. When the short side length is less than 50 μm, the proportion of FFT images of cross-sectional TEM images of the crystalline oxide thin film that exhibit FFT-specific plane orientations tends to be higher. The length of the short side of the crystalline oxide thin film is preferably 45 μm or less, more preferably 35 μm or less, even more preferably 25 μm or less, and particularly preferably 22 μm or less. Meanwhile, the length of the short side of the crystalline oxide thin film is, for example, 0.1 μm or more, or may be 0.3 μm or more, or may be 1 μm or more. By making the short side 1 μm or more, when fabricating a TFT using the crystalline oxide thin film, accurate alignment of the patterning mask can be performed, enabling stable production. However, in the manufacturing process of integrated circuits, etc., the alignment accuracy of the patterning mask varies, so in that case the short side may be less than 1 μm.

[0036] In one embodiment, the average distance D between crystal grain boundaries in the crystalline oxide thin film is preferably 0.01 μm or more and 2.0 μm or less, so that when the crystalline oxide thin film is used in a channel layer of a TFT, high mobility can be achieved, and fluctuations in threshold voltage (Vth) are small, resulting in excellent reliability.

[0037] The average spacing D between crystal grain boundaries in the thin film is measured based on a cross-sectional TEM image. The average spacing D is calculated by extracting a field of view centered on the center of the TFT in the channel length direction, with a film thickness of 5 μm and a crystalline oxide film size in the channel direction, from an image observed using a transmission electron microscope at a magnification of 20,000 times, and analyzing the spacing between crystal grains observed in the cross-sectional TEM image. Note that if the length of the oxide thin film in the channel direction is short, less than 5 μm, a field of view that matches the length in the channel direction may be extracted and calculated in the same manner.

[0038] In one embodiment, the crystalline oxide thin film contains crystal grains that have a bixbyite structure in an FFT image of a TEM image. Because the crystal grains with the bixbyite structure have a cubic crystal shape with good symmetry, degradation of TFT characteristics (mobility) can be suppressed even when the crystal grain boundaries are crossed.

[0039] 2. Method for Producing Crystalline Oxide Thin Film The crystalline oxide thin film of this embodiment can be produced by using a lower layer constituting a TFT, such as a substrate, a buffer layer, or an insulating layer, as a support, depositing a thin film containing an oxide of In as a main component on the support, and annealing (heat treating) it at a predetermined temperature. The deposition method is not particularly limited, and examples thereof include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, ion plating, ALD, PLD, MO-CVD, ICP-CVD, a sol-gel method, a coating method, and mist CVD.

[0040] When the film is formed by sputtering, the film may be formed by a planar sputtering cathode device or a rotary sputtering cathode device.

[0041] As an example of a film formation method, the crystalline oxide thin film can be produced by DC sputtering using a sputtering target containing an oxide sintered body mainly composed of an oxide of In. The atomic composition ratio of the crystalline oxide thin film obtained by sputtering reflects the atomic composition ratio of the oxide sintered body in the sputtering target. Therefore, it is preferable to form the film using a sputtering target containing an oxide sintered body having an atomic composition ratio similar to that of the desired oxide thin film.

[0042] The target used in the sputtering method preferably contains 500 ppm or less of impurity metals, more preferably 100 ppm or less. The content of impurity metals in the target can be measured by ICP or SIMS, as with crystalline oxide thin films. "Impurities" contained in the target refer to trace elements that are mixed in with raw materials or during the manufacturing process and are not intentionally added, and do not substantially affect the performance of the target or semiconductor. "Impurity metals" refer to metal elements among the elements considered as "impurities."

[0043] The method of annealing (heat treatment) is not particularly limited, but a hot air oven, an IR oven, a lamp annealing device, a laser annealing device, a thermal plasma device, or the like can be used.

[0044] In this embodiment, the sputtering target may consist essentially of In and an element selected from Mg, Al, Si, Zn, Ga, Mo, Sn, Ln elements (lanthanoid elements), and O. Here, "substantially" means that the sputtering target may contain other components in addition to the above-mentioned In, as long as the effects of the present invention resulting from the combination of Mg, Al, Si, Zn, Ga, Mo, Sn, Ln, and O are achieved.

[0045] As with the above-described crystalline oxide thin film of the present invention, in this embodiment, a more preferred first form of the sputtering target is an oxide containing metal elements In and Ga, and the atomic ratio satisfies the following formula (11): [Ga] / ([In]+[Ga])<22 at% (11).

[0046] A more preferred second embodiment of the sputtering target is an oxide composed of a metal element In and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, wherein when X is a metal element other than In, the atomic ratio satisfies the following formula (12): [X] / ([In]+[X])<15 at% (12).

[0047] A more preferred third embodiment of the sputtering target is an oxide comprising metal elements In, Ga, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, wherein when a metal element other than In or Ga is an additional element X, the atomic ratios satisfy the following formulas (13) and (14): [Ga] / ([In]+[Ga]+[X])<22.5 at% (13) [X] / ([In]+[Ga]+[X])<8.0 at% (14).

[0048] A fourth more preferred embodiment of the sputtering target is an oxide comprising metal elements In, Sn, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, wherein when a metal element other than In and Sn is defined as element X, the atomic ratios satisfy the following formulas (15) and (16): [Sn] / ([In]+[Sn]+[X])<20 at% (15) [X] / ([In]+[Sn]+[X])<8.0 at% (16).

[0049] A more preferred fifth embodiment of the sputtering target is an oxide comprising metal elements In, Zn, and one or more elements X selected from B, Al, Sc, Mg, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, wherein when a metal element other than In and Zn is element X, the atomic ratios satisfy the following formulas (17) and (18): [Zn] / ([In]+[Zn]+[X])<12 at% (17) [X] / ([In]+[Zn]+[X])<8.0 at% (18).

[0050] The oxide thin film obtained by sputtering using a sputtering target mainly composed of indium oxide and one or more gases selected from the group consisting of argon and oxygen, which are substantially free of impurities, is an amorphous oxide thin film. This oxide thin film is patterned into islands by photolithography, and then heated and crystallized before forming a protective film, thereby obtaining a crystalline oxide thin film whose surface crystals have a single plane orientation. Each step is described below.

[0051] (Oxide Thin Film Forming Step) In the oxide thin film forming step, the above-described sputtering target is used to form an oxide thin film by sputtering.

[0052] In one embodiment, the oxide thin film forming step uses a substrate such as a glass substrate as a support, and forms a crystalline oxide thin film directly on a stacked film including a buffer layer formed on the support, or a buffer layer and a layer other than the buffer layer, such as a metal layer. In the case of a stacked film, it is preferable to form the stacked film on the support so that the buffer layer included in the film is in direct contact with the crystalline oxide thin film. The buffer layer can be made of SiO ２ , SiN ｘ , Al ２ O ３ Among these, SiO ２ is preferred. ２ By directly forming an oxide thin film on a buffer layer or a laminated film mainly composed of the above, and then performing an annealing treatment as described later, the finally obtained crystalline oxide thin film tends to have a high proportion of FFT images of cross-sectional TEM images showing FFT-specific plane orientations, and has a good crystalline structure.

[0053] The gas introduced during sputtering deposition is not particularly limited, but examples thereof include argon, nitrogen, oxygen, water, hydrogen, and a mixed gas containing two or more of these gases. As an example, when argon and oxygen are used, the flow rate ratio of oxygen in the mixed gas ((O ２ flow rate) / (Ar flow rate)+(O ２ The oxygen flow ratio is preferably more than 0% and not more than 50%, more preferably more than 0% and not more than 20%. If the oxygen flow ratio is more than 0% and not more than 50%, the oxide thin film is easily crystallized and becomes a semiconductor when heated. By changing the oxygen flow ratio, the oxidation degree of the oxide thin film, i.e., the crystallization degree, can be adjusted. The oxygen flow ratio may be appropriately selected as needed. As an example, when argon and water are used, the water flow ratio ((H ２ O flow rate) / (Ar flow rate) + (H ２ The O flow rate) is preferably more than 0.03% and not more than 10%, and more preferably more than 0.03% and not more than 5%. If the flow rate ratio of water is more than 0.03% and not more than 5%, the material easily crystallizes and becomes a semiconductor when heated. Alternatively, a mixed gas of hydrogen and oxygen may be used instead of water.

[0054] In one embodiment, the oxide thin film is formed using one or more gases selected from the group consisting of argon and oxygen, which are substantially free of impurity gases, as a sputtering gas.

[0055] The phrase "the sputtering gas is substantially free of impurity gases" means that impurity gases other than argon and oxygen are not actively introduced, except for adsorbed water brought in with the gas introduction, and gases that cannot be eliminated (unavoidable impurity gases) such as gases leaking from the chamber or adsorbed gases. In this embodiment, for example, a commercially available mixed gas of high-purity argon and high-purity oxygen can be used as the sputtering gas. It is preferable to eliminate impurities from the sputtering gas if possible.

[0056] The proportion of impurity gas in the sputtering gas is preferably 0.1% by volume or less, more preferably 0.05% by volume or less. If the proportion of impurity gas is 0.1% by volume or less, crystallization of the oxide thin film proceeds without any problems. The purity of the high-purity argon and high-purity oxygen is preferably 99% by volume or more, more preferably 99.9% by volume or more, and even more preferably 99.99% by volume or more.

[0057] The sputtering pressure during film formation is not particularly limited as long as it is within a range in which plasma can be stably discharged, but is usually 0.1 to 5 Pa, and preferably 0.2 to 2 Pa. This increases the proportion of FFT images of cross-sectional TEM images that show FFT-specific plane orientations in the finally obtained crystalline oxide thin film, resulting in a favorable crystalline structure.

[0058] In the oxide thin film forming step, it is preferable to mount the sputtering target in an RF magnetron sputtering device or a DC magnetron sputtering device and perform sputtering.

[0059] The crystalline oxide thin film according to this embodiment preferably contains In as a main component before heat treatment. By heating this oxide thin film in the heat treatment step described below, columnar crystals can be grown on the support. By applying the crystalline oxide thin film formed as described above to a TFT, the injection of electron carriers during operation is excellent, resulting in a TFT with high mobility and excellent reliability with little fluctuation in threshold voltage (Vth).

[0060] In one embodiment, the oxide thin film is formed to a thickness of 3 nm or more and less than 50 nm in the oxide thin film formation step. The reason for setting the thickness of the oxide thin film in this range is the same as the reason for setting the thickness of the crystalline oxide thin film to 3 nm or more and less than 50 nm. The preferred thickness range of the oxide thin film is also the same as the preferred thickness range of the crystalline oxide thin film.

[0061] In one embodiment, in the oxide thin film forming step, the length of the short side of the oxide thin film is set to be less than 50 μm. The reason for setting the length of the short side of the oxide thin film in this range is the same as the reason for setting the length of the short side of the crystalline oxide thin film to be less than 50 μm. The preferred range of the length of the short side of the oxide thin film is also the same as the preferred range of the length of the short side of the crystalline oxide thin film.

[0062] (Heat Treatment Step) After the oxide thin film is formed, a heat treatment is performed. This heat treatment is sometimes called annealing. The heat treatment temperature is preferably higher than 300°C and lower than 500°C, preferably 320°C to 480°C, and more preferably 330°C to 450°C. If the heat treatment temperature after the oxide thin film formation is higher than 300°C, the oxide thin film is easily crystallized, and in the finally obtained crystalline oxide thin film, the FFT image of the cross-sectional TEM image shows a higher proportion of FFT-specific plane orientations, resulting in a good crystal structure. In addition, the average spacing D of the crystal grains can be formed within an appropriate range. If the heat treatment temperature after the oxide thin film formation is lower than 500°C, the occurrence of cracks and peeling can be suppressed.

[0063] The heating time in the heat treatment step is preferably 0.1 to 5 hours, more preferably 0.3 to 3 hours, and even more preferably 0.5 to 2 hours. If the heating time in the heat treatment step is 0.1 hours or more, crystallization is unlikely to occur and the oxide thin film is likely to crystallize. If the heating time in the heat treatment step is 5 hours or less, it is economical. "Heating time" refers to the time during which a predetermined maximum temperature is maintained (retention time) during heat treatment.

[0064] The temperature rise rate in the heat treatment step is preferably 2°C / min or more and 1000°C / min or less, and more preferably 3°C / min or more and 600°C / min or less. If the temperature rise rate in the heat treatment step is 2°C / min or more, the production efficiency of the oxide thin film is improved compared to when it is less than 1°C / min. If the temperature rise rate in the heat treatment step is 1000°C / min or less, the metal elements are uniformly diffused during crystallization, and crystals without metal segregation at grain boundaries can be formed. Furthermore, the temperature rise rate in the heat treatment step is different from a value calculated from the set temperature and set time of the furnace, but is a value obtained by dividing the actual temperature of the oxide thin film by time. The actual temperature of the oxide thin film can be determined, for example, by measuring an area within 1 cm of the oxide thin film in the furnace with a thermocouple.

[0065] The heat treatment step is preferably carried out in an air atmosphere at 25° C. with a humidity of 10% or more, more preferably 40% or more. By performing the heat treatment in an air atmosphere with a humidity of 10% or more during annealing, hydrogen and oxygen can diffuse into the film during annealing, promoting crystallization. The upper limit of the humidity is not particularly limited, but is generally 80% or less.

[0066] The heat treatment step is preferably carried out after patterning the oxide thin film. By carrying out the heat treatment after patterning, crystallization can be promoted while removing excess oxygen present in the film during film formation and organic substances that adhere during patterning. As a result, a film with few crystal defects and no organic substances or excess oxygen within the crystal grains can be formed, and an oxide thin film with few electron traps and good conductivity can be formed.

[0067] The heat treatment step may be performed multiple times. For example, the above-mentioned heat treatment step (first heat treatment step) may be performed after patterning the oxide thin film, and then, after fabricating the TFT element, a heat treatment step (second heat treatment step) may be performed as a final step. The second heat treatment step is preferably performed at a higher annealing temperature than the first heat treatment step.

[0068] A region having a lower resistance than the other regions may be formed in a part of the crystalline oxide thin film obtained by the heat treatment process. The method for forming the low-resistance region is not particularly limited, but for example, the low-resistance region can be formed by lowering the resistance of the target part of the crystalline oxide thin film by a method of heat treatment (annealing) using a gate insulating film and / or a gate electrode instead of a mask (self-alignment) in the presence of indium tin oxide (ITO), aluminum, etc.

[0069] 3. Thin Film Transistor (TFT) and Manufacturing Method Thereof The TFT according to this embodiment includes the above-described crystalline oxide thin film of the present invention. Preferably, the crystalline oxide thin film of the present invention is used as the channel layer of the TFT. The TFT according to this embodiment also has a buffer layer and a channel layer, the channel layer being the crystalline oxide thin film described above, and a gate insulating film and a gate electrode, in this order from the channel layer side, on the opposite side of the channel layer from the buffer layer.

[0070] In one embodiment, the TFT includes a substrate, a buffer layer, and a channel layer, in this order. The TFT also includes the channel layer, a source electrode and a drain electrode connected to both ends of the channel layer, and a gate electrode laminated on the channel layer via a gate insulating film. The channel layer is a crystalline oxide thin film. That is, the gate insulating film and the gate electrode are provided on the opposite side of the channel layer from the buffer layer.

[0071] The TFT according to this embodiment may have, for example, a conventionally known structure.

[0072] The TFT according to this embodiment can be manufactured by a method for manufacturing a thin film transistor, which includes the steps of forming an oxide thin film on a substrate, annealing the oxide thin film in an air atmosphere at a temperature exceeding 300° C. to form a crystalline oxide thin film, and forming a gate insulating film and a gate electrode in this order on the crystalline oxide thin film. In one embodiment, a buffer layer is formed on the substrate, and then the oxide thin film is formed on the buffer layer.

[0073] The TFT according to this embodiment can be manufactured by a thin film transistor manufacturing method including the steps of forming an oxide thin film on a substrate, annealing the oxide thin film in an air atmosphere at a temperature exceeding 300° C. to form a crystalline oxide thin film, and forming an interlayer insulating film on the crystalline oxide thin film in this order. In one embodiment, a gate electrode and a gate insulating film are formed on the substrate in this order, and then the oxide thin film is formed on the gate insulating film.

[0074] Here, the step of annealing the oxide thin film to form a crystalline oxide thin film can be achieved by the above-described method for manufacturing a crystalline oxide thin film. That is, the TFT of this embodiment can be manufactured by a manufacturing method including a step of forming an oxide thin film by sputtering using a sputtering target (sometimes referred to as a film formation step) and a step of subjecting the oxide thin film to a heat treatment (sometimes referred to as a heat treatment step). The conditions for the film formation step and the heat treatment step are the same as those described above in the method for manufacturing a crystalline oxide thin film. The source electrode, drain electrode, gate electrode, and gate insulating film can be formed using known materials and methods.

[0075] In the method for manufacturing the thin film transistor of this embodiment, the method for forming each layer other than the crystalline oxide thin film is not particularly limited, and known methods can be used.

[0076] (Step of forming TFT constituent layers) When forming TFT constituent layers such as an insulating layer on a crystalline oxide thin film, it is preferable to form the constituent layers on the oxide thin film after subjecting the obtained oxide thin film to heat treatment. By performing annealing before forming the TFT constituent layers, oxygen and hydrogen are diffused during annealing, resulting in columnar, high-quality crystals, and a small TFT with few interfacial electron trap levels and high mobility can be obtained after forming the constituent layers.

[0077] The shape of the thin film transistor according to this embodiment is not particularly limited, but is preferably a top gate type transistor, a back channel etch type transistor, an etch stopper type transistor, etc. Furthermore, these transistors may be of a self-aligned type.

[0078] Hereinafter, embodiments will be described with reference to the drawings, etc. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0079] In the drawings, sizes, layer thicknesses, regions, etc. may be exaggerated for clarity. Therefore, the present invention is not limited to the illustrated sizes, layer thicknesses, regions, etc. Note that the drawings are schematic illustrations of ideal examples, and the present invention is not limited to the shapes, values, etc. shown in the drawings.

[0080] FIG. 1 is a schematic cross-sectional view of an example of a TFT according to this embodiment. The TFT 50 is a top-gate TFT and includes a substrate 21, a buffer layer 22, a channel layer (crystalline oxide thin film) 11, an ITO layer 23, a gate insulating film 24, a gate electrode 25, an interlayer insulating film 26, a source electrode 27, a drain electrode 28, and a protective film 29. The TFT 50 has a structure in which the substrate 21, the buffer layer 22, and the channel layer (crystalline oxide thin film) 11 are stacked in this order. A high-resistance region 11B is located in the center of the channel layer 11, and a gate insulating film 24 and a gate electrode 25 are stacked in this order on the high-resistance region 11B. The gate insulating film 24 is an insulating film that blocks electrical conduction between the gate electrode 25 and the channel layer (crystalline oxide thin film) 11. Low-resistance regions 11A-1 and 11A-2 of the channel layer 11 are located on both sides of the high-resistance region 11B. The low-resistance regions 11A-1, 11A-2 and the gate electrode 25 are covered with an ITO layer 23 and an interlayer insulating film 26. The ITO layer 23 is used to form the low-resistance regions of the channel layer 11. A source electrode 27 and a drain electrode 28 are connected to the low-resistance regions 11A-1 and 11A-2, respectively, via contact holes provided in the ITO layer 23 and the interlayer insulating film 26. The source electrode 27 and the drain electrode 28 are conductive terminals for passing source current and drain current through the channel layer 11. A protective film 29 is provided to cover the TFT constituent layers, such as the interlayer insulating film 26, the source electrode 27, and the drain electrode 28.

[0081] The buffer layer 22 may be composed of a single layer or may have a laminated structure of two or more layers. A metal layer may be provided between the buffer layer 22 and the substrate 21. However, it is preferable that the channel layer 11 and the buffer layer 22 are in direct contact with each other as shown in FIG. 1. The material for forming the buffer layer 22 will be described later. The thickness of the buffer layer 22 is not particularly limited, but is, for example, 50 to 600 nm.

[0082] In addition, although the interlayer insulating film 26 is a single layer in FIG. 1, the interlayer insulating film 26 may have a two-layer structure.

[0083] The TFT of this embodiment can be improved by a known configuration. For example, although not shown in Fig. 1, the TFT 50 may have a write shield layer 31 formed between the substrate 21 and the buffer layer 22 as shown in Fig. 2, or the write shield layer 31 may be formed as an intermediate layer in the buffer layer 22, which is made up of multiple laminated layers.

[0084] 2 is a schematic cross-sectional view of another example of a TFT according to this embodiment. The TFT 51 has the same configuration as the TFT 50, except that a write shield layer 31 is provided between the substrate 21 and the buffer layer 22. The write shield layer 31 is formed to prevent malfunction of the TFT due to light. The write shield layer may be connected to either the source electrode 27 or the gate electrode 25.

[0085] 1 shows an example of a TFT of the present invention in which both ends of the channel layer 11, i.e., near the regions where the source electrode 27 and the drain electrode 28 are connected, are made of low-resistance regions 11A of a crystalline oxide thin film, and the region in contact with the lower surface of the gate insulating film 24 is made of high-resistance regions 11B. However, the TFT of the present invention is not limited to this configuration. That is, the TFT of the present invention may use a crystalline oxide thin film whose resistance value is uniform in the surface direction as the channel layer 11. In this case, as shown in FIG. 3, the ITO layer 23 does not need to be formed.

[0086] 3 is a schematic cross-sectional view of another example of a TFT according to the present embodiment. The TFT 52 has a similar configuration to the TFT 50, except that the channel layer (crystalline oxide thin film) 11 is a layer without a boundary between resistance values ​​(the channel layer (crystalline oxide thin film) 11 is not divided into a low resistance region 11A and a high resistance region 11B), and the ITO layer 23 is not provided.

[0087] In this embodiment, when the TFT is a small TFT, the crystalline oxide thin film as a channel layer for the source electrode and drain electrode has a channel length (L length; in FIG. 1, the length in the source electrode 27-drain electrode 28 direction in the contact region between the channel layer 11 and the gate insulating layer 24) of 1 μm or more and 50 μm or less, and a channel width (W length; in FIG. 1, the length in the direction perpendicular to the source electrode 27-drain electrode 28 direction in the contact region between the channel layer 11 and the gate insulating layer 24) of 1 μm or more and 80 μm or less.

[0088] The material for forming the substrate is not particularly limited, and any commonly used material can be selected. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. It is also possible to use a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, or an SIO (Silicon In Insulator) substrate. These substrates on which semiconductor elements are provided may also be used as the substrate.

[0089] A flexible substrate may also be used as the substrate. As a method for providing a TFT on a flexible substrate, in addition to a method for directly fabricating a TFT on a flexible substrate, there is also a method for fabricating a TFT on a non-flexible substrate, and then peeling the TFT and placing it on a flexible substrate. In this case, it is preferable to provide a peeling layer between the non-flexible substrate and the TFT.

[0090] There is no particular limitation on the material for forming the buffer layer, and any commonly used material can be selected. Alternatively, a laminated film can be used as the buffer layer. For example, SiO ２ , SiO ｘ , SiN ｘ , silicon oxynitride, Al ２ O ３ , Ta ２ O ５ , TiO ２ , MgO, ZrO ２ , Ga ２ O ３ , GeO ２ , Nd ２ O ３ , La ２ O３ , CeO ２ , K. ２ O, Li ２ O, Na ２ O, Rb ２ O, Sc ２ O ３ , Y ２ O ３ , HfO ２ , CaHfO ３ , PbTiO ３ ,BaTa ２ O ６ , SrTiO ３ , Sm ２ O ３ , AlN, etc. The oxidation number of each material may be varied.

[0091] The buffer layer 22 can be designed appropriately according to the type of substrate (for example, a glass substrate, a resin substrate such as polyimide). As the material of the buffer layer 22 in contact with the channel layer 11, among the above-mentioned materials, SiO ２ It is preferable that the material of the buffer layer 22 in contact with the channel layer 11 is SiO ２ If so, the channel layer (crystalline oxide thin film) 11 tends to have a high proportion of FFT images of cross-sectional TEM images showing the FFT specific plane orientation, and has a good crystal structure.

[0092] In FIG. 2, a second buffer layer may be provided between the write shield layer 31 and the substrate 21. There are no particular restrictions on the material for forming the second buffer layer, and any commonly used material may be selected. A laminated film may also be used as the second buffer layer. Examples of materials for the second buffer layer include SiO ２ , SiN ｘ , silicon oxynitride, Al ２ O ３ , Ta ２ O ５ , TiO ２ , MgO, ZrO ２ , Ga ２ O ３ , GeO ２ , Nd ２ O ３ , La ２ O ３ , CeO２ , K. ２ O, Li ２ O, Na ２ O, Rb ２ O, Sc ２ O ３ , Y ２ O ３ , HfO ２ , CaHfO ３ , PbTiO ３ ,BaTa ２ O ６ , SrTiO ３ , Sm ２ O ３ , AlN, etc. The oxidation number of each material may be varied.

[0093] There is no particular limitation on the material for forming the gate insulating film, and any commonly used material can be selected. Also, a laminated film can be used as the gate insulating film. For example, SiO ２ , SiN ｘ , silicon oxynitride, Al ２ O ３ , Ta ２ O ５ , TiO ２ , MgO, ZrO ２ , Ga ２ O ３ , GeO ２ , Nd ２ O ３ , La ２ O ３ , CeO ２ , K. ２ O, Li ２ O, Na ２ O, Rb ２ O, Sc ２ O ３ , Y ２ O ３ , HfO ２ , CaHfO ３ , PbTiO ３ ,BaTa ２ O ６ , SrTiO ３ , Sm ２ O ３ , AlN, etc. The oxidation number of each material may be varied.

[0094] There are no particular limitations on the materials for forming the drain electrode, source electrode, and gate electrode, and any commonly used material can be selected. For example, ITO, IZO, ZnO, and SnO ２ For example, a transparent electrode such as a metal electrode made of Al, Ag, Cu, Cr, Ni, Co, Mo, Au, Ti, Zr, Ru, Y, Nb, W, Ta, or an alloy containing any of these may be used. Also, a laminated electrode having two or more layers may be used.

[0095] There is no particular limitation on the material for forming each interlayer insulating film, and any commonly used material can be selected. Also, a laminated film can be used as the interlayer insulating film. For example, SiO ２ , SiN ｘ , silicon oxynitride, Al ２ O ３ , Ta ２ O ５ , TiO ２ , MgO, ZrO ２ , Ga ２ O ３ , GeO ２ , Nd ２ O ３ , La ２ O ３ , CeO ２ , K. ２ O, Li ２ O, Na ２ O, Rb ２ O, Sc ２ O ３ , Y2O ３ , HfO ２ , CaHfO ３ , PbTiO ３ ,BaTa ２ O ６ , SrTiO ３ , Sm ２ O ３ The oxidation number of each material may vary.

[0096] The material for forming the write shield layer is not particularly limited, and any commonly used material can be selected. Specifically, metal electrodes such as Al, Ag, Cu, Cr, Ni, Co, Mo, Au, Ti, Zr, Ru, Y, Nb, Ta, and W, alloys of these, and laminates of these can be used.

[0097] Regardless of the structure of the TFT, it is preferable to provide a protective film on the drain electrode, the source electrode, and the conductive region. By providing a protective film, the durability of the TFT is likely to be improved even when driven for a long period of time.

[0098] There is no particular limitation on the method for producing insulating films such as buffer layers, gate insulating films, interlayer insulating films, and protective films. Examples of the production methods include PE-CVD, ALD, PLD, MO-CVD, RF sputtering, ICP sputtering, reactive sputtering, ICP-CVD, ion plating, the sol-gel method, coating methods, and mist CVD. The gas species used in PE-CVD include silane (SiH ４ Besides, tetraethoxysilane (TEOS) can also be used.

[0099] For example, when forming the gate insulating film by PE-CVD, the process may require high temperatures. Furthermore, insulating films such as buffer layers, gate insulating films, interlayer insulating films, and protective films often contain impurity gases immediately after deposition, making it preferable to perform heat treatment (annealing). Removing the impurity gases through heat treatment results in a stable insulating film, facilitating the formation of highly durable TFTs. Furthermore, by performing annealing after gate insulating film formation, hydrogen contained in the gate insulating film diffuses into the oxide thin film, terminating crystal defects present on the surface of the oxide thin film with hydroxyl groups. As a result, an oxide thin film with few electron traps and good conductivity can be formed.

[0100] Among the methods mentioned above, the buffer layer can be preferably produced by RF sputtering, reactive sputtering, PE-CVD, coating, etc. Among these, the PE-CVD method is preferably used because it has high productivity and is a widely used method.

[0101] The saturated mobility of the TFT is 10.0 cm２ / V・s or more, 200.0cm ２ / V·s or less is preferable, and 20.0 cm ２ / V・s or more, 150.0cm ２ / V·s or less is more preferable. ２ By setting the value to be / V·s or more, it becomes possible to achieve higher resolution, a higher frame rate, and a larger display area.

[0102] The saturation mobility of the TFT is determined from the transfer characteristics when a drain voltage of 20 V is applied. The method for measuring the saturation mobility of the TFT will be explained in detail in the Examples.

[0103] The threshold voltage (Vth) is preferably −3.0 V or more and 3.0 V or less, more preferably −2.0 V or more and 2.0 V or less, and even more preferably −1.0 V or more and 1.0 V or less. When the threshold voltage (Vth) is −3.0 V or more and 3.0 V or less, a Vth correction circuit can be installed in the TFT to correct Vth to 0 V. When the TFT obtained in this way is installed in a panel, the display can be driven without uneven brightness or burn-in. The method for measuring the threshold voltage (Vth) will be described in detail in the Examples.

[0104] On-off ratio is 10 ６ That's it, 10 １２ The following is preferred: ７ That's it, 10 １１ More preferably, 10 or less ８ That's it, 10 １０ More preferably, the on-off ratio is 10 or less. ６ If the on-off ratio is 10 or more, the liquid crystal display can be driven. １２ When the on-off ratio is 10 or less, an organic EL element with high contrast can be driven. １２ If the off-state current is 10 －１２ A or less, and when used in the transfer transistor or reset transistor of a CMOS image sensor, it is possible to extend the image retention time and improve the sensitivity.

[0105] The on-off ratio is determined by determining the ratio [on current value / off current value], where the value of Id when Vg = -10 V is the off current value and the value of Id when Vg = 20 V is the on current value. －１０ A or less is preferable, and 10 －１１ A or less is more preferable, and 10 －１２ A or less is more preferable. －１０ When the dielectric constant is A or less, it is possible to drive an organic EL element with high contrast. Furthermore, when the dielectric constant is used in a transfer transistor or reset transistor of a CMOS image sensor, it is possible to extend the image retention time and improve the sensitivity.

[0106] The leakage current is 1 x 10 －１０ A or less is preferable, and 1 × 10 －１１ A or less is more preferable, and 1×10 －１２ The TFT of this embodiment has a high proportion of the crystalline oxide thin film of the channel layer exhibiting the FFT-specific plane orientation, and also has a good crystalline state in which, for example, double-layer crystallization in the film thickness direction is suppressed and many columnar single-layer crystals are present, so that the leakage current is suppressed as described above, and the TFT can exhibit good TFT characteristics. －１０ A value of 0.01 A or less allows driving of an organic EL element with high contrast. Furthermore, when used in a transfer transistor or reset transistor of a CMOS image sensor, it is possible to extend the image retention time and improve the sensitivity. The method for measuring the leakage current will be described in detail in the Examples.

[0107] The TFT according to this embodiment can be suitably used in display elements such as solar cells, liquid crystal elements, organic electroluminescence elements, and inorganic electroluminescence elements, power semiconductor elements, touch panels, and other electronic devices.

[0108] The thin film transistor according to this embodiment can be applied to various integrated circuits such as field-effect transistors, logic circuits, memory circuits, and differential amplifier circuits, and these can be applied to electronic devices, etc. Furthermore, the thin film transistor according to this embodiment can be applied to static induction transistors and Schottky barrier transistors in addition to field-effect transistors. The thin film transistor according to this embodiment can be suitably used in display devices such as portable or in-vehicle display devices, solid-state imaging devices, etc. Furthermore, the thin film transistor according to this embodiment can also be suitably used as a transistor for flat panel detectors for X-ray image sensors in medical applications. The crystalline oxide thin film according to this embodiment can also be applied to Schottky diodes, resistance change type memories, and resistance elements.

[0109] The present invention will be specifically described below based on examples, but the present invention is not limited to these examples.

[0110] [Manufacturing of a small TFT with a self-aligned top-gate (SA-TG) structure] Example 1 The thin film transistor 50 shown in FIG. 1 was manufactured by the following steps: (1-1) Buffer layer (SiO ｘ Formation of a layer (sputtering) SiO ２ A 300 nm thick SiO film was deposited by sputtering on a 4-inch diameter non-alkali glass substrate (support) 21 (manufactured by Corning Inc., EAGLE XG) using a sputtering target of ｘ The sputtering conditions were as follows: substrate temperature: 25°C, ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF300W Distance between S (substrate) and T (target): 70 mm

[0111] (2) Formation of Oxide Thin Film Next, an oxide thin film was formed by sputtering using an oxide sputtering target obtained from a raw material mixture having the composition ratio shown in Table 1. The composition ratio (unit: mass%) and metal composition ratio (unit: at%) of the oxide sputtering target are shown in Table 1. The film formation conditions in sputtering and the thickness of the channel layer are shown in Table 1. The sputtering conditions other than those shown in Table 1 were as follows: Substrate temperature: 25°C Ultimate pressure: 1.0 x 10 －４ Pa Input voltage: DC 300W Distance between S (substrate) and T (target): 70 mm

[0112] (3) Formation of Channel Layer Next, the oxide thin film was patterned into islands by photolithography to form a channel layer. First, a photoresist film was formed on the oxide thin film. AZ1500 (manufactured by AZ Electronic Materials) was used as the photoresist. Exposure was performed through a photomask with a pattern formed with the long and short side sizes shown in Table 1. After exposure, development was performed with tetramethylammonium hydroxide (TMAH). After development, the oxide thin film was etched with oxalic acid (ITO-06N, manufactured by Kanto Chemical). After etching, the photoresist was peeled off to obtain a substrate with a patterned oxide thin film (channel layer). The long and short side sizes of the obtained channel layer are shown in Table 1.

[0113] (4) Annealing Next, the substrate on which the channel layer was formed was placed in a furnace, and the temperature was increased to 350°C at a rate of 10°C / min in the atmosphere, and then maintained at that temperature for 1 hour. After the inside of the furnace was maintained at 350°C for 1 hour, the inside of the furnace was allowed to cool naturally, and after the temperature inside the furnace returned to room temperature, the substrate was removed from the furnace.

[0114] (5) Formation of the first gate insulating film. Then, SiO ２ The sputtering was performed using a sputtering target of 10 nm thick to obtain a SiO ｘ The sputtering conditions were as follows: substrate temperature: 25° C., ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar + O ２ Mixture of gases (O２ Flow rate 30%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF100W Distance between S (substrate) and T (target): 70 mm

[0115] (6) Annealing of first gate insulating film Next, the substrate was placed in a furnace, and the temperature was raised to 400°C at a rate of 10°C / min in the atmosphere, and then held for 1 hour. The inside of the furnace was held at 400°C for 1 hour, and then naturally cooled. After the temperature inside the furnace returned to room temperature, the substrate was removed from the furnace.

[0116] (7) Formation of second gate insulating film Next, SiO ２ A 100 nm thick SiO film was formed by sputtering using a sputtering target of ｘ The sputtering conditions were as follows: substrate temperature: 25° C., ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar + O ２ Mixture of gases (O ２ Flow rate: 30%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF100W Distance between S (substrate) and T (target): 70 mm As a result, the total thickness of the gate insulating film layer consisting of the first and second gate insulating films was 110 nm.

[0117] (8) Formation of Gate Electrode Next, a Mo film having a thickness of 150 nm was formed using a Mo sputtering target. The sputtering conditions were as follows: substrate temperature: 25°C, ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar Sputtering pressure (total pressure): 0.4 Pa Input voltage: DC 100 W Distance between S (substrate) and T (target): 70 mm

[0118] (9) Patterning of the Gate Electrode and Gate Insulating Film Layer Next, the Mo film and gate insulating film layer were patterned into islands by photolithography. First, a photoresist film was formed on the channel layer. AZ1500 (manufactured by AZ Electronic Materials) was used as the photoresist. Exposure was performed through a photomask with a pattern of 10 μm horizontal x 28 μm vertical. After exposure, development was performed with tetramethylammonium hydroxide (TMAH). After development, the Mo film was etched with PAN (a mixed acid of phosphoric acid, nitric acid, and acetic acid) to form a gate electrode. Next, the gate insulating film layer was etched with buffered hydrofluoric acid (BHF) to form an island pattern. Next, the photoresist was stripped, and the exposed region of the channel layer was etched to a thickness of 10 nm using oxalic acid (ITO-06N, manufactured by Kanto Chemical Co., Ltd.) and then washed. The dimensions of the obtained gate electrode layer and gate insulating layer were 10 μm in width×10 μm in length (size of the short side of the channel layer (μm)+8 (μm)).

[0119] (10) Resistance Reduction Treatment A low-resistance region was formed in the channel layer by self-alignment using the gate electrode. An ITO layer with a thickness of 2 nm was formed using an ITO sputtering target. The sputtering conditions were as follows: Substrate temperature: 25°C; Ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar + O ２ Mixture of gases (O ２ Flow rate 2%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: DC 100 W Distance between S (substrate) and T (target): 70 mm

[0120] Next, the substrate was placed in a furnace, and the temperature was raised to 350°C at a rate of 10°C / min in the atmosphere, and then held for 1 hour for annealing. The inside of the furnace was held at 350°C for 1 hour, and then allowed to cool naturally. After the temperature inside the furnace returned to room temperature, the substrate was removed from the furnace.

[0121] (11) Formation of interlayer insulating film Next, SiO ２ A sputtering target of 150 nm thick was used for sputtering. ｘThe sputtering conditions were as follows: substrate temperature: 25°C, ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar + O ２ Mixture of gases (O ２ Flow rate 30%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF100W Distance between S (substrate) and T (target): 70 mm

[0122] (12) Formation of Contact Holes in Interlayer Insulating Film The substrate on which the interlayer insulating film was formed was exposed to light through a photomask using photoresist AZ1500 (manufactured by AZ Electronic Materials Co., Ltd.), and then developed with tetramethylammonium hydroxide (TMAH). After development, contact holes measuring 6 μm wide x 6 μm long (the size of the short side of the channel layer (μm) - 4 (μm)) were formed using buffered hydrofluoric acid (BHF).

[0123] (13) Formation of Source and Drain Electrodes Using image reversal resist AZ5214 and a photomask, the source and drain electrode layers were patterned by a lift-off process. The image reversal resist AZ5214 was exposed through a photomask formed so as to be patterned into the final device shape shown in FIG. 1, and after a reversal bake process, the entire surface was exposed and developed with TMAH. A Mo layer with a thickness of 150 nm was formed on the substrate with the patterned resist under the following sputtering conditions: Substrate temperature: 25°C Ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar Sputtering pressure (total pressure): 0.4 Pa Input voltage: DC 100 W Distance between S (substrate) and T (target): 70 mm Thereafter, the substrate on which the Mo layer was formed was lifted off in acetone to pattern the source electrode and drain electrode layers.

[0124] (14) Final annealing Finally, N ２The resulting device (a self-aligned top-gate TFT) had a channel length (also called L length, hereinafter referred to as channel length) of 10 μm and a channel width equal to the short side size (μm) of the channel layer shown in Table 1.

[0125] Examples 2 to 6 TFTs were fabricated in the same manner as in Example 1, except that the film thickness and short side size of the channel layer and the method of forming the buffer layer were changed as shown in Table 1. The buffer layers in Examples 2 and 4 were formed by the following method.

[0126] (1-2) Buffer layer (SiO ｘ The formation of a film (PE-CVD; plasma-enhanced chemical vapor deposition) is performed using monosilane (SiH ４ ) and nitrous oxide (N ２ O) and a 300 nm thick SiO ｘ The film was formed under the conditions of a substrate temperature of 350°C, a film formation pressure of 1 Torr, and N ２ O / SiH ４ The gas flow rate ratio was 50 and the RF power was 100W.

[0127]

[0128] Examples 7 to 11 TFTs were fabricated in the same manner as in Example 1, except that the film formation conditions, film thickness, and short side size of the channel layer, and the method of forming the buffer layer were changed as shown in Table 2. The buffer layer of Example 8 was formed in the same manner as in Example 2. The buffer layer of Example 11 was formed by the following method.

[0129] (1-3) Buffer layer (SiN ｘ Formation of a film (PE-CVD) using monosilane (SiH ４ ) and nitrogen (N ２ ) and a 300 nm thick SiN film was deposited by PE-CVD. ｘ The film was formed under the conditions of a substrate temperature of 350°C, a film forming pressure of 0.5 Torr, and N ２ / SiH４ The gas flow rate ratio was 100 and the RF power was 200W.

[0130]

[0131] Examples 12 to 17 TFTs were fabricated in the same manner as in Example 1, except that the composition ratio of the sputtering target used to form the channel layer, the channel layer formation conditions, the annealing conditions, the channel layer thickness, and the buffer layer formation method were changed as shown in Table 3. The buffer layers of Examples 13 and 15 were formed in the same manner as in Example 2. The buffer layer of Example 14 was formed by the following method.

[0132] (1-4) Buffer layer (Al ２ O ３ Formation of a film (ALD; Atomic Layer Deposition) using trimethylaluminum (Al(CH ３ ) ３ ) and water (H ２ O) was used, and a 100 nm thick Al film was deposited by the ALD method at a substrate temperature of 300°C. ２ O ３ The film was formed by repeating 1000 cycles of a process in which trimethylaluminum was introduced into a film-forming chamber, followed by nitrogen purging, and then water was introduced and nitrogen purging.

[0133]

[0134] Comparative Examples 1 to 8 TFTs were fabricated in the same manner as in Example 1, except that the composition ratio of the sputtering target used to form the channel layer, the channel layer formation conditions, annealing conditions, channel layer thickness, long and short side size, and buffer layer formation method were changed as shown in Table 4. The buffer layers of Comparative Examples 1 and 3 were formed in the same manner as in Example 2. In Comparative Example 6, a Si substrate with a 100 nm-thick thermally oxidized film was used as the substrate, and this thermally oxidized film (100 nm thick) was used as the buffer layer. The Si substrate with the thermally oxidized film was obtained by placing the Si substrate in a heating furnace with an oxygen-containing atmosphere and heating it at a furnace temperature of approximately 900 to 1100°C for a predetermined time.

[0135]

[0136] Examples 18 to 225, Comparative Example 9 TFTs were fabricated in the same manner as in Example 1, except that the composition ratio of the sputtering target used for forming the channel layer, the film formation conditions for the channel layer, the film thickness, short side and long side sizes of the channel layer, the annealing conditions, and the method for forming the buffer layer were changed as shown in Tables 5 to 19.

[0137]

[0138]

[0139]

[0140]

[0141]

[0142]

[0143]

[0144]

[0145]

[0146]

[0147]

[0148]

[0149]

[0150]

[0151]

[0152] In Tables 1 to 19, "-" indicates "0".

[0153] (A) Evaluation of Oxide Thin Film (a) Crystallinity after Film Deposition In the examples and comparative examples, the substrates with oxide thin films prepared in the same manner as the substrates with oxide thin films obtained in "(3) Formation of Channel Layer" were subjected to X-ray diffraction measurement to determine the crystallinity after film deposition. Specifically, an X-ray diffractometer ("SmartLab" model, manufactured by Rigaku Corporation) was used to irradiate the oxide thin film with a parallel beam of CuKα radiation (1.5418 Å), and the diffraction pattern was measured by 2θ / θ measurement in the 2θ range of 10 to 80°. Similar measurements were also performed on the alkali-free glass substrate (support) before the oxide thin film was deposited. The diffraction patterns before and after the oxide thin film deposition were compared, and oxide thin films that did not show an increase in diffraction peaks after the oxide thin film deposition were determined to be "amorphous." On the other hand, oxide thin films that showed an increase in diffraction peaks after the oxide thin film deposition were determined to be "crystalline." The results are shown in Tables 1 to 19.

[0154] The TFTs obtained in the examples and comparative examples were evaluated as follows. The results are shown in Tables 20 to 31. In the tables, "E+XX" means "×10 ＸＸ " means.

[0155] (B) Evaluation of TFT Channel Layer (Crystalline Oxide Thin Film) Regarding the crystalline state of the cross section of the channel layer in the TFT, the channel layer was pretreated using a focused ion beam (FIB) and the cross section of the channel layer was observed using a transmission electron microscope (TEM) to evaluate (a) the average spacing D of the crystal grain boundaries and (b) the crystalline state.

[0156] Specifically, first, an ion beam was applied perpendicular to the surface of the channel layer using an FIB (Hitachi High-Technologies Corporation, "FB2100") device, and a test piece measuring 16 μm x 4 μm was sampled at an acceleration voltage of 40 kV. Then, a sample was extracted from the sampled test piece in the region where the gate electrode, gate insulating film, and oxide thin film overlapped in the channel length direction (horizontal direction in the drawing). The extracted sample was processed at an acceleration voltage of 20 kV using an FIB (JEOL Ltd., "JIB-4700F") device in the channel width direction (depth direction in the drawing), perpendicular to the channel length direction and film thickness direction, until the thickness of the thin piece was approximately 100 nm, thereby thinning the sample. Cross-sectional TEM images were observed using a transmission electron microscope (JEOL Ltd., "JEM-F200") under conditions where the substrate was flat and no external force was applied. Observations were performed at an acceleration voltage of 200 kV and at the magnification described below.

[0157] (a) Average spacing D of crystal grain boundaries. The average spacing D when observing the cross section of an oxide thin film can be calculated by analyzing the spacing between crystal grains observed by cross-sectional TEM. A field of view centered on the center of the thin film TFT in the channel length direction, with an oxide film thickness of 5 μm in the channel length direction, was extracted from an image observed at 20,000x magnification, and a cross-sectional TEM image was observed. Image analysis was performed on the obtained cross-sectional TEM image using "SPIP, Version 4.3.2.0" manufactured by Image Metrology, Inc. to calculate the average spacing D of crystal grain boundaries. Details are as follows. Lines with color codes H0, S0, and V10 were drawn on the crystal grain boundaries in the cross-sectional TEM image. Furthermore, image analysis software was used to quantify the contrast, and a height of (maximum density - minimum density) x 1 / 4 was set as the threshold. Regions showing a contrast below the threshold were defined as crystal grain boundaries, and the spacing between each crystal grain boundary and the nearest particle was determined to be the spacing of the crystal grain boundaries. The sum of the obtained intervals between the crystal grain boundaries was divided by the number of locations where the intervals were measured to obtain the average interval D between the crystal grain boundaries. In the evaluation of the crystalline state (b) described below, for samples determined to be "two-layer crystals," analysis of the grain boundaries of the columnar crystals was not possible, and therefore measurement was not possible.

[0158] (b) Crystalline State The crystalline state was determined by observing the electron beam diffraction pattern of the sample obtained by observing the cross-sectional TEM image. Specifically, using an electron microscope (JEOL "JEM-F200"), the oxide thin film area observed in the cross-sectional TEM image at a magnification of 1,000,000 times was irradiated with an electron beam at an accelerating voltage of 200 kV using a selected area aperture to set the irradiation area to approximately 100 nmφ. The diffraction pattern was measured. Ten fields of view were extracted at approximately equal intervals within a 10 μm range in the channel length direction of the cross-sectional TEM image sample, so that the observation points did not overlap. When the length in the channel length direction was short and the extraction range was limited to less than 10 μm, ten fields of view were extracted at approximately equal intervals within a range corresponding to the channel length, so that the observation points did not overlap. An oxide thin film that did not show a clear diffraction spot in any of the ten extracted fields of view was determined to be "amorphous." On the other hand, when symmetrical diffraction points were observed in the diffraction pattern in any field of view and no two-layer crystallization in the thickness direction of the oxide thin film was confirmed in the cross-sectional TEM image in any field of view, it was judged to be a "columnar crystal." Also, when two-layer crystallization in the thickness direction of the oxide thin film was confirmed in the cross-sectional TEM image, it was judged to be a "two-layer crystal."

[0159] (c) FFT specific plane orientation ratio The FFT specific plane orientation ratio was calculated by comparing the image obtained by performing a two-dimensional Fourier transform (FFT: Fast Fourier Transformation) on the TEM image obtained by observing the cross-sectional TEM image with the reciprocal lattice simulation results. The FFT image was obtained by performing calculations using the software ImageJ (free software ver. 1.451 (2011 / 07 / 20)). The simulation was performed using the software ReciPro (free software ver. 4.797 (2021 / 03 / 24)). ２ O ３A reciprocal lattice simulation and a TEM image simulation were carried out for the bixbyite structure of the above compound. In the simulation, the crystal structure data for the bixbyite structure used was 14388 from the Inorganic Crystal Structure Database (ICSD: Chemical Information Association), with a space group of Ia-3 and a lattice constant of a = 10.17700 Å. The reciprocal lattice simulation was carried out in a range where reciprocal lattice points with a lattice spacing of at least 0.8 Å were displayed, and the results were obtained with an image size with the same vertical and horizontal dimensions.

[0160] In ２ O ３FIG. 4 shows an FFT image obtained by two-dimensional Fourier transform of the TEM image simulation results of the bixbyite structure. The patterns A, B, C, D, E, F, G, H, and I shown in FIG. 4 correspond to the crystal planes (100), (110), (111), (211), (411), (125), (210), (310), and (320), in that order. The TEM images were taken from the oxide thin film area observed in the cross-sectional TEM image at a magnification of 1,000,000 times. Ten fields of view were extracted at approximately equal intervals within a 10 μm range in the channel length direction so that the observation points did not overlap. When the length in the channel length direction was short and the extraction range was limited to less than 10 μm, ten fields of view were extracted at approximately equal intervals within a range corresponding to the channel length so that the observation points did not overlap. In each extracted field of view, a TEM image of a lattice image in which a regular atomic arrangement can be confirmed was observed for a region that did not include grain boundaries in the channel length direction and did not include interfaces or grain boundaries in the film thickness direction. Whether or not the FFT image corresponded to any of the plane orientations of patterns A to I was evaluated by comparing it with the reciprocal lattice simulation (e.g., FIG. 6) for each crystal plane corresponding to the simulation pattern shown in FIG. 4. Specifically, the FFT image of each extracted field of view was enlarged or reduced within a range in which the size of the frequency domain was within an error of ±10% from the reciprocal lattice simulation so as not to change the aspect ratio of the image. The FFT image was then rotated in the two-dimensional plane direction of the image, and the FFT image with adjusted dimensions and tilt was superimposed so that the center of the image coincided with the reciprocal lattice simulation. Then, if the coordinates of eight or more points, from the brightest to the darkest bright points in the FFT image, matched for the crystal plane of any of patterns A to I, the field of view was determined to have an FFT-specific plane orientation. Here, if the central coordinates of each bright point in the FFT image fall within a radius of 2% of the pixel number of the image size of the reciprocal lattice simulation from the central coordinates of each reciprocal lattice point in the reciprocal lattice simulation, the coordinates are determined to match. The determination method for each crystal plane shown in Figure 4 is described below.

[0161] The crystal plane of A shown in Figure 4 is (100), and the image has a four-fold symmetry property, such that the pattern matches when the image is rotated 90° while the central coordinate is fixed. The interplanar spacings of the representative bright spots are 2.53 Å, 1.79 Å, and 1.27 Å, and bright spots with the same interplanar spacing exist at positions rotated 90°. The 1.79 Å bright spot is located on a coordinate axis rotated 45.0° from the 2.53 Å bright spot, and the 1.27 Å bright spot is on the same coordinate axis as the 2.53 Å bright spot. Eight bright spots randomly selected from a total of 12 bright spots, including four with interplanar spacings of 2.53 Å, four with interplanar spacings of 1.79 Å, and four with interplanar spacings of 1.27 Å, were checked for coincidence of coordinates.

[0162] The crystal plane of B shown in Figure 4 is (110), and has two-fold symmetry, so that the pattern matches when the image is rotated 180° while the central coordinate is fixed. The interplanar spacings of the representative bright spots are 2.53 Å, 2.92 Å, 1.79 Å, and 1.27 Å, and bright spots with the same interplanar spacing exist at positions rotated 180°. The 2.92 Å bright spot is located on a coordinate axis rotated 54.7° from the 2.53 Å bright spot, the 1.79 Å bright spot is located on a coordinate axis rotated 35.3° from the 2.92 Å bright spot, and the 1.27 Å bright spot is located on the same coordinate axis as the 2.53 Å bright spot. We checked whether the coordinates of eight bright points randomly selected from a total of 10 points: two bright points with a lattice spacing of 2.53 Å, four bright points with a lattice spacing of 2.92 Å, two bright points with a lattice spacing of 1.79 Å, and two bright points with a lattice spacing of 1.27 Å.

[0163] The crystal plane of C shown in Figure 4 is (111), and the pattern matches when the image is rotated 60° while the central coordinate is fixed. The interplanar spacings of the representative bright spots are 1.79 Å and 1.03 Å, and bright spots with the same interplanar spacing exist at a 60° rotation position. A bright spot with a 1.03 Å interplanar spacing is located on a coordinate axis rotated 30.0° from the 1.79 Å bright spot. Eight bright spots were randomly selected from a total of 12 bright spots, six with an interplanar spacing of 1.79 Å and six with an interplanar spacing of 1.03 Å, to confirm whether their coordinates matched.

[0164] The crystal plane of D shown in Figure 4 is (211), and has two-fold symmetry, so that the pattern matches when the image is rotated 180° while the central coordinate is fixed. The interplanar spacings of the representative bright spots are 2.92 Å, 1.53 Å, 1.79 Å, and 1.46 Å, and bright spots with the same interplanar spacing exist at positions rotated 180°. The 1.53 Å bright spot is located on a coordinate axis rotated 58.5° from the 2.92 Å bright spot, the 1.79 Å bright spot is located on a coordinate axis rotated 31.5° from the 1.53 Å bright spot, and the 1.46 Å bright spot is located on the same coordinate axis as the 2.92 Å bright spot. We checked whether the coordinates of eight bright points randomly selected from a total of 10 points: two bright points with a lattice spacing of 2.92 Å, four bright points with a lattice spacing of 1.53 Å, two bright points with a lattice spacing of 1.79 Å, and two bright points with a lattice spacing of 1.46 Å.

[0165] The crystal plane of E shown in Figure 4 is (411), and has two-fold symmetry, so that the pattern matches when the image is rotated 180° while the central coordinate is fixed. The interplanar spacings of the representative bright spots are 1.79 Å, 1.53 Å, 1.69 Å, and 0.89 Å, and bright spots with the same interplanar spacing exist at positions rotated 180°. The 1.53 Å bright spot is located on a coordinate axis rotated 64.8° from the 1.79 Å bright spot, the 1.69 Å bright spot is located on a coordinate axis rotated 25.2° from the 1.53 Å bright spot, and the 0.89 Å bright spot is located on the same coordinate axis as the 1.79 Å bright spot. We checked whether the coordinates of eight bright points randomly selected from a total of 10 points: two bright points with a lattice spacing of 1.79 Å, four bright points with a lattice spacing of 1.53 Å, two bright points with a lattice spacing of 1.69 Å, and two bright points with a lattice spacing of 0.89 Å.

[0166] The crystal plane of F shown in Figure 4 is (125), and has two-fold symmetry, so that the pattern matches when the image is rotated 180° while the central coordinate is fixed. The interplanar spacings of the representative bright spots are 2.26 Å, 1.53 Å, 2.07 Å, and 1.38 Å, and bright spots with the same interplanar spacing exist at positions rotated 180°. The 1.53 Å bright spot is located on a coordinate axis rotated 47.6° from the 2.26 Å bright spot, the 2.07 Å bright spot is located on a coordinate axis rotated 42.4° from the 1.53 Å bright spot, and the 1.38 Å bright spot is located on the same coordinate axis as the 2.07 Å bright spot. We checked whether the coordinates of eight bright points randomly selected from a total of 10 points: two bright points with a lattice spacing of 2.26 Å, four bright points with a lattice spacing of 1.53 Å, two bright points with a lattice spacing of 2.07 Å, and two bright points with a lattice spacing of 1.38 Å.

[0167] The crystal plane of G shown in Figure 4 is (210), and has two-fold symmetry, so that the pattern matches when the image is rotated 180° while the central coordinate is fixed. The interplanar spacings of the representative bright spots are 2.53 Å, 2.07 Å, 2.26 Å, and 1.27 Å, and bright spots with the same interplanar spacing exist at positions rotated 180°. The 2.07 Å bright spot is located on a coordinate axis rotated 65.9° from the 2.53 Å bright spot, the 2.26 Å bright spot is located on a coordinate axis rotated 24.1° from the 2.07 Å bright spot, and the 1.27 Å bright spot is located on the same coordinate axis as the 2.53 Å bright spot. We checked whether the coordinates of eight bright points randomly selected from a total of ten points: two bright points with a lattice spacing of 2.53 Å, four bright points with a lattice spacing of 2.07 Å, two bright points with a lattice spacing of 2.26 Å, and two bright points with a lattice spacing of 1.27 Å.

[0168] The crystal plane of H shown in Figure 4 is (310), and has two-fold symmetry, so that the pattern matches when the image is rotated 180° while the central coordinate is fixed. The interplanar spacings of the representative bright spots are 2.53 Å, 2.71 Å, 1.60 Å, and 1.27 Å, and bright spots with the same interplanar spacing exist at positions rotated 180°. The 2.71 Å bright spot is located on a coordinate axis rotated 57.7° from the 2.53 Å bright spot, the 1.60 Å bright spot is located on a coordinate axis rotated 32.3° from the 2.71 Å bright spot, and the 1.27 Å bright spot is located on the same coordinate axis as the 2.53 Å bright spot. We checked whether the coordinates of eight bright points randomly selected from a total of ten points: two bright points with a lattice spacing of 2.53 Å, four bright points with a lattice spacing of 2.71 Å, two bright points with a lattice spacing of 1.60 Å, and two bright points with a lattice spacing of 1.27 Å.

[0169] The crystal plane of I shown in Figure 4 is (320), and the pattern matches when the image is rotated 180° while the central coordinate is fixed. The interplanar spacings of the representative bright spots are 2.53 Å, 2.16 Å, and 2.71 Å, and bright spots with the same interplanar spacing exist at positions rotated 180°. A 2.16 Å bright spot is located on a coordinate axis rotated 50.2° from the 2.53 Å bright spot, and a 2.71 Å bright spot is located on a coordinate axis rotated 24.3° from the 2.16 Å bright spot. Eight bright spots randomly selected from a total of 10 bright spots (two with interplanar spacings of 2.53 Å, four with interplanar spacings of 2.16 Å, and four with interplanar spacings of 2.71 Å) were checked for coordinate agreement.

[0170] In the case of a "two-layer crystal" in which a two-layer crystallization state in the film thickness direction of the oxide thin film was confirmed in the cross-sectional TEM image, the largest region not including the two-layer crystallization state in the film thickness direction was extracted, and this region was evaluated for its FFT-specific plane orientation in the same manner as described above. The FFT images of the extracted 10 fields were compared with the simulation patterns (patterns A to I), and the number of fields determined to have the FFT-specific plane orientation was divided by the total number of fields observed (10) to calculate the FFT-specific plane orientation ratio (%) ((number of fields showing the FFT-specific plane orientation) / (total number of fields)).

[0171] (d) Average value of ε (lattice strain) The average value of ε (lattice strain) was calculated from the lattice constant obtained by analyzing the FFT image of the cross-sectional TEM image. ε (lattice strain) was calculated from the lattice constant obtained by analyzing each FFT image for each of the 10 fields of view extracted in "(c) FFT specific plane orientation ratio" that were determined to correspond to the FFT specific plane orientation. Each field of view was observed under conditions where the angle difference between the corresponding plane orientation and the axis of the observation direction was 1° or less. The lattice constant was calculated from the FFT image obtained from the TEM image of the lattice image observed at an observation magnification of 1,000,000 times (see Figure 5). The TEM image used included a layer in contact with the crystalline oxide thin film, and clearly identified the direction parallel to the interface of the crystalline oxide thin film on the alkali-free glass substrate (support) side (i.e., the direction parallel to the main surface of the crystalline oxide thin film, hereinafter referred to as the planar direction) and the direction perpendicular to the interface of the crystalline oxide thin film on the alkali-free glass substrate (support) side (i.e., the normal direction to the main surface of the crystalline oxide thin film, hereinafter referred to as the normal direction). In this TEM image, a region of 512 pixels x 512 pixels or more and 10 nm x 10 nm or more, which did not include the grain boundaries of the crystalline oxide thin film or adjacent layers, was subjected to two-dimensional Fourier transform processing to obtain an FFT image. The obtained FFT image was smoothed with a Gaussian filter to remove noise, and the coordinates of the vertices with the highest brightness among each bright spot were extracted, and these were used as the coordinates of the reciprocal lattice points.

[0172] Specifically, among the bright points located on a coordinate axis extending from the center coordinate of the FFT image in the normal direction, the vertex coordinates showing the highest brightness were designated as reciprocal lattice point P1. Furthermore, among the bright points located on a coordinate axis extending from the center coordinate of the FFT image in the planar direction, the vertex coordinates showing the highest brightness were designated as reciprocal lattice point P2. The sizes of the frequency domains (distances from the center coordinate of the FFT image) corresponding to these reciprocal lattice points P1 and P2 (vertex coordinates) were designated as plane spacing d1 and plane spacing d2, respectively. The plane spacing was calculated by converting the size of the frequency domain into the length of real space. Next, in the same manner as described in "(c) FFT specific plane orientation ratio", the In ２ O ３A reciprocal lattice simulation of the bixbyite structure was performed, and the simulation result of the obtained reciprocal lattice pattern (see FIG. 6; a pattern corresponding to any one of patterns A to I and the Miller indices of each bright spot) was compared with the pattern of the FFT image to be analyzed, and the Miller indices (h １ , k １ , l １ ), and the Miller indices of the reciprocal lattice point P2 (h ２ , k ２ , l ２ ) was identified. In the reciprocal lattice simulation, the Miller indices of each bright point can be identified, and by comparing with the FFT image to be analyzed, the Miller indices of each bright point of the FFT image can also be identified. Note that for each bright point of the FFT image, there is a bright point at a position rotated 180° from the central coordinates where the interplanar spacing is the same and the signs of the Miller indices are opposite to each other. However, since this does not affect the calculation results of the lattice constant, either positive or negative Miller indices may be used. The interplanar spacing d1 and Miller indices (h １ , k １ , l １ ) was used to calculate the lattice constant a in the normal direction by the following formula (1). ２ , k ２ , l ２ ) and the lattice constant b in the planar direction was calculated by the following formula (2).

[0173] Normal lattice constant a = √(h １ ２ +k １ ２ +h １ ２ )×d1...(Formula (1))

[0174] Lattice constant in the plane direction b = √(h ２ ２ +k ２ ２ +h ２ ２ )×d2...(Formula (2))

[0175] Specifically, the reciprocal lattice point P1 is a coordinate axis extending from the central coordinate of the FFT image, and the angle with the normal direction is in the range of ±30°. Among the bright points having a lattice spacing d1 in the range of 0.8 to 2.0 Å, the bright point that shows the highest brightness at an angle closer to the substrate normal was selected. Furthermore, the reciprocal lattice point P2 is a coordinate axis extending from the central coordinate of the FFT image, and the angle with the planar direction is in the range of ±30°. Among the bright points having a lattice spacing d2 in the range of 0.8 to 2.0 Å, the bright point that shows the highest brightness at an angle closer to the substrate plane was selected. Furthermore, the reciprocal lattice points P1 and P2 were selected such that the angle α between the coordinate axis on which the reciprocal lattice point P1 exists and the coordinate axis on which the reciprocal lattice point P2 exists is in the range of 70°<α<110°. The lattice strain ε was calculated from the lattice constant a in the normal direction and the lattice constant b in the planar direction according to the following formula (3).

[0176] Average value of ε (lattice strain) calculated for each field of view, ε ａｖｅｒ was calculated by arithmetic mean.

[0177] (C) Evaluation of TFT Performance The obtained TFTs were measured using a semiconductor parameter analyzer (Agilent Technologies, "B1500") at room temperature in a light-shielded environment (inside a shielded box). A drain voltage (Vd) of 20 V was applied. The Id-Vg characteristics were obtained by measuring the current value Id with respect to the applied Vd by varying the gate voltage (Vg) from -5 V to 20 V in 0.1 V steps. Various parameters calculated from the Id-Vg characteristics are shown in Tables 20 to 31. The calculation method for each parameter is as follows:

[0178] (a) Maximum Saturation Mobility The saturation mobility (μsat) was determined from the Id-Vg characteristics when Vd = 20 V was applied. To determine the maximum saturation mobility when Vd = 20 V was applied, a graph of the Id-Vg characteristics was created, the transconductance (Gm) for each Vg was calculated, and the saturation mobility (μsat) was derived using the formula for the saturation region. Specifically, Gm was calculated using the following formula (c1):

[0179] Furthermore, μsat was calculated using the following formula (c) in the saturation region: μsat = (2 Gm L) / (W Ci) (c) In formula (c), L is the channel length (L length) and W is the channel width (W length). Furthermore, the maximum value of μsat for Vg = 0 to 20 V was calculated from each Vg-μsat graph.

[0180] (b) S value and Vth The S value and threshold voltage (Vth) were evaluated from the graph of each Id-Vg characteristic. －１１ ~10 －１０ In the [A] region, the value obtained by the following formula (d) was calculated as the S value. －８ The value of Vg at [A] was calculated as the threshold voltage (Vth).

[0181]

[0182] (c) Leakage Current The leakage current was evaluated from the graph of each Id-Vg characteristic. The leakage current was the Id value measured when Vg was −5 V.

[0183] (d) Self-aligned Small TFT Reliability The reliability of the TFT was evaluated by stress tests. Three types of tests were performed: a positive bias heating stress test (PBTS), a negative bias heating stress test (NBTS), and a constant current stress test (CCS). In the PBTS test, Vg = +20 V was applied at 50°C, and the threshold voltage (Vth) after 10,000 seconds was compared with the threshold voltage before the test, and the difference was defined as ΔVth. In the NBTS test, Vg = -20 V was applied at 50°C, and the threshold voltage (Vth) after 10,000 seconds was compared with the threshold voltage before the test, and the difference was defined as ΔVth. In the CCS test, Vg = 10 V and Vd = 20 V were applied at room temperature, and Vg was controlled to maintain a constant current value Id before the stress application. The threshold voltage (Vth) after 10,000 seconds was compared with the threshold voltage before the test, and the difference was defined as ΔVth.

[0184]

[0185]

[0186]

[0187]

[0188]

[0189]

[0190]

[0191]

[0192]

[0193]

[0194]

[0195]

[0196] The crystalline oxide thin film of the present invention can be suitably used as a component of a thin film transistor, for example, as a channel layer, and can also be used in electronic circuits used in electrical equipment, electronic devices, vehicles, and power plants.

[0197] Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will readily be able to make numerous modifications to these exemplary embodiments and / or examples without substantially departing from the novel teachings and advantages of the present invention. Accordingly, these numerous modifications are within the scope of the present invention. The contents of all documents cited in this specification and of the applications from which this application claims priority under the Paris Convention are incorporated by reference in their entirety.

Claims

1. A crystalline oxide thin film having In as a main component, wherein more than 50% of the Fourier transform images obtained by subjecting the lattice images of a plurality of image regions extracted from a transmission electron microscope (TEM) image of the cross section of the crystalline oxide thin film to two-dimensional Fourier transform (FFT) processing each show any plane orientation selected from (100), (110), (111), (211), (411), (125), (210), (310), and (320). A crystalline oxide thin film.

2. For each of the Fourier transform images showing any plane orientation selected from (100), (110), (111), (211), (411), (125), (210), (310), and (320) obtained for the plurality of image regions, the magnitude of the frequency region from the center coordinates of the Fourier transform image to the reciprocal lattice point P1 selected from the bright spots located on the coordinate axis extending in the normal direction to the main plane of the crystalline oxide thin film is defined as the interplanar spacing d1 in the normal direction, and the magnitude of the frequency region from the center coordinates of the Fourier transform image to the reciprocal lattice point P2 selected from the bright spots located on the coordinate axis extending in the direction parallel to the main plane of the crystalline oxide thin film is defined as the interplanar spacing d2 in the plane direction. Let the Miller indices of the reciprocal lattice point P1 be (h １ , k １ , l １ ), and when the Miller indices of the reciprocal lattice point P2 are (h ２ , k ２ , l ２ ), The average value ε of the lattice strain ε of each of the plurality of image regions, calculated by the following formula (3) from the lattice constant a in the normal direction calculated by the following formula (1) and the lattice constant b in the plane direction calculated by the following formula (2) ａｖｅｒ where 1.0 < ε ａｖｅｒ < 1.1, the crystalline oxide thin film according to claim 1. The lattice constant a in the normal direction = √(h １ ２ + k １ ２ + l １ ２ ) × d1 … (Equation (1)) The lattice constant b in the plane direction = √(h ２ ２ + k ２ ２ + l ２ ２ ) × d2 … (Equation (2)) 【Number 6】

3. The crystalline oxide thin film according to claim 1, having a film thickness of 3 nm or more and less than 50 nm.

4. The crystalline oxide thin film according to claim 1, wherein the length of the short side of the crystalline oxide thin film is less than 50 μm.

5. The crystalline oxide thin film according to claim 1, wherein the average distance D between crystal grain boundaries is 0.01 μm or more and 2 μm or less.

6. The crystalline oxide thin film according to claim 1, containing 62 at% or more of In.

7. Furthermore, one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, and Bi. The crystalline oxide thin film according to claim 1.

8. A method for producing a crystalline oxide thin film according to any one of claims 1 to 7, wherein the oxide thin film formed on a support is annealed at a temperature exceeding 300 °C in an air atmosphere.

9. The manufacturing method of a crystalline oxide thin film according to claim 8, wherein the film thickness of the oxide thin film to be subjected to the annealing treatment is 3 nm or more and less than 50 nm.

10. The manufacturing method of a crystalline oxide thin film according to claim 8, wherein the short side of the oxide thin film to be subjected to the annealing treatment is less than 50 μm.

11. A thin film transistor including the crystalline oxide thin film according to any one of claims 1 to 7.

12. It has a buffer layer and a channel layer, wherein the channel layer is the crystalline oxide thin film, The thin film transistor according to claim 11, wherein, when viewed from the channel layer, a gate insulating film and a gate electrode are provided on the side opposite to the buffer layer in this order from the channel layer side.

13. A step of forming an oxide thin film on a substrate, a step of annealing the oxide thin film at a temperature exceeding 300°C in an air atmosphere to form a crystalline oxide thin film, A method for manufacturing a thin film transistor according to claim 11, comprising a step of forming a gate insulating film and a gate electrode in this order on the crystalline oxide thin film.

14. The method for manufacturing a thin film transistor according to claim 13, wherein after forming a buffer layer on the substrate, the oxide thin film is formed on the buffer layer.

15. A step of forming an oxide thin film on a substrate, a step of annealing the oxide thin film at a temperature exceeding 300°C in an air atmosphere to form a crystalline oxide thin film, A method for manufacturing a thin film transistor according to claim 11, comprising a step of forming an interlayer insulating film in this order on the crystalline oxide thin film.

16. The method for manufacturing a thin film transistor according to claim 15, wherein after forming a gate electrode and a gate insulating film on the substrate in this order, the oxide thin film is formed on the gate insulating film.

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