Nitride semiconductor device

Abstract

This nitride semiconductor device comprises: a substrate; a drift layer; a first high-resistance semiconductor layer; a p-type nitride semiconductor layer; a second high-resistance semiconductor layer; a gate opening portion reaching the drift layer; an electron running layer and an electron supply layer; a gate electrode; a source electrode in contact with the electron supply layer; a source opening portion reaching the p-type nitride semiconductor layer; a potential-fixed electrode provided in contact with the p-type nitride semiconductor layer and connected to the source electrode; a drain electrode; a groove portion provided in a terminus portion of the nitride semiconductor device, penetrating through the p-type nitride semiconductor layer, and reaching the first high-resistance semiconductor layer; and an insulation film covering the gate electrode and the source electrode and provided along an inner surface of the groove portion. The first high-resistance semiconductor layer is a high-resistance AlGaN layer.

Description

Nitride Semiconductor Devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] Nitride semiconductors, typified by GaN (gallium nitride), are wide-gap semiconductors with a large band gap, and are characterized by a large breakdown field and a higher electron saturation drift velocity than compound semiconductors such as GaAs (gallium arsenide) or Si (silicon) semiconductors. For example, the band gaps of GaN and AlN (aluminum nitride) are 3.4 eV and 6.2 eV, respectively, at room temperature. For this reason, research and development is being conducted on power transistors using nitride semiconductors, which are advantageous for achieving high output and high breakdown voltage. For example, Patent Documents 1 and 2 disclose vertical FETs (Field Effect Transistors) having a GaN-based semiconductor layer.

[0003] International Publication No. 2021 / 070469 International Publication No. 2021 / 140898

[0004] However, there is room for improvement in the off-characteristics of the above-described conventional semiconductor devices.

[0005] The present disclosure provides nitride semiconductor devices with improved off-state characteristics.

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided above the substrate, a first high-resistance semiconductor layer provided above the first nitride semiconductor layer and having a higher resistance than the first nitride semiconductor layer, a first p-type nitride semiconductor layer provided above the first high-resistance semiconductor layer, a second high-resistance semiconductor layer provided above the first p-type nitride semiconductor layer and having a higher resistance than the first nitride semiconductor layer, a first opening that penetrates the second high-resistance semiconductor layer, the first p-type nitride semiconductor layer, and the first high-resistance semiconductor layer and reaches the first nitride semiconductor layer, and an electric field provided in this order from below to cover an upper surface of the second high-resistance semiconductor layer and the first opening. the first high-resistance semiconductor layer is a high-resistance AlGaN layer, and the second high-resistance semiconductor layer is a high-resistance AlGaN layer.

[0007] According to the present disclosure, it is possible to provide a nitride semiconductor device with improved off-state characteristics.

[0008] Fig. 1 is a cross-sectional view of a nitride semiconductor device according to a first embodiment. Fig. 2 is a plan view of the nitride semiconductor device according to the first embodiment. Fig. 3 is a cross-sectional view of a nitride semiconductor device according to a second embodiment. Fig. 4 is a cross-sectional view of a nitride semiconductor device according to a third embodiment. Fig. 5 is a cross-sectional view of a nitride semiconductor device according to a fourth embodiment.

[0009] (Findings that Form the Basis of the Present Disclosure) The inventors of the present application have found that the conventional nitride semiconductor devices described in the "Background Art" section have the following problems.

[0010] In the nitride semiconductor device disclosed in Patent Document 1, a highly resistive GaN layer and a p-type GaN layer located on the GaN layer are provided between the source electrode and the drift layer. The provision of the highly resistive GaN layer improves the breakdown voltage.

[0011] Furthermore, in the nitride semiconductor device disclosed in Patent Document 2, an undoped AlGaN layer and a p-type GaN layer located on the undoped AlGaN layer are provided between the source electrode and the drift layer. The undoped AlGaN layer generates two-dimensional electron gas near the interface with the undoped AlGaN layer in the drift layer. This widens the current path laterally, thereby reducing resistance during operation.

[0012] The present inventors have been studying the creation of a trench penetrating the p-type GaN layer at the device termination of such a conventional nitride semiconductor device. By creating the trench, the p-type GaN layer is prevented from appearing at the end facet, thereby suppressing leakage current flowing through the end facet.

[0013] However, in the nitride semiconductor device disclosed in Patent Document 1, when etching the p-type GaN layer to form the trenches, it is difficult to leave the highly resistive GaN layer with a uniform thickness. Specifically, microspikes occur, where etching locally reaches the drift layer. When the device is off, a voltage applied between the source and drain electrodes can cause leakage current between the p-type GaN layer and the drift layer through these microspikes.

[0014] Furthermore, the nitride semiconductor device disclosed in Patent Document 2 does not have a high-resistance layer, which may cause a decrease in breakdown voltage due to an increase in off-leakage during reverse conduction. Furthermore, the presence of two-dimensional electron gas in the drift layer makes it easy for the electric field to concentrate at the end faces of the trenches, which induces a deterioration in off-state characteristics.

[0015] Thus, degradation of off-state characteristics is a problem in conventional nitride semiconductor devices.

[0016] In contrast, a nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided above the substrate, a first high-resistance semiconductor layer provided above the first nitride semiconductor layer and having a higher resistance than the first nitride semiconductor layer, a first p-type nitride semiconductor layer provided above the first high-resistance semiconductor layer, a second high-resistance semiconductor layer provided above the first p-type nitride semiconductor layer and having a higher resistance than the first nitride semiconductor layer, a first opening that penetrates the second high-resistance semiconductor layer, the first p-type nitride semiconductor layer, and the first high-resistance semiconductor layer and reaches the first nitride semiconductor layer, and a second opening that is provided in this order from below to cover an upper surface of the second high-resistance semiconductor layer and the first opening. the first high-resistance semiconductor layer is a high-resistance AlGaN layer, and the second high-resistance semiconductor layer is a high-resistance AlGaN layer.

[0017] As a result, the high-resistivity AlGaN layer is provided between the source electrode and the first nitride semiconductor layer, thereby improving the breakdown voltage. Furthermore, the high-resistivity AlGaN layer functions as an etching stopper layer when forming the trench. This allows the high-resistivity AlGaN layer located at the bottom of the trench to remain, preventing the formation of leakage current paths such as microspikes. This prevents a decrease in the breakdown voltage of the device and improves the off-state characteristics.

[0018] Furthermore, for example, the nitride semiconductor device according to one aspect of the present disclosure may include a second nitride semiconductor layer provided between the first nitride semiconductor layer and the first high-resistance semiconductor layer, and the second nitride semiconductor layer may be an undoped AlGaN layer.

[0019] As a result, two-dimensional electron gas is generated in the first nitride semiconductor layer near the interface with the undoped AlGaN layer. Current spreads more easily laterally within the first nitride semiconductor layer, reducing the on-state resistance. The two-dimensional electron gas in the first nitride semiconductor layer also spreads near the grooves, making it easier for the electric field to concentrate at the end faces of the grooves. However, since a high-resistivity AlGaN layer is disposed at the bottom of the grooves, the device can withstand a high electric field, improving the breakdown voltage. In this way, both improved off-state characteristics and reduced on-state resistance can be achieved.

[0020] In addition, when the nitride semiconductor layer is etched to form the grooves, nitrogen is removed from the nitride semiconductor layer, and N vacancies are generated in the nitride semiconductor layer. In contrast, for example, the insulating film may contain at least Si and N.

[0021] This allows the N vacancies in the nitride semiconductor layer to be terminated, thereby suppressing the occurrence of current collapse.

[0022] Furthermore, for example, the nitride semiconductor device according to one aspect of the present disclosure may include a second p-type nitride semiconductor layer provided between the gate electrode and the electron supply layer.

[0023] This allows the second p-type nitride semiconductor layer to reduce the carrier concentration directly below the gate electrode, shifting the threshold voltage of the FET to the positive side, and therefore allowing the transistor portion of the nitride semiconductor device to operate as a normally-off FET.

[0024] Furthermore, for example, the nitride semiconductor device according to one aspect of the present disclosure may include a field plate provided above the insulating film so as to extend into the trench.

[0025] This can alleviate the concentration of the electric field at the end portion, further improving the off-state characteristics.

[0026] Furthermore, for example, the field plate may be electrically connected to the source electrode.

[0027] This further reduces the concentration of the electric field at the end portion, thereby further improving the off-state characteristics.

[0028] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0029] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0030] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0031] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangle or trapezoid, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0032] In this specification and the drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional Cartesian coordinate system. When the planar shape of the substrate is rectangular, the x-axis and y-axis are directions parallel to a first side of the rectangle and a second side perpendicular to the first side, respectively. The z-axis is the thickness direction of the substrate. In this specification, the "thickness direction" of the substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may also be referred to as the "lateral direction."

[0033] Furthermore, the side of the substrate on which the gate electrode and source electrode are provided (positive side of the z-axis) is considered to be the "upper" or "upper side," and the side of the substrate on which the drain electrode is provided (negative side of the z-axis) is considered to be the "lower" or "lower side."

[0034] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between them, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0035] In this specification, the term "plan view" refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, a view of the main surface of the substrate from the front.

[0036] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0037] In this specification, AlGaN refers to a ternary mixed crystal Al ｘ Ga １－ｘHereinafter, multi-element mixed crystals are abbreviated by the arrangement of the symbols of the respective constituent elements, such as AlInN, GaInN, etc. For example, AlInN, which is an example of a nitride semiconductor, ｘ Ga １－ｘ－ｙ In ｙ N (0<x<1, 0<y<1, and 0<x+y<1) is abbreviated as AlGaInN.

[0038] First Embodiment [Outline] First, an outline of a nitride semiconductor device according to a first embodiment will be described with reference to FIGS. 1 and 2. FIG.

[0039] Fig. 1 is a cross-sectional view of a nitride semiconductor device 1 according to this embodiment. Fig. 2 is a plan view of the nitride semiconductor device 1 according to this embodiment. Fig. 1 shows a cross section taken along line II in Fig. 2. Note that Fig. 1 shows a transistor section 2 and a termination section 3 separated from each other.

[0040] 1 , the nitride semiconductor device 1 includes a transistor portion 2 and a termination portion 3. Specifically, the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a first high-resistance semiconductor layer 14, a p-type nitride semiconductor layer 16, a second high-resistance semiconductor layer 18, a gate opening 20, an electron transit layer 22, an electron supply layer 24, a source opening 26, a source electrode 28, a potential fixing electrode 30, a gate electrode 32, and a drain electrode 34. The nitride semiconductor device 1 also includes a groove 40 provided in the termination portion 3, and an insulating film 42 provided across the transistor portion 2 and the termination portion 3.

[0041] 2, the transistor section 2 is a region including a FET, and is a region including the center of the nitride semiconductor device 1. Specifically, the transistor section 2 is a region in which the second high-resistance semiconductor layer 18, the gate opening 20, the electron transit layer 22, the electron supply layer 24, and the source electrode 28 or the gate electrode 32 are arranged in a plan view (see FIG. 1).

[0042] 2 does not show details of the components arranged in the transistor portion 2. As an example, a plurality of source electrodes 28 each elongated in one direction in plan view are arranged in a stripe pattern, and a gate electrode 32 and a gate opening 20 are arranged between adjacent source electrodes 28. Alternatively, a plurality of source electrodes 28 each hexagonal in plan view may be arranged so as to fill a plane with gaps between them.

[0043] The termination section 3 is a region other than the transistor section 2, and is provided in a ring shape surrounding the transistor section 2. The termination section 3 does not include the second high-resistance semiconductor layer 18, the gate opening 20, the electron transit layer 22, the electron supply layer 24, the source electrode 28, and the gate electrode 32.

[0044] In this embodiment, the nitride semiconductor device 1 is a device having a stacked structure of semiconductor layers mainly composed of nitride semiconductors such as GaN and AlGaN. Specifically, the nitride semiconductor device 1 has a heterostructure of an AlGaN film and a GaN film.

[0045] In a heterostructure of an AlGaN film and a GaN film, spontaneous polarization or piezoelectric polarization on the (0001) plane generates a high concentration of two-dimensional electron gas at the heterointerface. Therefore, even in an undoped state, a high concentration of two-dimensional electron gas of 1×10 １３ cm －２ The sheet carrier concentration can be obtained as above.

[0046] The nitride semiconductor device 1 according to this embodiment is a field effect transistor (FET) that uses, as a channel, a two-dimensional electron gas generated in the electron transit layer 22. Specifically, the nitride semiconductor device 1 is a so-called vertical FET.

[0047] The nitride semiconductor device 1 according to this embodiment is a normally-off FET. In the nitride semiconductor device 1, for example, the source electrode 28 is grounded (i.e., the potential is 0 V), and a positive potential is applied to the drain electrode 34. The potential applied to the drain electrode 34 is, for example, not limited to, 100 V or more and 1200 V or less. When the nitride semiconductor device 1 is in the off state, 0 V or a negative potential (e.g., −5 V) is applied to the gate electrode 32. When the nitride semiconductor device 1 is in the on state, a positive potential (e.g., +5 V) is applied to the gate electrode 32. Note that the nitride semiconductor device 1 may be a normally-on FET.

[0048] [Configuration of Transistor Portion] The configuration of the transistor portion 2 of the nitride semiconductor device 1 will be described below with reference to FIG.

[0049] The substrate 10 is a substrate made of a nitride semiconductor. The substrate 10 has a thickness of, for example, 300 μm and a donor concentration of 1×10 １８ cm －３ n ＋ The substrate 10 is made of GaN of the type 10. The top surface of the substrate 10 is substantially aligned with the (0001) plane (c-plane) of GaN.

[0050] In addition, n-type, n ＋ Type and n － type, as well as p-type, p ＋ Type and p － The type indicates the conductivity type of the semiconductor. ＋ Type and n － The p-type is an example of the first conductivity type of a nitride semiconductor. ＋ Type and p － The type is an example of a second conductivity type that has a polarity different from that of the first conductivity type.

[0051] The substrate 10 does not have to be a nitride semiconductor substrate, but may be, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate.

[0052] The drift layer 12 is an example of a first nitride semiconductor layer provided above the substrate 10. The drift layer 12 is, for example, an n-type nitride semiconductor layer having a thickness of 8 μm. － The drift layer 12 is a film made of GaN of the type. The drift layer 12 is provided in contact with the upper surface of the substrate 10. The donor concentration of the drift layer 12 is lower than the donor concentration of the substrate 10, for example, 1×10 １５ cm －３ 1x10 or more １７ cm －３ The drift layer 12 may also contain carbon (C). The carbon concentration of the drift layer 12 is lower than the carbon concentration of the first high-resistance semiconductor layer 14, for example, 1×10 １５ cm －３ 2 x 10 or more １７ cm －３ The following is the result.

[0053] The first high-resistance semiconductor layer 14 is an example of a first high-resistance semiconductor layer provided above the drift layer 12. The resistance of the first high-resistance semiconductor layer 14 is higher than the resistance of the drift layer 12. The thickness of the first high-resistance semiconductor layer 14 is, for example, 200 nm. The first high-resistance semiconductor layer 14 is provided in contact with the upper surface of the drift layer 12.

[0054] The first high-resistance semiconductor layer 14 is a high-resistance AlGaN layer. The high-resistance AlGaN layer is a layer containing AlGaN as a main component, and by containing a predetermined element, the layer has a higher resistance than undoped AlGaN. Note that "undoped" means that the layer is not substantially doped with a dopant such as Si, O (oxygen), or Mg (magnesium) that changes the polarity of a nitride semiconductor to n-type or p-type.

[0055] Specifically, the first high resistance semiconductor layer 14 is an AlGaN layer containing carbon (C). The carbon concentration is, for example, 3×10 １７ cm －３ or more, preferably 1 × 10 １８ cm －３The first high-resistance semiconductor layer 14 may be formed by implanting ions of magnesium (Mg), iron (Fe), boron (B), or the like into AlGaN. Ion species other than those mentioned above can be used for the ion implantation, and similar effects can be obtained as long as they are ion species that can increase the resistance.

[0056] The p-type nitride semiconductor layer 16 is an example of a first p-type nitride semiconductor layer provided above the first high-resistance semiconductor layer 14. The p-type nitride semiconductor layer 16 has a thickness of 400 nm and a carrier concentration of 1×10 １７ cm －３ p － The p-type nitride semiconductor layer 16 is a film made of p-type GaN. The p-type nitride semiconductor layer 16 contains, for example, magnesium (Mg) as a p-type impurity. The p-type nitride semiconductor layer 16 is provided in contact with the upper surface of the first high-resistance semiconductor layer 14.

[0057] The second high-resistance semiconductor layer 18 is an example of a second high-resistance semiconductor layer provided above the p-type nitride semiconductor layer 16. The resistance of the second high-resistance semiconductor layer 18 is higher than the resistance of the drift layer 12. The thickness of the second high-resistance semiconductor layer 18 is, for example, 200 nm. The second high-resistance semiconductor layer 18 is provided in contact with the upper surface of the p-type nitride semiconductor layer 16.

[0058] The second high-resistance semiconductor layer 18 is a high-resistance GaN layer. The high-resistance GaN layer is a layer containing GaN as a main component, and is a layer having a higher resistance than undoped GaN due to the inclusion of a predetermined element. Specifically, the second high-resistance semiconductor layer 18 is a GaN layer containing carbon (C). The carbon concentration is, for example, 3×10 １７ cm －３ or more, preferably 1 × 10 １８ cm －３ It may be more than that.

[0059] The gate opening 20 is an example of a first opening that penetrates the second high-resistance semiconductor layer 18, the p-type nitride semiconductor layer 16, and the first high-resistance semiconductor layer 14 and reaches the drift layer 12. As shown in FIG. 1 , the gate opening 20 has a bottom 20 a and a sidewall 20 b. The bottom 20 a is the upper surface of the drift layer 12 and is located below the interface between the first high-resistance semiconductor layer 14 and the drift layer 12. The sidewall 20 b is each of the end surfaces of the second high-resistance semiconductor layer 18, the p-type nitride semiconductor layer 16, and the first high-resistance semiconductor layer 14 and a part of the upper surface of the drift layer 12. The sidewall 20 b of the gate opening 20 is inclined obliquely with respect to the major surface of the substrate 10. For example, the cross-sectional shape of the gate opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid. Note that the cross-sectional shape of the gate opening 20 may be rectangular.

[0060] The electron transit layer 22 is provided to cover the upper surface of the second high-resistance semiconductor layer 18 and the gate opening 20. Specifically, the electron transit layer 22 is provided in contact with the upper surface of the second high-resistance semiconductor layer 18 and the sidewall 20b and bottom 20a of the gate opening 20. The electron transit layer 22 is a first regrowth layer formed by regrowth of a nitride semiconductor after the gate opening 20 is formed. The electron transit layer 22 has a substantially uniform thickness and is curved to fit the inner surface shape of the gate opening 20. The electron transit layer 22 is, for example, a 100 nm-thick film made of undoped GaN. The electron transit layer 22 may be doped with Si or the like to be n-type.

[0061] Furthermore, an AlN layer having a thickness of approximately 1 nm may be provided as a second regrown layer between the electron transit layer 22 and the electron supply layer 24. The AlN layer can suppress alloy scattering and improve channel mobility. The AlN layer does not necessarily have to be provided, and the electron transit layer 22 and the electron supply layer 24 may be in direct contact with each other. Within the electron transit layer 22, a two-dimensional electron gas (not shown) that serves as a channel is generated near the interface between the AlN layer and the electron transit layer 22.

[0062] The electron supply layer 24 is provided above the electron transit layer 22. Specifically, the electron supply layer 24 is provided along the upper surface of the electron transit layer 22. The electron supply layer 24 is a third regrowth layer formed by regrowth of a nitride semiconductor after the gate opening 20 is formed. The electron supply layer 24 has a substantially uniform thickness and is curved along the curved shape of the upper surface of the electron transit layer 22. The electron supply layer 24 is, for example, a 50 nm thick film made of AlGaN.

[0063] The source opening 26 is an example of a second opening that penetrates the second high-resistance semiconductor layer 18 at a position away from the gate electrode 32 and reaches the p-type nitride semiconductor layer 16. Specifically, the source opening 26 penetrates the electron supply layer 24, the electron transit layer 22, and the second high-resistance semiconductor layer 18 and reaches the p-type nitride semiconductor layer 16.

[0064] As shown in FIG. 1 , the source opening 26 has a bottom 26 a and a sidewall 26 b. The bottom 26 a is the upper surface of the p-type nitride semiconductor layer 16 and is located below the interface between the p-type nitride semiconductor layer 16 and the second high-resistance semiconductor layer 18. The sidewall 26 b is each of the end surfaces of the electron supply layer 24, the electron transit layer 22, and the second high-resistance semiconductor layer 18, and a part of the upper surface of the p-type nitride semiconductor layer 16. The sidewall 26 b of the source opening 26 is inclined obliquely with respect to the major surface of the substrate 10. For example, the cross-sectional shape of the source opening 26 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid. Note that the cross-sectional shape of the source opening 26 may also be rectangular.

[0065] The source electrode 28 is provided away from the gate electrode 32 and is in contact with the electron supply layer 24 and the electron transit layer 22. The source electrode 28 is provided so as to cover the bottom 26a and sidewall 26b of the source opening 26. The source electrode 28 is in direct contact with the two-dimensional electron gas in the electron transit layer 22 at the sidewall 26b of the source opening 26.

[0066] The source electrode 28 is formed using a conductive material such as a metal. The source electrode 28 may be made of a material that makes ohmic contact with an n-type semiconductor, such as titanium (Ti). The source electrode 28 may have a layered structure of a Ti film and an Al film. In this layered structure, the Al film is located below the Ti film, and this structure is referred to as Ti / Al in this specification.

[0067] The potential fixed electrode 30 is in contact with the p-type nitride semiconductor layer 16 at the bottom 26a of the source opening 26. In the present embodiment, the potential fixed electrode 30 is electrically connected to the source electrode 28. Specifically, the potential fixed electrode 30 is a part of the source electrode 28. The potential fixed electrode 30 can be regarded as the part of the source electrode 28 that is in contact with the bottom 26a of the source opening 26. The potential fixed electrode 30 is formed using the same material as the source electrode 28.

[0068] The gate electrode 32 is provided above the electron supply layer 24 so as to cover the gate opening 20. The gate electrode 32 is formed to a shape that conforms to the upper surface of the electron supply layer 24, to be in contact with the upper surface of the electron supply layer 24, and to have a substantially uniform thickness.

[0069] The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 is formed using Pd. Note that the material of the gate electrode 32 can be a material that forms a Schottky contact with an n-type semiconductor, such as a Ni-based material, WSi, or Au.

[0070] The drain electrode 34 is provided below the substrate 10. Specifically, the drain electrode 34 is provided in contact with the lower surface of the substrate 10 (the surface opposite to the crystal growth surface). The drain electrode 34 is formed using a conductive material such as a metal. For example, the drain electrode 34 can be made of a material that forms ohmic contact with an n-type semiconductor, similar to the material of the source electrode 28.

[0071] Each nitride semiconductor layer can be formed by epitaxial growth such as MOVPE (Metal-Organic Vapor Phase Epitaxy). Specifically, the drift layer 12, the first high-resistance semiconductor layer 14, the p-type nitride semiconductor layer 16, the second high-resistance semiconductor layer 18, the electron transit layer 22, and the electron supply layer 24 can be formed by sequentially depositing the layers using an MOVPE apparatus. The drift layer 12, the first high-resistance semiconductor layer 14, the p-type nitride semiconductor layer 16, and the second high-resistance semiconductor layer 18 are successively formed in this order, for example, in the same chamber. Thereafter, a gate opening 20 is formed, and then the electron transit layer 22 and the electron supply layer 24 are successively formed in the same chamber by crystal regrowth.

[0072] P-type impurities and impurities for increasing resistance can be added to each layer by introducing impurity elements during crystal growth, or impurities can be added by ion implantation or the like after forming an undoped semiconductor layer.

[0073] The gate opening 20, the source opening 26, and the groove 40 are formed by photolithography and etching, for example, dry etching.

[0074] The source electrode 28, the potential fixed electrode 30, the gate electrode 32, and the drain electrode 34 are each formed by depositing a metal film by a method such as vapor deposition or sputtering, and then patterning the film into a predetermined shape. The patterning can be performed by photolithography and etching. The drain electrode 34 may not be patterned, but may be provided on the entire lower surface of the substrate 10.

[0075] [Configuration of Termination Portion] Next, the configuration of the termination portion 3 of the nitride semiconductor device 1 according to this embodiment will be described.

[0076] 1 , the second high-resistance semiconductor layer 18, the electron transit layer 22, the electron supply layer 24, the source electrode 28, and the gate electrode 32 are not provided in the termination section 3. For example, the second high-resistance semiconductor layer 18, the electron transit layer 22, and the electron supply layer 24 in the termination section 3 are removed simultaneously with the formation of the source opening 26.

[0077] A groove 40 is provided in the termination portion 3. The groove 40 is an isolation trench for partitioning and separating the transistor portion 2. The groove 40 penetrates the p-type nitride semiconductor layer 16 and reaches the first high-resistance semiconductor layer 14. A portion of the p-type nitride semiconductor layer 16 is provided in the termination portion 3. In other words, in a plan view, the termination portion 3 includes a region where the p-type nitride semiconductor layer 16 is arranged and a region where the p-type nitride semiconductor layer 16 is not arranged (specifically, a region where the groove 40 is provided).

[0078] The groove 40 has a bottom 40a and a sidewall 40b. In this embodiment, the groove 40 is a stepped portion having the sidewall 40b only on the transistor portion 2 side. In other words, the bottom 40a of the groove 40 is connected to the end face of the nitride semiconductor device 1. As shown in FIG. 2 , the groove 40 is provided in a ring shape surrounding the transistor portion 2.

[0079] A bottom 40a of the groove 40 is part of the upper surface of the first high resistance semiconductor layer 14. The bottom 40a is parallel to the upper surface of the substrate 10, for example.

[0080] 1 , the groove 40 is formed so that the opening area is constant regardless of the distance from the substrate 10. Specifically, the sidewall 40b of the groove 40 is perpendicular to the bottom 40a. That is, the cross-sectional shape of the groove 40 is rectangular. Note that the cross-sectional shape of the groove 40 may also be an inverted trapezoid, similar to the gate opening 20.

[0081] The groove 40 is formed, for example, by performing dry etching with a different etching mask following the dry etching step for forming the source opening 26. Alternatively, the groove 40 may be formed by dry etching after the source electrode 28 or the potential fixed electrode 30, or after the gate electrode 32, is formed.

[0082] [Major Characteristic Configuration and Actions and Effects] Next, the major characteristic configuration and actions and effects of the nitride semiconductor device 1 described above will be described.

[0083] In this embodiment, a first high-resistance semiconductor layer 14 is provided between the drift layer 12 and the p-type nitride semiconductor layer 16. That is, by inserting the first high-resistance semiconductor layer 14 into the parasitic p-n junction of the parasitic p-n diode that was formed of n-type GaN (drift layer 12) and p-type GaN (p-type nitride semiconductor layer 16), it becomes difficult for a current to flow between the p-type nitride semiconductor layer 16 and the drift layer 12. That is, it is possible to block the current path of the parasitic p-n junction diode.

[0084] As a result, when the nitride semiconductor device 1 is off, even if the drain-side potential becomes lower than the source-side potential, it is possible to prevent a large current from flowing from the source electrode 28 to the drain electrode 34. Since a large current is less likely to flow through the parasitic pn diode in reverse conduction, it is possible to prevent a decrease in breakdown voltage due to reverse conduction.

[0085] Furthermore, the potential of the p-type nitride semiconductor layer 16 is fixed by the potential fixed electrode 30. Specifically, the p-type nitride semiconductor layer 16 is fixed to the same potential as the potential of the source electrode 28 (source potential). This depletes carriers between the p-type nitride semiconductor layer 16 and the gate electrode 32, making it possible to suppress leakage current between the drain and gate during the off state. In other words, the p-type nitride semiconductor layer 16 functions as a blocking layer that suppresses leakage current that flows from the drain electrode 34 toward the source electrode 28 without passing through a channel (two-dimensional electron gas in the electron transit layer 22).

[0086] Furthermore, in the termination portion 3, the provision of the groove 40 allows the p-type nitride semiconductor layer 16 to be spaced apart from the end facet of the nitride semiconductor device 1. This makes it possible to suppress the occurrence of leakage current along the end facet of the device when it is off, thereby increasing the breakdown voltage.

[0087] In this embodiment, the p-type nitride semiconductor layer 16 and the first high-resistance semiconductor layer 14 are formed using different materials. Specifically, the p-type nitride semiconductor layer 16 is a p-type GaN layer, while the first high-resistance semiconductor layer 14 is an AlGaN layer doped with carbon. The AlGaN layer functions as a stopper layer against dry etching of the GaN layer. That is, when the p-type nitride semiconductor layer 16 (GaN layer) is removed by dry etching, the first high-resistance semiconductor layer 14 (AlGaN layer) remains. Since localized openings and small-film-thickness portions are not formed in the first high-resistance semiconductor layer 14, the generation of a leakage current path between the p-type nitride semiconductor layer 16 and the n-type drift layer 12 can be suppressed. This suppresses the generation of leakage current during off-state operation, thereby increasing the breakdown voltage.

[0088] As described above, the nitride semiconductor device 1 according to this embodiment can improve the off-state characteristics.

[0089] The insulating film 42 is provided across the transistor section 2 and the termination section 3. Specifically, the insulating film 42 covers the gate electrode 32 and the source electrode 28, and is provided along the inner surface (bottom 40 a and sidewall 40 b) of the groove 40. For example, the insulating film 42 is a protective film that covers almost the entire area of ​​the nitride semiconductor device 1.

[0090] The insulating film 42 is formed using an insulating material. For example, the insulating film 42 contains silicon (Si) and nitrogen (N). This allows the insulating film 42 to terminate N vacancies even if they occur in the GaN layer due to nitrogen loss during dry etching. This prevents deterioration of the film quality of the GaN layer and suppresses the occurrence of current collapse. Note that the insulating film 42 does not necessarily need to contain Si and N. The insulating film 42 has a single layer or multilayer structure made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, or the like.

[0091] Second Embodiment Next, a second embodiment will be described.

[0092] The nitride semiconductor device according to the second embodiment differs from the first embodiment in that it includes a semiconductor layer that forms a heterointerface with the drift layer 12. The following description will focus on the differences from the first embodiment, and description of the commonalities will be omitted or simplified.

[0093] 3 is a cross-sectional view of the nitride semiconductor device 101 according to the present embodiment. As shown in Fig. 3, the nitride semiconductor device 101 includes an electron supply layer 114 in addition to the configuration of the nitride semiconductor device 1 shown in Fig. 1.

[0094] The electron supply layer 114 is an example of a second nitride semiconductor layer provided between the drift layer 12 and the first high-resistance semiconductor layer 14. The electron supply layer 114 is, for example, a film made of undoped AlGaN with a thickness of 50 nm. The electron supply layer 114 is formed by MOVPE following the formation of the drift layer 12.

[0095] The electron supply layer 114 is disposed in contact with the upper surface of the drift layer 12, and forms an AlGaN / GaN heterointerface with the drift layer 12. As a result, two-dimensional electron gas is generated in the drift layer 12 near the interface with the electron supply layer 114.

[0096] That is, in the nitride semiconductor device 101, the two-dimensional electron gas is formed in the drift layer 12 so as to extend laterally (specifically, in a direction parallel to the upper surface of the substrate 10) from near the bottom 20 a of the gate opening 20. Therefore, electrons moving through the two-dimensional electron gas (channel) in the electron transit layer 22 tend to spread laterally through the two-dimensional electron gas in the drift layer 12 near the bottom 20 a. As a result, not only the portion of the drift layer 12 located directly below the bottom 20 a, but also the portion located outside of this portion (outside the bottom 20 a in a plan view) can be used as a path for current flow. Therefore, the source-drain current is likely to diffuse over a wide region in the drift layer 12. This allows the resistance value of the nitride semiconductor device 101 to be reduced during operation.

[0097] Note that the two-dimensional electron gas in the drift layer 12 also spreads near the trench 40, which makes it easier for the electric field to concentrate at the end face of the trench 40. However, since the first high-resistance semiconductor layer 14 is disposed at the bottom 40a of the trench 40, it can withstand a high electric field and improve the breakdown voltage. In this way, the nitride semiconductor device 101 according to this embodiment can achieve both improved off-state characteristics and reduced on-state resistance.

[0098] Third Embodiment Next, a third embodiment will be described.

[0099] The nitride semiconductor device according to the third embodiment differs from the first embodiment in that a p-type nitride semiconductor layer is provided between the gate electrode and the electron transit layer. The following description will focus on the differences from the first embodiment, and description of the commonalities will be omitted or simplified.

[0100] 4 is a cross-sectional view of a nitride semiconductor device 201 according to this embodiment. As shown in Fig. 4, the nitride semiconductor device 201 includes a p-type nitride semiconductor layer 232 in addition to the configuration of the nitride semiconductor device 1 shown in Fig. 1.

[0101] 4 , the p-type nitride semiconductor layer 232 is an example of a second p-type nitride semiconductor layer provided between the gate electrode 32 and the electron supply layer 24. The p-type nitride semiconductor layer 232 is in contact with the upper surface of the electron supply layer 24 and the lower surface of the gate electrode 32.

[0102] The p-type nitride semiconductor layer 232 has a thickness of 100 nm and a carrier concentration of 1×10 １７ cm －３ The p-type nitride semiconductor layer 232 is a nitride semiconductor layer made of p-type AlGaN, which is a p-type nitride semiconductor layer having a structure similar to that of the electron supply layer 24. The p-type nitride semiconductor layer 232 is formed by depositing the layer by MOVPE and patterning it.

[0103] According to this embodiment, the potential of the conduction band edge of the channel portion is raised by the p-type nitride semiconductor layer 232. This increases the threshold voltage of the nitride semiconductor device 201. In other words, the transistor portion 2 of the nitride semiconductor device 201 can be operated as a normally-off type FET.

[0104] Instead of the p-type nitride semiconductor layer 232, silicon nitride (SiN) or silicon oxide (SiO ２ In other words, there is no particular limitation on the material as long as it has the effect of increasing the potential of the channel.

[0105] The nitride semiconductor device 201 may also include an electron supply layer 114, as in the second embodiment.

[0106] (Fourth embodiment) Next, a fourth embodiment will be described.

[0107] The nitride semiconductor device according to the fourth embodiment differs from the first embodiment in that it includes a field plate. The following description will focus on the differences from the first embodiment, and description of the commonalities will be omitted or simplified.

[0108] Fig. 5 is a cross-sectional view of a nitride semiconductor device 301 according to this embodiment. As shown in Fig. 5, the nitride semiconductor device 301 includes a field plate 344 in addition to the configuration of the nitride semiconductor device 1 shown in Fig. 1. Furthermore, the nitride semiconductor device 301 includes an insulating film 342 instead of the insulating film 42.

[0109] The insulating film 342 is provided along the inner surface of the groove 40. Specifically, the insulating film 342 is provided to electrically insulate the field plate 344 from components other than the source electrode 28 (specifically, the gate electrode 32, the electron supply layer 24, the p-type nitride semiconductor layer 16, the first high-resistance semiconductor layer 14, and the drift layer 12). For example, after the gate electrode 32 and the groove 40 are formed, the insulating film 342 is formed on the entire upper surface thereof and patterned to expose only at least a portion of the source electrode 28. That is, a contact hole for electrically connecting the source electrode 28 and the field plate 344 is formed in the insulating film 342. The insulating film 342 can be formed using, for example, the same material as the insulating film 42.

[0110] The field plate 344 is provided above the insulating film 342 so as to extend into the trench 40. In other words, the field plate 344 overlaps the bottom 40a of the trench 40 in a plan view.

[0111] The field plate 344 is formed using a conductive material such as a metal. For example, the material of the field plate 344 can be the same as that of the source electrode 28. In this embodiment, the field plate 344 is electrically connected to the source electrode 28. In other words, the same potential as that of the source electrode 28 is supplied to the field plate 344.

[0112] In termination portion 3, the electric field in the off state tends to concentrate at the intersection between bottom 40 a and sidewall 40 b of trench 40, i.e., at the corner of trench 40. By providing field plate 344 so that it overhangs trench 40, part of the electric field that concentrates at the intersection between bottom 40 a and sidewall 40 b can be dispersed to the overhanging portion of field plate 344. A pn ​​junction containing etching damage is present near the intersection between bottom 40 a and sidewall 40 b, and the electric field concentration at the pn junction is alleviated, thereby improving the off characteristics of nitride semiconductor device 301.

[0113] In the present embodiment, an example has been described in which the field plate 344 is electrically connected to the source electrode 28, but this is not limiting. The field plate 344 may be insulated from the source electrode 28, and may be supplied separately with the same or a different potential as that of the source electrode 28. In this case, no contact hole for electrically connecting the source electrode 28 and the field plate 344 is provided in the insulating film 342.

[0114] The nitride semiconductor device 301 may also include an electron supply layer 114, as in the second embodiment. The nitride semiconductor device 301 may also include a p-type nitride semiconductor layer 232, as in the third embodiment.

[0115] While nitride semiconductor devices according to one or more aspects have been described above based on embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0116] For example, in the above embodiment, an example was shown in which the potential fixed electrode 30 is part of the source electrode 28, but this is not limiting. The potential fixed electrode 30 and the source electrode 28 may be physically separated from each other. In this case, the potential fixed electrode 30 and the source electrode 28 can be electrically connected by a field plate 344 provided above the insulating film 342. Furthermore, the potential fixed electrode 30 may be formed using a different material from that of the source electrode 28.

[0117] For example, the potential fixed electrode 30 can be made of a material that makes ohmic contact with the p-type nitride semiconductor layer 16. For example, palladium (Pd), nickel (Ni), gold (Au), tungsten silicide (WSi), etc. can be used. Since these are the same materials as those used for the gate electrode 32, the gate electrode 32 and the potential fixed electrode 30 can be formed in the same process.

[0118] Furthermore, for example, the source electrode 28 does not have to be provided within the source opening 26. For example, the source electrode 28 may be disposed on the upper surface of the electron supply layer 24 and not in contact with the electron transit layer 22. In this case, the source opening 26 is an opening through which the potential fixed electrode 30 contacts the p-type nitride semiconductor layer 16, and is provided at a position separated from the source electrode 28.

[0119] Furthermore, for example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) gradually decreases from the substrate 10 side to the first high-resistance semiconductor layer 14 side. The donor concentration may be controlled by Si, which acts as a donor, or by carbon, which acts as an acceptor that compensates for Si. Alternatively, the drift layer 12 may be composed of multiple nitride semiconductor layers with different impurity concentrations.

[0120] Furthermore, for example, the termination portion 3 does not have to include an end face of the nitride semiconductor device 1. The termination portion 3 is a portion for separating the transistor portion 2 from other devices. Another element may be disposed in an adjacent region of the transistor portion 2, sandwiching the termination portion 3 therebetween. For example, the other element is a pn diode that utilizes a pn junction between the drift layer 12 and the p-type nitride semiconductor layer 16. In this case, the nitride semiconductor device 1 includes the transistor portion 2, the termination portion 3, and the pn diode.

[0121] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0122] The present disclosure can be used as a nitride semiconductor device with improved off-state characteristics, and can be used, for example, in a power device used in a power supply circuit of a consumer device.

[0123] REFERENCE SIGNS LIST 1, 101, 201, 301 nitride semiconductor device 2 transistor portion 3 termination portion 10 substrate 12 drift layer 14 first high-resistance semiconductor layer 16, 232 p-type nitride semiconductor layer 18 second high-resistance semiconductor layer 20 gate opening 20a, 26a, 40a bottom portion 20b, 26b, 40b sidewall portion 22 electron transit layer 24, 114 electron supply layer 26 source opening 28 source electrode 30 potential fixing electrode 32 gate electrode 34 drain electrode 40 groove portion 42, 342 insulating film 344 field plate

Claims

1. 1. A nitride semiconductor device, comprising: A substrate; a first nitride semiconductor layer provided above the substrate; a first high-resistance semiconductor layer provided above the first nitride semiconductor layer and having a higher resistance than the first nitride semiconductor layer; a first p-type nitride semiconductor layer provided above the first high resistance semiconductor layer; a second high-resistance semiconductor layer provided above the first p-type nitride semiconductor layer and having a higher resistance than the first nitride semiconductor layer; a first opening that penetrates the second high-resistance semiconductor layer, the first p-type nitride semiconductor layer, and the first high-resistance semiconductor layer and reaches the first nitride semiconductor layer, and an electron transit layer and an electron supply layer that are provided in this order from below so as to cover an upper surface of the second high-resistance semiconductor layer; a source electrode in contact with the electron supply layer; a potential fixed electrode provided in a second opening portion that penetrates the second high-resistance semiconductor layer and reaches the first p-type nitride semiconductor layer, the potential fixed electrode being connected to the source electrode; a drain electrode provided below the substrate; an insulating film covering the source electrode; the insulating film is further provided along an inner surface of a groove portion that penetrates the first p-type nitride semiconductor layer and reaches the first high-resistance semiconductor layer at a termination portion of the nitride semiconductor device; The first high resistance semiconductor layer is a high resistance AlGaN layer. Nitride semiconductor devices.

2. a second nitride semiconductor layer provided between the first nitride semiconductor layer and the first high resistance semiconductor layer; The second nitride semiconductor layer is an undoped AlGaN layer. The nitride semiconductor device of claim 1 .

3. The high-resistance AlGaN layer has a higher resistance than the undoped AlGaN layer. The nitride semiconductor device of claim 2 .

4. The insulating film contains at least Si and N. The nitride semiconductor device according to claim 1 .

5. A gate electrode provided above the electron supply layer and spaced apart from the source electrode; a second p-type nitride semiconductor layer provided between the gate electrode and the electron supply layer; The nitride semiconductor device according to claim 1 .

6. a field plate provided above the insulating film so as to extend into the trench; The nitride semiconductor device according to claim 1 .

7. The field plate is electrically connected to the source electrode. The nitride semiconductor device of claim 6.

8. A gate electrode is provided above the electron supply layer and away from the source electrode so as to cover the first opening. The nitride semiconductor device according to claim 1 .