Etching composition and method for producing wiring board using same

Abstract

The present invention relates to an etching composition for selectively etching a copper seed layer from a substrate that has a copper wiring pattern and the copper seed layer. An etching composition according to the present invention is used for the purpose of selectively etching a copper seed layer from a substrate that has a copper wiring pattern and the copper seed layer, and is characterized by containing (A) hydrogen peroxide, (B) sulfuric acid, (C) an azole or a salt thereof, (D) a glycol ether, (E) a halide ion and (F) water, while being also characterized in that: the content of the hydrogen peroxide (A) is 0.1 to 10% by mass based on the total amount of the etching composition; the content of the sulfuric acid (B) is 0.5 to 5% by mass based on the total amount of the etching composition; the ratio of the hydrogen peroxide (A) to the sulfuric acid (B) is 2 or more in terms of the molar ratio; and the content of the halide ion (E) is 0.01 to 3 ppm based on the total amount of the etching composition.

Description

Etching composition and method for manufacturing wiring board using same

[0001] The present invention relates to an etching composition for selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer, and a method for producing a wiring board using the same.

[0002] In recent years, there has been a demand for improved processing of fine metal wiring and its precision in the manufacture of substrates for smartphones and wearable devices. As a processing method that can accommodate miniaturized metal wiring, the semi-additive process (SAP), which forms copper wiring patterns only in necessary locations using electrolytic copper plating, is known. In particular, the modified-semi-additive process (M-SAP), which can also accommodate finer pitches, has attracted attention in recent years. In SAP, a copper seed layer is first formed on an insulating layer by forming an electroless copper-plated film, and in some cases, an even thinner electrolytic copper-plated film. Next, a resist pattern for forming copper wiring is formed on the copper seed layer using a photoresist, and the copper wiring pattern is then formed between the resist patterns by electrolytic copper plating. The resist pattern is then removed, and the exposed copper seed layer is removed by chemical etching, allowing a fine copper wiring pattern to be formed on the insulating layer. In M-SAP, electrolytic copper foil with a carrier foil is first laminated on an insulating layer. This electrolytic copper foil is then, if necessary, half-etched to form an ultrathin copper layer, on which an electroless copper plating film is then formed to form a copper seed layer. Next, a resist pattern for forming copper wiring is formed on the copper seed layer, and a copper wiring pattern is formed between the resist patterns by electrolytic copper plating. The resist pattern is then removed, and the exposed copper seed layer is removed by chemical etching, thereby forming a fine copper wiring pattern on the insulating layer. Thus, in SAP or M-SAP, the copper seed layer must be removed after forming the copper wiring pattern. However, removing the copper seed layer often reduces the height and width of the copper wiring, resulting in the wiring cross-section not maintaining its rectangular shape. Patent Document 1 describes that an etching solution primarily composed of hydrogen peroxide and sulfuric acid and containing an azole as an additive can suppress thinning and footing of the circuit portion during removal of the copper seed layer in SAP. However, to further improve processing accuracy, more selective etching of the copper seed layer is required.The Embedded Trace Substrate (ETS) method (hereinafter referred to as the "ETS method") is also known as a processing method capable of supporting miniaturization of copper wiring (see Patent Document 2). However, even in the ETS method, after a copper wiring pattern formed on an electrolytic copper foil as a copper seed layer is embedded in a resin, the electrolytic copper foil as the copper seed layer must be removed by etching. During etching, depending on the degree of etching of the copper wiring along the sidewalls of the interlayer insulating resin (side etching) and the etching of the top surface of the copper wiring, the rectangular shape of the cross section of the wiring may not be maintained. For this reason, even in the ETS method, it is required to selectively etch the electrolytic copper foil as the copper seed layer.

[0003] JP 2006-009122 A International Publication No. 2019 / 208461 A

[0004] Under these circumstances, there is a need for an etching composition for selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer. In this specification, the term "copper seed layer" refers to a thin copper film formed as an underlayer when forming copper wiring on an insulating layer using a plating technique, and the method for forming the copper seed layer is not particularly limited. This copper thin film may be, for example, an electrolytic copper foil, an electrolytic copper-plated film, or an electroless copper-plated film, or a combination thereof.

[0005] The present invention relates to the following etching composition and a method for manufacturing a wiring board using the same. [1] An etching composition for selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer, comprising: hydrogen peroxide (A), sulfuric acid (B), an azole or its salt (C), glycol ethers (D), halide ions (E), and water (F), wherein the content of hydrogen peroxide (A) is 0.1 to 10 mass% based on the total amount of the etching composition; the content of sulfuric acid (B) is 0.5 to 5 mass% based on the total amount of the etching composition; the ratio of hydrogen peroxide (A) to sulfuric acid (B) is 2 or more, expressed as a molar ratio; and the content of halide ions (E) is 0.01 to 3 ppm based on the total amount of the etching composition. [2] The etching composition according to [1] above, wherein the azole is a heterocyclic compound having a five-membered heterocycle having two nitrogen atoms or a fused heterocycle thereof. [3] The etching composition according to the above [2], wherein the azole is at least one selected from the group consisting of pyrazoles, imidazoles, and benzimidazoles. [4] The azole is a compound represented by the following formula: [In the formula, R １ , R ２ , R ３ , R ４ , R ５ and R ６ are each independently a hydrogen atom, C １ ~C ６ Alkyl group, C ６ ~C １０ Aryl group, carboxyl group, carboxy C １ ~C ６ Alkyl group, nitro group, hydroxyl group, C ２ ~C ７a carboxylic acid ester, or a halogen atom.] [5] The etching composition according to [4] above, wherein the azole is at least one selected from the group consisting of imidazole, 1,2,4,5-tetramethylimidazole, 4-methyl-2-phenylimidazole, benzimidazole, 1-methylbenzimidazole, 2-methylbenzimidazole, 5-methylbenzimidazole, 2,5-dimethylbenzimidazole, 5-nitrobenzimidazole, pyrazole, and 3,5-dimethylpyrazole. [6] The etching composition according to any one of [1] to [5] above, wherein the content of the azole is 0.01 to 0.5 mass% based on the total amount of the etching composition. [7] The etching composition according to any one of [1] to [6], wherein the glycol ether (D) is at least one selected from the group consisting of ethylene glycol monobutyl ether, diethylene glycol monomethyl ether, diethylene glycol monophenyl ether, and dipropylene glycol monomethyl ether. [8] The etching composition according to any one of [1] to [7], wherein the content of the glycol ether (D) is 0.01 to 1 mass% based on the total amount of the etching composition. [9] The etching composition according to any one of [1] to [8], wherein the halide ion (E) is a chloride ion.

[10] At a treatment temperature of 30°C, the etching rate ratio of the interconnect height is calculated based on the following formula (1): Etching rate ratio of interconnect height = Δheight / seed layer thickness (1) [wherein seed layer thickness represents the thickness (μm) of the copper seed layer removed by etching, and Δheight represents the etching thickness (μm) of the top surface of the copper interconnect removed by etching in just the right etching time for removing the entire copper seed layer by etching.

[0023] The etching composition according to any one of [1] to [9], wherein the etching rate ratio of the copper wiring to the wiring height defined by the following formula is 1.2 or less.

[11] The etching composition according to

[10] , wherein the etching rate ratio of the wiring width of the copper wiring defined by the following formula at a treatment temperature of 30°C is 1.4 or less: wiring width etching rate ratio = Δ one-side width / seed layer thickness (2) (wherein seed layer thickness represents the thickness (μm) of the copper seed layer removed by etching, and Δ one-side width represents the value (μm) obtained by converting the lateral width of the copper wiring removed by etching to one side (½) at just the etching time required for the entire copper seed layer to be removed by etching.)

[12] The etching composition according to any one of [1] to

[11] , wherein the copper seed layer is at least one selected from the group consisting of electrolytic copper foil, electrolytic copper-plated film, and electroless copper-plated film.

[13] A method for producing a wiring substrate, comprising a step of selectively etching the copper seed layer from a substrate having a copper wiring pattern and a copper seed layer using the etching composition according to any one of [1] to

[12] .

[14] The method for producing a wiring board according to

[13] above, wherein the copper seed layer is at least one selected from the group consisting of an electrolytic copper foil, an electrolytic copper-plated film, and an electroless copper-plated film.

[15] A method for producing a wiring board, comprising: selectively etching the copper seed layer from a substrate having a copper wiring pattern and a copper seed layer using the etching composition according to any one of [1] to

[12] above in a semi-additive process (SAP), a modified semi-additive process (M-SAP), or an embedded trace substrate process (ETS process), to form a wiring circuit.

[0006] According to the present invention, an etching composition for selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer can be provided. The etching composition of the present invention can be suitably used in producing a wiring board having a wiring circuit consisting of a fine copper wiring pattern, such as in the SAP, M-SAP, or ETS process. According to a preferred embodiment of the present invention, the copper seed layer can be selectively removed while suppressing thinning of the copper wiring and maintaining the rectangularity of the wiring cross section.

[0007]

[0023] Figure 1 is a diagram for explaining a method for manufacturing a wiring board in SAP, in which a wiring circuit is formed by selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer. Figure 2 is a diagram for explaining a method for manufacturing a wiring board in M-SAP, in which a wiring circuit is formed by selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer. Figure 3 is a diagram for explaining a method for manufacturing a wiring board in ETS, in which a wiring circuit is formed by selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer. Figure 4 is a diagram showing a specific example of evaluation criteria for rectangularity of copper wiring after etching treatment.

[0008] 1. Etching Composition The etching composition of the present invention is an etching composition for selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer, and is characterized in that it contains hydrogen peroxide (A), sulfuric acid (B), an azole or a salt thereof (C), a glycol ether (D), a halide ion (E), and water (F), the content of hydrogen peroxide (A) is 0.1 to 10 mass% based on the total amount of the etching composition, the content of sulfuric acid (B) is 0.5 to 5 mass% based on the total amount of the etching composition, the ratio of hydrogen peroxide (A) to sulfuric acid (B) is 2 or more, expressed as a molar ratio, and the content of halide ion (E) is 0.01 to 3 ppm based on the total amount of the etching composition.

[0009] Each component will be described below.

[0010] [Hydrogen Peroxide (A)] In the present invention, hydrogen peroxide (A) (hereinafter sometimes simply referred to as component (A)) is a component that functions as an oxidizing agent for copper. There are no particular limitations on component (A), and various grades, such as those for industrial and electronics industries, can be used. In general, it is preferable to use hydrogen peroxide in the form of an aqueous hydrogen peroxide solution in terms of availability and operability.

[0011] The content of component (A) is in the range of 0.1 to 10 mass % based on the total amount (mass basis) of the etching composition, preferably 0.5 to 8 mass %, more preferably 1 to 7.5 mass %, and even more preferably 2 to 7 mass %. By having the content of component (A) within the above range, it is possible to selectively remove the copper seed layer while suppressing thinning of the copper wiring and maintaining the rectangularity of the wiring cross section. When a numerical range is given in this specification, the upper and lower limits can be appropriately combined, and the resulting numerical range is also considered to be disclosed.

[0012] [Sulfuric Acid (B)] In the present invention, sulfuric acid (B) (hereinafter sometimes simply referred to as component (B)) is a component that acts as an etching agent for copper oxidized by hydrogen peroxide (A).

[0013] The content of component (B) is in the range of 0.5 to 5 mass % based on the total amount (mass basis) of the etching composition, preferably 1 to 5 mass %, more preferably 2 to 5 mass %, and even more preferably 2.5 to 5 mass %. By having the content of component (B) within the above range, it is possible to selectively remove the copper seed layer while suppressing thinning of the copper wiring and maintaining the rectangularity of the wiring cross section.

[0014] In the etching composition of the present invention, the ratio of hydrogen peroxide (A) to sulfuric acid (B) (component (A) / component (B)), expressed as a molar ratio, is 2 or more, preferably 2.0 or more, more preferably 2 to 20, even more preferably 2.0 to 20, still more preferably 3 to 15, even more preferably 3.5 to 10, and particularly preferably 3.5 to 8. By controlling the compounding ratio of component (A) and component (B), it is possible to selectively remove the copper seed layer while suppressing thinning of the copper wiring and maintaining the rectangularity of the wiring cross section.

[0015] [Azoles or Salts (C)] In the present invention, the azoles or salts (C) (hereinafter sometimes simply referred to as component (C)) can selectively remove a copper seed layer by adsorbing to the surface of a copper wiring. In the present invention, the azoles are heterocyclic compounds having a five-membered heterocycle or a fused heterocycle containing one or more nitrogen atoms, and the atoms constituting the five-membered heterocycle or the fused heterocycle may have one or more substituents selected from alkyl groups, carboxyl groups, carboxyalkyl groups, nitro groups, hydroxyl groups, carboxylic acid esters, halogen atoms, and the like. Examples of azoles include pyrazoles, imidazoles, benzimidazoles, triazoles, and tetrazoles. Among these, in terms of being able to selectively etch the copper seed layer relative to the copper wiring, the azole is preferably a heterocyclic compound having a five-membered heterocycle having two nitrogen atoms or a fused heterocycle thereof, and more preferably at least one selected from the group consisting of pyrazoles, imidazoles, and benzimidazoles. The component (C) may be a salt of the azole. The salt of the azole is not particularly limited, but is preferably an inorganic acid salt from the standpoint of economy, such as nitrate, sulfate, or hydrochloride. When the salt of the azole is hydrochloride, the chloride ion of the hydrochloride can function as the halide ion (E).

[0016] <Pyrazoles> The pyrazoles are not particularly limited as long as they have a pyrazole skeleton. For example, pyrazoles represented by the following formula: [In the formula, R １ , R ２ , R ３ and R ４ are each independently a hydrogen atom, C １ ~C ６ Alkyl group, C ６ ~C １０ Aryl group, carboxyl group, carboxy C １ ~C ６ Alkyl group, nitro group, hydroxyl group, C ２ ~C ７a carboxylic acid ester, or a halogen atom.

[0017] In this specification, "C １ ~C ６ "Alkyl group" means an alkyl group having 1 to 6 carbon atoms. １ ~C ６ Examples of the alkyl group include a methyl group, an ethyl group, a propyl group, an isopropyl group, an n-butyl group, a sec-butyl group, a tert-butyl group, a pentyl group, and a hexyl group. Among these, a methyl group and an ethyl group are preferred. ６ ~C １０ The term "aryl group" means an aryl group having 6 to 10 carbon atoms. ６ ~C １０ Examples of the aryl group include a phenyl group, a 1-naphthyl group, a 2-naphthyl group, an indenyl group, a biphenyl group, an anthryl group, and a phenanthryl group. Among these, a phenyl group is preferred. １ ~C ６ The term "alkyl group" means an alkyl group having 1 to 6 carbon atoms and a carboxyl group. １ ~C ６ Examples of the alkyl group include the same as those described above. １ ~C ６ Specific examples of alkyl groups include carboxymethyl groups (-CH ２ -COOH), carboxyethyl group (-CH ２ CH ２ —COOH) is preferred. ２ ~C ７ "Carboxylic acid ester" is -COOR (R is C １ ~C ６ C is an alkyl group. １ ~C ６ Examples of the alkyl group include the same as those described above. ２ ~C ７Specific examples of preferred carboxylate esters include methyl carboxylate and ethyl carboxylate. The "halogen atom" may be any of a fluorine atom, chlorine atom, bromine atom and iodine atom, with a chlorine atom and a bromine atom being particularly preferred.

[0018] In formula (a), R １ , R ２ , R ３ and R ４ are each independently a hydrogen atom or C １ ~C ６ It is preferably an alkyl group. Examples of pyrazoles include pyrazole and 3,5-dimethylpyrazole.

[0019] <Imidazoles> The imidazoles are not particularly limited as long as they have an imidazole skeleton. For example, imidazoles represented by the following formula: [In the formula, R １ , R ２ , R ３ and R ４ are each independently a hydrogen atom, C １ ~C ６ Alkyl group, C ６ ~C １０ Aryl group, carboxyl group, carboxy C １ ~C ６ Alkyl group, nitro group, hydroxyl group, C ２ ~C ７ a carboxylic acid ester, or a halogen atom.

[0020] In formula (b), R １ , R ２ , R ３ and R ４ are each independently a hydrogen atom, C １ ~C ６ An alkyl group or a phenyl group is preferred. Examples of imidazoles include imidazole, 1,2,4,5-tetramethylimidazole, and 4-methyl-2-phenylimidazole.

[0021] <Benzimidazoles> The benzimidazoles are not particularly limited as long as they have a benzimidazole skeleton. For example, benzimidazoles represented by the following formula: [In the formula, R １ , R ２ , R ３ , R ４ , R ５ and R ６ are each independently a hydrogen atom, C １ ~C ６ Alkyl group, C ６ ~C １０ Aryl group, carboxyl group, carboxy C １ ~C ６ Alkyl group, nitro group, hydroxyl group, C ２ ~C ７ a carboxylic acid ester, or a halogen atom.

[0022] In formula (c), R １ , R ２ , R ３ , R ４ , R ５ and R ６ is a hydrogen atom, C １ ~C ６ An alkyl group or a nitro group is preferred. Examples of benzimidazoles include benzimidazole, 1-methylbenzimidazole, 2-methylbenzimidazole, 5-methylbenzimidazole, 2,5-dimethylbenzimidazole, and 5-nitrobenzimidazole nitrate.

[0023] <Triazoles> The triazoles are not particularly limited as long as they have a triazole skeleton, and examples thereof include 1,2,4-triazole.

[0024] <Benzotriazoles> The benzotriazoles are not particularly limited as long as they have a benzotriazole skeleton, and examples thereof include 1H-benzotriazole and 5-methyl-1H-benzotriazole.

[0025] <Tetrazoles> The tetrazoles are not particularly limited as long as they have a tetrazole skeleton, and examples thereof include 1H-tetrazole, 5-methyl-1H-tetrazole, 5-phenyl-1H-tetrazole, and 1,5-pentamethylenetetrazole.

[0026] Among the above, the azole is more preferably at least one selected from the group consisting of imidazole, 1,2,4,5-tetramethylimidazole, 4-methyl-2-phenylimidazole, benzimidazole, 1-methylbenzimidazole, 2-methylbenzimidazole, 5-methylbenzimidazole, 2,5-dimethylbenzimidazole, 5-nitrobenzimidazole, pyrazole, and 3,5-dimethylpyrazole, and is particularly preferably at least one selected from the group consisting of 4-methyl-2-phenylimidazole, benzimidazole, 1-methylbenzimidazole, 2-methylbenzimidazole, 5-methylbenzimidazole, 2,5-dimethylbenzimidazole, 5-nitrobenzimidazole, and pyrazole. As mentioned above, component (C) may be a salt of an azole. The component (C) is particularly preferably at least one selected from the group consisting of 4-methyl-2-phenylimidazole, benzimidazole, 1-methylbenzimidazole, 2-methylbenzimidazole, 5-methylbenzimidazole, 2,5-dimethylbenzimidazole, 5-nitrobenzimidazole nitrate, and pyrazole.

[0027] The component (C) may be used alone or in combination of two or more.

[0028] The content of the azoles is preferably in the range of 0.01 to 0.5 mass% (100 to 5000 ppm) based on the total amount (mass basis) of the etching composition, more preferably 0.05 to 0.4 mass% (500 to 4000 ppm), even more preferably 0.1 to 0.3 mass% (1000 to 3000 ppm), and particularly preferably 0.15 to 0.25 mass% (1500 to 2500 ppm). By having the content of the azoles within the above range, it is possible to selectively remove the copper seed layer while suppressing thinning of the copper wiring and maintaining the rectangularity of the wiring cross section. When a salt of an azole is used as component (C), the content of the azole is calculated by converting it into the content of the azole excluding the salt portion. When two or more types of component (C) are used, the total amount of the azoles contained therein may be within the above range.

[0029] [Glycol Ethers (D)] In the present invention, glycol ethers (D) (hereinafter sometimes simply referred to as component (D)) can have the effect of uniforming the amount of copper dissolved within the surface of a substrate and / or on the front and back sides during etching. Specifically, they can have the effect of uniforming the etching rate and etching amount of copper wiring within the surface of a substrate and / or on the front and back sides during etching. As a result, they can have the effect of uniforming the degree of thinning of copper wiring within the surface of a substrate and / or on the front and back sides, and the rectangularity of the wiring cross section. The component (D) is not particularly limited, but is preferably at least one selected from the group consisting of ethylene glycol monobutyl ether, diethylene glycol monomethyl ether, diethylene glycol monophenyl ether, and dipropylene glycol monomethyl ether. The content of component (D) is preferably in the range of 0.01 to 1 mass % (100 to 10,000 ppm) based on the total amount (mass basis) of the etching composition, more preferably 0.05 to 0.75 mass % (500 to 7,500 ppm), and even more preferably 0.1 to 0.5 mass % (1,000 to 5,000 ppm). By having the content of component (D) within the above range, it is possible to selectively remove the copper seed layer while suppressing thinning of the copper wiring and maintaining the rectangularity of the wiring cross section. Furthermore, according to a preferred embodiment of the present invention, by having the content of component (D) within the above range, the composition is less susceptible to the influence of physical conditions such as spray pressure during the etching process. When two or more types of component (D) are used, the total amount of all components may be within the above range.

[0030] [Halide Ion (E)] In the present invention, halide ion (E) (hereinafter sometimes simply referred to as component (E)) has the effect of stabilizing the etching rate. As component (E), fluoride ion, chloride ion, bromide ion, and iodide ion are preferred, with chloride ion and bromide ion being more preferred, and chloride ion being particularly preferred. Sources of component (E) (hereinafter sometimes referred to as halide ion source) include acids such as hydrochloric acid and hydrobromic acid; and salts such as sodium chloride, ammonium chloride, calcium chloride, potassium chloride, potassium bromide, sodium fluoride, potassium iodide, cupric chloride, and cupric bromide. Among these, at least one selected from the group consisting of hydrochloric acid and sodium chloride is preferred. For example, when the azole or its salt (C) is a halide salt, component (E) may be supplied from component (C). In this case, component (C) can also be used as a halide ion source. In the present invention, since copper dissolves when the copper seed layer is etched, copper ions may be added in advance to suppress fluctuations in the copper concentration in the etching composition, and cupric chloride and cupric bromide can be used as halide ion sources and copper ion sources. The halide ions (E) may be used singly or in combination of two or more.

[0031] The content of component (E) is in the range of 0.01 to 3 ppm, preferably 0.05 to 2 ppm, and more preferably 0.1 to 1 ppm, based on the total amount (mass basis) of the etching composition. By having the content of component (E) within the above range, the etching rate can be stabilized, and the copper seed layer can be selectively removed while suppressing thinning of the copper wiring and maintaining the rectangularity of the wiring cross section. When two or more types of halide ions (E) are used, the total amount of component (E) resulting from these ions should be within the above range.

[0032] [Water (F)] The water (F) used in the present invention (hereinafter, sometimes simply referred to as component (F)) is not particularly limited, but is preferably water from which metal ions, organic impurities, particle particles, etc. have been removed by distillation, ion exchange treatment, filtration, various adsorption treatments, etc., and pure water or ultrapure water is particularly preferred. The content of water is the balance of other components and is not particularly limited, but is preferably in the range of 85 to 99 mass % based on the total amount of the etching composition.

[0033] [Other Components] In addition to the above components, the etching composition of the present invention may contain, as needed, one or more of the various additives commonly used in etching compositions, as long as they do not impair the effects of the etching composition described above. Furthermore, a trace amount of alkali may be added as long as the pH does not change significantly. Furthermore, known hydrogen peroxide stabilizers such as alcohols, phenylurea, organic carboxylic acids, and organic amine compounds, as well as etching rate adjusters, may also be added to the etching composition of the present invention as needed. The etching solution of the present invention is preferably a solution, and does not contain solid particles such as abrasive particles.

[0034] [Preparation of Etching Composition] The etching composition of the present invention can be prepared by uniformly stirring and mixing the components (A), (B), (C), (D), (E), and (F), as well as other components added as needed. The stirring method for mixing these components is not particularly limited, and any stirring method commonly used in the preparation of etching compositions can be used.

[0035] [Uses of Etching Composition] The etching composition of the present invention can be used as an etching composition for selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer. The copper seed layer selectively etched by the etching composition of the present invention is preferably an electrolytic copper foil, an electrolytic copper-plated film, an electroless copper-plated film, or a combination of two or more of these. In this specification, "selectively" means that the etching rate of the copper seed layer is higher than the etching rate of the copper wiring. For example, in the present invention, the ratio of the etching rate of the copper wiring to the etching rate of the copper seed layer can be evaluated by the etching rate ratio of the wiring height and the etching rate ratio of the wiring width of the copper wiring, based on the etching rate of the copper seed layer at a treatment temperature of 30°C. The etching rate ratio of the wiring height and the etching rate ratio of the wiring width are defined by the following equations (1) and (2): Etching rate ratio of wiring height = Δ height / seed layer thickness (1) Etching rate ratio of wiring width = Δ one-side width / seed layer thickness (2) (In the formula, seed layer thickness represents the thickness (μm) of the copper seed layer removed by etching, Δ height represents the etching thickness (μm) of the upper surface of the copper wiring removed by etching at the just-etching time when the entire copper seed layer is just removed by etching, and Δ one-side width represents the value (μm) obtained by converting the lateral width of the copper wiring removed by etching to one side (1 / 2) at the just-etching time when the entire copper seed layer is just removed by etching.) In the present invention, the etching rate ratio of wiring height is preferably 1.2 or less. Furthermore, the etching rate ratio of wiring width is preferably 1.4 or less, more preferably 1.0 or less. In the present invention, it is preferable that the etching rate ratio of wiring height satisfies the above range, and it is more preferable that both the etching rate ratio of wiring height and the etching rate ratio of wiring width satisfy the above range.

[0036] For example, the etching composition of the present invention can be suitably used in SAP or M-SAP to remove a copper seed layer that is exposed upon removal of the resist pattern after forming a copper wiring pattern. The etching composition of the present invention can also be suitably used in the ETS process to remove electrolytic copper foil as a copper seed layer. According to a preferred embodiment of the present invention, etching a copper seed layer using the etching composition of the present invention can selectively remove the copper seed layer while suppressing thinning of the copper wiring and maintaining the rectangularity of the wiring cross section. The thickness of the copper seed layer suitable for removal by the etching composition of the present invention is not particularly limited, but is typically 1.5 to 15 μm, preferably 1.5 to 10 μm, and more preferably 1.5 to 5 μm.

[0037] 2. Method for manufacturing a wiring board The method for manufacturing a wiring board according to the present invention is characterized by comprising a step of selectively etching the copper seed layer from a substrate having a copper wiring pattern and a copper seed layer using the etching composition. The etching composition and the copper seed layer to be etched are as described above in "1. Etching composition."

[0038] Although there are no particular limitations on the temperature at which the etching composition of the present invention is used, a temperature of 10 to 50°C is preferred, more preferably 20 to 45°C, and even more preferably 25 to 40°C. If the temperature of the etching composition is 10°C or higher, the etching rate is good, resulting in excellent production efficiency. On the other hand, if the temperature of the etching composition is 50°C or lower, changes in the liquid composition can be suppressed and etching conditions can be maintained constant. Increasing the temperature of the etching solution increases the etching rate, but the optimal treatment temperature can be determined as appropriate, taking into consideration factors such as minimizing changes in the composition of the etching solution (decomposition of hydrogen peroxide).

[0039] The etching time is not particularly limited, but is preferably 1 to 600 seconds, more preferably 5 to 300 seconds, even more preferably 10 to 180 seconds, and particularly preferably 15 to 120 seconds. The etching time may be appropriately selected depending on various conditions such as the treatment temperature and the treatment method.

[0040] The method for contacting the etching composition with the etching target containing a copper seed layer is not particularly limited. For example, wet etching methods such as contacting the etching target with the etching composition by dropping (single wafer spin processing) or spraying the etching composition, or immersing the etching target in the etching composition can be used. Either method can be used in the present invention.

[0041] The method for producing a wiring board according to the present invention is suitable for forming a wiring circuit by selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer using the etching composition in, for example, a semi-additive process (SAP), a modified semi-additive process (M-SAP), or an embedded trace substrate process (ETS process).

[0042] An example of a method for manufacturing a wiring board according to the present invention will be described below, but the method for manufacturing a wiring board according to the present invention is not limited to this.

[0043] <Method for manufacturing a wiring board using SAP> Fig. 1 is a diagram for explaining a method for manufacturing a wiring board in which a wiring circuit is formed by selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer in SAP. Fig. 1 shows only the structure necessary for the explanation.

[0044] First, an insulating resin substrate (1) is prepared ( FIG. 1( a) ). If necessary, vias or trenches (1a) are formed by drilling or other methods ( FIG. 1( b) ). Next, electroless copper plating is applied to the surface of the insulating resin substrate (1), including the inner walls of the vias or trenches (1a), to form an electroless copper-plated film (2) as a copper seed layer ( FIG. 1( c) ). Although not shown, an electrolytic copper-plated film may also be formed on the surface of the electroless copper-plated film (2). When an electrolytic copper-plated film is formed, the electroless copper-plated film (2) and the electrolytic copper-plated film are referred to as the "copper seed layer." Next, a dry film resist (3) is formed on the surface of the electroless copper-plated film (2) or, when an electrolytic copper-plated film is formed, on the surface of the electrolytic copper-plated film ( FIG. 1( d) ). This is then exposed and developed to form a resist pattern (3a) ( FIG. 1( e) ). Subsequently, electrolytic copper plating is applied to the copper seed layer between the resist patterns (3a) to form an electrolytic copper-plated film (4) ( FIG. 1( f) ). Next, the resist pattern (3a) is stripped with a stripping solution to form a copper wiring pattern (4a) (FIG. 1(g)). Finally, the etching composition of the present invention is applied to the surface of the copper seed layer to remove the exposed portion of the copper seed layer, thereby producing a wiring board (10) on which the copper wiring pattern (4a) is formed (FIG. 1(h)).

[0045] According to a preferred embodiment of the present invention, by etching a copper seed layer in an SAP using the etching composition of the present invention, it is possible to selectively etch the copper seed layer while suppressing side etching and / or etching of the top surface of the copper wiring pattern (4 a) and maintaining the rectangularity of the wiring cross section, and to produce a wiring board (10) that is compatible with miniaturized wiring.

[0046] <Method for manufacturing a wiring board using M-SAP> Figure 2 is a diagram for explaining a method for manufacturing a wiring board using M-SAP, in which a wiring circuit is formed by selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer. In Figure 2, only the structure necessary for explanation is shown schematically.

[0047] First, an insulating resin substrate (1) is prepared, and an electrolytic copper foil (5) is laminated onto the substrate using an electrolytic copper foil with a carrier foil (not shown) (FIG. 2(a)). Examples of the carrier foil include aluminum foil, copper foil, stainless steel foil, resin film, resin film with a metal-coated surface, and glass plate. After peeling and removing the carrier foil, the electrolytic copper foil (5) is optionally half-etched to form a thin copper layer (6) (FIG. 2(b)). If necessary, vias or trenches (1a) are formed by drilling or the like (FIG. 2(c)). Next, electroless copper plating is applied to the thin copper layer (6), including the inner walls of the vias or trenches (1a), to form an electroless copper-plated film (2) (FIG. 2(d)). Although not shown, an electrolytic copper-plated film (not shown) may be further formed on the electroless copper-plated film (2). If no electrolytic copper-plated film is formed, the thin copper layer (6) and the electroless copper-plated film (2) are referred to as a "copper seed layer." When forming an electrolytic copper-plated film, the thin copper layer (6), the electroless copper-plated film (2), and the electrolytic copper-plated film are referred to as the "copper seed layer." Next, a dry film resist (3) is formed on the surface of the electroless copper-plated film (2), or the electrolytic copper-plated film (not shown) when forming an electrolytic copper-plated film (FIG. 2(e)). This is then exposed and developed to form a resist pattern (3a) (FIG. 2(f)). Subsequently, electrolytic copper plating is performed on the copper seed layer between the resist patterns (3a), forming an electrolytic copper-plated film (4) (FIG. 2(g)). Next, the resist pattern (3a) is stripped with a stripping solution to form a copper wiring pattern (4a) (FIG. 2(h)). Finally, the etching composition of the present invention is applied to the surface of the copper seed layer, and the exposed portions of the copper seed layer are removed, thereby producing a wiring board (10) on which a copper wiring pattern (4a) is formed (FIG. 2(i)).

[0048] According to a preferred embodiment of the present invention, by etching a copper seed layer in M-SAP using the etching composition of the present invention, the copper seed layer can be selectively etched while suppressing side etching and / or etching of the top surface of the copper wiring pattern (4 a), and a wiring board (10) that is compatible with miniaturized wiring can be produced.

[0049] <Method for manufacturing a wiring board using the ETS process> Fig. 3 is a diagram for explaining a method for manufacturing a wiring board in which a wiring circuit is formed by selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer in the ETS process. In Fig. 3, only the structure necessary for the explanation is shown schematically.

[0050] First, an electrolytic copper foil (5) with a carrier foil (5a) is laminated onto an insulating resin substrate (1) (FIG. 3(a)). Examples of the carrier foil (5a) include aluminum foil, copper foil, stainless steel foil, resin film, resin film with a metal-coated surface, and glass plate.

[0051] Next, a dry film resist is formed on the surface of the electrolytic copper foil (5), which is then exposed and developed to form a resist pattern (3a) (FIG. 3(b)). In the ETS method, the electrolytic copper foil (5) serves as a copper seed layer. Thereafter, electrolytic copper plating is applied to the exposed portions of the electrolytic copper foil (5) where the resist pattern (3a) is not formed, forming an electrolytic copper plating film (4) (FIG. 3(c)). The resist pattern (3a) is then stripped using a stripping solution to form a copper wiring pattern (4a) composed of copper wiring (FIG. 3(d)).

[0052] Next, the resulting structure is inverted, and a copper wiring pattern (4a) is embedded in the interlayer insulating resin (7) (FIG. 3(e)). The interlayer insulating resin (7) is not particularly limited as long as it is one generally used in the manufacture of printed wiring boards. Thereafter, the insulating resin substrate (1) and the carrier foil (5a) are peeled off (FIG. 3(f)). Finally, the electrolytic copper foil (5) is etched back using the etching composition of the present invention, thereby obtaining a printed wiring board (10) with an embedded copper wiring pattern (4a) (FIG. 3(g)).

[0053] According to a preferred embodiment of the present invention, in the ETS method, by etching an electrolytic copper foil (copper seed layer) using the etching composition of the present invention, it is possible to selectively etch the electrolytic copper foil (5) while suppressing side etching of the copper wiring pattern (4a) along the side wall of the interlayer insulating resin (7) and / or etching of the upper surface, while maintaining the rectangularity of the wiring cross section, and to produce a printed wiring board (10) that is compatible with miniaturized wiring.

[0054] Next, the present invention will be explained in more detail using examples and comparative examples, but the present invention is not limited to these examples in any way.

[0055] Examples 1 to 24 (1) Preparation of Etching Compositions Each component was mixed in the composition ratio shown in Table 1A and stirred to a homogeneous state to prepare an etching composition.

[0056]

[0057] (2) Evaluation Samples <Evaluation Samples for M-SAP (Examples 1 to 13, Examples 15 to 24, Comparative Examples 1 to 9)> Evaluation samples for the etching compositions of Examples 1 to 13, Examples 15 to 24, and Comparative Examples 1 to 9 were prepared as follows. First, an ultra-thin copper foil with a carrier foil, "Micro Thin 18EX" (manufactured by Mitsui Mining & Smelting Co., Ltd.) having a thickness of 3 μm, was laminated to an insulating resin substrate (detachable core) with the electrolytic copper foil side in contact. Next, the carrier foil was peeled off, and the exposed electrolytic copper foil was subjected to electroless copper plating (0.6 μm) and electrolytic copper plating (3.4 μm) to a total thickness of 4 μm to form a copper seed layer with a thickness of 7 μm. Subsequently, a dry film resist was laminated on the copper seed layer, and the dry film resist was exposed to light with a line / space (L / S) of 45 / 15 μm. The exposed dry film resist was developed using an aqueous sodium carbonate solution to form a resist pattern. Next, electrolytic copper plating was applied to exposed portions of the copper seed layer that were not covered with the resist, forming an electrolytic copper-plated film with a wiring height of 20 μm. The resist pattern was then stripped using a dry film stripper "R-100S" (manufactured by Mitsubishi Gas Chemical Company, Inc.) to obtain a substrate (evaluation sample) with copper wiring formed on the copper seed layer. The copper wiring width in the evaluation sample was 43.8 μm, and the copper wiring height from the top surface of the copper seed layer was 21.3 μm. <Evaluation Sample for ETS Method (Example 14)> An evaluation sample of the etching composition of Example 14 was prepared as follows. First, an ultra-thin copper foil with a carrier foil, "MT18SD-H-T5" (manufactured by Mitsui Mining & Smelting Co., Ltd.) having a thickness of 5 μm, was laminated to a 100 μm thick detachable core (substrate: "HL-832NSF") (manufactured by Mitsubishi Gas Chemical Co., Inc.) so that the carrier foil side was in contact. Next, a dry film resist was laminated on the surface of the electrolytic copper foil, and the dry film resist was exposed to light with a wiring design of line / space (L / S) = 10 / 10 μm. The exposed dry film resist was developed using an aqueous sodium carbonate solution to form a resist pattern.Next, electrolytic copper plating was applied to the exposed portions of the electrolytic copper foil (copper seed layer) that were not covered with the resist, forming an electrolytic copper-plated film with a wiring height of 10 μm. The resist pattern was then removed using a dry film stripper "R-100S" (manufactured by Mitsubishi Gas Chemical Co., Ltd.), forming copper wiring on the electrolytic copper foil. The resulting structure was then inverted and laminated so that the copper wiring was embedded in a prepreg "GHPL-830NS SH65" (manufactured by Mitsubishi Gas Chemical Co., Ltd.). The outer layer copper foil laminated on the prepreg on the side opposite the copper wiring used when laminating the copper wiring to the prepreg was an ultra-thin copper foil with a carrier foil "MT18Ex" (manufactured by Mitsui Mining & Smelting Co., Ltd.) with a thickness of 5 μm, with the electrolytic copper foil facing the prepreg. The detachable core and carrier foil were then peeled off, producing a substrate having an electrolytic copper foil on its surface and embedded copper wiring. The obtained substrate had copper wiring formed thereon with a wiring width of 10 to 10.5 μm at a pitch of 20 μm.

[0058] (3) Etching Treatment The evaluation sample was subjected to an etching treatment using the etching composition prepared in (1) above at a treatment temperature of 30°C using a spray etching machine. The spray pressure was 0.05 MPa in Example 4 and 0.15 MPa in the other Examples and Comparative Examples. The etching endpoint was observed using an optical microscope (Olympus Corporation, "MX-63L") and was determined as the point at which the remaining copper in the copper seed layer between the copper wirings disappeared (just etching time). The evaluation sample was removed from the etching composition and immersed in ultrapure water for 10 seconds, 5 mass% sulfuric acid for 10 seconds, and ultrapure water for 10 seconds for cleaning. The evaluation sample was removed from the ultrapure water and dried with a nitrogen blower.

[0059] (4) Evaluation of Width and Height of Copper Wiring After Etching Treatment The wiring width and height of the copper wiring after etching treatment in each evaluation sample of the Examples and Comparative Examples were measured from the wiring cross-sectional direction using an SEM ("S-3700" manufactured by Hitachi High-Technologies Corporation) and evaluated according to the following criteria: <Width> ◎: 30 μm or more ◯: 25 μm or more and less than 30 μm ×: less than 25 μm <Height> ◎: 20 μm or more ×: less than 20 μm

[0060] (5) Evaluation of rectangularity of copper wiring after etching treatment The wiring cross section of the copper wiring after etching treatment was observed with an SEM ("S-3700" manufactured by Hitachi High-Technologies Corporation), and the rectangularity of the wiring cross section shape was visually evaluated. The rectangularity was evaluated according to the following criteria. <Rectangularity> ◎: Rectangularity was maintained ◯: Slightly trapezoidal, but rectangularity was maintained ×: Trapezoidal, and rectangularity could not be maintained, or undercut or side etching occurred Specific examples of the evaluation criteria are shown in Figure 4 for the cases of SAP, M-SAP, and the ETS method.

[0061] (6) Evaluation of Etching Rate of Copper Seed Layer The etching rate of the copper seed layer (ER, μm / min) was determined by dividing the thickness (μm) of the copper seed layer by the just etching time (min).

[0062] (7) Evaluation of Etching Rate Ratio According to the following formula, the etching rate ratio of the wiring width and the etching rate ratio of the wiring height were calculated and evaluated according to the following criteria: Etching rate ratio of wiring height = Δ height / seed layer thickness (1) Etching rate ratio of wiring width = Δ side width / seed layer thickness (2) <Etching rate ratio of wiring height> ◎: 1.2 or less ×: More than 1.2 <Etching rate ratio of wiring width> ◎: 1.0 or less ◯: More than 1.0 and 1.4 or less ×: More than 1.4

[0063] The results are shown in Table 1B. The overall evaluation was determined based on the lowest evaluation among the evaluation items.

[0064]

[0065] Comparative Examples 1 to 9 Etching compositions were prepared in the same manner as in the Examples except that the composition ratios shown in Table 2A were used, and etching treatments were carried out using evaluation samples. The shape (width, height, and rectangularity) of the copper wiring after the etching treatment, the etching rate, and the etching rate ratio were evaluated.

[0066]

[0067] The results are shown in Table 2B. The overall evaluation was determined based on the lowest evaluation among the evaluation items.

[0068]

[0069] As shown by the above results, by using the etching composition of the present invention, it is possible to selectively remove the copper seed layer while suppressing thinning of the copper wiring and maintaining the rectangularity of the wiring cross section (Examples 1 to 24). On the other hand, when the etching composition did not contain the components (A) and (B), etching did not proceed (Comparative Example 1). When only the components (A) and (B) were present, or when the component (C) was not present, the wiring height was significantly reduced, and the copper seed layer could not be selectively etched (Comparative Examples 2 and 3). When the component (E) was not present, both the wiring width and wiring height were significantly reduced, and the copper seed layer could not be selectively etched (Comparative Example 4). Furthermore, when the content of the component (E) exceeded the predetermined range, the wiring height was significantly reduced, and the copper seed layer could not be selectively etched (Comparative Example 5). When the ratio of the component (A) / the component (B) was smaller than the predetermined range, the copper seed layer could not be selectively etched (Comparative Examples 6 and 7). When the component (D) was not present and the ratio of the component (A) / the component (B) was smaller than the predetermined range, the rectangularity could not be maintained (Comparative Example 8). Furthermore, when the (D) component and the (E) component were not included and the (A) component / (B) component ratio was smaller than the specified range, the wiring height was significantly reduced and rectangularity could not be maintained (Comparative Example 9).

[0070] REFERENCE SIGNS LIST 1 insulating resin substrate 1a via or trench 2 electroless copper plating film 3 dry film resist 3a resist pattern 4 electrolytic copper plating film 4a copper wiring pattern 5 electrolytic copper foil 5a carrier foil 6 thin copper layer 7 interlayer insulating resin 10 wiring board or printed wiring board

Claims

1. An etching composition for selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer, comprising: The composition contains hydrogen peroxide (A), sulfuric acid (B), an azole or its salt (C), a glycol ether (D), a halide ion (E), and water (F), the content of hydrogen peroxide (A) is 0.1 to 10 mass% based on the total amount of the etching composition, the content of sulfuric acid (B) is 0.5 to 5 mass% based on the total amount of the etching composition, the ratio of hydrogen peroxide (A) to sulfuric acid (B) is 2 or more in molar ratio; the content of the halide ion (E) is 0.01 to 3 ppm based on the total amount of the etching composition; Etching compositions.

2. 2. The etching composition according to claim 1, wherein the azole is a heterocyclic compound having a five-membered heterocycle having two nitrogen atoms or a condensed heterocycle thereof.

3. 3. The etching composition according to claim 2, wherein the azole is at least one selected from the group consisting of pyrazoles, imidazoles, and benzimidazoles.

4. The azoles are of the formula: 【Chemistry 1】 [In the formula, R １ , R ２ , R ３ , R ４ , R ５ and R ６ are each independently a hydrogen atom, C １ ~C ６ Alkyl group, C ６ ~C １０ Aryl group, carboxyl group, carboxy C １ ~C ６ Alkyl group, nitro group, hydroxyl group, C ２ ~C ７ a carboxylic acid ester, or a halogen atom.

4. The etching composition according to claim 3, wherein the compound is one or more selected from the group consisting of compounds represented by the formula:

5. 5. The etching composition according to claim 4, wherein the azole is at least one selected from the group consisting of imidazole, 1,2,4,5-tetramethylimidazole, 4-methyl-2-phenylimidazole, benzimidazole, 1-methylbenzimidazole, 2-methylbenzimidazole, 5-methylbenzimidazole, 2,5-dimethylbenzimidazole, 5-nitrobenzimidazole, pyrazole, and 3,5-dimethylpyrazole.

6. 2. The etching composition according to claim 1, wherein the content of the azole is 0.01 to 0.5 mass % based on the total amount of the etching composition.

7. 2. The etching composition according to claim 1, wherein the glycol ether (D) is at least one selected from the group consisting of ethylene glycol monobutyl ether, diethylene glycol monomethyl ether, diethylene glycol monophenyl ether, and dipropylene glycol monomethyl ether.

8. 2. The etching composition according to claim 1, wherein the content of the glycol ether (D) is 0.01 to 1 mass % based on the total amount of the etching composition.

9. 2. The etching composition according to claim 1, wherein the halide ion (E) is a chloride ion.

10. Formula (1): at a treatment temperature of 30°C Etching rate ratio of wiring height = Δ height / seed layer thickness (1) [In the formula, the seed layer thickness represents the thickness (μm) of the copper seed layer removed by etching, and the Δheight represents the etching thickness (μm) of the top surface of the copper wiring removed by etching in just the etching time required to remove the entire copper seed layer by etching.] 2. The etching composition according to claim 1, wherein the etching rate ratio of the copper wiring to the wiring height defined by

11. Formula (2): at a treatment temperature of 30°C Etching rate ratio of wiring width = Δ width / seed layer thickness (2) [In the formula, the seed layer thickness represents the thickness (μm) of the copper seed layer removed by etching, and the Δ one-side width represents the value (μm) obtained by converting the lateral width of the copper wiring removed by etching to one side (½) in just the etching time when the entire copper seed layer is removed by etching.] The etching composition according to claim 10, wherein the etching rate ratio of the copper wiring to the wiring width defined by

12. 2. The etching composition according to claim 1, wherein the copper seed layer is at least one selected from the group consisting of an electrolytic copper foil, an electrolytic copper-plated film, and an electroless copper-plated film.

13. A method for producing a wiring board, comprising a step of selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer, using the etching composition according to claim 1 .

14. The method for producing a wiring board according to claim 13, wherein the copper seed layer is at least one selected from the group consisting of an electrolytic copper foil, an electrolytic copper plating film, and an electroless copper plating film.

15. A method for producing a wiring board, comprising the steps of: selectively etching a copper seed layer from a substrate having a copper wiring pattern and a copper seed layer using the etching composition according to any one of claims 1 to 12 in a semi-additive process (SAP), a modified semi-additive process (M-SAP), or an embedded trace substrate process (ETS process), thereby forming a wiring circuit.

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