Ai computing power server PCB mainboard manufacturing process

Abstract

The invention discloses an Ai computing power server PCB mainboard manufacturing process, which comprises the following steps: a pressing step: pressing a plurality of sub-cards into a total card, the thickness of the total card being L; in the drilling step, a through hole is drilled in the main clamp, the diameter of the through hole is D, and the aperture ratio L / D is not smaller than 10: 1; an electroplating step: electroless copper electroplating; a first hole plugging step, wherein the through hole is filled with heat-conducting resin; a back drilling step: detecting and adjusting back drilling processing parameters, and performing back drilling processing on the through hole; a micro-etching step: washing the total card by using a micro-etching liquid medicine; and a second hole filling step of filling resin or solder mask ink in the through hole. According to the Ai computing power server PCB mainboard manufacturing process, the heat conduction resin is adopted to plug the hole, then back drilling is conducted, it is guaranteed that no liquid medicine is left in the hole, the hole is not blocked during back drilling, the heat conduction coefficient of the heat conduction resin is high, the heat dissipation performance of the mainboard is improved, back drilling machining parameters are detected and adjusted during back drilling, and the back drilling machining precision is guaranteed.

Description

A manufacturing process for an AI computing server PCB motherboard Technical Field

[0001] This invention relates to the field of printed circuits, and in particular to a manufacturing process for an AI computing server PCB motherboard. Background Technology

[0002] In the era of 5G and 6G computing power, AI computing servers combine high-performance computing, cloud computing, and big data technologies to support training tasks for large models with hundreds of billions of parameters, as well as high-concurrency AI cloud inference in data centers and other technological scenarios and applications. Its supporting PCB products include five categories: arbitrary-layer HDI (High-Density Interconnect Board, a high-density printed circuit board manufactured using micro-blind via technology and multilayer process), high-density GPU carrier boards, thick copper power module PCBs, high-speed connector substrates, and high-speed server motherboards. Among these, the server motherboard, which carries the high-speed analysis and computing tasks of GPU clusters, is the core. It needs to process massive amounts of data quickly and efficiently and extract valuable information for users, thus placing stricter requirements on product reliability.

[0003] As the core of data processing, the PCB motherboard of an AI computing server is composed of multiple layers laminated together, resulting in a relatively thick board, typically 2-4mm thick, with some reaching 6mm, and 20-60 layers. The holes drilled on this PCB are relatively small in diameter compared to the board thickness, creating a high aperture ratio PCB. Using conventional designs and processes for this type of PCB presents several problems: Conventional HDI designs cannot be processed with HDI filling plating on boards thicker than 3.2mm, and HDI has a higher risk of pad detachment and reliability issues compared to through-hole or resin blind via processes. Resin blind via processes are limited by current processing technology; conventional back-drilling of high aperture ratio deep micro-holes can lead to hole blockage, and subsequent resin plugging presents technical challenges such as voids. Furthermore, residual etching chemicals from conventional copper plating processes remain inside the holes, eroding the copper layer over time, eventually causing copper breakage and performance degradation leading to failure. High-speed AI computing server motherboards or cluster computer groups have high heat dissipation requirements, necessitating high thermal conductivity for AI computing server PCB motherboards, which conventional resin-filled vias cannot meet. Furthermore, due to copper plating design and PP adhesive flow, the thickness of AI computing server PCB motherboards varies at different locations, hindering precise control of back-drilling depth and residual post length.

[0004] To address these issues, there is an urgent need for a manufacturing process for AI computing server PCB motherboards that ensures the quality of the processed PCB boards and meets the reliability requirements of AI computing server PCB motherboards. Summary of the Invention

[0005] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a manufacturing process for an AI computing server PCB motherboard, which uses thermally conductive resin to plug the holes before back-drilling. This ensures that there are no voids or residual chemicals in the holes, and that the holes will not be blocked during back-drilling. Furthermore, the thermally conductive resin has a high thermal conductivity, which improves the heat dissipation performance of the motherboard. In addition, the back-drilling processing parameters are detected and adjusted during back-drilling to ensure the accuracy of the back-drilling process.

[0006] According to an embodiment of the present invention, a manufacturing process for an AI computing server PCB motherboard includes the following steps: a lamination step, in which multiple individual cards are laminated into a single card, the thickness of the single card being L; a drilling step, in which through holes are drilled in the single card, the diameter of the through holes being D, wherein L and D have the same unit, the hole diameter ratio is L / D, and L / D is not less than 10:1; an electroplating step, in which copper is plated onto the walls of the through holes; a first plugging step, in which thermally conductive resin is filled into the through holes; a back-drilling step, in which back-drilling processing parameters are detected and adjusted, and back-drilling is performed on the through holes; a micro-etching step, in which the single card is washed with water using a micro-etching solution; and a second plugging step, in which resin or solder resist ink is filled into the through holes.

[0007] According to an embodiment of the present invention, a manufacturing process for an AI computing server PCB motherboard has at least the following technical effects: by using thermally conductive resin to plug the holes and then performing back drilling, it is ensured that there are no voids or residual chemicals in the holes, and the holes will not be blocked during back drilling. In addition, the thermally conductive resin has a high thermal conductivity, which improves the heat dissipation performance of the motherboard. Furthermore, the back drilling processing parameters are detected and adjusted during back drilling to ensure the back drilling processing accuracy.

[0008] According to some embodiments of the present invention, in the drilling step, multiple drilling operations are performed at the through-hole forming position, wherein the drilling diameter and / or drilling depth of the later drilling operation is larger than that of the previous drilling operation, and the through hole is formed at the through-hole forming position after the last drilling operation.

[0009] According to some embodiments of the present invention, when performing multiple drilling operations, double-sided drilling is performed from the first drilling operation to the Zth drilling operation, where Z is a positive integer.

[0010] According to some embodiments of the present invention, pulse electroplating is used in the electroplating step, and pulse electroplating solution is employed.

[0011] According to some embodiments of the present invention, in the electroplating step, the copper plating is performed a predetermined number of times. Each time the copper plating is performed, the plating time is calculated based on the total area to be plated, the predetermined current density, the predetermined plating efficiency, and the predetermined copper thickness of the through-hole wall. As the total thickness increases, the predetermined number of times increases, and the predetermined current density, the predetermined plating efficiency, and the predetermined copper thickness of the through-hole wall decrease.

[0012] According to some embodiments of the present invention: when the thickness of different total cards is within the same thickness range, the drilling step and the electroplating step are performed on the different total cards using the same scheme; wherein, the drilling diameter, drilling depth, and number of double-sided drilling operations in the drilling step are drilling parameters, and the specific configuration of the pulse electroplating solution, the number of electroplating operations, the current density, the electroplating efficiency, and the predetermined copper thickness of the through-hole wall in the electroplating step are electroplating parameters; in the same scheme, the drilling parameters and the electroplating parameters are the same.

[0013] According to some embodiments of the present invention, in the electroplating step, pulse electroplating is used. Each time the copper plating is performed, the parameters of the pulse waveform are: M segments of DC positive and negative pulse waveforms, the positive and negative current ratio increases sequentially, the positive and negative time ratio decreases sequentially, and M is a positive integer greater than 2.

[0014] According to some embodiments of the present invention, in the back-drilling step, a drilling device is used to back-drill the first total card according to a first predetermined back-drilling depth value H1. A measuring device is used to measure the actual depth value h1 of the back-drilled hole. The back-drilled residual pile of the first total card is analyzed by slicing, and the residual pile difference Δh is calculated to obtain a second predetermined back-drilling depth value H2, where H2 = H1 + Δh. The predetermined depth value h2 is obtained, where h2 = h1 + Δh. The second predetermined back-drilling depth value is used to back-drill the subsequent total cards. A measuring device is used to measure the actual depth value h3 of the back-drilled hole. The back-drilling reprocessing of the total card is determined based on the difference between h2 and h3.

[0015] According to some embodiments of the present invention: in the drilling step, the through hole includes normal through holes and test through holes provided in the waste area of ​​the total card, and the test through holes are provided in N groups, each group having multiple test through holes, where N is a positive integer; in the back drilling step, the normal through holes are provided with N back drilling depths, and the test through holes in the nth group are back drilled using a drilling device according to the nth predetermined back drilling depth value until all the test through holes in the N groups are back drilled, where n is a positive integer not greater than N, and the nth predetermined back drilling depth value is one of the N back drilling depths; the residual pile difference value of all the test through holes in the nth group is analyzed by slicing, the average value of all residual pile differences is statistically calculated, the specific value of the nth predetermined back drilling depth value is re-determined based on the average value of the residual pile differences, and the normal through holes in the nth group are back drilled based on the re-determined nth predetermined back drilling depth value until all the normal through holes are back drilled.

[0016] According to some embodiments of the present invention, after the electroplating step and before the first hole plugging step, at least one of the test vias is subjected to cross-sectional analysis to confirm whether the copper layer thickness on the wall of the test via is qualified.

[0017] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Detailed Implementation

[0018] The embodiments of the present invention are described in detail below.

[0019] In the description of this invention, it should be understood that the descriptions of orientation are for the convenience of describing the invention and for simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention. In the description of this invention, sidewalls refer to the left sidewall and / or the right sidewall.

[0020] In the description of this invention, "a plurality of" means two or more; "greater than," "less than," "exceeding," etc., are understood to exclude the number itself; and "above," "below," "within," etc., are understood to include the number itself. Where "first" or "second" is used, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the sequential relationship of the indicated technical features.

[0021] In the description of this invention, it should be understood that "A is set on B" or "A is set on B" describes the connection or positional relationship between A and B, and does not mean that A is necessarily above B.

[0022] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, movable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention in conjunction with the specific circumstances. It should be understood that multiple similar features in this invention are distinguished only by different prefixes. Therefore, in this invention, feature names without distinguishing prefixes (or feature names with partial prefixes) are used to represent this type of feature or its combination, such as using "plugging hole" to represent the first plugging hole step and the second plugging hole step.

[0023] The manufacturing process of the AI ​​computing server PCB motherboard according to an embodiment of the present invention includes the following steps: a lamination step, in which multiple individual cards are laminated into a single card, the thickness of which is L; a drilling step, in which through holes are drilled in the single card, the diameter of which is D, where L and D have the same unit, the diameter ratio is L / D, and L / D is not less than 10:1; an electroplating step, in which copper is plated onto the walls of the through holes; a first plugging step, in which thermally conductive resin is filled into the through holes; a back-drilling step, in which back-drilling processing parameters are detected and adjusted, and back-drilling is performed on the through holes; a micro-etching step, in which the single card is washed with water using a micro-etching solution; and a second plugging step, in which resin or solder resist ink is filled into the through holes.

[0024] A PCB (Printed Circuit Board), also known as a circuit board, is a crucial component of the electronics industry. The term "board" in "total board" and "sub-board" strictly refers to an unfinished circuit board (or a semi-finished product; its "unfinished" state is relative to the final finished circuit board, but broadly speaking, it can also be called a circuit board). It's a process distinction used in the manufacturing of the final finished circuit board. A sub-board is a single-layer circuit board, while a total board is a circuit board formed by stacking and laminating multiple single-layer circuit boards together. In this invention, PCB, total board, and sub-board (generally total board) can be simply referred to as "board." PCB total board processing is one of many processes in the entire PCB manufacturing process; therefore, in actual PCB manufacturing, there are usually other processes before and after it. Since the inner layer sub-cards are relatively thin and the aperture ratio is generally below 8:1, which is a standard setting, the inner layer sub-cards can be manufactured using the original process: material cutting, inner layer circuitry, etching, lamination, drilling, plasma desmearing, electroplating, tin plating, back drilling, alkaline etching, resin plugging, inner layer etching, inner layer inspection, and finally, the sub-cards are laminated into a complete card.

[0025] In some embodiments, aluminum alloy cover plates, cold-stamped plates, or special back-drilling aluminum sheets can be used as cover plates or backing plates to assist in drilling and improve drilling quality. Using cover plates and backing plates protects the PCB during drilling, prevents drilling contamination, and aids in heat dissipation. Through holes can be simply referred to as holes. In some embodiments, after drilling, the entire board undergoes a high-pressure water wash at a pressure of 60-80 kg to facilitate cleaning of the board surface and residual dust inside the holes before electroplating. In some embodiments, after drilling and before electroplating, plasma desmearing is performed to remove residue from the hole walls, exposing the copper layer and ensuring the reliability of subsequent chemical copper plating and electroplating.

[0026] Immersion copper plating, which involves plating copper onto the walls of through-holes, is a common process for metallizing through-holes in PCB manufacturing. Its specific working process and principles will not be elaborated here. It is important to understand that specialized development can be carried out on top of the conventional immersion copper plating process to improve the plating quality, thereby enhancing product quality.

[0027] Via plugging, performed using a specialized via plugging machine, is a common process in PCB manufacturing. Conventional via plugging resins have very low thermal conductivity, while specialized thermally conductive resins offer high thermal conductivity, enhancing the heat dissipation performance of the PCB motherboard. Specific thermally conductive resins include standard copper paste, interconnect copper paste, and nano-silver paste. These resins, with the addition of thermally conductive metal materials to conventional resins, offer superior thermal conductivity, heat dissipation, and electrical conductivity compared to conventional resins. The high thermal conductivity improves the thermal effect during product use and facilitates electrical conduction between components through vias, thus improving product quality. Specifically, for products with lower thermal conductivity requirements, standard copper paste is used. Standard copper paste is a mixture of approximately 70% copper powder and epoxy resin, with a thermal conductivity below 3 W / mK. For products requiring a thermal conductivity of 20-60 W / mK, tin-bismuth-copper thermoelectric interconnect copper paste is selected. For products requiring a thermal conductivity ≥200 W / mK, nano-silver paste with a silver content of 75%~85% is selected. It is important to understand that in the AI ​​computing server PCB motherboard manufacturing process of this invention, all through holes in the first hole-filling step are filled with thermally conductive resins such as silver paste and high-performance copper paste instead of conventional ordinary resin. In the second hole-filling step, the relatively few back-drilled holes are still filled with conventional resin, or only serve an insulating and isolating function. That is, the communication part of the back-drilled hole is filled with thermally conductive resin pillars such as silver paste and high-performance copper paste, while the isolation part is filled with conventional resin or solder resist ink. This satisfies the technical and quality requirements of high-speed AI computing server PCB motherboards for heat dissipation and signal transmission, while also reducing production costs. The first hole-filling step facilitates back-drilling; the second hole-filling step fills the back-drilled holes, keeping the board surface flat, ensuring the integrity of the entire board, increasing the board structure, and preventing internal components from contacting the outside world and being contaminated or corroded. It is important to understand that in some embodiments, during the second plugging step, a dedicated back-drilled hole plugging aluminum sheet is placed on the outer surface of the main card to prevent resin from entering other areas of the main card. This facilitates the second plugging after back-drilling, ensuring the plugging quality of the back-drilled holes, improving the flatness of SMT surface mount technology, and significantly enhancing product quality. Specifically, since the hole diameter is increased by 0.1-0.3mm compared to the original hole during back-drilling, the plugging aluminum sheet is increased by 0.1mm to the diameter of the back-drilled hole, which is more conducive to resin plugging and leveling. When using the plugging aluminum sheet, resin flows more easily into the hole during selective back-drilled hole resin plugging. After the plugging is cured, excess resin around the hole is ground down to maintain a flat board surface. Furthermore, in double-sided back-drilling, the component side needs to be plugged first, cured at 150℃ for 5-8 minutes, and then the solder side is plugged, followed by final curing.

[0028] Micro-etching serves two purposes: first, it removes excess copper from the board surface during electroplating; second, it removes burrs, impurities, residues, and oil stains from various processing steps, especially cleaning the environment inside holes. Specifically, on an acidic copper reduction production line (or micro-etching production line), the high-pressure water washing pressure is adjusted to 60-80KG, and the speed is adjusted according to the amount of copper removed each time, washing the board twice in both directions. Micro-etching approximately 5µm of copper layer is sufficient to complete the cleaning process.

[0029] In conventional master card processing, the master card is first electroplated with tin to protect the copper layer during subsequent etching, then back-drilling is performed, followed by alkaline etching, and finally resin plugging. However, this process can cause many problems. Due to the small diameter of deep microvias, and the different material properties, copper foil has good ductility, and the copper drill chips are curled and ribbon-like after being cut by the drill bit. In contrast, glass fiber / resin chips are brittle and appear as broken particles. The copper chips form a spiral entanglement, increasing the chip removal resistance. During back drilling of deep microvias, the tin protection inside the hole cannot be baked into the board, and the damp dust and tin cannot be completely removed, clogging the chip removal groove. The deeper the drill bit goes, the more blockage it forms. Therefore, in the conventional master card processing technology, the back drilling process for deep microvias smaller than 0.2mm has an extremely high clogging rate, especially after electroplating. Because the copper plating on the hole wall during electroplating further reduces the through-hole diameter and increases the hole diameter ratio, the back drilling process is difficult and prone to clogging. Etching after back drilling and then plugging the hole can leave some etching solution inside the hole, which can corrode the copper layer inside the hole over time. This can lead to copper breakage, resulting in poor performance or even failure. In addition, the presence of tin inside the hole can affect the back drilling process, making it difficult to plug the hole completely in the future, and causing voids due to gas expansion.

[0030] To address the aforementioned problems in existing technologies, this invention abandons the traditional total card processing method and innovatively fills the holes with thermally conductive resin instead of electroplating them with tin. Due to the copper plating, all holes are fully conductive, facilitating smoother filling with the thermally conductive resin. Therefore, this type of hole filling only requires adjusting the filling pressure to the upper limit after baking the board and reducing the filling speed by more than 30% to ensure filling quality. Furthermore, after filling, firstly, there will be no copper curling up during back drilling; instead, there will be broken granular resin debris, reducing chip removal resistance. Secondly, the holes are already filled with thermally conductive resin before micro-etching and etching, preventing chemicals from entering and corroding the copper layer inside. Thirdly, the holes are free of tin and other residues (e.g., moisture can be removed by baking due to the absence of tin), the hole walls are copper-coated, and the holes have good conductivity during filling, making them easy to fill without voids or blockages. The overall card processing technology of this invention solves the problems of hole blockage, hole plugging and subsequent quality issues in the existing back-drilling process for high aperture ratio resin pads by first replacing tin plating with thermally conductive resin plugging. This addresses the technical defects of traditional processes and improves the back-drilling hole plugging of high aperture ratio AI computing server products, preventing long-term corrosion of the copper layer by micro-etching solutions, thereby ensuring the stability and service life of PCB products.

[0031] The AI ​​computing server PCB motherboard manufacturing process of this invention uses thermally conductive resin to plug the holes before back drilling, ensuring that there are no voids or residual chemicals in the holes and that the holes will not be blocked during back drilling. In addition, the thermally conductive resin has a high thermal conductivity, which improves the heat dissipation performance of the motherboard. Furthermore, the back drilling processing parameters are detected and adjusted during back drilling to ensure the back drilling processing accuracy.

[0032] In some embodiments of the present invention, the drilling and plugging steps are designed and processed according to the size of the outer BGA pads and the expected spacing of the via walls: Option 1: For products with 0.10mm ≤ hole wall spacing < 0.15mm and outer BGA pad size: 4mil ≤ pad diameter < 8mil, a padless via design technology is used (i.e., the pad and hole diameter are the same size, and there are no pads after drilling); a padless nano silver paste via process is used to replace the conventional HDI laser stacking process, the via drilling diameter is designed to be 0.10mm-0.12mm, and the via is plugged using high-performance nano silver paste via filling interconnect technology.

[0033] Option 2: For products with a hole wall spacing of 0.15mm ≤ hole size < 0.25mm and an outer BGA pad size of 8mil ≤ pad diameter < 14mil, a 1-2mil micro-pad hole design is used (i.e., the pad contains a 1-2mil extension pad); a high-performance copper paste pad-in-hole structure is used to replace the conventional HDI laser stacked via structure, the hole diameter of the pad-in-hole is designed to be 0.15-0.175mm, and the via is plugged using high-performance interconnect copper paste filling interconnect technology.

[0034] Option 3: For HDI or high-multilayer products with hole wall spacing ≥ 0.25mm and outer BGA pad size ≥ 14mil, use a pad design with pad ring width > 2mil, process with 0.2mm pad-in-hole technology, and use standard copper paste to plug the holes instead of the solder and resin filling solution.

[0035] In some embodiments of the present invention, during the drilling step, multiple drilling operations are performed at the through-hole forming position, wherein the drilling diameter and / or drilling depth of the later drilling operation is larger than that of the previous drilling operation, and a through hole is formed at the through-hole forming position after the last drilling operation.

[0036] In some embodiments of the present invention, when performing multiple drilling operations, double-sided drilling is performed from the first drilling operation to the Zth drilling operation, where Z is a positive integer.

[0037] Specifically, in some embodiments of the present invention, in the drilling step: a pilot hole machining step, using a primary drill bit to perform double-sided pilot hole machining on the main chuck to form a primary hole; a reaming step, using a secondary drill bit to ream the primary hole to form a secondary hole; a forming hole machining step, using a tertiary drill bit to form a through hole based on the secondary hole; wherein, the diameter of the primary drill bit is smaller than the diameter of the secondary drill bit, and the diameter of the secondary drill bit is smaller than the diameter of the tertiary drill bit; furthermore, the drilling depth of the primary drill bit is smaller than the drilling depth of the secondary drill bit, and the drilling depth of the secondary drill bit is less than or equal to the drilling depth of the tertiary drill bit; and the drilling depth of the primary drill bit is less than the hole depth of the through hole.

[0038] It is important to understand that the drilling process in this invention involves micro-hole drilling with a high aperture ratio and a hole diameter of less than 0.2 mm. Furthermore, the core component of the AI ​​computing server motherboard is high-hardness quartz cloth (Q cloth), which has a melting point as high as 1650-1700℃, far exceeding that of traditional fiberglass cloth. This results in a dramatic increase in PCB hardness. Products with a diameter of less than 0.2 mm can only drill about 100-300 holes using traditional cemented carbide tungsten carbide drill bits, far below the technical requirement of 1000 holes. Therefore, a specialized drill bit is required. Specifically, the drill bit body is made of tungsten-cobalt cemented carbide, using 92% tungsten carbide powder as the matrix and 8% cobalt as the binder. Diamond bonds are formed through high-temperature, high-pressure liquid-phase sintering. The drill bit uses a diamond-coated extended drill bit, and the drill tip adopts a low helix angle design of 130 degrees ± 2 degrees to increase drilling and cutting strength. A high helix angle of 35-38 degrees is used in the chip removal section to optimize chip removal. The drill bit uses a diamond-coated material, which has strong resistance to bending deformation and increased hardness, making drilling easier. Conventional drill bits have a 118-degree helix angle, while the drill bit of this invention is designed with a low helix angle of 130 degrees ± 2 degrees, increasing drilling and cutting strength. Regarding the chip removal flute, conventional drill bits have a chip removal section of 10-30 degrees, while this technology uses a high helix angle design of 35-38 degrees to optimize chip removal while maintaining flexibility. Since conventional cutting lengths and diameters cannot process the high aperture ratio deep micro-holes required in this invention, a dedicated series of ultra-long cutting length drill bits has been developed. The specific diameters and cutting lengths of this series are as follows: 0.075mm diameter, 2.5mm cutting length; 0.11mm diameter, 3.5mm cutting length; 0.13mm diameter, 4.5mm cutting length; 0.15mm diameter, 6.0mm cutting length; 0.175mm diameter, 7.0mm cutting length; 0.20mm diameter, 7.5mm cutting length.

[0039] Because the overall card plate is relatively thick (the plate thickness is large), the drilling in this invention is deep micro-hole machining, with a large hole diameter ratio (the ratio of plate thickness to through-hole diameter). Therefore, in this invention, the drill bit diameter is very small, and the diameter of the drilled hole is also very small. When the drill bit diameter is less than 0.2 mm, the stiffness of the micro-drill decreases exponentially. The bending deformation of a 0.1 mm diameter drill bit under lateral force is more than 8 times that of a 0.3 mm drill bit. Direct deep micro-hole machining is prone to deformation or even breakage. Moreover, the chip flute volume is only 1 / 10 of that of a conventional drill bit, but the chip size is not reduced proportionally, resulting in chips that are very easy to clog. The chip clogging probability in micro-drilling is as high as 5 times that of conventional drilling, which can further cause heat dissipation problems, making the drill bit more prone to bending deformation or even breakage. Therefore, in addition to developing and using specialized drill bits, a three-stage drilling process is specifically implemented in the drilling steps to reduce drilling difficulty and increase drilling quality: First, a smaller diameter primary drill bit is used to drill a primary hole on both sides, with a shallow drilling depth (even equivalent to a conventional hole rather than a deep micro-hole). Due to the shallow initial drilling depth and the deliberate use of double-sided machining, chip removal is not a serious problem during the initial drilling, and the shallow drilling depth makes the drill bit less prone to bending and deformation. Then, a larger diameter secondary drill bit is used to process the hole based on the primary hole, expanding the diameter and depth of the hole. Because of the foundation of the primary hole, the resistance during secondary drilling is reduced, the drill bit is less prone to bending and deformation, and the number of chips generated is reduced compared to drilling directly on the main chuck. The chips can also be stored and discharged along the original primary hole, making them less prone to clogging and improving heat dissipation. Finally, a tertiary drill bit of a predetermined diameter is used to process the hole based on the secondary hole, forming a through hole of the predetermined diameter. The effect is similar to that of the secondary drill bit drilling described above, and will not be repeated here.

[0040] Through multiple drilling processes, the planar displacement accuracy of the holes was improved from 0.1mm to 0.05mm, meeting the precision cabling requirements of high-speed AI computing servers with power exceeding 100G. Furthermore, the hole diameter of the HDI stacked vias was changed from a 0.1mm design to a hole in the mechanical disk, with a diameter of 0.10-0.175mm, saving 2-5 times or more of the process steps, improving efficiency, mitigating thermal effects, and enhancing quality reliability, thus meeting the reliability requirements of high-speed AI computing server products.

[0041] It is important to understand that in some embodiments, a through-hole process is used to process the master card. Therefore, the diameter of the through-hole is related to the thickness of the master card board and the size of the outer pads. When the board thickness is large and the outer pad size is large, the through-hole diameter can generally be set to be larger accordingly. In the original master card processing technology, the master card was an HDI laser blind via structure. Taking a 3rd-order HDI laser blind via as an example, the average number of processes required to fabricate a 3rd-order laser blind via was 48, and the hole diameter was only 0.1mm. However, the current master card processing technology changes the HDI laser blind via to a mechanical through-hole with a hole diameter of 0.11-0.175mm (i.e., the aforementioned 'through-hole'). The through-hole only requires 10 processing steps to achieve conductivity, reducing the number of processes and improving efficiency. Furthermore, since the reliability of mechanical through-hole is much higher than that of the multiple laser stacking via solution, it also meets the product reliability requirements. The processing scheme is designed based on the size of the outer pads of the product. Specifically, for products with an outer pad size of 8mil ≤ pad diameter ≤ 10mil (mil, also known as milliinch, is a unit of length), a conventional HDI laser blind via can be designed as a mechanical pad-in-hole, with a pad-in-hole drilling diameter of 0.11mm. For products with an outer pad size of 10mil < pad diameter ≤ 15mil, a conventional HDI laser blind via can also be designed as a mechanical pad-in-hole, with a finished pad-in-hole diameter of 0.15mm. For products with an outer pad size > 15mil, a conventional resin blind-buried via structure can be designed using a 0.2mm pad-in-hole process. It should be understood that in some embodiments, ball grid array (BGA) packaging technology is used to form spherical pads. Ball grid array packaging is a surface mount technology for integrated circuits that replaces traditional pins with a bottom solder ball array. Compared with dual in-line package, it can accommodate more pins, shorten the wire length to improve high-speed performance, and has the advantages of low inductance and high thermal conductivity. It should be understood that the '...hole processing' described in this invention refers to drilling, which involves processing a specific hole. It should also be understood that double-sided drilling means drilling the same hole on both the upper and lower surfaces of the main card.

[0042] Replacing HDI laser stacking with mechanical disk-based hole-through technology shortens the processing cycle, reduces production costs, and improves product quality and reliability. Furthermore, HDI laser stacking cannot perform electroplating filling on HDI boards thicker than 3.2mm, while mechanical disk-based holes have larger diameters, lower aperture-to-diameter ratios, and a through-hole structure, allowing for electroplating filling. It's important to understand that, to better facilitate mechanical disk-based hole-through technology production, this invention also specifically developed extended drill bits with different cutting lengths and dedicated diamond coatings to meet product processing quality requirements.

[0043] In some embodiments of the present invention, during the drilling step: when the thickness of the total card is ≤2mm, the drilling depth of both the secondary and tertiary drill bits is greater than the depth of the through hole (or the plate thickness); when 2mm < the thickness of the total card is ≤5mm, during the reaming step, a secondary drill bit is used to perform double-sided reaming on the basis of the primary hole to form a secondary hole; wherein, the drilling depth of the secondary drill bit is less than the depth of the through hole, and the drilling depth of the tertiary drill bit is greater than the depth of the through hole; when 5mm < the thickness of the total card is ≤10mm, during the reaming step, a secondary drill bit is used to perform double-sided reaming on the basis of the primary hole to form a secondary hole; during the forming hole step, a tertiary drill bit is used to perform double-sided forming hole on the basis of the secondary hole to form a through hole; wherein, the drilling depth of the secondary drill bit is less than the depth of the through hole, the drilling depth of the tertiary drill bit is less than the depth of the through hole, and twice the drilling depth of the tertiary drill bit is greater than the depth of the through hole.

[0044] In the drilling process, specifically in some embodiments, the following process parameters are used for drilling: when the total thickness (i.e., plate thickness) is ≤2.0mm, the pilot hole is drilled by using a 0.075mm diameter drill bit with a 2.5mm cutting edge, with each side drilled once at a depth of 0.5mm; the reaming is done by using a 0.11mm diameter drill bit with a 3.0mm cutting edge; and the forming hole is drilled by using a 0.15mm diameter drill bit with a 4.0mm cutting edge.

[0045] When 2.0mm < total card thickness ≤ 5.0mm, for pilot hole machining, use a 0.1mm diameter drill bit with a 2.5mm cutting edge to perform a 1.0mm depth control drill once on each side; for reaming, use a 0.13mm diameter drill bit with a 4.5mm cutting edge to perform a 1.8mm depth control drill once on each side; for forming hole machining, use a 0.15mm diameter drill bit with a 6.0mm cutting edge to perform a straight drill to complete the forming hole machining.

[0046] When the plate thickness is 5.0mm < plate thickness ≤ 10.0mm, for pilot hole machining, use a 0.13mm diameter drill bit with a 4.5mm cutting edge to drill a 2.0mm depth on both sides once; for hole reaming, use a 0.15mm diameter drill bit with a 5.0mm cutting edge to drill a 3.5mm depth on both sides once; for forming hole machining, use a 0.175mm diameter drill bit with a 7.0mm cutting edge to drill a 6.0mm depth on both sides to form the forming hole.

[0047] Double-sided drilling refers to drilling from both sides; controlled-depth drilling refers to drilling using controlled-depth milling equipment, which offers high drilling precision; the formed hole refers to the final hole to be formed, which is the through hole in this invention. It should be understood that the above is only a specific embodiment of this invention, and adjustments can be made according to actual circumstances.

[0048] In the drilling process, when the thickness of the total stencil is ≤2mm, the plate thickness is relatively small, and a two-stage drill bit can be used to drill through the stencil directly in the reaming step. When 2mm < total stencil thickness ≤5mm, the plate thickness increases, and a two-stage drill bit can be used to perform double-sided reaming based on the first-stage hole in the reaming step, instead of drilling through directly or drilling from one side, reducing drilling difficulty and facilitating subsequent forming hole processing steps. When 5mm < total stencil thickness ≤10mm, the plate thickness further increases, and to protect the drill bit and reduce drilling difficulty, a double-sided processing process is used even in the final forming hole processing step, ultimately forming a through hole. Furthermore, based on the plate thickness data, the drilling process is divided into three fixed processes, which facilitates the formation of regulations and standards, enabling rapid processing on assembly lines. In particular, when combined with the subsequent electroplating step, three dedicated production lines can be established to quickly differentiate, process, and manufacture the plates according to their thickness. Using three basically fixed sets of process parameters, no major adjustments are required, simplifying the process, improving the difficulty of quality control, enabling mass production, and meeting the processing requirements of different materials.

[0049] In some embodiments of the present invention, pulse electroplating is used in the electroplating step, and a special pulse electroplating solution is used. The special pulse electroplating solution is prepared as follows: the amount of copper sulfate crystals is 30g / L-40g / L; the amount of carrier is 280g / L-300g / L; and the amount of wetting agent is 20mL / L-30mL / L.

[0050] Copper sulfate crystals, CuSO4•5H2O, also known as blue vitriol, copper sulfate pentahydrate, or copper alum, are the source of copper for the copper layer on the hole walls. The carrier agent, H2SO4, transports the effective components in electroplating to the surface of the part, assisting in refining the plating layer, leveling the surface, and helping to achieve a more uniform current distribution and a more uniform copper plating thickness. The wetting agent, a surfactant, forms a thin film on the electroplating solution and substrate surface, reducing the surface tension of the electroplating solution and the contact angle of the substrate surface, thereby improving the wetting performance of the electroplating solution on the substrate surface. It also helps hydrogen escape from the electroplating solution. Simultaneously, the wetting agent can form an organic film in the electroplating solution, preventing air and impurities from entering, thus ensuring the surface quality and electroplating efficiency of the copper plating, reducing defective copper holes and copper breaks, and improving the production efficiency and quality of PCB boards. Specifically, it can be aliphatic amine polyoxyethylene ether. It should be understood that, depending on the actual situation, other chemical agents, such as leveling agents and accelerators, can be added to the special pulse electroplating solution. The special pulse electroplating solution, in the description of this invention, can be simply referred to as electroplating solution, solution, etc.; other similar descriptions are similar.

[0051] In the overall card processing method of the present invention, the deep micro-hole electroplating method was redesigned, pulse electroplating was selected, and the electroplating solution and pulse parameters were specially developed to meet the copper plating needs of special products.

[0052] The specific electroplating solution development involves adjusting the CuSO4·5H2O concentration from the conventional 45-55 g / L to 30-40 g / L, reducing the copper sulfate solution concentration, decreasing the total copper deposition on the outer surface, and increasing the copper content within the holes to meet the concentration requirements of deep microvias. The carrier H2SO4 concentration is adjusted from the conventional 240-260 g / L to 280-300 g / L, enhancing its carrying capacity and allowing more copper to be transported into the vias. The wetting agent concentration is adjusted from the conventional 10-16 ml / L to 20-30 ml / L, increasing the wettability at the center of the deep microvia and improving the quality of the copper layer within the holes. These adjustments create a dedicated pulse electroplating solution for deep microvias, enhancing the electroplating quality of deep microvias.

[0053] In some embodiments of the present invention, pulse electroplating is used in the electroplating step. Each time copper plating is performed, the parameters of the pulse waveform (pulse parameters) are: M segments of DC positive and negative pulse waveforms, the positive and negative current ratio increases sequentially, the positive and negative time ratio decreases sequentially, and M is a positive integer greater than 2.

[0054] The distinction between positive and negative currents is a standard feature of pulse electroplating technology. Specifically, the positive current direction is generally defined as the direction in which copper ions adhere to (or are reduced to) the main platen under the influence of current to form a copper layer, with the main platen typically acting as the cathode. A reverse current is used to reduce thicker, protruding portions of the copper layer, thus smoothing it and making the copper layer crystallize more densely. This is repeated sequentially, representing the first pulse electroplating segment, the second pulse electroplating segment, and so on up to the Mth pulse electroplating segment; the value increases (decreases) sequentially, meaning the value of the (P-1)th segment is greater (less) than the value of the Pth segment, where P is a positive integer less than or equal to M. During a single copper plating process, the entire process is divided into M segments. As pulse plating proceeds sequentially, copper ions in the plating solution gradually adhere to the main platen, forming a copper layer. The concentration of copper ions in the solution decreases, and at this point, the copper plating layer on the outer surface of the main platen is relatively large. However, in deep micro-holes (through-holes), due to their small size and high aperture ratio, the copper plating capacity inside the holes is relatively poor, and the copper layer on the hole walls is relatively thin. Reducing the forward / reverse time ratio at this point allows the reverse current to occupy a larger proportion of time in each pulse plating segment, thereby further breaking down the copper layer on the outer surface of the main platen, especially around the through-holes. This reduces the surface copper thickness, minimizing copper waste and reducing... This reduces the workload of subsequent copper reduction processes and increases the concentration of copper ions in the electroplating solution, especially the copper ions released from the periphery of the through-hole. These ions are close to the hole wall, making it easier for them to adhere to the hole wall and form a copper layer during subsequent forward electroplating. Increasing the forward-reverse current ratio results in a relatively larger forward current value and a relatively smaller reverse current value. This allows even low-concentration copper ions to adhere to the inner wall of the through-hole and form a copper layer normally and quickly during forward current. Although the reverse current time is longer during reverse current, the current value is relatively smaller, making it less likely to affect the copper layer on the hole wall and basically preventing the breakdown of the copper layer on the hole wall.

[0055] In some embodiments, the pulse waveform parameters can be specifically set as follows: 11 segments of DC forward and reverse pulse waveforms, with the forward and reverse current ratio decreasing from 1:3 to 1:2 in increments of 0.1, and the forward and reverse time ratio decreasing from 60:1 to 30:1 in increments of 3. That is, during one copper plating operation, the entire plating process (time) is divided into 11 segments. The first segment of pulse plating has a forward and reverse current ratio of 1:3 and a forward and reverse time ratio of 60:1; the second segment has a forward and reverse current ratio of 1:2.9 and a forward and reverse time ratio of 57:1; the third segment has a forward and reverse current ratio of 1:2.8 and a forward and reverse time ratio of 54:1... and the eleventh segment has a forward and reverse current ratio of 1:2 and a forward and reverse time ratio of 30:1.

[0056] In some embodiments of the present invention, in the electroplating step, a predetermined number of copper plating operations are performed. Each time copper plating is performed, the plating time is calculated based on the total area to be plated, a predetermined current density, a predetermined plating efficiency, and a predetermined copper thickness of the through-hole wall. As the total thickness increases, the predetermined number of operations increases, while the predetermined current density, predetermined plating efficiency, and predetermined copper thickness of the through-hole wall decrease.

[0057] The total area to be plated is generally calculated by adding the wall area of ​​all through holes to the total outer surface area of ​​the card. In some embodiments, the total area to be plated is calculated by adding the wall area of ​​all through holes to the total outer surface area of ​​the card. In other embodiments, the total area to be plated is calculated by using the wall area of ​​all through holes. In these cases, the number of through holes is large, and the total outer surface area of ​​the card can be ignored relative to the total wall area of ​​the holes. The "preset..." value refers to the value set in advance during or after a single copper plating process. Specifically, the preset current density is the current density value set during a single copper plating process, the preset plating efficiency is the efficiency by which the thickness of the copper layer on the hole wall increases (or the depth of the copper layer spreading inward) after a single copper plating process is completed. It is generally a relative value to the increase in the thickness of the copper layer on the outer surface (surface copper layer) of the hole (for example, if the expected increase in the surface copper layer thickness is 40um, and the preset plating efficiency is 50%, then the expected increase in the thickness of the copper layer on the hole wall is 20um), and the preset through-hole wall copper thickness is the increase in the thickness of the copper layer on the hole wall after a single copper plating process is completed.

[0058] As the total card thickness increases and the through-hole diameter ratio increases, the difficulty of copper plating increases, especially for deep micro-holes where various plating solutions are difficult to penetrate and plate with copper. Therefore, increasing the number of copper plating cycles can improve the quality and thickness of the copper layer on the hole walls. Furthermore, after each copper plating cycle, the plating solution and current can more easily penetrate deeper into the hole along the already copper-coated hole walls during the next plating cycle, facilitating deeper copper plating within the hole. To prevent excessive copper deposition on the outer surface of the total card, a setting similar to the CuSO4·5H2O concentration variation in dedicated pulse plating solutions is adopted, i.e., reducing the predetermined current density, thereby reducing the copper plating capacity during each copper plating cycle. Since the difficulty of copper plating on the hole walls increases with the total card thickness, the copper plating efficiency and the increase in copper layer thickness are expected to be smaller during copper plating, resulting in a smaller predetermined plating efficiency and a smaller predetermined through-hole wall copper thickness. By setting it up in this way, the desired copper layer thickness on the hole wall can be reasonably estimated and obtained, and the thickness of the surface copper layer can be minimized. This reduces the impact of the surface copper layer on the copper plating of the hole wall (reduces the adsorption of copper ions by the surface copper layer relative to the hole wall), reduces copper waste, reduces the workload of subsequent copper reduction processes, and lowers production costs.

[0059] In some embodiments of the present invention, during the electroplating step: when the total card thickness is ≤2mm, the predetermined number of times is once, the predetermined electroplating efficiency is 80%, the predetermined current density is a first current density, and the predetermined copper thickness of the through-hole wall is a first copper thickness; when 2mm < total card thickness ≤5mm, the predetermined number of times is twice, the predetermined electroplating efficiency is 60%, the predetermined current density is a second current density, and the predetermined copper thickness of the through-hole wall is a second copper thickness; when 5mm < total card thickness ≤10mm, the predetermined number of times is three times, the predetermined electroplating efficiency is 40%, the predetermined current density is a third current density, and the predetermined copper thickness of the through-hole wall is a third copper thickness; wherein, the first copper thickness is greater than the second copper thickness, the second copper thickness is greater than the third copper thickness; and, the first current density is greater than the second current density, the second current density is greater than the third current density.

[0060] Based on the board thickness data, the electroplating (immersion copper plating) process is divided into three fixed processes, which facilitates the formation of regulations and standards, and enables rapid processing on assembly lines. In particular, in conjunction with the previous drilling step, three dedicated production lines can be established to quickly distinguish, process, and process the board based on its thickness. Using three basically fixed sets of process parameters, no major adjustments are required, which simplifies the process, improves the difficulty of quality control, enables mass production, and can meet the processing requirements of different materials.

[0061] In some embodiments, specifically, based on the board thickness, deep microvia pulse plating is performed using the adjusted dedicated pulse plating solution and pulse parameters as described above, as follows: For total card products with a board thickness ≤ 2.0 mm (or total card products with an aperture ratio ≤ 15:1), a scheme of one copper plating pass and one pulse plating pass is adopted, with a current density designed at 15 ASF for 120 minutes, an efficiency calculated at 80%, and a hole copper thickness (predetermined through-hole wall copper thickness) of 28 μm; if the predetermined hole copper thickness is 20 μm, the current density is designed at 12 ASF; for 2.0 mm... For total card products with m < board thickness ≤ 5.0mm (or total card products with aperture ratio 15-25:1), a two-stage copper plating and pulse electroplating process is adopted, with an efficiency of 60%. The copper thickness of each hole is designed to be 15um, and the pulse electroplating parameters are 10ASF for 140 minutes. For total card products with 5.0mm < board thickness ≤ 10.0mm (or total card products with aperture ratio 25-40:1), a three-stage copper plating and pulse electroplating process is adopted, with an efficiency of 40%. The parameters are a current density of 9ASF for 160 minutes, and the copper thickness of each hole is designed to be 10um.

[0062] It is important to understand that during the electroplating process, after the copper plating, the board can be polished by a grinding machine. At the same time, the temperature of the grinding machine is increased to bake the board, cleaning the surface and the moisture in the through holes, which facilitates the subsequent plugging of the holes.

[0063] In some embodiments of the present invention: when the thickness of different master cards is within the same thickness range, drilling and electroplating steps are performed on different master cards using the same scheme; wherein, the drilling parameters are the drilling diameter, drilling depth, and number of double-sided drilling operations in the drilling step, and the electroplating parameters are the specific configuration of the pulse electroplating solution, the number of electroplating operations, the current density, the electroplating efficiency, and the predetermined copper thickness of the through-hole wall in the electroplating step; in the same scheme, the drilling parameters and electroplating parameters are the same. Referring to the above-mentioned related content, the drilling and electroplating processes of master cards of different thicknesses are divided into three fixed processes according to the board thickness data, which facilitates the formation of regulations and standards and enables rapid processing on an assembly line; three dedicated production lines are established to quickly distinguish, process, and process according to the board thickness, using three basically fixed sets of process parameters, which do not require additional major adjustments, simplifying the process, improving the difficulty of quality control, enabling mass production, and meeting the processing requirements of different materials.

[0064] In some embodiments of the present invention, in the back-drilling step, a drilling device is used to back-drill the first master card according to a first predetermined back-drilling depth value H1. A measuring device is used to measure the actual depth value h1 of the back-drilled hole. The back-drilled residual pile of the first master card is analyzed by slicing, and the residual pile difference Δh is calculated to obtain a second predetermined back-drilling depth value H2, where H2 = H1 + Δh. The predetermined depth value h2 is obtained, where h2 = h1 + Δh. The second predetermined back-drilling depth value is used to back-drill subsequent master cards. A measuring device is used to measure the actual depth value h3 of the back-drilled hole. The difference between h2 and h3 is used to determine the back-drilling reprocessing of the master card.

[0065] Drilling equipment is commonly used in PCB manufacturing and is existing technology. Its working process and principles will not be elaborated here. Specifically, it can be a drilling machine, a CCD high-precision depth control router, etc. Measuring equipment (such as a high-precision depth meter) works similarly. It is important to understand that there are generally multiple through-holes mentioned above. Therefore, in the back drilling step, each through-hole has corresponding H1, h1, Δh, H2, h2, and h3 values.

[0066] Back drilling is a technique used to remove unused copper from through-holes (vias) in electronic PCBs. For example, consider a ten-layer board (L1-L10, a composite board made of ten individual plates). After electroplating, the copper plating in the through-holes allows for electrical conductivity between layers L1 to L10 (and all layers in between). However, in actual design, only L1 to L7 need to be connected, not between L7 and L10. Therefore, back drilling is necessary. A drill bit slightly larger than the original through-hole diameter is used to re-drill the through-holes, removing the copper layer. This process is crucial to prevent over-drilling (due to equipment drilling errors, positioning errors, and plate defects). (Due to thickness errors, etc.), the drilling process typically starts from L10 and proceeds to the area between L7 and L8, completely removing the copper layer between L10 and L8. A portion of the copper layer between L8 and L7 (the part closest to L8) is also removed. The copper layer intentionally retained between L8 and L7 (the part closest to L7) is called the 'residual stud'. The smaller the designed residual stud value, the better. However, the accuracy of the actual processing equipment and the approximate sum of various processing errors must be considered. Similarly, the actual residual stud value after processing should ideally be smaller than the designed residual stud value (maximum tolerance). Of course, the drilling should not be excessively deep, so that the residual stud is completely eliminated. The copper layer between L1 and L7 is then completely retained, facilitating the connection between L1 and L7.

[0067] The first predetermined back-drilling depth value H1 is a preset value. Generally, it will refer to the thickness of the sub-plate and the specific number of layers to be drilled. For example, in the above example, assuming the thickness of the sub-plate is 1mm and the designed reserved residual pile value is 0.2mm, then drilling the two layers from L10 to L9 and from L9 to L8 requires drilling two layers of plate thickness 2mm. In addition, drilling the part between L8 and L7 and retaining the residual pile, the total amount to be drilled is 2.8mm. Therefore, the first predetermined back-drilling depth value H1 of the through hole can be set to 2.8mm (or smaller, to retain more margin and prevent over-drilling). Due to various manufacturing and processing errors, such as the drilling depth error of the drill bit descending, the positioning error of the drill bit at the initial distance from various parts of the board surface, the error of different thicknesses of the different sub-cards, the error of different thicknesses of the different parts of the sub-cards, and the error of different compression degrees of the boards during pressing, the actual depth value h1 of the back-drilled hole measured after back drilling (refer to the above example, and the same applies thereafter, assuming it is 2.75mm) is generally different from the first predetermined back-drilling depth value H1, and the actual value of the residual pile left after back drilling is generally not the same as the designed residual pile value ( Since the difference is the same as 0.2mm, the residual pile difference Δh can be calculated after slicing analysis (assuming it is 0.1mm in the example above). It should be understood that the residual pile difference Δh can be a positive or negative value. For example, if the residual pile value of a through hole is 0.3mm after slicing analysis, which is 0.1mm more than 0.2mm, the residual pile difference Δh is 0.1mm. If the residual pile value of a through hole is 0.14mm after slicing analysis, which is 0.06mm less than 0.2mm, the residual pile difference Δh is -0.06mm.After obtaining the residual pile difference value Δh from the slice, the processing error can be determined based on this value. This allows for parameter correction and comparison during subsequent back-drilling processing. Specifically, in the example above, the second predetermined back-drilling depth value H2 = H1 + Δh = 2.8mm + 0.1mm = 2.9mm. That is, during the second processing, the drilling equipment uses a set value of 2.9mm for back-drilling, resulting in a predetermined depth value h2 = h1 + Δh = 2.75mm + 0.1mm = 2.85mm. After the back-drilling processing is completed, the actual depth value h3 of the back-drilled hole can be re-checked and compared with the predetermined depth value h2 to determine the overall back-drilling reprocessing status. When the actual depth value h3 is greater than the predetermined depth value h2 (or h3 = h2), and the difference between h3 and h2 is within a predetermined range (generally the residual pile design value or a value slightly smaller than the residual pile design value), the processing error is considered acceptable. When the actual depth h3 is less than the predetermined depth h2, the difference is ΔK = h2 - h3, and the total card's "back-drilling reprocessing status" is "back-drilling reprocessing is required, and the predetermined back-drilling reprocessing depth of the drilling equipment is H2 + ΔK". For example, if the actual depth h3 is 2.9 mm, which is 0.05 mm more than the predetermined depth h2, it is within the residual pile value retention range, so the total card's "back-drilling reprocessing status" is "no further processing is required". If the actual depth h3 is 2.83 mm, the difference is ΔK = h2 - h3 = 2.85 mm - 2.83 mm = 0.02 mm, so the total card's "back-drilling reprocessing status" is "back-drilling reprocessing is required, and the predetermined back-drilling reprocessing depth of the drilling equipment is 2.92 mm".

[0068] It is important to understand that performing back-drilling with a second predetermined back-drilling depth value H2, and then checking and determining the back-drilling reprocessing status based on the predetermined depth value h2, can maximize the elimination of various errors in the back-drilling process. In other words, it can maximize the inclusion (calculation) of various errors in the back-drilling process, thereby resulting in higher precision in subsequent back-drilling processes and qualified precision of the residual pile after back-drilling reprocessing. This also conforms to Occam's razor principle of 'entity should not be multiplied unnecessarily,' that is, simply assuming that the second and subsequent processing are the same as the first processing, with the same positioning, plate thickness, and plate components. The errors caused by various factors such as unevenness and concavity are the same as those during the first processing (or the deviation is very small). However, since PCB manufacturing is indeed an assembly line process, the errors that can occur in each main board component will be largely the same. For example, due to the existence of the sub-card pattern, some parts of the sub-card are thicker and more difficult to compress during lamination, which ultimately results in some parts of the main board being thicker than other areas, causing errors during back drilling. Since the sub-card patterns of each main board are the same, this error will exist in each main board and the value will be roughly the same.

[0069] In the original process, the detection effect of residual piles after back drilling was poor, and full measurement and precise control could not be achieved, which affected the signal quality. Moreover, for unqualified products with excessively long residual piles, since the solder had been removed, they could not be re-drilled and had to be scrapped, resulting in a high scrap rate.

[0070] In the new process, back-drilling is performed using a high-precision CCD-based depth-controlled milling machine, with depth control within ±0.05mm, and some designs achieving ±0.02mm. The testing tool is a high-precision depth meter with ±0.01mm accuracy. The depth of each depth-controlled milling hole (back-drilled hole) can be monitored in real-time, achieving 100% full measurement with a single slicing confirmation. This ensures precise control of the residual length and allows for re-milling (back-drilling reprocessing) of holes with insufficient precision to meet higher product quality requirements, based on customer's extreme capability requirements. This new process controls residual length to ±0.05mm, far exceeding the conventional residual length of 0.2-0.3mm, meeting the control requirements of high-speed products with transmission rates exceeding 200G. It prevents excessively long residual lengths from affecting signal transmission and completely eliminates resonance caused by high-speed signal through-holes.

[0071] Furthermore, in some embodiments, it may be difficult to perform slicing analysis on the through holes in some areas (difficult-to-slice through holes), so it is difficult to know the residual pile difference Δh of these difficult-to-slice through holes. In this case, the residual pile difference Δh of each area can be statistically analyzed to estimate the estimated residual pile difference ΔY of these difficult-to-slice through holes. For example, a contour map of the residual pile difference Δh can be created, and the range of residual pile difference Δh in which the difficult-to-slice through hole is located can be viewed from the map. The average of the upper and lower limits of the residual pile difference in that range can be used as the estimated residual pile difference ΔY. Alternatively, the average of the residual pile difference Δh after slicing analysis of the four other through holes closest to the difficult-to-slice through hole can be used as the estimated residual pile difference ΔY of the difficult-to-slice through hole.

[0072] Furthermore, in some embodiments, through holes in certain areas may be difficult to slice for analysis (difficult-to-slice through holes). Simply put, the difference between the first predetermined back-drilling depth value H1 and the measured actual depth value h1 can be used as the residual pile difference value Δh.

[0073] In some embodiments of the present invention: In the drilling step, the through holes include normal through holes and test through holes set in the waste area of ​​the main card (the area around the main card plate, the middle of the plate without lines, and the area that can be processed and removed). There are N groups of test through holes, and each group has multiple test through holes, where N is a positive integer. In the back drilling step, the normal through holes are set with N back drilling depths. The drilling equipment is used to back drill the test through holes of the nth group according to the nth predetermined back drilling depth value until the back drilling of all N groups of test through holes is completed, where n is a positive integer not greater than N, and the nth predetermined back drilling depth value is one of the N back drilling depths. The residual pile difference value of all test through holes in the nth group is analyzed by slicing, and the average value of all residual pile differences is statistically calculated. The specific value of the nth predetermined back drilling depth value is re-determined based on the average value of the residual pile difference value. The normal through holes in the nth group are back drilled based on the re-determined nth predetermined back drilling depth value until the back drilling of all normal through holes is completed.

[0074] It's important to understand that the predetermined back-drilling depth of the test vias should ideally be the same as or only slightly different from the back-drilling depth of the surrounding normal vias. Furthermore, during PCB design, it's best to design the back-drilling depths of normal vias within a given area to be the same or only slightly different. Additionally, the positions of the test vias can be set to facilitate cross-section observation, for example, arranging test vias in a row within a region for easy observation of multiple test vias in a single cross-section. It's crucial to understand that the treatment of vias during the drilling, electroplating, and first via plugging steps involves both normal and test vias; however, in the subsequent second via plugging step, due to the presence of the plugging aluminum sheet and the possibility of cross-sectioning, only the normal vias may need to be filled with resin or solder resist ink. The waste area refers to the area that can be discarded. Specifically, during the early and middle stages of PCB manufacturing, the PCB is generally a square, rectangular, thin plate structure. However, in the final stage, to meet assembly requirements, the PCB is cut into specific shapes (such as convex, L-shaped, U-shaped, cross-shaped, or mountain-shaped plates), retaining its functional areas while removing other areas. These areas that can be removed are the waste areas. 'N types of back-drilling depths', referring to the above, are the aforementioned 'first predetermined back-drilling depth value H1'. For example, the back-drilling depth required to connect L1 to L7 (first predetermined back-drilling depth value H1) is one type of back-drilling depth; the back-drilling depth required to connect L1 to L6 is also one type of back-drilling depth; the back-drilling depth required to connect L10 to L7 is also one type of back-drilling depth; and the back-drilling depth required to connect L10 to L5 is also one type of back-drilling depth. 'The specific value of the nth predetermined back drilling depth is re-determined based on the average value of the residual pile difference, and the re-determined nth predetermined back drilling depth value is used as the basis for further determination.' Referring to the above content, the 'average value of the residual pile difference' is the aforementioned 'residual pile difference Δh', and the 'specific value of the nth predetermined back drilling depth' and the 're-determined nth predetermined back drilling depth' are the 'second predetermined back drilling depth value H2, H2=H1+Δh'.

[0075] As described above, this embodiment avoids complete destruction of the main card during slicing analysis by setting test vias in the waste area. Even after slicing, the main card's functional areas remain intact, allowing for further processing and ultimately producing a qualified PCB board, thus preventing waste. This allows for an unlimited increase in the proportion of main cards suitable for slicing analysis. For example, for high-precision PCB products, slicing analysis can be performed on a predetermined number of cards, or even on each card, significantly improving the quality of each main card (and the resulting PCB board). It's important to understand that slicing analysis can utilize specialized equipment and programs, followed by CCD high-precision camera imaging. Computer-generated image information is then automatically detected. Even during large-scale production of the same PCB board, a vast amount of image information can be collected and processed using AI, further enhancing the accuracy of automatic detection. The presence of multiple test vias in each group minimizes the impact of uneven board thickness.

[0076] Specifically, a trial drilling can be performed on the first piece of each PNL (standard size substrate) with nine 20*20mm back-drilled holes, three on each side and one in the middle. A depth-controlled back-drilling calibration hole is designed for each area. During drilling, the calibration holes are drilled first, and then drilling is performed based on the inspection and correction results to improve back-drilling accuracy. Through the above back-drilling processing and inspection, the accuracy of the back-drilled residual stud length is improved from 0.25mm to 0.05mm, which can meet the signal transmission loss requirements of high-speed AI computing servers with speeds exceeding 100G.

[0077] Furthermore, for the same type of board, the step-by-step drilling, drilling of the center hole, drilling of through holes, and back drilling are all designed to be done on the same machine to ensure the consistency of drilling displacement accuracy. Among them, the diameter of the back drilling hole can be increased from the conventional design of 0.3mm larger than the through hole to 0.1mm.

[0078] In some embodiments of the present invention, after the electroplating step and before the first hole plugging step, at least one test via is subjected to cross-sectional analysis to confirm whether the copper layer thickness on the wall of the test via is qualified.

[0079] Because of the test vias, after the electroplating step, one, several (one or more per batch), or all master cards can be cross-sectionally analyzed. Without compromising the functionality of the master card, this allows us to determine if the copper layer thickness on the test via walls is acceptable, thus roughly determining if the copper layer thickness on the walls of the normal vias on the master card is acceptable. If the copper layer thickness on the test via walls is unacceptable, the overall copper plating result of the master card is deemed unacceptable; conversely, if the copper layer thickness is acceptable, the overall copper plating result is deemed acceptable, and the first via plugging step can proceed. This copper thickness cross-sectional inspection step allows test vias to serve multiple purposes, ultimately improving the PCB's forming quality. At least one test via is required from all test vias (without needing to distinguish which group); the acceptance of copper layer thickness is generally determined based on the copper thickness of the via walls set during PCB design.

[0080] Furthermore, cross-sectional analysis can be performed on the test vias in each area (e.g., one test via is selected on each of the four sides of the main card) to facilitate a comprehensive assessment of the copper layer thickness of the normal vias in each area of ​​the main card.

[0081] In some embodiments of the present invention, in the second via plugging step, a selective resin via plugging machine is used to fill the back-drilled surface with resin. For surfaces without solder pads, solder resist ink can be used for via plugging. The resin-filled products can be inspected using an AVI via plugging inspection machine. AVI inspection: AVI optical inspection is performed on products with silver paste, copper paste, and resin via plugging.

[0082] It should be understood that in the description of this invention, A±B (unit of measurement) and AB (unit of measurement), A and B have the same unit of measurement and include the stated number; specifically, for example, 0.2-0.3mm means 0.2mm-0.3mm, and includes both 0.2mm and 0.3mm. Other similar descriptions in this invention are analogous. It should also be understood that, in practice, the data settings in this invention generally have an allowable error range of ±10%, unless otherwise specified. For example, the aforementioned 0.2mm can actually have an error of ±10%, that is, it can be 0.18mm or 0.22mm. Since it is the starting point of the range, it can actually be 0.18mm.

[0083] The overall card processing method of this invention employs a special drill bit and drilling design to ensure drilling quality. The electroplating solution is adjusted to use a multi-pulse electroplating method to ensure uniform copper plating at the hole opening and inside the hole. Simultaneously, the tin plating process is eliminated, and thermally conductive resin is used to plug the holes after electroplating instead of tin plating. This allows the highly conductive holes to be protected with thermally conductive resin first, preventing copper curling in the center of deep micro-holes during back drilling and the inability of wet board powder to drain and cause blockages. It also prevents problems such as etching and desoldering holes not being conductive under tin protection. By filling the deep micro-holes with thermally conductive resin and grinding them smooth, controlled-depth milling can be used for production, preventing copper curling. After micro-etching and cleaning the resin holes, only conventional resin or solder resist ink needs to be used to plug the back-drilled holes to obtain a hole-free, flat product. Multiple testing methods are used to detect the quality of electroplating copper plating and back drilling, improving the overall product quality.

[0084] In this invention, in addition to designing specialized tools, processing methods, and testing methods, the original master card processing flow is simplified. The original master card processing flow was: laser drilling, plasma desmearing, electroplating, pattern tinning (tin plating), back drilling, alkaline etching, and resin plugging. The newly developed master card processing flow of this invention is: step-by-step drilling, plasma desmearing, pulse electroplating, thermally conductive resin plugging, controlled depth milling, micro-etching, and back-drilled hole plugging. This simplifies the process, improves quality control, enables mass production, and meets the processing requirements of different materials.

[0085] The embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A manufacturing process for an AI computing server PCB motherboard, characterized in that, The process includes the following steps: a pressing step, in which multiple individual cards are pressed into a single card, the thickness of which is L; a drilling step, in which through holes are drilled in the single card, the diameter of which is D, where L and D have the same unit, the hole diameter ratio is L / D, and L / D is not less than 10:1; an electroplating step, in which copper is plated onto the walls of the through holes; a first plugging step, in which thermally conductive resin is filled into the through holes; a back drilling step, in which back drilling processing parameters are detected and adjusted, and the through holes are back drilled; and a micro-etching step, in which the single card is washed with water using a micro-etching solution. The second hole-plugging step involves filling the through-hole with resin or solder resist ink.

2. The AI ​​computing server PCB motherboard manufacturing process according to claim 1, characterized in that, In the drilling step, multiple drilling operations are performed at the through-hole forming position, with the drilling diameter and / or drilling depth of the later drilling operation being larger than that of the previous drilling operation, and the through hole is formed at the through-hole forming position after the last drilling operation.

3. The AI ​​computing server PCB motherboard manufacturing process according to claim 2, characterized in that, When performing multiple drilling operations, from the first drilling operation to the Zth drilling operation, double-sided drilling is performed, where Z is a positive integer.

4. The AI ​​computing server PCB motherboard manufacturing process according to claim 1, characterized in that, In the electroplating step, pulse electroplating is used, employing a pulse electroplating solution.

5. The AI ​​computing server PCB motherboard manufacturing process according to claim 4, characterized in that, In the electroplating step, the copper plating is performed a predetermined number of times. Each time the copper plating is performed, the plating time is calculated based on the total area to be plated, the predetermined current density, the predetermined plating efficiency, and the predetermined copper thickness of the through-hole wall. As the total thickness increases, the predetermined number of times increases, and the predetermined current density, the predetermined plating efficiency, and the predetermined copper thickness of the through-hole wall decrease.

6. The manufacturing process of the AI ​​computing server PCB motherboard according to any one of claims 1 to 5, characterized in that: When the thickness of different total cards is within the same thickness range, the drilling and electroplating steps are performed on the different total cards using the same scheme; wherein, the drilling diameter, drilling depth, and number of double-sided drilling operations in the drilling step are drilling parameters, and the specific configuration of the pulse electroplating solution, the number of electroplating operations, the current density, the electroplating efficiency, and the predetermined copper thickness of the through-hole wall in the electroplating step are electroplating parameters; in the same scheme, the drilling parameters and the electroplating parameters are the same.

7. The manufacturing process of the AI ​​computing server PCB motherboard according to claim 1 or 5, characterized in that, In the electroplating step, pulse electroplating is used. Each time the copper plating is performed, the parameters of the pulse waveform are: M segments of DC positive and negative pulse waveforms, the positive and negative current ratio increases sequentially, the positive and negative time ratio decreases sequentially, and M is a positive integer greater than 2.

8. The manufacturing process of the AI ​​computing server PCB motherboard according to claim 1, characterized in that, In the back-drilling step, a drilling device is used to back-drill the first total card according to a first predetermined back-drilling depth value H1. A measuring device is used to measure the actual depth value h1 of the back-drilled hole. The back-drilled residual pile of the first total card is analyzed by slicing, and the residual pile difference Δh is calculated to obtain a second predetermined back-drilling depth value H2, where H2 = H1 + Δh. The predetermined depth value h2 is obtained, where h2 = h1 + Δh. The second predetermined back-drilling depth value is used to back-drill the subsequent total cards. A measuring device is used to measure the actual depth value h3 of the back-drilled hole. The difference between h2 and h3 is used to determine the back-drilling reprocessing of the total card.

9. The manufacturing process of the AI ​​computing server PCB motherboard according to claim 1, characterized in that: In the drilling step, the through holes include normal through holes and test through holes located in the waste area of ​​the total card. There are N groups of test through holes, each group containing multiple test through holes, where N is a positive integer. In the back-drilling step, the normal through holes are configured with N back-drilling depths. Drilling equipment is used to back-drill the test through holes in the nth group according to the nth predetermined back-drilling depth value until all N groups of test through holes have been back-drilled, where n is a positive integer not greater than N, and the nth predetermined back-drilling depth value is one of the N back-drilling depths. The residual pile difference of all test through holes in the nth group is analyzed by slicing, and the average value of all residual pile differences is calculated. The specific value of the nth predetermined back-drilling depth value is re-determined based on the average residual pile difference value. The re-determined nth predetermined back-drilling depth value is then used to back-drill the normal through holes in the nth group until all normal through holes have been back-drilled.

10. The AI ​​computing server PCB motherboard manufacturing process according to claim 9, characterized in that, After the electroplating step and before the first hole plugging step, at least one of the test vias is cross-sectionally analyzed to confirm whether the copper layer thickness on the wall of the test via is qualified.