Semiconductor device

Abstract

This semiconductor device comprises: a chip having a main surface; a pn joint that extends in the horizontal direction along the main surface inside the chip; a trench insulation structure that is formed on the main surface so as to penetrate the pn joint, and that defines a diode region on the chip; a barrier formation region formed on a surface layer section of the main surface in the diode area; and a metal layer that is positioned above the main surface so as to cover the barrier formation region in the diode region, and that forms a Schottky joint with the barrier formation region.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Patent Application No. 2022-055515 filed with the Japan Patent Office on March 30, 2022, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device including a p-type region, a first p-epitaxial region, an n-type buried region, a second p-epitaxial region, and a deep trench isolation (DTI) structure. The first p-type epitaxial layer is formed on the p-type region. The n-type buried region is formed on the first p-epitaxial region. The second p-epitaxial region is formed on the n-type buried region. The DTI structure surrounds a region where a high-voltage lateral MOS transistor is formed in a plan view. The DTI structure penetrates the second p-epitaxial region, the n-type buried region, and the first p-epitaxial region to reach the p-type region.

[0004] JP 2015-122543 A

[0005] One embodiment of the present disclosure provides a semiconductor device having a novel layout in a region where a Schottky junction is formed.

[0006] A semiconductor device according to one embodiment of the present disclosure includes a chip having a main surface, a pn junction extending horizontally along the main surface inside the chip, a trench isolation structure formed in the main surface so as to penetrate the pn junction and define a diode region in the chip, a barrier formation region formed in a surface layer portion of the main surface in the diode region, and a metal layer disposed on the main surface so as to cover the barrier formation region in the diode region and forming a Schottky junction with the barrier formation region.

[0007] FIG. 1 is a schematic perspective view of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is an enlarged plan view of a diode region in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4A is a diagram illustrating a portion of a manufacturing process for the Schottky barrier diode of FIG. 3. FIG. 4B is a diagram illustrating a next step in the manufacturing process of FIG. 4A. FIG. 4C is a diagram illustrating a next step in the manufacturing process of FIG. 4B. FIG. 4D is a diagram illustrating a next step in the manufacturing process of FIG. 4C. FIG. 4E is a diagram illustrating a next step in the manufacturing process of FIG. 4D. FIG. 4F is a diagram illustrating a next step in the manufacturing process of FIG. 4E. FIG. 4G is a diagram illustrating a next step in the manufacturing process of FIG. 4F. FIG. 4H is a diagram illustrating a next step in the manufacturing process of FIG. 4G. FIG. 4I is a diagram illustrating a next step in the manufacturing process of FIG. 4H. FIG. 4J is a diagram illustrating a next step in the manufacturing process of FIG. 4I. FIG. 4K is a diagram illustrating a next step in the manufacturing process of FIG. 4J. FIG. 4L is a diagram illustrating a next step in the manufacturing process of FIG. 4K.

[0008] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0009] FIG. 1 is a schematic perspective view of a semiconductor device 1 according to an embodiment of the present disclosure.

[0010] In this embodiment, the semiconductor device 1 is a so-called SOP (Small Outline Package). The semiconductor device 1 includes a sealing resin 2, a die pad 3, a semiconductor chip 4, a conductive bonding material 5, a plurality of lead terminals 6, and a plurality of conductive wires 7.

[0011] The sealing resin 2 may contain, for example, an epoxy resin. The sealing resin 2 may also be referred to as a resin package. The sealing resin 2 is formed in a rectangular parallelepiped shape. The sealing resin 2 includes a first main surface 8 on one side, a second main surface 9 on the other side, and four side surfaces 10A, 10B, 10C, and 10D connecting the first main surface 8 and the second main surface 9. The four side surfaces 10A to 10D specifically include a first side surface 10A, a second side surface 10B, a third side surface 10C, and a fourth side surface 10D. The first side surface 10A and the second side surface 10B face each other. The third side surface 10C and the fourth side surface 10D face each other.

[0012] The die pad 3 is disposed within the sealing resin 2. The die pad 3 may be exposed from the second main surface 9. The die pad 3 includes a metal plate formed in a rectangular parallelepiped shape. The die pad 3 may include at least one of Fe, Au, Ag, Cu, and Al. The die pad 3 may have an outer surface on which at least one of a Ni plating layer, an Au plating layer, an Ag plating layer, and a Cu plating layer is formed.

[0013] The plurality of lead terminals 6 include a first lead terminal 6A, a second lead terminal 6B, a third lead terminal 6C, a fourth lead terminal 6D, a fifth lead terminal 6E, a sixth lead terminal 6F, a seventh lead terminal 6G, and an eighth lead terminal 6H. The number of lead terminals 6 is adjusted depending on the function of the semiconductor chip 4 and is not limited to the number shown in FIG.

[0014] The four lead terminals 6A to 6D are arranged on the first side surface 10A side of the sealing resin 2. The four lead terminals 6A to 6D are arranged at intervals from the die pad 3. The four lead terminals 6A to 6D are arranged at intervals in the direction in which the first side surface 10A extends. The four lead terminals 6A to 6D are drawn from within the sealing resin 2 across the first side surface 10A to the outside of the sealing resin 2.

[0015] The four lead terminals 6E to 6H are arranged on the second side surface 10B side of the sealing resin 2. The four lead terminals 6E to 6H are arranged at intervals from the die pad 3. The four lead terminals 6E to 6H are arranged at intervals in the direction in which the second side surface 10B extends. The four lead terminals 6E to 6H are drawn from within the sealing resin 2 across the second side surface 10B to the outside of the sealing resin 2.

[0016] The lead terminals 6 may contain at least one of Fe, Au, Ag, Cu, and Al. The lead terminals 6 may have outer surfaces on which at least one of a Ni plating layer, an Au plating layer, an Ag plating layer, and a Cu plating layer is formed.

[0017] The semiconductor chip 4 includes, for example, an LSI (Large Scale Integration) chip. The semiconductor chip 4 is disposed on a die pad 3. The semiconductor chip 4 has a first main surface 11 on one side and a second main surface 12 on the other side. A plurality of element regions 13, in which elements constituting an LSI circuit are formed, are formed on the first main surface 11 of the semiconductor chip 4. The plurality of element regions 13 may include, for example, a diode region 13A, a transistor region 13B, a resistor region 13C, and the like. A plurality of pads 14 are formed on the first main surface 11 of the semiconductor chip 4. The plurality of pads 14 are arranged on the first main surface 11 of the semiconductor chip 4 on the side of the four lead terminals 6A to 6D and the four lead terminals 6E to 6H. The plurality of pads 14 are electrically connected to various functional elements (circuit elements constituting the LSI) formed in the element regions 13.

[0018] The conductive bonding material 5 is interposed between the semiconductor chip 4 and the die pad 3 and bonds the semiconductor chip 4 to the die pad 3. The conductive bonding material 5 includes solder or a conductive paste. The solder may be lead-free solder. The solder may include at least one of SnAgCu, SnZnBi, SnCu, SnCuNi, and SnSbNi. The metal paste may include at least one of Au, Ag, and Cu. The conductive bonding material 5 is preferably made of silver paste. It is particularly preferable that the silver paste includes sintered silver paste. The sintered silver paste may include a paste in which nano-sized or micro-sized Ag particles are dispersed in an organic solvent.

[0019] The number of the conductive wires 7 is adjusted depending on the function of the semiconductor chip 4 and is not limited to the number shown in FIG. 1 . The conductive wires 7 electrically connect the lead terminals 6 and the pads 14. In this embodiment, the conductive wires 7 include aluminum wires as an example of bonding wires. Instead of aluminum wires, the conductive wires 7 may be gold wires or copper wires.

[0020] The semiconductor device 1 may have a package form other than SOP. For example, the semiconductor device 1 may have a variety of package forms such as a TO (Transistor Outline), a QFN (Quad For Non-Lead Package), a DFP (Dual Flat Package), a DIP (Dual Inline Package), a QFP (Quad Flat Package), a SIP (Single Inline Package), or an SOJ (Small Outline J-leaded Package), or similar.

[0021] Fig. 2 is an enlarged plan view of the diode region 13A of Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III shown in Fig. 2. For clarity, the shallow trench isolation structure 29 is shown hatched in Fig. 2.

[0022] In this embodiment, the diode region 13A is a region where a Schottky barrier diode 100 is formed. The Schottky barrier diode 100 may be controlled by, for example, a switching element (e.g., a MOSFET) formed in the transistor region 13B.

[0023] The semiconductor chip 4 includes a p-type first layer 15, a p-type or n-type second layer 16, and an n-type third layer 17. The first layer 15 may be referred to as a "base layer." The second layer 16 may be referred to as a "device-forming layer." The third layer 17 may be referred to as a "buried layer." The first layer 15, the second layer 16, and the third layer 17 may be considered components of the semiconductor chip 4.

[0024] The first layer 15 is formed in a region on the second main surface 12 side within the semiconductor chip 4 and forms the second main surface 12. The first layer 15 may have a concentration gradient in which the p-type impurity concentration on the first main surface 11 side is lower than the p-type impurity concentration on the second main surface 12 side. Specifically, the first layer 15 may have a stacked structure including a high-concentration layer and a low-concentration layer stacked in this order from the second main surface 12 side. The first layer 15 may have a thickness of, for example, 100 μm or more and 600 μm or less. In this embodiment, the first layer 15 may be made of a p-type semiconductor substrate (Si substrate).

[0025] The second layer 16 is formed in a region on the first main surface 11 side within the semiconductor chip 4, forming the first main surface 11. The conductivity type (n-type or p-type) of the second layer 16 is arbitrary and is selected according to the specifications of the semiconductor device 1. In this embodiment, an example in which the second layer 16 has n-type conductivity will be described, but the conductivity type of the second layer 16 is not intended to be limited to n-type. The second layer 16 may have a uniform n-type impurity concentration in the thickness direction, or may have an n-type impurity concentration gradient that increases toward the first main surface 11. In this embodiment, the second layer 16 may be made of an n-type epitaxial layer (Si epitaxial layer).

[0026] The third layer 17 is interposed in the region between the first layer 15 and the second layer 16 within the semiconductor chip 4. The third layer 17 forms a pn junction J1 at the boundary with the first layer 15. That is, within the semiconductor chip 4, a pn junction J1 (a pn-junction portion) is formed in the middle of the thickness direction between the first main surface 11 and the second main surface 12, extending horizontally along the first main surface 11 (orthogonal to the thickness direction). The pn junction J1 may also be referred to as a "pn-connection portion" or a "pn-boundary portion."

[0027] The third layer 17 has a higher n-type impurity concentration than the second layer 16. Specifically, the third layer 17 may have a concentration gradient in which the n-type impurity concentration on the first main surface 11 side is higher than the n-type impurity concentration on the second main surface 12 side. The third layer 17 may have a thickness of, for example, 0.1 μm or more and 10 μm or less. In this embodiment, the third layer 17 may be made of an n-type epitaxial layer (Si epitaxial layer).

[0028] The semiconductor device 1 includes a trench insulation structure 18 that defines the diode region 13A on the first main surface 11. The trench insulation structure 18 defines the diode region 13A having a predetermined shape in a plan view. The trench insulation structure 18 electrically isolates the diode region 13A from the other element regions 13. Therefore, the trench insulation structure 18 may also be referred to as an "element isolation structure."

[0029] Referring to FIG. 2 , the trench insulation structure 18 is formed in a band shape extending along the diode region 13A in plan view. In this embodiment, the trench insulation structure 18 is formed in a ring shape (a square ring shape in this embodiment) in plan view, and defines a diode region 13A of a predetermined shape (a square shape in this embodiment). In this embodiment, the four corners of the trench insulation structure 18 have rounded shapes that curve in a direction away from the diode region 13A in plan view. The planar shape of the trench insulation structure 18 (the planar shape of the diode region 13A) is arbitrary. The trench insulation structure 18 may be formed in a polygonal ring shape, a circular ring shape, or an elliptical ring shape in plan view, and define a diode region 13A that is polygonal, circular, or elliptical in plan view.

[0030] 2, trench insulation structure 18 has a trench width W1. Trench width W1 is the width in a direction perpendicular to the direction in which trench insulation structure 18 extends in a plan view. Trench width W1 may be 0.5 μm or more and 10 μm or less.

[0031] 3 , trench insulation structure 18 is formed in first main surface 11 to penetrate pn junction J1, and defines diode region 13A in first main surface 11. Specifically, trench insulation structure 18 penetrates second layer 16 and third layer 17 to reach first layer 15, and defines diode region 13A in second layer 16. In this embodiment, trench insulation structure 18 extends from first main surface 11 toward second main surface 12 to reach first layer 15, and penetrates second layer 16 and third layer 17.

[0032] The trench insulation structure 18 includes an inner wall on the diode region 13A side, an outer wall on the opposite side of the inner wall (the peripheral side of the semiconductor chip 4), and a bottom wall connecting the inner and outer walls. The trench insulation structure 18 is electrically connected to the semiconductor chip 4 at the bottom wall and electrically insulated from the semiconductor chip 4 at the side walls (inner and outer walls). That is, the trench insulation structure 18 has a lower end electrically connected to the semiconductor chip 4. Specifically, the trench insulation structure 18 is electrically connected to the first layer 15 and electrically insulated from the second layer 16 and the third layer 17. That is, the trench insulation structure 18 is fixed at the same potential as the first layer 15.

[0033] The trench isolation structure 18 includes an isolation trench 19 , an isolation insulating film 20 , and an isolation electrode 21 .

[0034] Referring to FIG. 2 , the element isolation trench 19 is formed in a ring shape in a plan view. The width of the element isolation trench 19 may be the trench width W1 described above. Referring to FIG. 3 , the element isolation trench 19 is formed on the first main surface 11 side of the semiconductor chip 4 so as to penetrate the pn junction J1. Specifically, the element isolation trench 19 penetrates the second layer 16 and the third layer 17 so as to reach the first layer 15. The element isolation trench 19 includes an inner wall 22 on the diode region 13A side, an outer wall 23 on the opposite side of the inner wall 22 (the peripheral edge side of the semiconductor chip 4), and a bottom wall 24 connecting the inner wall 22 and the outer wall 23. The inner wall 22 and the outer wall 23 may be referred to as the "inner wall" and the "outer wall," or as the "first side wall" and the "second side wall," respectively.

[0035] The element isolation insulating film 20 covers the inner wall 22 and the outer wall 23 of the element isolation trench 19 so as to expose the semiconductor chip 4 from the bottom wall 24 of the element isolation trench 19. Specifically, the element isolation insulating film 20 exposes the first layer 15 from the bottom wall 24 of the element isolation trench 19. The element isolation insulating film 20 preferably covers the entire inner wall 22 and the entire outer wall 23 of the element isolation trench 19. The region where the bottom wall 24 of the element isolation trench 19 is exposed may be a contact hole 25 in the element isolation insulating film 20. The element isolation insulating film 20 may include a silicon oxide film. The element isolation insulating film 20 preferably includes a silicon oxide film made of an oxide of the semiconductor chip 4.

[0036] The element isolation electrode 21 is embedded in the element isolation trench 19 with the element isolation insulating film 20 sandwiched therebetween and is electrically connected to the semiconductor chip 4 at the bottom wall 24 of the element isolation trench 19. Specifically, the element isolation electrode 21 is electrically connected to the first layer 15 via a contact hole 25 and is electrically insulated from the second layer 16 and the third layer 17 by the element isolation insulating film 20. The element isolation electrode 21 preferably contains conductive polysilicon. The element isolation electrode 21 preferably contains conductive polysilicon of the same conductivity type (p-type in this embodiment) as the first layer 15. The p-type impurity of the element isolation electrode 21 is preferably boron. Wiring (not shown) may be connected to the element isolation electrode 21. This allows the potential of the element isolation electrode 21 to be controlled via the wiring.

[0037] The semiconductor device 1 further includes a sinker layer 26 formed in the second layer 16. The sinker layer 26 extends across the pn junction J1 in the depth direction of the element isolation trench 19, and is in contact with the first layer 15 and the element isolation insulating film 20. More specifically, the sinker layer 26 is formed in an annular shape along the inner wall 22 and the outer wall 23 of the element isolation trench 19, and is in contact with the element isolation insulating film 20 over the entire depth direction of the element isolation trench 19, as shown in FIG. 3 . The sinker layer 26 may have a thickness of 0.5 μm to 5 μm in a direction perpendicular to the depth direction of the element isolation trench 19.

[0038] A cathode region 27 is formed at an end of the sinker layer 26 on the first main surface 11 side along the inner circumferential wall 22. The cathode region 27 is exposed from the first main surface 11. The cathode region 27 is formed in an annular shape along the element isolation trench 19 as shown in FIG. 2. Referring to FIG. 3, the cathode region 27 may cross a boundary 28 between the sinker layer 26 and the second layer 16 that are adjacent in the horizontal direction along the first main surface 11. As a result, the cathode region 27 may straddle the sinker layer 26 and the second layer 16 and be connected to both the sinker layer 26 and the second layer 16.

[0039] The sinker layer 26 has the same conductivity type as the third layer 17, which is n-type in this embodiment. The cathode region 27 also has the same conductivity type as the third layer 17 and the sinker layer 26, which is n-type in this embodiment. ＋ The impurity concentration of the cathode region 27 may be higher than that of the sinker layer 26.

[0040] A shallow trench isolation structure 29 is formed in the surface layer of the semiconductor chip 4. In this embodiment, the shallow trench isolation structure 29 includes a trench 30 formed in the second layer 16 and a buried insulator 31 buried in the trench 30.

[0041] The trench 30 has a side surface 32 and a bottom surface 33. The side surface 32 of the trench 30 may be a surface perpendicular to the first main surface 11, or may be a surface inclined with respect to the first main surface 11 as shown in Fig. 3. In a cross-sectional view, the trench 30 may have a tapered shape whose width narrows from the first main surface 11 toward the bottom surface 33 in the third direction Z.

[0042] The buried insulator 31 is, for example, silicon oxide (SiO ２ ), silicon nitride (SiN), or the like. In this embodiment, the buried insulator 31 is made of silicon oxide. The shallow trench isolation structure 29 may be generally called STI (Shallow Trench Isolation).

[0043] In this embodiment, the shallow trench isolation structure 29 may include a plurality of shallow trench isolation structures 29. The plurality of shallow trench isolation structures 29 may include a first shallow trench isolation structure 34 and a second shallow trench isolation structure 35 that are physically separated from each other. A barrier formation region 36 is defined in an inner region of the first shallow trench isolation structure 34, and a cathode region 27 is defined between the first shallow trench isolation structure 34 and the second shallow trench isolation structure 35.

[0044] In this embodiment, the first shallow trench isolation structure 34 is formed in a ring shape in plan view, with a first opening 37 (inner opening) in the center that exposes the barrier formation region 36. The first shallow trench isolation structure 34 is formed in an elongated ring shape in plan view, and the first opening 37 in the center is also formed in a similarly elongated, approximately rectangular shape. The barrier formation region 36 may be a portion of the semiconductor chip 4 (second layer 16) exposed from the first opening 37 defined by the inner peripheral edge of the first shallow trench isolation structure 34. The barrier formation region 36 may include a portion having the same n-type impurity concentration as the second layer 16.

[0045] A silicide layer 38 is formed in the barrier formation region 36. The silicide layer 38 is formed on the outermost surface of the silicide layer 38 on the first main surface 11 side of the semiconductor chip 4. In this embodiment, the silicide layer 38 is exposed over the entire area of ​​the first opening 37. The silicide layer 38 is, for example, a TiSi layer, TiSi ２ layer, NiSi layer, CoSi layer, CoSi ２ layer, MoSi ２ layer and WSi ２ In this embodiment, the silicide layer 38 comprises at least one of the following layers: CoSi ２ It consists of layers.

[0046] 2 , the second shallow trench isolation structure 35 is formed at a distance outward from the annular first shallow trench isolation structure 34 and surrounds the first shallow trench isolation structure 34 in plan view. The second shallow trench isolation structure 35 is formed at a constant width apart from the first shallow trench isolation structure 34. As a result, a second opening 39 (outer opening) having a constant width in the circumferential direction and an elongated, approximately square annular shape is formed between the first shallow trench isolation structure 34 and the second shallow trench isolation structure 35.

[0047] The cathode region 27 is exposed from a second opening 39 defined by the outer circumferential edge of the first shallow trench isolation structure 34 and the inner circumferential edge of the second shallow trench isolation structure 35. The cathode region 27 does not have to be formed over the entire circumferential area of ​​the second opening 39. In other words, a plurality of cathode regions 27 may be arranged at intervals along the circumferential direction of the second opening 39.

[0048] Furthermore, the second shallow trench isolation structure 35 straddles both sides of the diode region 13A and the element region 13 outside the diode region 13A with respect to the trench isolation structure 18. That is, in plan view, the second shallow trench isolation structure 35 overlaps both the diode region 13A and the other element regions 13.

[0049] A first conductive layer 40 and a second conductive layer 41 are formed on the first main surface 11 of the semiconductor chip 4. The first conductive layer 40 may be rephrased as the anode conductive layer of the Schottky barrier diode 100, and the second conductive layer 41 may be rephrased as the cathode conductive layer of the Schottky barrier diode 100.

[0050] As shown in FIG. 2 , the first conductive layer 40 has an elongated, generally rectangular shape in plan view that follows the shape of the first opening 37. Referring to FIGS. 2 and 3 , the first conductive layer 40 covers the entire first opening 37 and is in contact with the barrier formation region 36. The first conductive layer 40 also has a lead-out portion 42 that is led out from above the barrier formation region 36 to above the first shallow trench isolation structure 34. The lead-out portion 42 is formed in an annular shape over the entire circumferential direction of the first opening 37. The first opening 37 is surrounded by the lead-out portion 42.

[0051] The first conductive layer 40 includes a first layer 43 and a second layer 44 stacked in this order from the first main surface 11. The first layer 43 is in direct contact with the barrier-forming region 36 (silicide layer 38), and forms a Schottky junction SJ between the first layer 43 and the barrier-forming region 36. The metal material constituting the first layer 43 is not particularly limited as long as it is a material capable of forming a Schottky junction with the n-type second layer 16, and examples thereof include titanium (Ti), nickel (Ni), cobalt (Co), molybdenum (Mo), and tungsten (W). In this embodiment, the first layer 43 is a Co layer. As a result, CoSi ２ A silicide layer 38 made of the above can be formed.

[0052] The second layer 44 is stacked directly on the first layer 43 and supplies a voltage to the first layer 43. The metal material constituting the second layer 44 may be, for example, aluminum (Al), but a polycrystalline material such as polysilicon may also be used. The thickness of the second layer 44 may be greater than that of the first layer 43, for example.

[0053] As shown in Fig. 2, the second conductive layer 41 has a rectangular ring shape in plan view that follows the shape of the second opening 39. Referring to Fig. 3, the second conductive layer 41 may have a single-layer structure. The second conductive layer 41 is in direct contact with the cathode region 27 and forms an ohmic contact with the cathode region 27. The metal material that forms the second conductive layer 41 may be, for example, aluminum (Al), but a polycrystalline material such as polysilicon may also be used.

[0054] A guard region 45 is further formed in the surface layer on the first main surface 11 side of the semiconductor chip 4. In this embodiment, the guard region 45 may be a p-type diffusion region selectively diffused into the n-type second layer 16. The guard region 45 forms a pn junction J2 with the second layer 16. The p-type impurity concentration of the guard region 45 is preferably higher than the p-type impurity concentration of the first layer 15. For example, the p-type impurity concentration of the guard region 45 is 1×10 １６ cm －３ 1x10 or more １７ cm －３ In FIG. 3, in order to visually distinguish the difference in density between the guard region 45 and the first layer 15, the guard region 45 is indicated as "p-type" and the first layer 15 is indicated as "p － It is shown as "p type". － The terms "p-type" and "p-type" do not refer to conductivity types having a specific range of impurity concentration, but are merely used for convenience to indicate that there is a concentration difference between the guard region 45 and the first layer 15.

[0055] The guard region 45 is connected to the first conductive layer 40 in the barrier formation region 36, and extends from the first main surface 11 toward the second main surface 12 in the thickness direction of the semiconductor chip 4. The guard region 45 is directly connected to the first conductive layer 40, and therefore may be referred to as a p-type connection region.

[0056] 2 , the guard region 45 is formed in a ring shape along the periphery of the first opening 37 in a plan view. In this embodiment, the guard region 45 straddles both the inside and outside of the first opening 37 relative to the inner periphery of the first shallow trench isolation structure 34. As a result, a portion of the guard region 45 overlaps the first shallow trench isolation structure 34 in a plan view. More specifically, the guard region 45 may integrally include an inner periphery 46 exposed inside the first opening 37 and an outer periphery 47 formed outside the inner periphery 46 and overlapping the first shallow trench isolation structure 34. The inner periphery 46 may be formed in a closed ring shape in a plan view, having a constant width and exposed from the first opening 37 around the entire inner periphery of the first opening 37. Similarly, the outer periphery 47 may be formed in a closed ring shape in a plan view, having a constant width and covered by the first shallow trench isolation structure 34 around the entire inner periphery of the first opening 37. Comparing the widths of the inner periphery 46 and the outer periphery 47, the width W2 of the inner periphery 46 may be narrower than the width W3 of the outer periphery 47. Furthermore, the width W2 of the inner periphery 46 may be narrower than the width W4 (width in the first direction X) of the portion of the second layer 16 (anode region 48) that is surrounded by the inner periphery 46 and exposed from the barrier formation region 36. This allows the area occupied by the guard region 45 (inner periphery 46) in the barrier formation region 36 to be smaller than that of the anode region 48, thereby ensuring a wide flow path width for the forward current of the Schottky barrier diode 100.

[0057] 3 , the cross-sectional structure of the guard region 45 will be described. The guard region 45 is connected to the first conductive layer 40 in the barrier formation region 36 and has a curved shape that wraps around from the side surface 32 to the bottom surface 33 of the first shallow trench isolation structure 34 in a cross-sectional view. The guard region 45 may also have a shape that bulges out from the side surface 32 and the bottom surface 33 of the first shallow trench isolation structure 34 in a direction intersecting the thickness direction of the semiconductor chip 4 and in the thickness direction of the semiconductor chip 4, respectively. As a result, the guard region 45 has a protrusion 49 that protrudes toward the second main surface 12 beyond the cathode region 27 and the first shallow trench isolation structure 34.

[0058] The guard region 45 is in direct contact with the side surface 32 and bottom surface 33 of the first shallow trench isolation structure 34. The guard region 45 may be formed in a layered manner such that both its inner surface 50, which is in contact with the side surface 32 and bottom surface 33 of the first shallow trench isolation structure 34, and its opposite outer surface 51 conform to the side surface 32 and bottom surface 33 of the first shallow trench isolation structure 34. In other words, the guard region 45 may be formed in a layered manner such that the outer surface 51 of the guard region 45 is approximately parallel to the side surface 32 and bottom surface 33. The guard region 45 has a depth, relative to the first main surface 11, that is greater than the depth of the cathode region 27 and the thickness of the first shallow trench isolation structure 34.

[0059] Furthermore, the guard region 45 may integrally include a first portion 52 and a second portion 53 as a configuration that can be distinguished in the lateral direction along the first main surface 11 of the semiconductor chip 4. The first portion 52 may be a portion of the guard region 45 that extends along the side surface 32 of the first shallow trench isolation structure 34 from the first main surface 11 toward the second main surface 12 in the thickness direction of the semiconductor chip 4. The second portion 53 may be a portion of the guard region 45 that is formed from the first portion 52 along the bottom surface 33 of the first shallow trench isolation structure 34 in a direction intersecting the thickness direction of the semiconductor chip 4 and covers the bottom surface 33 of the first shallow trench isolation structure 34 from the second main surface 12 side. Both the first portion 52 and the second portion 53 are in direct contact with the side surface 32 and the bottom surface 33 of the first shallow trench isolation structure 34.

[0060] A guard contact region 54 is formed at the end of the guard region 45 on the first main surface 11 side. The guard contact region 54 is formed in the surface layer portion of the guard region 45 exposed from the first opening 37. As shown in FIG. 2, the guard contact region 54 is formed in an annular shape along the inner periphery of the first opening 37. The guard contact region 54 forms an ohmic contact with the first conductive layer 40 (first layer 43). The guard contact region 54 has the same conductivity type as the guard region 45, that is, p-type. The p-type impurity concentration of the guard contact region 54 is preferably higher than the p-type impurity concentration of the guard region 45. For example, the p-type impurity concentration of the guard contact region 54 is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ It may be the following:

[0061] In the Schottky barrier diode 100, a voltage is applied between the first conductive layer 40 and the second conductive layer 41 so that the first conductive layer 40 (anode conductive layer) is on the positive side and the second conductive layer 41 (cathode conductive layer) is on the negative side. As a result, a forward voltage is applied to the Schottky junction SJ, and a forward current I flows between the first conductive layer 40 and the second conductive layer 41. Ｆ is playing.

[0062] On the other hand, by applying a voltage such that the first conductive layer 40 (anode conductive layer) is negative and the second conductive layer 41 (cathode conductive layer) is positive, a reverse voltage is applied to the Schottky junction SJ, blocking conduction through the Schottky junction SJ. At this time, a reverse voltage is also applied to the pn junction J2, allowing the depletion layer to expand from the pn junction J2. This effectively suppresses leakage current when a reverse voltage is applied. As a result, the advantages of a Schottky barrier diode, such as a low forward voltage (VF) and a fast switching speed, can be achieved, while also suppressing reverse leakage current.

[0063] 4A to 4L are diagrams sequentially showing some of the manufacturing processes for the Schottky barrier diode 100 of Fig. 3. Only the processes related to the fabrication of the Schottky barrier diode 100 are shown below, but functional elements in the element region 13 (such as the transistor region 13B and the resistor region 13C) other than the diode region 13A may be formed in parallel with or independently of the processes shown in Fig. 4A to 4L.

[0064] To manufacture the Schottky barrier diode 100, referring to FIG. 4A , a p-type semiconductor wafer 55 (first layer 15) that will become the semiconductor chip 4 is prepared, and a buried layer (third layer 17) and a second layer 16 are formed on the semiconductor wafer 55. For example, n-type impurities (e.g., phosphorus) are implanted into the surface of the first layer 15. Next, the second layer 16 is formed on the first layer 15 by epitaxially growing silicon while introducing the n-type impurities. Subsequently, an annealing process is performed, which diffuses the n-type impurities implanted into the surface of the first layer 15 to both sides of the semiconductor wafer 55 in the thickness direction. As a result, the third layer 17 (buried layer) is formed between the first layer 15 and the second layer 16. The resulting semiconductor wafer 55 has the first main surface 11 and the second main surface 12 described above.

[0065] 4B , a hard mask (e.g., silicon oxide) is formed on the first main surface 11 of the first layer 15, and the second layer 16 and the third layer 17 are selectively etched through the hard mask. As a result, an isolation trench 19 is formed, and a diode region 13A is defined in the first layer 15.

[0066] Next, referring to FIG. 4C , n-type impurities are selectively implanted into the inner walls (inner peripheral wall 22, outer peripheral wall 23, and bottom wall 24) of the element isolation trench 19 and the first main surface 11 of the diode region 13A. In this embodiment, the n-type impurities are implanted at a tilt angle θ of 3° to 7° with respect to the direction n normal to the first main surface 11. This allows the n-type impurities to be efficiently implanted into the inner peripheral wall 22 and outer peripheral wall 23 of the element isolation trench 19. Phosphorus (P) or the like can be used as the n-type impurity. This introduces the impurity for the sinker layer 26. For clarity, in FIG. 4C , the region into which the impurity has been introduced is shown as the sinker layer 26.

[0067] 4D , an isolation insulating film 20 is formed on the inner walls (inner peripheral wall 22, outer peripheral wall 23, and bottom wall 24) of the isolation trench 19. The isolation insulating film 20 is formed by, for example, thermal oxidation. Heat generated during the formation of the isolation insulating film 20 diffuses n-type impurities on the inner peripheral wall 22 and outer peripheral wall 23 of the isolation trench 19, forming a sinker layer 26. Next, the portion of the isolation insulating film 20 on the bottom wall 24 of the isolation trench 19 is removed by etching. This forms a contact hole 25.

[0068] Next, referring to Fig. 4E, an isolation electrode 21 is buried in the isolation trench 19. Next, referring to Fig. 4F, a trench 30 of a shallow trench isolation structure 29 is formed in a surface layer portion of the first main surface 11. Next, referring to Fig. 4G, a buried insulator 31 is formed by backfilling the trench 30 with an insulating material.

[0069] Next, referring to FIG. 4H, p-type impurities for the guard regions 45 are introduced into the second layer 16. For example, a mask (SiO ２A hard mask (e.g., a hard mask, resist, etc.) is formed on the first main surface 11. A portion of the barrier formation region 36 and a portion of the first shallow trench isolation structure 34 are exposed through the openings in the mask. Next, p-type impurities are implanted into the first main surface 11 through the openings in the mask. The acceleration voltage during the implantation may be appropriately set so that the p-type impurities penetrate the first shallow trench isolation structure 34 and reach below the first shallow trench isolation structure 34. As a result, the p-type impurities for the guard region 45 are introduced into the surface portion of the second layer 16. For clarity, in FIG. 4H , the region into which the p-type impurities are introduced is shown as the guard region 45.

[0070] 4I, n-type impurities for forming the cathode region 27 are then introduced into the second layer 16. For example, a mask (SiO ２ A hard mask, resist, or the like is formed on the first main surface 11. A portion of the second layer 16 is exposed through an opening in the mask. Next, n-type impurities are implanted into the first main surface 11 through the opening in the mask. As a result, n-type impurities for the cathode region 27 are introduced into the surface portion of the second layer 16. In FIG. 4I , for clarity, the region into which the n-type impurities have been introduced is shown as the cathode region 27.

[0071] 4J, p-type impurities for forming the guard contact regions 54 are introduced into the second layer 16. For example, a mask (SiO ２ A hard mask (e.g., a resist, etc.) is formed on the first main surface 11. A portion of the guard region 45 is exposed through an opening in the mask. Next, p-type impurities are implanted into the first main surface 11 through the opening in the mask. As a result, the p-type impurities for the guard contact region 54 are introduced into the surface layer of the second layer 16. Next, a heat treatment is performed to diffuse the previously introduced n-type impurities and p-type impurities within the second layer 16. As a result, the guard region 45, the cathode region 27, and the guard contact region 54 are formed.

[0072] 4K, the first layer 43 of the first conductive layer 40 is formed on the first main surface 11 of the semiconductor wafer 55. The first layer 43 can be formed by a known conductive layer forming method such as sputtering, vapor deposition, or plating. After that, a heat treatment is performed to form a silicide layer 38 on the portion of the first main surface 11 that contacts the first layer 43. In this embodiment, a Co layer is deposited as the material for the first layer 43, and the Co layer is reacted with the semiconductor wafer 55 (Si) to form CoSi ２ A silicide layer 38 made of the above can be formed.

[0073] 4L , the second layer 44 of the first conductive layer 40 and the second conductive layer 41 are formed. The second layer 44 of the first conductive layer 40 and the second conductive layer 41 can be formed by a known method for forming a conductive layer, such as a sputtering method, a vapor deposition method, or a plating method. Through the above steps, the above-described Schottky barrier diode 100 is obtained.

[0074] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0075] For example, in the foregoing description and accompanying drawings, n-type regions may be replaced with p-type regions, and p-type regions may be replaced with n-type regions.

[0076] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0077] The following characteristics can be extracted from the description of this specification and the drawings.

[0078] [Supplementary Note 1-1] A semiconductor device comprising: a chip having a main surface; a pn junction extending horizontally along the main surface inside the chip; a trench insulating structure formed on the main surface so as to penetrate the pn junction and defining a diode region in the chip; a barrier formation region formed on a surface layer of the main surface in the diode region; and a metal layer disposed on the main surface so as to cover the barrier formation region in the diode region, and forming a Schottky junction with the barrier formation region.

[0079] [Supplementary Note 1-2] The semiconductor device according to Supplementary Note 1-1, wherein the Schottky junction portion is connected to the pn junction portion in reverse bias.

[0080] [Appendix 1-3] The semiconductor device according to Appendix 1-1 or Appendix 1-2, wherein the trench isolation structure includes a trench formed in the main surface, an insulating film covering a sidewall of the trench so as to expose a portion of the chip from a bottom wall of the trench, and an embedded electrode embedded in the trench across the insulating film so as to be electrically connected to the chip at the bottom wall of the trench.

[0081] [Supplementary Note 1-4] The semiconductor device according to Supplementary Note 1-3, wherein the buried electrode is made of conductive polysilicon.

[0082] [Supplementary Note 1-5] The semiconductor device according to any one of Supplementary Note 1-1 to Supplementary Note 1-4, further including a cathode region formed in a surface layer portion of the main surface in the diode region and spaced from the barrier formation region.

[0083] [Supplementary Note 1-6] The semiconductor device according to Supplementary Note 1-5, further comprising a shallow trench isolation structure formed in a region between the barrier formation region and the cathode region in the main surface.

[0084] [Supplementary Note 1-7] The semiconductor device according to Supplementary Note 1-6, wherein the metal layer has a portion extending from above the barrier formation region to above the shallow trench isolation structure.

[0085] [Supplementary Note 1-8] The semiconductor device according to Supplementary Note 1-6 or Supplementary Note 1-7, further including a guard region formed in a region along the shallow trench isolation structure inside the chip, the guard region having a conductivity type different from that of the cathode region.

[0086] [Supplementary Note 1-9] The semiconductor device according to Supplementary Note 1-8, wherein the guard region has a protruding portion that protrudes from a portion along the shallow trench isolation structure toward the barrier formation region, and the metal layer is electrically connected to the protruding portion of the guard region in the barrier formation region.

[0087] [Appendix 1-10] The semiconductor device according to Appendix 1-9, further including a high-concentration guard region formed in a surface layer portion of the protruding portion and having a higher impurity concentration than the guard region, wherein the metal layer is electrically connected to the high-concentration guard region in the barrier formation region.

[0088] [Supplementary Note 1-11] The semiconductor device according to any one of Supplementary Note 1-8 to Supplementary Note 1-10, wherein the shallow trench isolation structure surrounds the barrier formation region in a planar view, and the guard region surrounds the barrier formation region in a planar view.

[0089] [Supplementary Note 1-12] The semiconductor device according to any one of Supplementary Note 1-5 to Supplementary Note 1-11, further including a sinker region formed in a surface layer portion of the main surface along the trench insulation structure in the diode region, the sinker region having the same conductivity type as the cathode region.

[0090] [Supplementary Note 1-13] The semiconductor device according to Supplementary Note 1-12, wherein the sinker region is connected to the cathode region.

[0091] [Supplementary Note 1-14] The semiconductor device according to Supplementary Note 1-12 or Supplementary Note 1-13, wherein the sinker region crosses the pn junction in the thickness direction of the chip.

[0092] [Supplementary Note 1-15] The semiconductor device according to any one of Supplementary Note 1-1 to Supplementary Note 1-14, further including a silicide layer formed in the portion of the barrier formation region covered with the metal layer.

[0093] [Supplementary Note 1-16] The metal layer includes at least one of a Ti layer, a Ni layer, a Co layer, a Mo layer, and a W layer, and the silicide layer includes a TiSi layer, a TiSi ２ layer, NiSi layer, CoSi layer, CoSi ２ layer, MoSi ２ layer and WSi ２ 16. The semiconductor device of claim 1-15, comprising at least one of the layers.

[0094] [Supplementary Note 1-17] The metal layer is a Co layer, and the silicide layer is a CoSi ２17. The semiconductor device of claim 1-16, comprising a layer.

[0095] [Supplementary Note 1-18] The semiconductor device according to any one of Supplementary Note 1-1 to Supplementary Note 1-17, further including a plurality of device regions provided on the main surface, wherein the trench isolation structure electrically isolates the diode region from the plurality of device regions.

[0096] [Supplementary Note 1-19] The semiconductor device according to Supplementary Note 1-18, wherein the plurality of device regions each include a functional device that forms part of an integrated circuit.

[0097] [Supplementary Note 1-20] The semiconductor device according to Supplementary Note 1-19, wherein the Schottky junction forms part of the integrated circuit.

[0098] 1: Semiconductor device 2: Sealing resin 3: Die pad 4: Semiconductor chip 5: Conductive bonding material 6: Lead terminal 6A: First lead terminal 6B: Second lead terminal 6C: Third lead terminal 6D: Fourth lead terminal 6E: Fifth lead terminal 6F: Sixth lead terminal 6G: Seventh lead terminal 6H: Eighth lead terminal 7: Conductive wire 8: First main surface 9: Second main surface 10A: First side surface 10B: Second side surface 10C: Third side surface 10D: Fourth side surface 11: First main surface 12: Second main surface 13: Element region 13A: Diode region 13B: Transistor region 13C: Resistor element region 14: Pad 15: First layer 16: Second layer 17: Third layer 18: Trench insulating structure 19: Element isolation trench 20: Element isolation insulating film 21: Element isolation electrode 22: Inner peripheral wall 23: Outer peripheral wall 24: Bottom wall 25: Contact hole 26: Sinker layer 27: Cathode region 28: Boundary portion 29: Shallow trench insulating structure 30: Trench 31: Buried insulator 32: Side surface 33: Bottom surface 34: First shallow trench insulating structure 35: Second shallow trench insulating structure 36: Barrier formation region 37: First opening 38: Silicide layer 39: Second opening 40: First conductive layer 41: Second conductive layer 42: Lead portion 43: First layer 44: Second layer 45: Guard region 46: Inner peripheral portion 47 : Outer peripheral portion 48 : Anode region 49 : Protrusion 50 : Inner surface 51 : Outer surface 52 : First portion 53 : Second portion 54 : Guard contact region 55 : Semiconductor wafer 66 : Semiconductor wafer 100 : Schottky barrier diode J1 : pn junction J2 : pn junction SJ : Schottky junction

Claims

1. a chip having a major surface; a pn junction extending horizontally along the main surface inside the chip; a trench isolation structure formed on the main surface so as to penetrate the pn junction and define a diode region in the chip; a barrier formation region formed in a surface layer portion of the main surface in the diode region; a metal layer disposed on the main surface in the diode region to cover the barrier formation region, the metal layer forming a Schottky junction with the barrier formation region.

2. The semiconductor device according to claim 1 , wherein the Schottky junction is connected to the pn junction with a reverse bias.

3. 2. The semiconductor device according to claim 1, wherein the trench isolation structure includes a trench formed in the main surface, an insulating film covering a sidewall of the trench so as to expose a portion of the chip from a bottom wall of the trench, and an embedded electrode embedded in the trench across the insulating film so as to be electrically connected to the chip at the bottom wall of the trench.

4. 4. The semiconductor device according to claim 3, wherein said buried electrode is made of conductive polysilicon.

5. 5. The semiconductor device according to claim 1, further comprising a cathode region formed in a surface layer portion of said main surface and spaced from said barrier formation region in said diode region.

6. 6. The semiconductor device of claim 5, further comprising a shallow trench isolation structure formed in said major surface in a region between said barrier formation region and said cathode region.

7. 7. The semiconductor device according to claim 6, wherein the metal layer has a portion extending from above the barrier formation region onto above the shallow trench isolation structure.

8. 7. The semiconductor device according to claim 6, further comprising a guard region formed in an area along said shallow trench isolation structure inside said chip, said guard region having a conductivity type different from that of said cathode region.

9. the guard region has a protruding portion protruding from a portion along the shallow trench isolation structure toward the barrier formation region, The semiconductor device according to claim 8 , wherein the metal layer is electrically connected to the protruding portion of the guard region in the barrier formation region.

10. a high-concentration guard region formed in a surface layer of the protruding portion and having a higher impurity concentration than the guard region; The semiconductor device according to claim 9 , wherein the metal layer is electrically connected to the high-concentration guard region in the barrier formation region.

11. the shallow trench isolation structure surrounds the barrier formation region in a plan view; The semiconductor device according to claim 8 , wherein said guard region surrounds said barrier formation region in a plan view.

12. 6. The semiconductor device according to claim 5, further comprising a sinker region formed in a surface layer portion of said main surface along said trench insulating structure in said diode region, said sinker region having the same conductivity type as said cathode region.

13. The semiconductor device according to claim 12 , wherein the sinker region is connected to the cathode region.

14. The semiconductor device according to claim 12 , wherein the sinker region crosses the pn junction in a thickness direction of the chip.

15. 5. The semiconductor device according to claim 1, further comprising a silicide layer formed on a portion of said barrier formation region covered with said metal layer.

16. the metal layer includes at least one of a Ti layer, a Ni layer, a Co layer, a Mo layer, and a W layer; The silicide layer is a TiSi layer, a TiSi ２ layer, NiSi layer, CoSi layer, CoSi ２ layer, MoSi ２ layer and WSi ２ 20. The semiconductor device of claim 15, comprising at least one of the layers.

17. the metal layer is a Co layer, The silicide layer is CoSi ２ 17. The semiconductor device of claim 16, comprising a layer.

18. further comprising a plurality of device regions disposed on the major surface; 5. The semiconductor device of claim 1, wherein the trench isolation structure electrically isolates the diode region from a plurality of the device regions.

19. 20. The semiconductor device of claim 18, wherein a plurality of said device regions each include a functional device that each forms a portion of an integrated circuit.

20. 20. The semiconductor device of claim 19, wherein the Schottky junction forms part of the integrated circuit.