Semiconductor device for power amplification

Abstract

A semiconductor device (1) for power amplification comprises: a substrate (10); a lower surface electrode (64); a semiconductor layer (20); a source electrode (60); a drain electrode (50); a gate electrode (40); and a field plate (80). The semiconductor layer (20) is partitioned into active regions (31) and element separation regions (30). A channel region is composed of a plurality of unit channel regions (90) divided by the element separation regions (30) and arranged side by side in the Y-axis direction in a plan view. The source electrode (60) is composed of a plurality of unit source electrodes facing the respective unit channel regions (90). The field plate (80) is composed of a plurality of unit plates (81) facing the respective unit channel regions (90). A plurality of plate driving lines (82) extend in the X-axis direction and electrically connect the plurality of unit source electrodes and the plurality of unit plates (81). At least one of the plate driving lines (82) is provided to each of the unit plates (81) in the range of the element separation regions (30).

Description

Power amplifier semiconductor device

[0001] The present disclosure relates to a semiconductor device for power amplification.

[0002] Patent Document 1 discloses a high electron mobility transistor (HEMT) that uses two-dimensional electron gas (2DEG) as a channel.

[0003] Patent No. 5390768

[0004] 2. Description of the Related Art Semiconductor devices such as high electron mobility transistors have a problem in that their characteristics deteriorate due to heat generated during operation.

[0005] Therefore, the present disclosure provides a power amplifier semiconductor device that can suppress the deterioration of characteristics caused by heat.

[0006] a semiconductor layer provided above the substrate, the semiconductor layer including a plurality of active layers made of Group III nitride, the semiconductor layer generating two-dimensional electron gas at a heterointerface of the plurality of active layers; a source electrode and a drain electrode provided above the semiconductor layer with a gap therebetween, the source electrode and the drain electrode being electrically connected to the two-dimensional electron gas; a gate electrode provided above the semiconductor layer with a gap therebetween, the gate electrode being in contact with the semiconductor layer and being provided with a gap therebetween from the source electrode and the drain electrode; a field plate provided above the semiconductor layer between the gate electrode and the drain electrode, the field plate being set to the same potential as the source electrode; a gate finger provided above the plurality of gate electrodes arranged linearly in a first direction, the gate finger being in contact with and covering all of the gate electrodes; and drain fingers in contact with and covering the plurality of drain electrodes, wherein the semiconductor layer is divided into an active region in which the two-dimensional electron gas is present and an isolation region in which the two-dimensional electron gas is not present in a planar view of the substrate, a channel region which is an overlapping portion between the active region and the gate electrode in the planar view is a plurality of unit channel regions which are divided in the first direction by the isolation region and are arranged in a row, the source electrode is a plurality of unit source electrodes facing each of the plurality of unit channel regions, the field plate is a plurality of unit plates facing each of the plurality of unit channel regions, and a plurality of plate driving lines which extend in a second direction perpendicular to the first direction and electrically connect the plurality of unit source electrodes to the plurality of unit plates, respectively, are provided within the isolation region, one or more for each of the unit plates.

[0007] According to the power amplifying semiconductor device according to the present disclosure, it is possible to suppress deterioration of characteristics due to heat.

[0008] FIG. 1 is a plan view of a power amplifier semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view of the power amplifier semiconductor device according to the embodiment taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view of the power amplifier semiconductor device according to the embodiment taken along line III-III in FIG. 1. FIG. 4 is a cross-sectional view of the power amplifier semiconductor device according to the embodiment taken along line IV-IV in FIG. 1. FIG. 5 is an enlarged plan view showing a characteristic portion of the power amplifier semiconductor device according to the embodiment. FIG. 6 is a cross-sectional view of the power amplifier semiconductor device according to the embodiment taken along line VI-VI in FIG. 5. FIG. 7 is a cross-sectional view of the power amplifier semiconductor device according to the embodiment taken along line VII-VII in FIG. 5. FIG. 8 is a plan view of a power amplifier semiconductor device according to a comparative example. FIG. 9 is a cross-sectional view of the power amplifier semiconductor device according to the comparative example taken along line IX-IX in FIG. 8. FIG. 10 is a plan view of an application example of the power amplifier semiconductor device according to the embodiment. FIG. 11 is a cross-sectional view of the application example of the power amplifier semiconductor device according to the embodiment taken along line XI-XI in FIG. FIG. 12 is a cross-sectional view of a power amplifier semiconductor device according to a first modification of the embodiment. FIG. 13 is an XZ cross-sectional view passing through a plate drive line of a power amplifier semiconductor device according to a second modification of the embodiment. FIG. 14 is a cross-sectional view of a power amplifier semiconductor device according to a third modification of the embodiment. FIG. 15 is a cross-sectional view of a power amplifier semiconductor device according to a fourth modification of the embodiment. FIG. 16 is a plan view of a power amplifier semiconductor device according to a fifth modification of the embodiment. FIG. 17 is a plan view showing another example of a source via in the power amplifier semiconductor device according to the embodiment and the first to fifth modifications. FIG. 18 is a plan view showing another example of a source via in the power amplifier semiconductor device according to the embodiment and the first to fifth modifications. FIG. 19 is a plan view showing another example of a source via in the power amplifier semiconductor device according to the embodiment and the first to fifth modifications. FIG. 20 is a plan view showing another example of a source via in the power amplifier semiconductor device according to the embodiment and the first to fifth modifications. FIG. 21 is a plan view showing another example of a source via in the power amplifier semiconductor device according to the embodiment and the first to fifth modifications. FIG. 22 is a plan view showing another example of a source via in the power amplifier semiconductor device according to the embodiment and the first to fifth modifications.FIG. 23 is a plan view showing another example of a source via in a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 24 is a plan view showing another example of a source via conductor in a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 25 is a plan view showing another example of a source via in a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 26 is a plan view showing another example of a plate drive line in a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 27 is a plan view showing another example of a plate drive line in a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 28 is a plan view showing another example of a plate drive line in a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 29 is a plan view showing another example of a plate drive line and a source via in a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 30A is a cross-sectional view for explaining one step of a method for manufacturing a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 30B is a cross-sectional view for explaining one step of a method for manufacturing a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. 30C is a cross-sectional view for explaining one step of a manufacturing method of a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 30D is a cross-sectional view for explaining one step of a manufacturing method of a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 30E is a cross-sectional view for explaining one step of a manufacturing method of a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 30F is a cross-sectional view for explaining one step of a manufacturing method of a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 30G is a cross-sectional view for explaining one step of a manufacturing method of a power amplifier semiconductor device according to the embodiment and modifications 1 to 5. FIG. 30H is a cross-sectional view for explaining one step of a manufacturing method of a power amplifier semiconductor device according to the embodiment and modifications 1 to 5.

[0009] (Summary of the Present Disclosure) Hereinafter, embodiments will be specifically described with reference to the drawings.

[0010] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0011] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales in each figure do not necessarily match. Also, for example, the thickness, size, etc. of components in each figure may be exaggerated to make the explanation easier to understand. Furthermore, in each figure, substantially identical components are assigned the same reference numerals, and duplicate explanations are omitted or simplified.

[0012] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangular or circular, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0013] Furthermore, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between the two components, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0014] In this specification and the drawings, the X-axis, Y-axis, and Z-axis represent the three axes of a three-dimensional Cartesian coordinate system. In each embodiment, the Z-axis direction is the thickness direction of the substrate. In this specification, the "thickness direction" refers to the thickness direction of the substrate, and is the direction perpendicular to the main surface of the substrate. The Y-axis direction is an example of a first direction, and is the direction in which the gate fingers and drain fingers extend. The X-axis direction is an example of a second direction, and is the direction in which the source electrode, gate electrode, and drain electrode are arranged in this order. In addition, unless otherwise specified, "plan view" refers to a view from a direction perpendicular to the main surface of the substrate.

[0015] In this specification, a group III nitride layer refers to a semiconductor layer containing one or more group III elements and nitrogen. Examples of group III elements include aluminum (Al), gallium (Ga), and indium (In). Examples of group III nitrides include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. Group III nitrides may also contain one or more elements other than group III elements, such as silicon (Si) and phosphorus (P). In the following description, unless otherwise specified, when a group III nitride is referred to as AlInGaN, this means that the group III nitride contains all of Al, In, Ga, and N. The same applies to other notations such as AlGaN and GaN.

[0016] Furthermore, a layer of Group III nitride means that the layer contains substantially only Group III nitride, although the layer may contain other elements as impurities, such as elements that are unavoidable during manufacturing, at a rate of 1% or less.

[0017] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0018] (Embodiment) [1. Configuration] First, the configuration of a power amplifying semiconductor device according to an embodiment will be described with reference to FIGS. 1 to 7. FIG.

[0019] Fig. 1 is a plan view of a power amplifier semiconductor device according to this embodiment. Figs. 2 to 4 are cross-sectional views of the power amplifier semiconductor device according to this embodiment. Specifically, Fig. 2 shows a cross section taken along line II-II in Fig. 1. Fig. 3 shows a cross section taken along line III-III in Fig. 1. Fig. 4 shows a cross section taken along line IV-IV in Fig. 1.

[0020] 5 is an enlarged plan view showing a characteristic portion of the power amplifying semiconductor device according to this embodiment. FIG. 5 shows the positional relationship of each component in more detail than FIG. 1. FIGS. 6 and 7 are cross-sectional views of the power amplifying semiconductor device according to this embodiment. Specifically, FIG. 6 shows a cross-section taken along line VI-VI in FIG. 5. FIG. 7 shows a cross-section taken along line VII-VII in FIG. 5.

[0021] The power amplifier semiconductor device 1 shown in FIGS. 1 to 4 is a HEMT formed using a GaN (gallium nitride)-based semiconductor material, and is sometimes called a GaN HEMT. A GaN-based semiconductor material is a semiconductor material containing Ga (gallium) and N (nitrogen). The GaN-based semiconductor material may contain Al (aluminum), In (indium), and the like in addition to Ga and N. GaN-based semiconductor materials are characterized by a wide band gap, a high breakdown field, and a fast saturated drift velocity. Therefore, a GaN HEMT can achieve the characteristics of low on-resistance, high breakdown voltage, and fast switching speed.

[0022] The power amplifier semiconductor device 1 according to the present embodiment is used, for example, as a high-frequency transistor, and can be used, for example, as a power amplifier in a communication device such as a mobile phone or a base station.

[0023] The power amplifier semiconductor device 1 has a configuration in which unit components of a transistor are repeatedly arranged in a matrix in a two-dimensional plane (specifically, an XY plane). The unit components of a transistor are portions including a unit channel region 90, a gate electrode 40, a drain electrode 50, and a unit source region 92 (specifically, a source electrode 60, a source via 70, etc.) shown in FIG. 5, and refer to the smallest unit operable as a transistor.

[0024] 1 to 4, the power amplifier semiconductor device 1 includes a substrate 10, a semiconductor layer 20, a gate electrode 40, a gate finger 42, a gate bus 44, a drain electrode 50, a drain finger 52, a drain bus 54 (see FIG. 10), a source electrode 60, a source coupling portion 62, a lower surface electrode 64, a source via 70, a field plate 80, and a plate drive line 82. In a plan view, the semiconductor layer 20 is divided into an element isolation region 30 and an active region 31. A plurality of gate electrodes 40, gate fingers 42, drain electrodes 50, drain fingers 52, source electrodes 60, source vias 70, field plates 80, and plate drive lines 82 are provided.

[0025] The substrate 10 is a Si (silicon) substrate, but is not limited to this. The substrate 10 may also be a sapphire substrate, a SiC (silicon carbide) substrate, or a GaN substrate.

[0026] The semiconductor layer 20 is provided above the substrate 10 and includes a plurality of active layers made of group III nitrides. The group III nitrides are, for example, GaN-based nitrides. Two-dimensional electron gas 22 is generated at the heterointerfaces of the plurality of active layers. In FIG. 2, the two-dimensional electron gas 22 is schematically represented by dashed lines.

[0027] The multiple active layers are, for example, two GaN-based semiconductor layers with different bandgaps. As shown in Figures 6 and 7, the two GaN-based semiconductor layers are specifically a GaN layer 24 and an AlGaN layer 26. The GaN layer 24 and the AlGaN layer 26 are stacked in this order from the substrate 10 side. Two-dimensional electron gas 22 is generated at the heterointerface between the AlGaN layer 26 with a large bandgap and the GaN layer 24 with a small bandgap. In plan view, the semiconductor layer 20 is divided into an active region 31 with the two-dimensional electron gas 22 and an element isolation region 30 with no two-dimensional electron gas 22.

[0028] The semiconductor layer 20 has a channel region that includes at least a portion of the two-dimensional electron gas 22. The channel region is an overlapping portion of the active region 31 and the gate electrode 40 in a plan view. The channel region is part of the current path between the drain electrode 50 and the source electrode 60 in the power amplifier semiconductor device 1, and is a region whose conduction and non-conduction are controlled by the gate electrode 40. The channel region is divided in the X-axis direction by the element isolation region 30 and is made up of a plurality of unit channel regions 90 that are lined up.

[0029] The semiconductor layer 20 may include a layer other than the active layer. For example, the layer other than the active layer may be a layer made of GaN, AlGaN, InGaN, InAlGaN, AlN, InN, or the like. For example, the semiconductor layer 20 may include a buffer layer disposed between the substrate 10 and the GaN layer 24. By providing the buffer layer, the film quality of the GaN layer 24 and the AlGaN layer 26 can be improved. Each layer included in the semiconductor layer 20 is formed by epitaxial growth.

[0030] The element isolation region 30 is a region free of the two-dimensional electron gas 22. The element isolation region 30 divides the channel region of the semiconductor layer 20 into a plurality of unit channel regions 90 arranged in the Y-axis direction. The unit channel regions are sometimes called split channel regions. As shown in FIGS. 5 and 6 , the unit channel regions 90 are regions that overlap the gate electrode 40 in a plan view, i.e., regions directly below the gate electrode 40. The gate length Lg (see FIG. 6 ), which is the length of the gate electrode 40 in the X-axis direction, corresponds to the length of the unit channel region 90 in the X-axis direction. In FIG. 5 , the outline of the unit channel region 90 is represented by a thick long dashed line.

[0031] The element isolation region 30 is formed in a region including at least the heterointerface between the epitaxially grown GaN layer 24 and AlGaN layer 26, i.e., a region where two-dimensional electron gas 22 is generated. The element isolation region 30 is formed by inactivating a portion of the semiconductor layer 20 by ion implantation. For example, the element isolation region 30 is formed by ion implantation of Ar (argon), B (boron), He (helium), or the like into a region including at least the heterointerface between the epitaxially grown GaN layer 24 and AlGaN layer 26. No two-dimensional electron gas 22 is generated in the element isolation region 30.

[0032] Alternatively, the element isolation region 30 may be formed by etching away the epitaxially grown GaN layer 24 and AlGaN layer 26 to a depth at least sufficient to generate the two-dimensional electron gas 22. For example, the element isolation region 30 may be an insulating layer formed in the portion where the GaN layer 24 and AlGaN layer 26 have been removed.

[0033] The gate electrode 40 is provided at a distance from the source electrode 60 and the drain electrode 50 and is in contact with the semiconductor layer 20. The gate electrode 40 is electrically connected to the gate fingers 42 and is disposed between the gate fingers 42 and the semiconductor layer 20. Specifically, the gate electrode 40 is in Schottky contact with the semiconductor layer 20. The gate electrode 40 is a control electrode of the power amplifier semiconductor device 1. Specifically, the unit channel regions 90 can be switched between conductive and non-conductive states depending on a gate potential applied to the gate electrode 40 via the gate fingers 42. When the power amplifier semiconductor device 1 is in operation, a gate potential of, for example, approximately −1.5 V to −3 V is applied to the gate electrode 40. Note that the magnitude of the gate potential is not particularly limited as long as it can operate the power amplifier semiconductor device 1.

[0034] In this embodiment, a plurality of gate electrodes 40 are provided lined up in a straight line in the Y-axis direction. Each of the plurality of gate electrodes 40 has an elongated shape in the Y-axis direction, and is lined up in a straight line along the Y-axis direction. In other words, the plurality of gate electrodes 40 have a configuration in which one long gate electrode extending along the Y-axis direction is divided into a plurality of gate electrodes spaced apart from each other. For this reason, the gate electrodes 40 can also be called divided gate electrodes or unit gate electrodes.

[0035] Furthermore, a plurality of gate electrodes 40 are provided for each gate finger 42. That is, the plurality of gate electrodes 40 are arranged side by side not only in the Y-axis direction but also in the X-axis direction. In other words, the gate electrodes 40 are repeatedly arranged in a matrix in a two-dimensional plane (specifically, the XY plane).

[0036] The gate electrode 40 is formed using a conductive material. For example, the gate electrode 40 is a single layer or a laminate of a metal, an alloy, or a conductive metal nitride. Examples of metals that can be used include Ti (titanium), Ta (tantalum), W (tungsten), Ni (nickel), Pd (palladium), Au (gold), and Al. Examples of conductive metal nitrides that can be used include TiN and TaN. The gate electrode 40 is formed into a predetermined shape by, for example, forming a film by vapor deposition, sputtering, or the like, and patterning by etching, or the like.

[0037] The gate fingers 42 are provided above the semiconductor layer 20 and extend in the Y-axis direction. The gate fingers 42 are above the plurality of gate electrodes 40 that are aligned in a straight line in the Y-axis direction, and are in contact with and cover all of the gate electrodes 40. In this embodiment, as shown in FIG. 3 , the gate fingers 42 are provided above the plate drive lines 82 and spaced apart from the plate drive lines 82. The gate fingers 42 are wiring lines for supplying a gate potential to the gate electrodes 40. The gate fingers 42 can be called gate drive lines that drive the gate electrodes 40.

[0038] For example, the cross-sectional area of ​​the gate finger 42 in the XZ cross section is larger than that of the gate electrode 40. For example, as shown in FIGS. 5 and 6 , the length of the gate finger 42 in the X-axis direction is longer than that of the gate electrode 40. This can reduce the gate resistance Rg. For example, it can suppress variations in the gate potential within a plane and stabilize the transistor operation.

[0039] The gate fingers 42 are formed using a conductive material. For example, the gate fingers 42 may be formed using a material with higher conductivity than the gate electrode 40. This makes it possible to further reduce the gate resistance Rg. As an example, the gate fingers 42 are formed using Al, Au, Cu (copper), or the like. The gate fingers 42 are formed into a predetermined shape by, for example, forming a film by vapor deposition, sputtering, or the like, and patterning by etching, or the like.

[0040] In this embodiment, a plurality of gate fingers 42 are arranged side by side in the X-axis direction and are set to the same potential. For example, the plurality of gate fingers 42 are arranged parallel to each other and spaced apart at predetermined intervals. As an example, the plurality of gate fingers 42 are arranged so that the gate pitch (see FIG. 11 ) is equal. The negative end of each of the plurality of gate fingers 42 in the Y-axis direction is connected to a gate bus 44.

[0041] The gate bus 44 is an aggregated wiring that aggregates multiple gate fingers 42 and extends in the X-axis direction. The gate bus 44 may be formed integrally with the multiple gate fingers 42 using the same material. The gate bus 44 is formed in a predetermined shape by, for example, forming a film by vapor deposition, sputtering, or the like, and patterning by etching, or the like.

[0042] In this embodiment, the gate bus 44 is provided on the negative side in the Y-axis direction, but it may also be provided on the positive side in the Y-axis direction, or on both the positive and negative sides in the Y-axis direction.

[0043] The drain electrode 50 is provided above the semiconductor layer 20 and electrically connected to the two-dimensional electron gas 22. The drain electrode 50 is also electrically connected to the drain fingers 52 and is disposed between the drain fingers 52 and the semiconductor layer 20. Specifically, the drain electrode 50 is an electrode that is ohmic-connected to the two-dimensional electron gas 22 in the semiconductor layer 20. A drain potential is supplied to the drain electrode 50 via the drain fingers 52. When the power amplifier semiconductor device 1 is in operation, for example, a drain potential of up to approximately 150 V may be applied to the drain electrode 50. Note that the magnitude of the drain potential is not particularly limited as long as it can operate the power amplifier semiconductor device 1.

[0044] In this embodiment, a plurality of drain electrodes 50 are provided and aligned linearly in the Y-axis direction. Each of the plurality of drain electrodes 50 has an elongated shape in the Y-axis direction, and is aligned in a straight line along the Y-axis direction. That is, the plurality of drain electrodes 50 have a configuration in which one long drain electrode extending along the Y-axis direction is divided into a plurality of electrodes spaced apart from each other. For this reason, the drain electrodes 50 can also be called divided drain electrodes or unit drain electrodes.

[0045] Furthermore, a plurality of drain electrodes 50 are provided for each drain finger 52. That is, the plurality of drain electrodes 50 are arranged side by side not only in the Y-axis direction but also in the X-axis direction. In other words, the drain electrodes 50 are repeatedly arranged in a matrix in a two-dimensional plane (specifically, the XY plane).

[0046] The drain electrode 50 is formed using a conductive material. For example, the drain electrode 50 is a single layer or a laminate of a metal or an alloy. Examples of the metal that can be used include Ti, Al, and Au. The drain electrode 50 is formed into a predetermined shape by, for example, forming a film by vapor deposition, sputtering, or the like, and patterning by etching, or the like.

[0047] The drain finger 52 is provided above the semiconductor layer 20 and extends in the Y-axis direction. The drain finger 52 is above the plurality of drain electrodes 50 that are aligned in a straight line in the Y-axis direction, and contacts and covers all of the plurality of drain electrodes 50. The drain finger 52 is a wiring for supplying a drain potential to the drain electrode 50. In other words, the drain finger 52 can be called a drain drive line that drives the drain electrode 50.

[0048] For example, the drain finger 52 has a larger cross-sectional area in the XZ cross section than the drain electrode 50. For example, as shown in FIGS. 5 and 6 , the drain finger 52 has a longer length in the X-axis direction than the drain electrode 50. This can reduce the drain resistance Rd. For example, it can suppress variations in the drain potential in a plane and stabilize the transistor operation.

[0049] The drain fingers 52 are formed using a conductive material. For example, the drain fingers 52 may be formed using a material that is more conductive than the drain electrode 50. This can further reduce the drain resistance Rd. As an example, the drain fingers 52 are formed using Al, Au, Cu, or the like. The drain fingers 52 are formed into a predetermined shape by forming a film using vapor deposition, sputtering, or the like, and then patterning the film using etching, or the like.

[0050] In this embodiment, the drain fingers 52 are arranged side by side in the X-axis direction and are set to the same potential. For example, the drain fingers 52 are arranged parallel to each other and at equal intervals. The positive end of each of the drain fingers 52 in the Y-axis direction is connected to a drain bus 54 (see FIG. 10 ).

[0051] The drain bus 54 shown in FIG. 10 is an aggregated wiring that aggregates multiple drain fingers 52 (not shown in FIG. 10 ) and extends in the X-axis direction. The drain bus 54 may be integrally formed using the same material as the multiple drain fingers 52. The drain bus 54 may be formed, for example, by plating in the same process as the metal filling portion 72 of the source via 70. Alternatively, the drain bus 54 may be formed in a different process from the metal filling portion 72, and may be formed into a predetermined shape by, for example, performing film formation by vapor deposition, sputtering, or the like, and patterning by etching, or the like.

[0052] In this embodiment, the drain bus 54 is provided on the positive side in the Y-axis direction, but it may also be provided on the negative side in the Y-axis direction, or on both the positive and negative sides in the Y-axis direction. The drain bus 54 may also be provided on the same side as the gate bus 44.

[0053] The source electrode 60 is provided above the semiconductor layer 20 at a distance from the drain electrode 50 and is electrically connected to the two-dimensional electron gas 22. The source electrode 60 is arranged so as to sandwich the gate electrode 40 between the source electrode 60 and the drain electrode 50. Specifically, the source electrode 60 is an electrode that is in ohmic contact with the two-dimensional electron gas 22 in the semiconductor layer 20. A source potential is supplied to the source electrode 60 via the lower electrode 64, the source via 70, and the source connector 62. The source potential is, for example, a potential lower than the drain potential. When the power amplifier semiconductor device 1 is operating, for example, a source potential of 0 V is applied to the source electrode 60. Note that the magnitude of the source potential is not particularly limited as long as it can operate the power amplifier semiconductor device 1.

[0054] In this embodiment, a plurality of source electrodes 60 are provided lined up in the Y-axis direction. Each of the plurality of source electrodes 60 has an elongated shape in the Y-axis direction, and is lined up in a straight line along the Y-axis direction. In other words, the plurality of source electrodes 60 have a configuration in which one long source electrode extending along the Y-axis direction is divided into a plurality of electrodes spaced apart from each other. For this reason, the source electrodes 60 can also be called divided source electrodes or unit source electrodes.

[0055] A plurality of source electrodes 60 are provided for each unit channel region 90. Specifically, a source electrode 60 is provided for each unit source region 92 facing a unit channel region 90. In this embodiment, the plurality of source electrodes 60 are arranged side by side not only in the Y-axis direction but also in the X-axis direction. In other words, the source electrodes 60 are repeatedly arranged in a matrix in a two-dimensional plane (specifically, the XY plane).

[0056] Here, "facing" means being located in front of the unit source region 92 when viewed from the unit channel region 90 in the direction along the gate length direction, i.e., in the X-axis direction. Specifically, the length and position of the unit source region 92 in the Y-axis direction match the length and position of the unit channel region 90 in the Y-axis direction. The outlines of the unit source region 92 on the positive and negative sides in the X-axis direction are defined by the outline of the source electrode 60 on the positive side in the X-axis direction and the outline of either the source via 70 or the source coupling portion 62 on the most negative side in the X-direction. For example, the unit source region 92 is defined as a rectangular region as indicated by the thick two-dot chain line in FIG. 5 .

[0057] The source electrode 60 is formed using a conductive material. For example, the source electrode 60 is a single layer or a laminate of a metal or an alloy. Examples of metals that can be used include Ti, Al, and Au. The source electrode 60 is formed into a predetermined shape by, for example, forming a film by vapor deposition, sputtering, or the like, and patterning by etching, or the like. The source electrode 60 can be formed using the same material and process as the drain electrode 50.

[0058] The source electrode 60 may be provided so as to straddle the semiconductor layer 20 and the element isolation region 30. That is, a part of the source electrode 60 may be provided on the element isolation region 30.

[0059] The source connecting portion 62 is provided to connect the plurality of source electrodes 60. The source connecting portion 62 is a wiring for supplying a source potential to the source electrode 60. The source connecting portion 62 can be called a source driving line that drives the source electrode 60.

[0060] 1, in this embodiment, the source connector 62 extends along the Y-axis direction and is provided so as to cover the plurality of source vias 70, at least a portion of the plurality of source electrodes 60, and a portion of the plurality of plate driving lines 82. As shown in Figures 2 and 3, the source connector 62 is in contact with at least a portion of the upper surfaces of the plurality of source electrodes 60 and a portion of the upper surfaces of the plurality of plate driving lines 82, and is electrically connected to them.

[0061] In plan view, the source coupling portion 62 includes a portion that overlaps with the source via 70 and a portion that does not overlap with the source via 70. In this case, the portion that overlaps with the source via 70 in plan view is considered to be a portion above the upper surface of the metal coating 74 of the source via 70. Note that if the source via 70 does not have the metal coating 74, the portion that overlaps with the source via 70 in plan view is considered to be a portion above the upper surface of the element isolation region 30.

[0062] The source coupling portion 62 may be provided so as to electrically connect the plurality of source vias 70 to the plurality of source electrodes 60 and the plurality of plate driving lines 82. For example, the source coupling portion 62 may be provided so as to contact a part of a side surface of the source via 70, a part of a side surface of the source electrode 60, and a part of a side surface of the plate driving line 82 without overlapping with any of the source vias 70, the source electrode 60, and the plate driving line 82 in a plan view. When the source electrode 60 and the plate driving line 82 are in contact with each other and electrically connected, the source coupling portion 62 may be in contact with one of the source electrode 60 and the plate driving line 82 but not with the other.

[0063] The source connector 62 is formed using a conductive material. For example, the source connector 62 is a single layer or a laminate of a metal or an alloy. Examples of metals that can be used include Ti, Al, and Au. The source connector 62 can be formed by plating or the like using the same material and process as the metal filling portion 72 of the source via 70. Alternatively, the source connector 62 may be formed by the same material and process as the source electrode 60 or the metal coating 74 of the source via 70. For example, the source connector 62 may be formed into a predetermined shape by performing film formation by vapor deposition, sputtering, or the like, and patterning by etching or the like.

[0064] The lower electrode 64 is provided below the substrate 10. The lower electrode 64 is also called a back surface source electrode. Specifically, the lower electrode 64 is provided over the entire lower surface of the substrate 10. The lower electrode 64 is set to the same potential as the source electrodes 60. Specifically, the lower electrode 64 is connected to the source vias 70, and supplies a source potential to each of the multiple source electrodes 60 via the source vias 70 and the source coupling portions 62.

[0065] The lower electrode 64 is formed using a conductive material. For example, the lower electrode 64 is a single layer or laminate of a metal or an alloy. Examples of the metal that can be used include Au, Sn (tin), and Ag (silver). The power amplifier semiconductor device 1 is mounted on a submount substrate or the like using, for example, silver paste, solder, or a metal bonding material. The lower electrode 64 also functions as a connection electrode to the submount substrate or the like.

[0066] The source via 70 is an opening that penetrates the substrate 10 and the semiconductor layer 20 and includes a conductor that contacts the lower electrode 64. The source via 70 electrically connects the lower electrode 64 and the source electrode 60. The source via 70 is provided in at least one of the plurality of unit source regions 92. In this embodiment, the source vias 70 and the unit source regions 92 are provided in a one-to-one correspondence. That is, one source via 70 is provided in each of the plurality of unit source regions 92. In other words, the number of one or more source vias 70 that a unit source region 92 has is one. Only one source via 70 provided in one unit source region 92 can be called a single source via.

[0067] The source via 70 includes a conductor filled in a via hole 71 that penetrates the substrate 10, the semiconductor layer 20, and the element isolation region 30. As shown in Figures 1 and 2, the source via 70 includes a metal filling portion 72 and a metal coating 74. The metal filling portion 72 and the metal coating 74 are each an example of a conductor that contacts the lower electrode 64.

[0068] The metal filling portion 72 is a conductive member that fills the via hole 71. The metal filling portion 72 is also called a filled via. In this embodiment, the metal filling portion 72 is provided so as to completely fill the via hole 71.

[0069] The metal coating 74 is a conductive thin film that contacts and covers the side surface of the via hole 71. As shown in FIGS. 2 and 3 , the metal coating 74 further covers the upper surfaces of the semiconductor layer 20 and the element isolation region 30 at the edge portion of the opening of the via hole 71. The metal coating 74 is also called a lined via. Note that, although the cross section shown in FIG. 3 (the XZ cross section passing through the plate driving line 82) shows an example in which only the metal coating 74 is provided in the via hole 71, this is not limiting. In the XZ cross section passing through the plate driving line 82, a metal filling portion 72 may be provided as in FIG. 2 .

[0070] The source via 70 is formed by, for example, forming a via hole 71 by etching or the like, and then sequentially forming a metal coating 74 and a metal filling portion 72 by plating or the like. The via hole 71 may be formed from either the top surface side or the bottom surface side of the substrate 10.

[0071] Furthermore, the source via 70 may include only one of the metal filling portion 72 and the metal coating 74. That is, after the metal coating 74 is formed in the via hole 71, it is not necessary to fill the via hole 71 with a metal material. Alternatively, the metal filling portion 72 may be formed by filling the via hole 71 with a metal material without forming the metal coating 74 in the via hole 71.

[0072] The field plate 80 is provided above the semiconductor layer 20 and between the gate electrode 40 and the drain electrode 50 in a plan view. The field plate 80 is set to the same potential as the source electrode. The field plate 80 is provided to reduce the electric field between the gate electrode 40 and the drain electrode 50 by being fixed to the source potential.

[0073] In this embodiment, the field plate 80 is made up of a plurality of unit plates 81 facing a plurality of unit channel regions 90. The plurality of unit plates 81 can also be called split field plate electrodes obtained by splitting the field plate 80. In this embodiment, as shown in FIGS. 1 and 5 , the unit plates 81 do not overlap the gate fingers 42 in plan view, but this is not limiting. Parts of the unit plates 81 may overlap the gate fingers 42 in plan view.

[0074] The field plate 80 is formed using a conductive material. For example, the field plate 80 is a single layer or a laminate of a metal or an alloy. Examples of the metal that can be used include Al, Au, and Cu. The field plate 80 is formed into a predetermined shape by forming a film using deposition, sputtering, or the like, and then patterning the film using etching, or the like.

[0075] The plate driving lines 82 are wiring for supplying a source potential to the field plate 80. One or more plate driving lines 82 are provided for each unit plate 81. In this embodiment, as shown in FIGS. 5 and 7, two plate driving lines 82 are provided for each unit plate 81. The two plate driving lines 82 are connected to both ends of the unit plate 81 in the Y-axis direction.

[0076] The plate driving lines 82 extend in the X-axis direction from the corresponding source electrode 60 side to connect to the corresponding unit plates 81. The plate driving lines 82 electrically connect the corresponding unit plates 81 to the source connecting portions 62. The plate driving lines 82 supply a source potential to each of the unit plates 81. As shown in FIG. 3 , the plate driving lines 82 contact the metal coating 74 and the source connecting portions 62 at the ends on the source via 70 side. The source connecting portions 62 contact the upper surfaces of the plate driving lines 82, increasing the contact area and reducing the contact resistance. This stabilizes the source potential of the field plate 80, i.e., the multiple unit plates 81.

[0077] The plate driving line 82 is provided within the element isolation region 30 in plan view. Specifically, the plate driving line 82 is provided above the element isolation region 30. In this embodiment, as shown in FIGS. 3 and 7 , the plate driving line 82 is in contact with the element isolation region 30.

[0078] 3 , the plate driving line 82 is provided so as to rise toward the positive side in the Z axis direction at the end on the drain finger 52 side, and is connected to the unit plate 81 of the field plate 80 at the tip portion on the positive side in the Z axis direction.

[0079] The plate driving line 82 is formed using a conductive material. For example, the plate driving line 82 is a single layer or a laminate of a metal or an alloy. The plate driving line 82 may be formed using the same material as the field plate 80. The plate driving line 82 is formed into a predetermined shape by forming a film by vapor deposition, sputtering, or the like, and patterning by etching, or the like.

[0080] 2. Characteristic Configuration, Actions, and Effects Next, the characteristic configuration, actions, and effects of the power amplifying semiconductor device 1 according to this embodiment will be described in comparison with a comparative example.

[0081] [2-1. Configuration of the Comparative Example and Its Problems] First, the configuration of the power amplifier semiconductor device according to the comparative example and its problems will be described with reference to Fig. 8 and Fig. 9. Fig. 8 and Fig. 9 are a plan view and a cross-sectional view, respectively, of the power amplifier semiconductor device 1x according to the comparative example. Fig. 9 shows the cross section taken along line IX-IX in Fig. 8.

[0082] 8 and 9 , a power amplifier semiconductor device 1x according to the comparative example includes a substrate 10x, a semiconductor layer 20x, a gate electrode 40x, a gate bus 44x, a drain electrode 50x, a drain bus 54x, a source electrode 60x, a bottom electrode 64x, and a source via 70x. The substrate 10x, the semiconductor layer 20x, the gate bus 44x, the drain bus 54x, and the bottom electrode 64x are the same as the substrate 10, the semiconductor layer 20, the gate bus 44, the drain bus 54, and the bottom electrode 64 included in the power amplifier semiconductor device 1 according to the embodiment.

[0083] 8, in the power amplifier semiconductor device 1x according to the comparative example, the gate electrode 40x and the drain electrode 50x both extend along the Y-axis direction and are not divided, i.e., the gate electrode 40x and the drain electrode 50x have the same configuration as the gate finger 42 and the drain finger 52 of the power amplifier semiconductor device 1 according to the embodiment.

[0084] Furthermore, the power amplifying semiconductor device 1x according to the comparative example does not include the element isolation region 30. That is, the channel region of the semiconductor layer 20 is not divided into a plurality of unit channel regions 90.

[0085] The source electrodes 60x also extend along the Y-axis direction and are not divided. One source via 70x is provided at the end of each source electrode 60x on the negative side in the Y-axis direction.

[0086] In the power amplifier semiconductor device 1x, the channel region and its vicinity are heat sources. Specifically, the heat source can be considered to be the region from directly below the gate electrode 40x toward the drain electrode 50x. In Figure 8, the heat source is indicated by a thick dashed line. The heat source is the region directly below the two drain electrodes 50x sandwiching the gate electrode 40x.

[0087] 9, the spread of heat from the heat source is schematically represented by dotted hatching and open arrows. The generated heat is diffused through the semiconductor layer 20x and then spreads laterally (in the X-axis direction and the Y-axis direction) via the substrate 10x and the lower electrode 64x. The heat that reaches the lower electrode 64x is released to the outside via a submount substrate (not shown) on which the power amplifier semiconductor device 1x is mounted, or the like.

[0088] Heat generated near the gate electrode 40x diffuses in the thickness direction (Z-axis direction) of the semiconductor layer 20x and also spreads laterally (X-axis direction and Y-axis direction). The heat diffusion angle can be schematically considered to be 45°. Because the gate electrodes 40x are aligned in the X-axis direction, if heat generated near two adjacent gate electrodes 40x overlap before reaching the substrate 10x, a locally high-temperature region is created. For this reason, it is necessary to ensure a large spacing between the gate electrodes 40x in the X-axis direction (called the gate pitch). Note that in FIG. 9, the gate pitch refers to the distance (distance in the X-axis direction) between two adjacent gate electrodes 40x sandwiching a source electrode 60x therebetween, without sandwiching a drain electrode 50x therebetween.

[0089] For the above reasons, in the power amplifier semiconductor device 1x according to the comparative example, the gate pitch is increased to arrange the multiple gate electrodes 40x, which increases the length of the gate bus 44x in the X-axis direction. As the gate bus 44x becomes longer, the gate resistance Rg and parasitic inductance components increase, degrading the high-frequency characteristics of the power amplifier semiconductor device 1x. For example, the gain, efficiency, and saturation power of the power amplifier semiconductor device 1x decrease.

[0090] Furthermore, since the source via 70x is provided at the end on the negative side in the Y-axis direction, the source potential is supplied to the source electrode 60x from a biased position, which increases the likelihood of in-plane variations in the source potential, potentially causing instability in the transistor operation of the power amplifying semiconductor device 1x.

[0091] Furthermore, if a field plate is placed between the gate electrode 40x and the drain electrode 50x, the source potential supplied to the field plate also becomes unstable. The impedance of the field plate at a location far from the power supply becomes high, weakening the potential fixation of the field plate. This may result in insufficient electric field relaxation between the gate electrode 40x and the drain electrode 50x, resulting in a deterioration in the characteristics and reliability of the power amplifier semiconductor device 1x.

[0092] In order to suppress the variation in source potential, it is necessary to reduce the length of the source electrode 60x in the Y-axis direction. In this case, the gate width (channel width) becomes shorter, and therefore, in order to ensure the necessary amount of drain current, it is necessary to increase the number of sets of the gate electrode 40x, the drain electrode 50x, and the source electrode 60x. As a result, the length of the gate bus 44x in the X-axis direction becomes longer, and as described above, the high-frequency characteristics of the power amplifier semiconductor device 1x deteriorate.

[0093] The source vias 70x can also contribute to heat dissipation, details of which will be described later in the explanation of the effects of the source vias 70. However, in the power amplifier semiconductor device 1x, the source vias 70x are provided in an offset position, and therefore, they hardly contribute to improving heat dissipation.

[0094] In response to the above problems, the power amplifier semiconductor device 1 according to this embodiment is provided with a plurality of unit channel regions 90, a plurality of source vias 70 that are long in the X-axis direction, and a plurality of plate driving lines 82 that extend in the X-axis direction, thereby improving the high-frequency characteristics of the power amplifier semiconductor device 1. Note that in this embodiment, at least one of the source vias 70 and the plate driving lines 82 is not an essential component. Below, the effects of each of the unit channel regions 90, the source vias 70, and the plate driving lines 82 will be described in detail.

[0095] [2-2. Unit Channel Region] First, the effects and the like of the unit channel region 90 will be described with reference to Fig. 10. Fig. 10 is a plan view of an application example of the power amplifying semiconductor device according to the embodiment.

[0096] In the power amplifier semiconductor device 1 according to this embodiment, the unit channel region 90 and its vicinity serve as heat sources. Specifically, the heat source can be considered to be the region from directly below the gate electrode 40 toward the drain electrode 50. In the following, for ease of explanation, the unit channel region 90 may be considered to be the heat source.

[0097] In this embodiment, the unit channel regions 90 correspond one-to-one to the gate electrodes 40 and are arranged side by side along the Y-axis direction. Between two adjacent unit channel regions 90 in the Y-axis direction, an isolation region 30 that does not function as a channel, i.e., does not form a current path, is provided. Therefore, as shown by the bold dashed lines in FIG. 10 , the heat sources are also arranged separately. By arranging the heat sources separately in the Y-axis direction, the regions between adjacent heat sources (specifically, the isolation regions 30) can be used to efficiently diffuse heat. In other words, the thermal resistance in the Y-axis direction can be reduced, thereby improving the heat dissipation performance of the power amplifier semiconductor device 1. By improving heat dissipation performance, heat-induced degradation of characteristics can be suppressed.

[0098] [2-3. Source Via] Next, the effects and the like of the source via 70 will be described with reference to Fig. 10 and Fig. 11. Fig. 11 is a cross-sectional view of an application example of the power amplifier semiconductor device according to the embodiment. Specifically, Fig. 11 shows a cross section taken along line XI-XI in Fig. 10.

[0099] The source via 70 is provided in the unit source region 92 (see FIG. 5 ) facing the unit channel region 90. In other words, the source via 70 is disposed in close proximity to the heat source. Simply put, the source via 70 is disposed at a position that is the shortest distance from the heat source in the X-axis direction. As shown in FIG. 11 , heat spreading in the X-axis direction reaches the source via 70 before reaching the substrate 10. The source via 70 is formed using metal and has higher thermal conductivity than the semiconductor layer 20. Therefore, heat is efficiently conducted to the substrate 10 and the lower electrode 64 via the source via 70, thereby improving the heat dissipation performance of the power amplifier semiconductor device 1.

[0100] As a result, the gate pitch can be narrowed, thereby shortening the length in the X-axis direction of the gate bus 44. Note that the "gate pitch" refers to the distance (distance in the X-axis direction) between two adjacent gate electrodes 40 that sandwich the source electrode 60 therebetween, but not the drain electrode 50.

[0101] This reduces the gate resistance Rg and the parasitic inductance component, and suppresses deterioration of the high frequency characteristics of the power semiconductor device 1. For example, it is possible to suppress decreases in the gain, efficiency, and saturation power of the power semiconductor device 1.

[0102] 5, the source via 70 has an elongated shape in the X-axis direction in a plan view. That is, when the length of the source via 70 in the X-axis direction is Lvx and the length of the source via 70 in the Y-axis direction is Lvy, Lvx > Lvy is satisfied. This promotes the spread of heat transferred from the unit channel region 90 in the X-axis direction, thereby improving heat dissipation. Note that the length of the source via 70 in the X-axis direction is the length of the contour of the opening of the source via 70 in the X-axis direction. The length of the contour of the opening in the X-axis direction corresponds to the maximum distance in the X-axis direction of the contour of the opening on the semiconductor layer 20 side of the via hole 71 for filling the conductor (metal filling portion 72 and metal coating 74) of the source via 70. The same applies to the Y-axis direction. That is, when the term "length of the contour in a certain direction" is used, it refers to the linear distance along the certain direction, not the length along the contour.

[0103] 5, the length of the opening contour of the source via 70 in the Y-axis direction is longer than that of the corresponding unit source region 92. That is, the source via 70 is also located outside the unit source region 92. In other words, the source via 70 protrudes from the unit source region 92 in the Y-axis direction.

[0104] Specifically, when the length of the unit channel region 90 in the Y-axis direction is Lcy, Lvy > Lcy is satisfied. That is, the source via 70, which is wider than the width of the heat source, is disposed near the heat source. Therefore, of the heat generated in the unit channel region 90, the heat that spreads in the Y-axis direction can also be efficiently dissipated by the source via 70.

[0105] In this embodiment, the source vias 70 are provided in one-to-one correspondence with the unit channel regions 90. That is, one source via 70 is provided to correspond to each of the multiple heat sources. Therefore, the source vias 70 are provided without uneven distribution in the plane, and local deterioration of heat dissipation can be suppressed. Therefore, the heat dissipation of the power amplifying semiconductor device 1 can be improved.

[0106] Furthermore, the source potential can be supplied to each of the plurality of source electrodes 60 at a substantially shortest distance from the lower electrode 64. This stabilizes the source potential of each of the plurality of source electrodes 60. Furthermore, the parasitic inductance component can be reduced, thereby reducing high-frequency loss.

[0107] As described above, the power amplifier semiconductor device 1 according to this embodiment includes the substrate 10, the lower electrode 64 provided below the substrate 10, the semiconductor layer 20 provided above the substrate 10, including a plurality of active layers of Group III nitride, where a two-dimensional electron gas 22 is generated at a heterointerface of the plurality of active layers, the source electrode 60 and the drain electrode 50 provided above the semiconductor layer 20 at intervals and electrically connected to the two-dimensional electron gas 22, the gate electrode 40 provided at intervals from the source electrode 60 and the drain electrode 50 and in contact with the semiconductor layer 20, the gate finger 42 above the plurality of gate electrodes 40 aligned in a straight line in the Y-axis direction and in contact with and covering all of the gate electrodes 40, and the drain finger 52 above the plurality of drain electrodes 50 aligned in a straight line in the Y-axis direction and in contact with and covering all of the drain electrodes 50. The gate fingers 42 are aligned in the X-axis direction, which is orthogonal to the Y-axis direction, and are set to the same potential. In a plan view of the substrate 10, the semiconductor layer 20 is divided into an active region 31 containing a two-dimensional electron gas 22 and an element isolation region 30 containing no two-dimensional electron gas 22. In a plan view, the channel region, which is the overlapping portion between the active region 31 and the gate electrode 40, is divided in the Y-axis direction by the element isolation region 30 into a plurality of unit channel regions 90 arranged side by side. The source electrode 60 is a plurality of unit source electrodes facing each of the plurality of unit channel regions 90. The plurality of unit source regions 92, each including the plurality of unit source electrodes, have one or more source vias 70 that penetrate the substrate 10 and the semiconductor layer 20 and include a conductor therein that contacts a lower electrode 64 set to the same potential as the source electrode 60. In a plan view, the side length of the smallest rectangular region surrounding the one or more source vias 70 is longer in the X-axis direction than in the Y-axis direction.

[0108] As a result, since a plurality of unit channel regions 90 are arranged in the Y-axis direction, the heat sources are dispersed in the Y-axis direction, thereby improving heat dissipation in the Y-axis direction. Furthermore, since the source vias 70 are arranged in the unit source regions 92 facing the unit channel regions 90, heat dissipation in the X-axis direction can also be improved. Therefore, the heat dissipation of the power amplifier semiconductor device 1 can be improved, and characteristic degradation due to heat can be suppressed.

[0109] Furthermore, by arranging the source electrode 60 and the source via 70 close to each other, the source potential of the source electrode 60 can be stabilized. Also, the parasitic inductance component of the source wiring can be reduced. Therefore, the high-frequency loss of the power amplifying semiconductor device 1 can be reduced.

[0110] In this embodiment, the number of one or more source vias 70 is 1. In a plan view, the length of the opening contour of a source via 70 in the X-axis direction is longer than the length in the Y-axis direction. Therefore, the lengths of the X-axis direction and the Y-axis direction of the smallest rectangular region surrounding one or more source vias 70 are equal to the length Lvx in the X-axis direction and the length Lvy in the Y-axis direction of the opening contour of the source via 70 shown in FIG. 5 . Therefore, the length Lvx in the X-axis direction of the opening contour of the source via 70 is longer than the length Lvy in the Y-axis direction of the opening contour of the source via 70.

[0111] This further improves heat dissipation in the X-axis direction.

[0112] Furthermore, for example, the length of the contour of the opening of the source via 70 is longer than the length of the unit channel region 90 in the Y-axis direction.

[0113] This can further improve heat dissipation in the Y-axis direction. In addition, the increased area of ​​the source via 70 can contribute to improving the stability of the source potential and reducing the parasitic inductance component.

[0114] Furthermore, for example, one or more source vias 70 are provided in all of the unit source regions 92 .

[0115] This allows the source vias 70 to be arranged in a balanced manner within the plane, thereby suppressing localized heat concentration and suppressing in-plane variations in the source potential.

[0116] [2-4. Plate Drive Lines] Next, the effects and advantages of the plate drive lines 82 will be described.

[0117] 5, the plate driving lines 82 extend in the X-axis direction and electrically connect the source electrodes 60 to the unit plates 81 of the field plate 80. One or more plate driving lines 82 are provided on each of the unit plates 81.

[0118] As described above, the source electrode 60 is stably supplied with a source potential from the lower electrode 64 via the source via 70 and the source connector 62 provided in the corresponding unit source region 92. Therefore, a stable source potential can be supplied to each unit plate 81 by the plate driving line 82 provided for each unit plate 81. In other words, since the potential variation of the unit plates 81 in the XY plane is suppressed, the electric field between the gate electrode 40 and the drain electrode 50 can be more easily relaxed uniformly in the plane. This allows the saturation power of the power amplifier semiconductor device 1 to be increased.

[0119] Furthermore, since the source potential is supplied to the unit plates 81 from the X-axis direction, a large number of unit plates 81 can be arranged in the Y-axis direction with the source potential being more stable. That is, the length of the gate fingers 42 in the Y-axis direction can be increased. As a result, the length of the gate bus 44 in the X-axis direction can be shortened, and the number of drain fingers 52 can be reduced. Therefore, the capacitance Cds between the drain electrode 50 and the source electrode 60 can be reduced, thereby improving the efficiency performance of the power amplifying semiconductor device 1.

[0120] As described above, the power amplifier semiconductor device 1 according to the present embodiment includes: the substrate 10; the bottom electrode 64 provided below the substrate 10; the semiconductor layer 20 provided above the substrate 10, including a plurality of active layers of Group III nitride, in which a two-dimensional electron gas 22 is generated at a heterointerface of the plurality of active layers; the source electrode 60 and the drain electrode 50 provided above the semiconductor layer 20 at a distance from each other and electrically connected to the two-dimensional electron gas 22; the gate electrode 40 provided at a distance from the source electrode 60 and the drain electrode 50 and in contact with the semiconductor layer 20; the field plate 80 provided between the gate electrode 40 and the drain electrode 50 above the semiconductor layer 20 and set to the same potential as the source electrode 60; the gate finger 42 above the plurality of gate electrodes 40 arranged in a straight line in the Y-axis direction, in contact with and covering all of the gate electrodes 40; and the drain finger 52 above the plurality of drain electrodes 50 arranged in a straight line in the Y-axis direction, in contact with and covering all of the drain electrodes 50. In a plan view of the substrate 10, the semiconductor layer 20 is divided into an active region 31 having a two-dimensional electron gas 22 and an element isolation region 30 having no two-dimensional electron gas 22. In a plan view, the channel region, which is the overlapping portion between the active region 31 and the gate electrode 40, is divided into a plurality of unit channel regions 90 arranged in the Y-axis direction by the element isolation region 30. The source electrode 60 is a plurality of unit source electrodes facing each of the plurality of unit channel regions 90. The field plates 80 are a plurality of unit plates 81 facing each of the plurality of unit channel regions 90. One or more plate driving lines 82 extending in the X-axis direction perpendicular to the Y-axis direction and electrically connecting the plurality of unit source electrodes to the plurality of unit plates 81 are provided for each unit plate 81 within the element isolation region 30.

[0121] As a result, since a plurality of unit channel regions 90 are arranged in the Y-axis direction, the heat sources are dispersed in the Y-axis direction, and heat dissipation in the Y-axis direction can be improved. Therefore, the heat dissipation of the power amplifying semiconductor device 1 can be improved, and characteristic degradation due to heat can be suppressed.

[0122] Furthermore, a stable source potential can be supplied to each of the unit plates 81 from the X-axis direction via the plate driving lines 82. This reduces the impedance of the field plates 80 (unit plates 81) and suppresses potential variations in the unit plates 81 in the XY plane, making it easier to evenly relax the electric field between the gate electrode 40 and the drain electrode 50 in the plane. This increases the saturation power of the power amplifier semiconductor device 1.

[0123] Furthermore, since a large number of unit plates 81 can be arranged in the Y-axis direction while increasing the stability of the source potential, the length of the gate fingers 42 in the Y-axis direction can be increased. This allows the length of the gate bus 44 in the X-axis direction to be shortened, and the number of drain fingers 52 can be reduced. Since the capacitance Cds between the drain electrode 50 and the source electrode 60 can be reduced, the efficiency performance of the power amplifying semiconductor device 1 can be improved.

[0124] Furthermore, for example, the plate driving lines 82 are in contact with the element isolation region 30 .

[0125] As a result, the plate driving line 82 is located near the unit channel region 90 and can be used as a path for dissipating heat, thereby improving the heat dissipation performance of the power amplifying semiconductor device 1.

[0126] Furthermore, for example, the gate finger 42 is provided above and spaced apart from the plurality of plate driving lines 82 .

[0127] This makes it easier to increase the distance between the gate finger 42 and the plate drive line 82 to which the source potential is supplied, thereby reducing the gate-source capacitance Cgs. As an example, when the thickness of the plate drive line 82 is 0.2 μm, the distance between the bottom surface of the gate finger 42 and the top surface of the plate drive line 82 is 0.8 μm. Reducing the gate-source capacitance Cgs can improve the gain performance of the power amplifying semiconductor device 1.

[0128] Furthermore, by ensuring a long distance, for example, it becomes easier to increase the cross-sectional area of ​​the gate finger 42. As a result, the gate resistance Rg can be reduced, and for example, variations in the gate potential within a plane can be suppressed, thereby stabilizing the transistor operation.

[0129] Furthermore, for example, the plurality of unit source regions 92 each including a plurality of unit source electrodes have one or more source vias 70 that penetrate the substrate 10 and the semiconductor layer 20 and contain a conductor therein that contacts a lower electrode 64 that is set to the same potential as the source electrode 60.

[0130] As a result, the source via 70 is disposed in the unit source region 92 facing the unit channel region 90, thereby improving heat dissipation in the X-axis direction, thereby improving the heat dissipation of the power amplifying semiconductor device 1 and suppressing characteristic degradation caused by heat.

[0131] Furthermore, by arranging the source electrode 60 and the plate driving line 82 close to the source via 70, the source potential of the source electrode 60 and the source potential of each unit plate 81 supplied via the plate driving line 82 can be stabilized. Also, the parasitic inductance component of the source wiring can be reduced. Therefore, the high-frequency loss of the power amplifying semiconductor device 1 can be reduced.

[0132] Furthermore, for example, the unit plates 81 and the unit channel regions 90 are in one-to-one correspondence.

[0133] This makes it possible to suppress variations in the electric field relaxation performance within the surface, thereby improving the uniformity of the transistor operation of the power amplifying semiconductor device 1.

[0134] [3. Modifications] Next, a number of modifications of the power amplifying semiconductor device 1 according to the embodiment will be described. In the following description, differences from the embodiment will be mainly described, and descriptions of commonalities will be omitted or simplified.

[0135] [3-1. Modification 1] FIG. 12 is a cross-sectional view of a power amplifying semiconductor device 2 according to Modification 1. As shown in FIG.

[0136] 12 , in the power amplifier semiconductor device 2, the drain electrode 50 and the source electrode 60 each have a recess structure. Specifically, the semiconductor layer 20 is provided with recesses (concave portions) 50r and 60r that penetrate the AlGaN layer 26 and reach the GaN layer 24. The recesses 50r and 60r can be formed by etching away the GaN layer 24 and the AlGaN layer 26 to a depth at least sufficient for the generation of the two-dimensional electron gas 22. The heterointerface between the AlGaN layer 26 and the GaN layer 24 is exposed on the side surfaces of the recesses 50r and 60r, and the edge of the two-dimensional electron gas 22 is exposed.

[0137] The drain electrode 50 is provided so as to contact the side surface of the recessed portion 50r. The source electrode 60 is provided so as to contact the side surface of the recessed portion 60r. In the example shown in FIG. 12, the drain electrode 50 and the source electrode 60 are both provided so as to fill the recessed portions 50r and 60r, respectively. As a result, the drain electrode 50 and the source electrode 60 each come into contact with the two-dimensional electron gas 22, thereby reducing contact resistance and reducing resistance between the drain and source.

[0138] Alternatively, only one of the recessed portions 50r and 60r may be provided. For example, the drain electrode 50 may be disposed on the surface of the semiconductor layer 20, similar to the embodiment, without providing the recessed portion 50r. Alternatively, the source electrode 60 may be disposed on the surface of the semiconductor layer 20, without providing the recessed portion 60r.

[0139] 13A and 13B are a plan view and a cross-sectional view, respectively, of a power amplifying semiconductor device 3 according to Modification 2. Like Fig. 3, Fig. 13A shows an XZ cross section passing through the plate driving line 82.

[0140] 13, the plate driving line 82 is provided away from the element isolation region 30. Specifically, the plate driving line 82 is provided above the gate finger 42.

[0141] This makes it easier to ensure a long distance between the plate driving line 82 and the gate finger 42. This makes it possible to reduce the gate-source capacitance Cgs, thereby improving the gain characteristics of the power amplifying semiconductor device 3.

[0142] [3-3. Modification 3] FIG. 14 is a cross-sectional view of a power amplifying semiconductor device 4 according to Modification 3. As shown in FIG.

[0143] 14 , in the power amplifier semiconductor device 4, the semiconductor layer 20 includes contact layers 28d and 28s. The contact layer 28d is in contact with the drain electrode 50 and the two-dimensional electron gas 22. The contact layer 28s is in contact with the source electrode 60 and the two-dimensional electron gas 22. The contact layers 28d and 28s have lower resistance than both the GaN layer 24 and the AlGaN layer 26.

[0144] The contact layers 28d and 28s are formed by ion implantation to reduce the resistance of a portion of the semiconductor layer 20. Specifically, they are formed by ion implantation of Si or the like into a region including at least the heterointerface between the epitaxially grown GaN layer 24 and AlGaN layer 26, i.e., a region where the two-dimensional electron gas 22 is generated. Annealing is performed after the ion implantation to form the contact layers 28d and 28s.

[0145] Alternatively, the contact layers 28d and 28s may be formed by crystal regrowth after removing the epitaxially grown GaN layer 24 and AlGaN layer 26 by etching at least to a depth at which the two-dimensional electron gas 22 is generated. For example, the contact layers 28d and 28s may be low-resistance semiconductor layers epitaxially grown in the portions from which the GaN layer 24 and AlGaN layer 26 have been removed.

[0146] After the contact layers 28d and 28s are formed, the drain electrode 50 and the source electrode 60 are formed. Specifically, the drain electrode 50 is provided in contact with the upper surface of the contact layer 28d. The source electrode 60 is provided in contact with the upper surface of the contact layer 28s.

[0147] As described above, in the power amplifying semiconductor device 4 according to this modification, the semiconductor layer 20 includes the contact layer 28 s that electrically connects the two-dimensional electron gas 22 and the source electrode 60 on the surface of the semiconductor layer 20 .

[0148] In this way, the provision of the contact layer 28s shortens the effective gate-source distance Lgs, thereby reducing the source resistance. Incidentally, if the sole purpose was to shorten the gate-source distance Lgs, it would be conceivable to position the source electrode 60 itself closer to the gate electrode 40. However, in this case, the gate-source capacitance Cgs increases, deteriorating the high-frequency characteristics. According to this modification, the provision of the contact layer 28s makes it possible to reduce the source resistance while suppressing an increase in the gate-source capacitance Cgs.

[0149] Furthermore, in this modification, since the contact layer 28d is provided, the same can be said for the drain electrode 50 side. Since the field plate 80 to which the source potential is supplied is provided on the drain electrode 50 side, it is possible to reduce the drain resistance while suppressing an increase in the source-drain capacitance Cds.

[0150] It is also possible to provide only one of the contact layers 28s and 28d. For example, the contact layer 28s may be provided, but the contact layer 28d may not be provided.

[0151] [3-4. Modification 4] FIG. 15 is a cross-sectional view of a power amplifying semiconductor device 5 according to Modification 4. As shown in FIG.

[0152] 15 , the power amplifier semiconductor device 5 has a configuration in which the drain electrode 50 and source electrode 60 of the power amplifier semiconductor device 2 according to Modification 1 are combined with the contact layers 28d and 28s of the power amplifier semiconductor device 4 according to Modification 3. That is, the power amplifier semiconductor device 5 includes recessed drain electrode 50 and source electrode 60 and contact layers 28d and 28s.

[0153] In this modification, as in modification 3, the source resistance can be reduced while suppressing an increase in the gate-source capacitance Cgs. Also, the drain resistance can be reduced while suppressing an increase in the source-drain capacitance Cds.

[0154] [3-5. Modification 5] FIG. 16 is a plan view of a power amplifying semiconductor device 6 according to Modification 5. In FIG.

[0155] 16, in the power amplifier semiconductor device 6, the lengths of the element isolation regions 30 in the Y-axis direction are not uniform. Specifically, the power amplifier semiconductor device 6 includes an element isolation region 32 whose length in the Y-axis direction is different from that of the element isolation region 30. The length L of the element isolation region 32 in the Y-axis direction ＩＭ is the length L of the element isolation region 30 in the Y-axis direction ＩＮ Longer.

[0156] The element isolation region 32 is located, for example, in the center in the Y-axis direction of the power amplifier semiconductor device 6 in a plan view. In the power amplifier semiconductor device 6, heat tends to concentrate more easily in the center than on the periphery. By enlarging the element isolation region 32 in the portion where heat tends to concentrate, it is possible to alleviate heat concentration and improve heat dissipation.

[0157] 4. Modified Examples of Source Via Next, several modified examples of the source via 70 will be described with reference to FIGS.

[0158] 17 to 25 are plan views showing other examples of source vias in the power amplifier semiconductor devices according to the embodiment and the first to fifth modifications, respectively.

[0159] [4-1. Lightly Filled Source Vias] First, lightly filled source vias will be described with reference to FIG.

[0160] A lightly filled source via is a source via that does not completely fill the via hole 71 that penetrates the substrate 10 and the semiconductor layer 20, i.e., has a fill factor of less than 100%. The fill factor is the ratio of the volume of the metal material disposed in the via hole 71 to the volume of the via hole 71.

[0161] 17 , in the source via 70, the metal filling portion 72 does not completely fill the area surrounded by the metal coating 74. Specifically, the metal filling portion 72, like the metal coating 74, is provided in a ring shape along the side surface of the via hole 71 in a plan view. In other words, the source via 70 has a space 75.

[0162] The space 75 penetrates, for example, from the upper surface side of the semiconductor layer 20 to the lower surface side of the substrate 10. The opening of the space 75 on the lower surface side of the substrate 10 is covered by the lower surface electrode 64. Note that part of the metal material constituting the metal filling portion 72 or the metal coating 74 may be present discretely in the space 75. As will be described in detail later, the method for manufacturing a power amplifier semiconductor device includes a step of polishing the lower surface of the substrate 10. Part of the metal filling portion 72 or the metal coating 74 that was scraped off during polishing may remain in the space 75. The metal filling portion 72 may have a porous structure.

[0163] 17 shows an example in which the space 75 is visible in a plan view, i.e., an example in which the space 75 is open to the upper surface side of the semiconductor layer 20, but the present invention is not limited to this. The space 75 may not be open to the upper surface side of the semiconductor layer 20 and may be closed by the metal filling portion 72. In other words, the entire periphery of the space 75 may be covered by any one of the metal filling portion 72, the metal coating 74, and the lower electrode 64.

[0164] In this modification, the filling rate of the source via 70 is 50% or more. That is, the conductor inside the source via 70 occupies half or more of the opening volume of the source via 70.

[0165] This allows for improved heat dissipation by utilizing a metal member with high thermal conductivity. For example, a Si substrate has higher thermal resistance than a SiC substrate. However, by utilizing the source via 70 made of a filled metal member, heat dissipation can be improved, so that the characteristics of the power amplifier semiconductor device 1 can be fully exhibited even when a Si substrate is used as the substrate 10.

[0166] [4-2. Link Source Via] Next, the link source via will be described with reference to FIG.

[0167] A linked source via has a configuration in which two or more adjacent source vias are linked. Specifically, as shown in Fig. 18 , a via linking portion 76 is provided to link two source vias 70. Fig. 18 shows an example in which four source vias 70 are linked, but the number of linked vias is not particularly limited. For example, all source vias 70 aligned in the Y-axis direction may be linked, or N source vias 70 (N is a natural number of 2 or more) may be linked.

[0168] The method for forming the linked source vias 70 and via connection portions 76 is similar to the method for forming a plurality of separate source vias 70, except that the shapes of the via holes 71 penetrating the semiconductor layer 20 and the substrate 10 are made different. For example, after forming a via hole 71 that is elongated in the Y-axis direction and spans a plurality of unit source regions 92, the side surfaces are covered with a metal coating 74. Thereafter, by filling the area surrounded by the metal coating 74 with a metal material, the linked source vias 70 and via connection portions 76 can be formed.

[0169] As described above, the source vias 70 included in adjacent unit source regions 92 (not shown in FIG. 18 ) are connected to each other. In other words, the contours of the openings of the source vias 70, i.e., the contours of the openings of the via holes 71, are continuous in plan view.

[0170] In this way, by connecting the source vias 70, the volume occupied by the metal with high thermal conductivity can be increased, thereby further improving the heat dissipation performance.

[0171] [4-3. Group Source Vias] Next, group source vias will be described with reference to Figs. 19 to 25. Note that in Figs. 19 to 29, the via holes 71 are not shown in order to make the drawings easier to see. In each figure, the shape of the opening contour of the via hole 71 in plan view is the same as that of the source via in each figure (specifically, the same as but slightly smaller than the shape of the metal coating 74 in plan view).

[0172] The group source via has a configuration in which a plurality of source vias are provided in one unit source region 92. The plurality of source vias are arranged two-dimensionally in a plan view.

[0173] 19 to 21, a plurality of source vias 70A each having a rectangular shape elongated in the X-axis direction in plan view are provided in one unit source region 92 (not shown in the figures). Note that a portion of each of the plurality of source vias 70A may be located outside the unit source region 92.

[0174] In the example shown in Fig. 19, two source vias 70A are arranged side by side in the Y-axis direction. In the example shown in Fig. 20, four source vias 70A are arranged side by side in a matrix of two rows and two columns.

[0175] 21, five source vias 70A are arranged in a checkered pattern. Specifically, four source vias 70A are arranged diagonally around one source via 70A. No source vias 70A are arranged above, below, left, or right of the central source via 70A (on the positive and negative sides in the X-axis direction, and the positive and negative sides in the Y-axis direction).

[0176] The planar shape of the source via provided in one unit source region 92 does not have to be a rectangle elongated in the X-axis direction. In the example shown in Figures 22 and 23, a plurality of source vias 70B each having a circular shape in plan view are provided in one unit source region 92. The source vias 70B having a circular shape in plan view are free from anisotropy in shape and are therefore easy to fill with metal. This allows for increased accuracy in metal filling, which contributes to improved heat dissipation.

[0177] In the example shown in Fig. 22, ten source vias 70B are arranged in a matrix of two rows and five columns. In the example shown in Fig. 23, eleven source vias 70B are arranged such that the center positions of each row are shifted in the X-axis direction. Specifically, the source vias 70B are arranged such that connecting the centers of three adjacent source vias 70B forms an isosceles triangle.

[0178] 21 and 23 are examples of staggered arrangements. A staggered arrangement means that two adjacent source vias are arranged with a shift in at least one of the x-axis direction and the y-axis direction. The amount of shift may be small enough that two adjacent source vias face each other partially, or large enough that two adjacent source vias do not face each other completely (do not overlap when viewed from one direction). Not only may the source vias be arranged with a shift from one another, but sets of a plurality of source vias arranged in a matrix may also be arranged in a staggered manner.

[0179] 19 to 23 show examples in which the multiple source vias included in one unit source region 92 have the same shape and size, but this is not limiting. The multiple source vias included in one unit source region 92 may include source vias with different shapes and sizes.

[0180] 24, four source vias 70A each having a rectangular shape that is long in the X-axis direction in a plan view and one source via 70C each having a rectangular shape that is long in the Y-axis direction in a plan view are arranged side by side. The four source vias 70A are arranged in a matrix of two rows and two columns, and the source via 70C is disposed between the columns.

[0181] 25, nine source vias 70A and two source vias 70C are arranged side by side. The nine source vias 70A are arranged in a matrix of three rows and three columns, with one source via 70C disposed between each of the columns.

[0182] As described above, for example, the unit source region 92 may have a plurality of source vias 70A, 70B, or 70C. In this case, the minimum rectangular region 94 is a region that surrounds all of the source vias 70A, 70B, or 70C provided in the unit source region 92 in plan view.

[0183] This reduces the size of each of the source vias 70A, 70B, and 70C, making it easier to fill them with metal. By increasing the metal filling rate of each of the source vias 70A, 70B, and 70C, it is possible to further improve heat dissipation.

[0184] 19 to 25, a thick two-dot chain line indicates a minimum rectangular region 94. The minimum rectangular region 94 is a rectangular region that surrounds all of the source vias 70A, 70B, and / or 70C that are at least partially included in one unit source region 92, has sides parallel to the X-axis direction and the Y-axis direction, and is the region with the smallest area.

[0185] The length of the minimum rectangular region 94 in the X-axis direction is defined as Lmx, and the length of the minimum rectangular region 94 in the Y-axis direction is defined as Lmy. In this case, Lmx>Lmy holds. This allows for improved heat dissipation in the X-axis direction, similar to the case of a single source via (specifically, source via 70).

[0186] Furthermore, for example, one or more source vias 70A, 70B, or 70C are arranged in a two-dimensional array in a plan view.

[0187] This makes it possible to prevent localized heat concentration and improve heat dissipation.

[0188] 19 to 25 merely illustrate examples of the shape and arrangement of each of the multiple source vias, and are not limited to these examples. A source via having a rectangular shape in plan view may have a long side that is not parallel to the X-axis or Y-axis, and may have a long side that extends in a direction that intersects the X-axis or Y-axis at an angle. The shape of each of the multiple source vias may be a polygon other than a rectangle, such as a square or hexagon, or may be an ellipse. The multiple source vias may not be arranged regularly, but may be arranged randomly. For example, the total area of ​​the source vias within a unit source region 92 in plan view may be more than half, or less than half, of the unit source region 92. The number, shape, arrangement, etc. of the source vias may be changed as appropriate based on factors such as ease of processing.

[0189] 5. Modified Examples of Plate Drive Lines Next, several modified examples of the plate drive lines 82 will be described with reference to FIGS.

[0190] 26 to 29 are plan views showing other examples of plate driving lines in the power amplifying semiconductor devices according to the embodiment and the first to fifth modifications, respectively.

[0191] 26 , a connecting wire 84 is provided to connect two adjacent unit plates 81 of the multiple unit plates 81 of the field plate 80. The connecting wire 84 is disposed between the gate finger 42 and the drain finger 52. The connecting wire 84 is arranged alongside the unit plates 81 of the field plate 80 in the Y-axis direction. The length of the connecting wire 84 in the X-axis direction is the same as the length of the unit plates 81 in the X-axis direction.

[0192] The connecting wire 84 is formed using a conductive material. For example, the connecting wire 84 can be formed integrally with the plate driving line 82 using the same material. Alternatively, the connecting wire 84 can be formed integrally with the field plate 80 using the same material. In other words, the connecting wire 84 can be considered to be part of the plate driving line 82 or part of the field plate 80.

[0193] 27 is a configuration in which the number of plate driving lines 82 per unit plate 81 is reduced by one from the example shown in FIG. 26. That is, there is a one-to-one correspondence between the unit plates 81 and the plate driving lines 82. By reducing the number of plate driving lines 82, it is possible to reduce the gate-source capacitance Cgs. By reducing the gate-source capacitance Cgs, it is possible to improve the gain performance of the power amplifier semiconductor device.

[0194] As described above, the power amplifier semiconductor device according to the embodiment or each modification may include the connecting wire 84 that connects two adjacent unit plates 81. The connecting wire 84 may be located between the gate finger 42 and the drain finger 52 in plan view.

[0195] By connecting a plurality of unit plates 81 in the Y-axis direction, it is possible to reduce the wiring resistance of the field plate 80. This makes it easier to maintain the uniformity of the source potential of the field plate 80 within its surface.

[0196] 28 differs from the example shown in Fig. 26 in the position of the connecting wire 84. Specifically, the connecting wire 84 is provided on the opposite side of the gate finger 42 from the drain finger 52. Specifically, the connecting wire 84 is provided so as to come into contact with the source connecting portion 62.

[0197] This increases the area that contributes to heat dissipation, thereby further improving the heat dissipation effect.

[0198] 28, the position of the source via 70 may be different. Specifically, as shown in FIG. 29, the center position of the source via 70 is the same as the center position of the element isolation region 30 between adjacent unit channel regions 90 in the Y-axis direction. Specifically, the center of the source via 70 in the Y-axis direction and the center of the element isolation region 30 in the Y-axis direction are located on a straight line L extending in the X-axis direction. In this case, the connecting wiring 84 is in contact with the source via 70.

[0199] This allows the heat diffused through the connecting wires 84 to be easily transferred to the source vias 70, further improving the heat dissipation effect.

[0200] In the examples shown in Figures 26 to 29, the source via 70 may be a low-fill source via as shown in Figure 17, a linked source via as shown in Figure 18, or a group source via as shown in Figures 19 to 25.

[0201] [6. Manufacturing Method] Next, a method for manufacturing a power amplifier semiconductor device according to the above-described embodiment and each modification will be described with reference to Figures 30A to 30H. Figures 30A to 30H are cross-sectional views illustrating each step of the method for manufacturing a power amplifier semiconductor device according to the embodiment and each modification. Each cross-sectional view shows a cross section corresponding to line II-II in Figure 1, i.e., a cross section passing through the source electrode 60, gate electrode 40, and drain electrode 50. The film thicknesses, materials, etc. used in the following description are merely examples and are not limited to the examples shown.

[0202] First, as shown in Fig. 30A, a semiconductor layer 20 is formed on the main surface of a substrate 10. The semiconductor layer 20 is formed by forming a GaN-based semiconductor film by epitaxial growth while adjusting the film formation conditions. The substrate 10 used to form the semiconductor layer 20 is thicker than the substrate 10 after manufacture, and has a thickness of, for example, 1000 µm. The film thickness of the semiconductor layer 20 is, for example, 2 µm.

[0203] Although not shown in the figure, the element isolation region 30 is formed by implanting ions into predetermined regions of the grown semiconductor layer 20. The contact layers 28d and 28s shown in FIG. 14 and the like may also be formed by implanting ions into predetermined regions of the grown semiconductor layer 20.

[0204] Next, as shown in FIG. 30B , the gate electrode 40, the drain electrode 50, the source electrode 60, the gate finger 42, and the field plate 80 are formed. For example, a metal film is formed by vapor deposition or sputtering, and then patterned into a predetermined shape by etching, thereby forming the gate electrode 40, the drain electrode 50, the source electrode 60, the gate finger 42, and the field plate 80. The electrodes and the like may be formed using a lift-off method. When the same metal material can be used for the drain electrode 50 and the source electrode 60, they can be formed in the same process. Before forming each of the gate finger 42 and the field plate 80, an insulating film (not shown) is formed by plasma CVD (chemical vapor deposition) or the like. The thickness of the electrodes and the like is, for example, 0.2 μm. After the electrodes and the like are formed, an insulating film for protecting the electrodes and the like may be formed by plasma CVD or the like.

[0205] Next, as shown in FIG. 30C , via holes 71 are formed. The via holes 71 are formed by, for example, etching. The via holes 71 are formed so as to penetrate the semiconductor layer 20 and dig into at least a portion of the substrate 10. The depth of the via holes 71 is, for example, 150 μm. The shape of the via holes 71 in plan view is, for example, a rectangle with short sides of 20 μm or less. The shape and number of the via holes 71 are adjusted depending on the shape and number of the source vias 70. In addition to the example shown in FIG. 1 , examples such as those shown in FIGS. 18 to 25 can also be applied.

[0206] Next, as shown in FIG. 30D , a metal coating 74 is formed along the side surface of the via hole 71. The metal coating 74 is formed by, for example, plating. As an example, an Au film having a thickness of 5 μm is formed. The metal coating 74 is formed with a substantially uniform thickness along the side surface and bottom surface of the via hole 71. The metal coating 74 is also provided on the edge portion of the opening of the via hole 71 on the semiconductor layer 20 side. In the example shown in FIG. 30D , the metal coating 74 is in contact with the source electrode 60, but it does not have to be in contact with the source electrode 60.

[0207] Next, as shown in FIG. 30E , a metal filling portion 72 is formed. The metal filling portion 72 is formed by, for example, plating. As an example, an Au film or Cu film with a thickness of 5 μm is formed. This allows a via hole 71 with a short side of 20 μm to be filled. The via hole 71 can be filled by adjusting the film thickness of the metal coating 74 and the metal filling portion 72 according to the size of the via hole 71. As shown in FIG. 17 , it is not necessary to completely fill the via hole 71, so the metal coating 74 and the metal filling portion 72 may be formed with a constant film thickness regardless of the size of the via hole 71. This forms the source via 70.

[0208] 30E , the drain finger 52 and the source coupling portion 62 are formed in the same process as the formation of the metal filling portion 72. The source coupling portion 62 is formed integrally with the metal filling portion 72. In this case, a recess recessed downward from the upper surface may be formed in the portion of the upper surface of the source coupling portion 62 that overlaps with the via hole 71 in plan view. In other words, the upper surface of the source coupling portion 62 does not have to be flat in the portion that overlaps with the via hole 71 in plan view.

[0209] Next, as shown in Fig. 30F, the lower surface (back surface) of the substrate 10 is polished until at least the source via 70 is exposed. For example, polishing is performed until the thickness from the upper surface of the semiconductor layer 20 to the lower surface of the substrate 10 is about 100 µm. This makes it possible to reduce the thickness of the power amplifier semiconductor device.

[0210] Next, as shown in FIG. 30G , a lower electrode 64 is formed. For example, a metal film made of a metal element or alloy containing at least one of Ti, Ni, Cr, W, Au, and Ag is formed as the lower electrode 64 by vapor deposition, plating, or the like so as to cover the entire lower surface of the substrate 10. Because the source vias 70 are exposed on the lower surface of the substrate 10 by the polishing process, contact and electrical conduction between the lower electrode 64 and the source vias 70 is achieved. The film thickness of the lower electrode 64 is, for example, approximately 1 μm. As an example, the lower electrode 64 is formed as a metal laminate in which, from the substrate 10 side, a Ti film having a thickness of 100 nm, a Ni film having a thickness of 600 nm, and an Au film having a thickness of 200 nm are stacked in this order.

[0211] Through the above steps, the power amplifying semiconductor device according to the above-described embodiment and each of the modifications is manufactured.

[0212] The manufactured power amplifier semiconductor device may be packaged as needed, as shown in Fig. 30H. Specifically, the device is fixed to a package material made of resin, metal, ceramic, or the like, using a die bond material 66 such as AuSn or Ag.

[0213] Other Embodiments While the power amplifier semiconductor device according to one or more aspects has been described above based on the embodiments and modifications, the present disclosure is not limited to these embodiments, etc. As long as it does not deviate from the gist of the present disclosure, various modifications that a person skilled in the art can make to the present embodiments and embodiments constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0214] For example, although an example has been shown in which a plurality of gate electrodes 40, drain electrodes 50, and source electrodes 60 are arranged side by side in the Y-axis direction, this is not limiting. In other words, the gate electrodes, drain electrodes, and source electrodes do not have to be divided in the Y-axis direction. For example, the plurality of gate electrodes 40 arranged side by side in the Y-axis direction may be a single gate electrode connected to one another. In other words, a single gate electrode may be arranged not only on the semiconductor layer 20 but also on the element isolation region 30. The same applies to the drain electrodes 50 and the source electrodes 60.

[0215] Although an example has been shown in which one source via 70 or multiple source vias 70A, 70B, or 70C are provided in all of the multiple unit source regions 92, this is not limiting. There may be a unit source region 92 in which no source via 70, 70A, 70B, or 70C is provided.

[0216] Alternatively, a source via may not be provided in any of the unit source regions 92. For example, as in the power amplifying semiconductor device 1x according to the comparative example, the source via 70x may be provided outside the source region.

[0217] Although the source vias 70, 70A, 70B, and 70C each include the metal filling portion 72 and the metal coating 74, the present invention is not limited to this. The source vias 70, 70A, 70B, and 70C may include only the metal filling portion 72 or only the metal coating 74.

[0218] Furthermore, when the plurality of unit plates 81 are connected to each other, it is not necessary to provide the plurality of plate driving lines 82. In other words, the source potential may be supplied to each of the plurality of unit plates 81 along the Y-axis direction.

[0219] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0220] The present disclosure can be used as a power amplifier semiconductor device that can suppress characteristic degradation caused by heat, and can be used, for example, as a high-frequency transistor or in various electronic devices such as communication devices.

[0221] 1, 2, 3, 4, 5, 6 Power amplifier semiconductor device 10 Substrate 20 Semiconductor layer 22 Two-dimensional electron gas 24 GaN layer 26 AlGaN layer 28d, 28s Contact layer 30, 32 Element isolation region 31 Active region 40 Gate electrode 42 Gate finger 44 Gate bus 50 Drain electrode 50r, 60r Recessed portion 52 Drain finger 54 Drain bus 60 Source electrode 62 Source connecting portion 64 Lower electrode 66 Dice bond material 70, 70A, 70B, 70C Source via 71 Via hole 72 Metal filling portion 74 Metal coating 75 Space 76 Via connecting portion 80 Field plate 81 Unit plate 82 Plate drive line 84 Connecting wiring 90 Unit channel region 92 Unit source region 94 minimum rectangular area

Claims

1. A substrate; a lower electrode provided below the substrate; a semiconductor layer provided above the substrate, the semiconductor layer including a plurality of active layers made of Group III nitride, the two-dimensional electron gas being generated at a heterointerface of the plurality of active layers; a source electrode and a drain electrode disposed above the semiconductor layer in a spaced relationship, the source electrode and the drain electrode being electrically connected to the two-dimensional electron gas; a gate electrode provided at a distance from the source electrode and the drain electrode and in contact with the semiconductor layer; a field plate provided between the gate electrode and the drain electrode above the semiconductor layer and set to the same potential as the source electrode; a gate finger that is above the plurality of gate electrodes that are linearly arranged in a first direction and that contacts and covers all of the plurality of gate electrodes; a drain finger that is in contact with and covers all of the drain electrodes arranged linearly in the first direction above the drain electrodes, the semiconductor layer is divided into an active region in which the two-dimensional electron gas is present and an element isolation region in which the two-dimensional electron gas is not present, when viewed from above the substrate; a channel region, which is an overlapping portion between the active region and the gate electrode in the plan view, is a plurality of unit channel regions that are divided by the element isolation region and arranged in the first direction, the source electrode includes a plurality of unit source electrodes facing the plurality of unit channel regions, the field plate includes a plurality of unit plates facing the plurality of unit channel regions, a plurality of plate driving lines extending in a second direction perpendicular to the first direction and electrically connecting the plurality of unit source electrodes to the plurality of unit plates, respectively, are provided within the element isolation region, one or more for each of the unit plates; a connecting wire for connecting two adjacent unit plates to each other among the plurality of unit plates; the connecting wire is located between the gate finger and the drain finger in the plan view; Semiconductor device for power amplification.

2. the plate driving lines are in contact with the element isolation region; 2. The power amplifier semiconductor device according to claim 1.

3. The gate finger is provided above and spaced apart from the plate drive lines.

2. The power amplifier semiconductor device according to claim 1.

4. a plurality of unit source regions each including the plurality of unit source electrodes each have one or more source vias each having an opening penetrating the substrate and the semiconductor layer and including a conductor therein contacting the lower electrode set to the same potential as the source electrode; 2. The power amplifier semiconductor device according to claim 1.

5. a center position of the source via and a center position of the element isolation region between adjacent unit channel regions are the same in the first direction; 5. The power amplifying semiconductor device according to claim 4.

6. The semiconductor layer includes a contact layer that electrically connects the two-dimensional electron gas and the source electrode on a surface of the semiconductor layer.

2. The power amplifier semiconductor device according to claim 1.

7. The unit plates and the unit channel regions are in one-to-one correspondence.

2. The power amplifier semiconductor device according to claim 1.