Nitride semiconductor device

Abstract

This nitride semiconductor device (10) comprises: an electron transit layer (16); an electron supply layer (18) provided on the electron transit layer (16); a gate layer (22) provided on the electron supply layer (18); a gate electrode (24) which makes contact with the gate layer (22); and a drain electrode (34) and a source electrode (32) electrically connected to a two-dimensional electron gas (20) in the electron transit layer (16). The gate layer (22) includes a trench (50) provided as a recess in an upper surface (22S) of the gate layer (22) in a region making contact with the gate electrode (24). The trench (50) includes a trench opening end (52E), a trench bottom surface (54), and a curved surface (56) that is continuous with the trench bottom surface (54) and that curves from the trench bottom surface (54) toward the trench opening end (52E).

Description

nitride semiconductor devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conductive path (channel). Power devices using HEMTs are recognized as devices that enable lower on-resistance and higher speed / frequency operation compared to typical silicon (Si) power devices.

[0003] For example, a nitride semiconductor HEMT includes an electron transit layer formed of a gallium nitride (GaN) layer and an electron supply layer formed of an aluminum gallium nitride (AlGaN) layer. A 2DEG is formed in the electron transit layer near the heterojunction interface between the electron transit layer and the electron supply layer. In a normally-off HEMT, for example, a semiconductor layer containing acceptor impurities (e.g., a p-type GaN layer) is provided as a gate layer on the electron transit layer directly below the gate electrode. In this configuration, a depletion layer extending downward from the gate layer eliminates the channel directly below the gate layer, thereby achieving a normally-off state. Patent Document 1 discloses such a normally-off nitride semiconductor HEMT.

[0004] Japanese Patent Application Laid-Open No. 2017-73506

[0005] In nitride semiconductor HEMTs, for example, when a positive voltage is applied to the gate electrode, an electric field locally concentrates in a portion of the gate layer near the edge of the gate electrode. Such local electric field concentration can cause crystal defects in the gate layer and ultimately crystal destruction, resulting in a decrease in gate breakdown voltage. Therefore, there is a need to alleviate the local electric field concentration.

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes: an electron transit layer made of a nitride semiconductor; an electron supply layer disposed on the electron transit layer and made of a nitride semiconductor having a band gap larger than that of the electron transit layer so as to generate two-dimensional electron gas in the electron transit layer; a gate layer disposed on the electron supply layer and made of a nitride semiconductor containing acceptor-type impurities; a gate electrode in contact with the gate layer; and a source electrode and a drain electrode electrically connected to the two-dimensional electron gas. The gate layer includes a trench recessed in an upper surface of the gate layer in a region in contact with the gate electrode. The trench includes a trench opening edge, a trench bottom, and a curved surface that is continuous with the trench bottom and curves from the trench bottom toward the trench opening edge.

[0007] A nitride semiconductor device according to one aspect of the present disclosure can alleviate local electric field concentration.

[0008] FIG. 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a first embodiment. FIG. 2 is a partially enlarged cross-sectional view of the nitride semiconductor device of FIG. 1 , showing an exemplary structure of a gate layer and gate electrode having a trench. FIG. 3 is a partially enlarged cross-sectional view of FIG. 2 . FIG. 4 is a partially enlarged cross-sectional view showing a possible structure of a gate electrode. FIG. 5 is a diagram showing a simulation result of the electric field distribution (equipotential lines) around the gate electrode of the nitride semiconductor device of FIG. 1 . FIG. 6 is a diagram showing a simulation result of the electric field distribution (equipotential lines) around the gate electrode of a typical nitride semiconductor device including a gate layer without a trench. FIG. 7 is a graph showing the gate breakdown voltage characteristics of the nitride semiconductor device of FIG. 1 and the nitride semiconductor device of FIG. 6 . FIG. 8 is a graph showing the maximum electric field strength of the nitride semiconductor device of FIG. 1 and the nitride semiconductor device of FIG. 6 . FIG. 9 is a graph showing the relationship between the protrusion width of the gate electrode (protrusion), the trench depth, and the maximum electric field strength in the nitride semiconductor device of FIG. 1 . Fig. 10 is a graph showing the relationship between the protrusion width of the gate electrode (protrusion), the radius of curvature of the curved surface, and the maximum electric field strength in the nitride semiconductor device of Fig. 1. Fig. 11 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a second embodiment, showing a case where the trench wall surface of the gate layer includes a vertical surface. Fig. 12 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the second embodiment, showing a case where the trench wall surface of the gate layer includes an inclined surface. Fig. 13 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the second embodiment, showing a case where the trench wall surface of the gate layer includes a more gently inclined surface.

[0009] Hereinafter, several embodiments of a semiconductor device according to the present disclosure will be described with reference to the accompanying drawings. Note that components shown in the drawings may be partially enlarged for clarity and understanding, and are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10 according to a first embodiment. First, the overall structure of the nitride semiconductor device 10 will be described below with reference to FIG.

[0012] [Overall Structure of Nitride Semiconductor Device] The nitride semiconductor device 10 may be configured as a high electron mobility transistor (HEMT) using a nitride semiconductor such as gallium nitride (GaN), for example. The nitride semiconductor device 10 includes a substrate 12, a buffer layer 14 formed on the substrate 12, an electron transit layer 16 formed on the buffer layer 14, and an electron supply layer 18 formed on the electron transit layer 16.

[0013] The substrate 12 may be formed of silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), GaN, sapphire, or other substrate materials. For example, the substrate 12 is a Si substrate. The thickness of the substrate 12 may be, for example, 200 μm or more and 1500 μm or less. Note that the Z direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1 is a direction orthogonal to the main surface of the substrate 12. As used herein, the term "plan view" refers to viewing the nitride semiconductor device 10 from above along the Z direction, unless explicitly stated otherwise.

[0014] The buffer layer 14 is located between the substrate 12 and the electron transit layer 16 and may be formed of any material that can alleviate the lattice mismatch between the substrate 12 and the electron transit layer 16. For example, the buffer layer 14 may include one or more nitride semiconductor layers. For example, the buffer layer 14 may include at least one of an AlN layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 14 may be formed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0015] In one example, the buffer layer 14 includes a first buffer layer formed on the substrate 12 and a second buffer layer formed on the first buffer layer. The first buffer layer is, for example, an AlN layer and may have a thickness of, for example, about 200 nm. The second buffer layer includes, for example, a plurality of AlGaN layers, each of which may have a thickness of, for example, about 100 nm. Note that, in order to suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make it semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 １６ cm －３ It may be more than that.

[0016] The electron transit layer 16 is made of a nitride semiconductor, and may be, for example, a GaN layer. The electron transit layer 16 may have a thickness of, for example, 0.5 μm or more and 2 μm or less. In order to suppress leakage current in the electron transit layer 16, an impurity may be introduced into a portion of the electron transit layer 16 to make the electron transit layer 16 semi-insulating except for the surface region. In this case, the impurity may be, for example, C, and the impurity concentration may be, for example, 1×10 at a peak concentration. １９ cm －３ It may be more than that.

[0017] The electron supply layer 18 is made of a nitride semiconductor having a larger band gap than the electron transit layer 16, and may be, for example, an AlGaN layer. In the case of an AlGaN layer, the band gap increases as the Al composition increases, so the electron supply layer 18, which is an AlGaN layer, has a larger band gap than the electron transit layer 16, which is a GaN layer. For example, the electron supply layer 18 may be made of an Al ｘ Ga １－ｘ The electron supply layer 18 is made of N, and although not necessarily limited thereto, x satisfies 0.1<x<0.4, and more preferably 0.2<x<0.3. The electron supply layer 18 may have a thickness of, for example, 5 nm or more and 20 nm or less.

[0018] The electron transit layer 16 and the electron supply layer 18 are made of nitride semiconductors with different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transit layer 16 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 18 form a lattice-mismatched junction. Due to spontaneous polarization of the electron transit layer 16 and the electron supply layer 18 and piezoelectric polarization caused by stress on the heterojunction of the electron supply layer 18, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 20 spreads within the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 (e.g., at a distance of about several nanometers from the interface).

[0019] The nitride semiconductor device 10 further includes a gate layer 22 formed on the electron supply layer 18, a gate electrode 24 formed on the gate layer 22, and a passivation layer 26. The passivation layer 26 covers the electron supply layer 18, the gate layer 22, and the gate electrode 24.

[0020] The gate layer 22 is formed on the electron supply layer 18 using a nitride semiconductor containing acceptor-type impurities. The gate layer 22 may be made of any material having a band gap smaller than that of the electron supply layer 18. For example, when the electron supply layer 18 is an AlGaN layer, the gate layer 22 may be a GaN layer doped with acceptor-type impurities, i.e., a p-type GaN layer. The acceptor-type impurities may include, for example, at least one of zinc (Zn), magnesium (Mg), and carbon (C). The acceptor-type impurities may be, for example, 7×10 １８ cm －３ 1x10 or more ２０ cm －３ It may have the following maximum concentrations:

[0021] The gate electrode 24 forms a Schottky junction with the gate layer 22. The gate electrode 24 is composed of one or more metal layers, and may be, for example, a titanium nitride (TiN) layer. Alternatively, the gate electrode 24 may be composed of a first metal layer (e.g., a Ti layer) and a second metal layer (e.g., a TiN layer) provided on the first metal layer. The thickness of the gate electrode 24 from the upper surface 22S of the gate layer 22 to the upper surface of the gate electrode 24 may be, for example, 50 nm or more and 300 nm or less. In a structure in which a nitride semiconductor layer containing acceptor-type impurities is provided as the gate layer 22 directly below the gate electrode 24, the presence of the acceptor-type impurities in the gate layer 22 causes the channel (2DEG 20) in the electron transit layer 16 to disappear. This results in a normally-off nitride semiconductor HEMT.

[0022] The passivation layer 26 is, for example, a silicon nitride (SiN) film, a silicon dioxide (SiO ２ ) film, silicon oxynitride (SiON) film, alumina (Al ２ O ３ The substrate is composed of a single film selected from the group consisting of an aluminum oxynitride (AlON) film, an AlN film, and an aluminum oxynitride (AlON) film, or a composite film containing any combination of two or more of these films.

[0023] The passivation layer 26 includes a first opening 26A that exposes the upper surface of the electron supply layer 18 as a source connection region 18A and a second opening 26B that exposes the upper surface of the electron supply layer 18 as a drain connection region 18B. The gate layer 22 is located between the first opening 26A and the second opening 26B.

[0024] The nitride semiconductor device 10 further includes a source electrode 32 and a drain electrode 34. The source electrode 32 is in contact with the source connection region 18A of the electron supply layer 18 through a first opening 26A of the passivation layer 26, and is in ohmic contact with the 2DEG 20 immediately below the electron supply layer 18. The drain electrode 34 is in contact with the drain connection region 18B of the electron supply layer 18 through a second opening 26B of the passivation layer 26, and is in ohmic contact with the 2DEG 20 immediately below the electron supply layer 18.

[0025] The source electrode 32 and the drain electrode 34 are each made of one or more metal layers, for example, a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, or an AlCu layer, or are made of the same material.

[0026] 1, the gate layer 22 may have a step structure, although it is not necessarily limited to this configuration. In one example, the gate layer 22 includes a ridge portion 42 and a source side extension portion 44 and a drain side extension portion 46 extending in opposite directions from either side of the ridge portion 42. The step structure of the gate layer 22 is formed by the ridge portion 42, the source side extension portion 44, and the drain side extension portion 46.

[0027] The ridge portion 42 corresponds to a relatively thick portion of the gate layer 22. The gate electrode 24 is in contact with the ridge portion 42. The ridge portion 42 may have a rectangular or trapezoidal shape in a cross section taken along the XZ plane in FIG. 1 . The ridge portion 42 may have a thickness of, for example, 100 nm or more and 200 nm or less. The thickness of the ridge portion 42 refers to the distance from the upper surface of the ridge portion 42 to the lower surface (the lower surface of the gate layer 22 in contact with the electron supply layer 18). The thickness of the ridge portion 42 (gate layer 22) can be determined taking into consideration various parameters such as gate breakdown voltage.

[0028] The source-side extension 44 extends from the ridge 42 toward the first opening 26A of the passivation layer 26 (in the −X direction in FIG. 1 ). The drain-side extension 46 extends from the ridge 42 toward the second opening 26B of the passivation layer 26 (in the +X direction in FIG. 1 ). In the example of FIG. 1 , the drain-side extension 46 extends further from the ridge 42 than the source-side extension 44. However, the source-side extension 44 and the drain-side extension 46 may have the same length. The source-side extension 44 may have a length of, for example, 0.2 μm or more and 0.3 μm or less in the direction from the ridge 42 toward the first opening 26A. The drain-side extension 46 may have a length of, for example, 0.2 μm or more and 0.6 μm or less in the direction from the ridge 42 toward the second opening 26B. The source side extension 44 and the drain side extension 46 may have a thickness of, for example, 5 nm or more and 30 nm or less.

[0029] A portion of the source electrode 32 is filled in the first opening 26 A of the passivation layer 26 , and a portion of the drain electrode 34 is filled in the second opening 26 B of the passivation layer 26 .

[0030] Although the source electrode 32 is not necessarily limited to this configuration, it may include a source electrode portion 32A and a source field plate portion 32B continuous with the source electrode portion 32A. The source electrode portion 32A includes a filling region filled in the first opening 26A and an upper region formed integrally with the filling region and located around the first opening 26A in a plan view. The source field plate portion 32B is formed integrally with the upper region of the source electrode portion 32A and is provided on the passivation layer 26 so as to cover the entire gate layer 22 in a plan view (in the example of FIG. 1 , all of the ridge portion 42, the source-side extension portion 44, and the drain-side extension portion 46).

[0031] The source field plate portion 32B has an end portion 32C near the drain electrode 34. This end portion 32C is located between the drain electrode 34 and the drain-side extension portion 46 in a plan view. When a high voltage is applied between the source and the drain with the gate-source voltage at 0 V, the source field plate portion 32B extends a depletion layer toward the 2DEG 20 directly below the source field plate portion 32B, thereby playing a role in alleviating electric field concentration near the end portion of the gate electrode 24 and the end portion of the gate layer 22.

[0032] [Exemplary Structure of Gate Layer and Gate Electrode Having Trench] Figure 2 is a partially enlarged cross-sectional view of the nitride semiconductor device 10 of Figure 1. As shown in Figure 2, the gate layer 22 includes a trench 50 recessed in the upper surface 22S of the gate layer 22 in a region in contact with the gate electrode 24. The trench 50 includes a trench opening end 52E, a trench bottom surface 54, and a curved surface 56 that is continuous with the trench bottom surface 54 and curves from the trench bottom surface 54 toward the trench opening end 52E. The shape of the trench 50 is not particularly limited, but in the example of Figure 2, the trench 50 is formed in a bowl shape in cross section.

[0033] The trench opening end 52E of the trench 50 includes a first end 52EA and a second end 52EB that face each other in a first direction. The first direction is the direction in which the source electrode 32 (first opening 26A), gate layer 22, and drain electrode 34 (second opening 26B) are aligned in FIG. 1 , corresponding to the X-direction in FIG. 1 . The trench 50 has a trench width W1 corresponding to the distance between the first end 52EA and the second end 52EB in the first direction. The curved surface 56 of the trench 50 includes a first curved surface 56A that curves from the trench bottom 54 toward the first end 52EA and a second curved surface 56B that curves from the trench bottom 54 toward the second end 52EB. The gate electrode 24 has a gate electrode length L1 in the first direction. The trench 50 (gate layer 22) and the gate electrode 24 are configured so that the trench width W1 is equal to or less than the gate electrode length L1.

[0034] The gate electrode 24 includes an upper electrode portion 62 and a lower electrode portion 64. The lower electrode portion 64 corresponds to a lower region of the gate electrode 24 that fills the trench 50. The upper electrode portion 62 corresponds to an upper region of the gate electrode 24 that is formed integrally with the lower electrode portion 64 and is located above the position of the upper surface 22S of the gate layer 22.

[0035] 2 , the trench width W1 is less than the gate electrode length L1. In this case, the upper electrode portion 62 includes a protrusion 66 that protrudes laterally from the trench opening edge 52E along the upper surface 22S of the gate layer 22. The protrusion 66 includes a first protrusion 66A that protrudes laterally from a first end 52EA of the trench opening edge 52E along the upper surface 22S of the gate layer 22, and a second protrusion 66B that protrudes laterally from a second end 52EB of the trench opening edge 52E along the upper surface 22S of the gate layer 22.

[0036] 2, the gate electrode 24 includes a first electrode end 24EA and a second electrode end 24EB that contact the upper surface 22S of the gate layer 22. Note that, hereinafter, when there is no need to distinguish between the first electrode end 24EA and the second electrode end 24EB, they will be collectively referred to as the electrode end 24E. The first electrode end 24EA corresponds to the lower end of the side surface 66SA of the first protrusion 66A, and the second electrode end 24EB corresponds to the lower end of the side surface 66SB of the second protrusion 66B.

[0037] 3 and 4, the structural relationship between the trench 50 (gate layer 22) and the gate electrode 24 will be described. Fig. 3 is a partially enlarged cross-sectional view of Fig. 2. Fig. 4 is a partially enlarged cross-sectional view showing possible structures of the gate electrode 24.

[0038] 3, the trench 50 has a depth D1, and the first curved surface 56A (curved surface 56) has a radius of curvature R1. Note that while FIG. 3 shows the first curved surface 56A, the same applies to the second curved surface 56B. The depth D1 corresponds to the distance from the trench opening end 52E to the trench bottom surface 54 in a direction perpendicular to the top surface 22S of the gate layer 22.

[0039] 3, the upper electrode portion 62 of the gate electrode 24 includes a first protrusion 66A that protrudes laterally from the first end 52EA of the trench opening edge 52E along the upper surface 22S of the gate layer 22 by a protrusion width W2. Therefore, the gate electrode 24 includes a first electrode end 24EA (electrode end 24E) that contacts the upper surface 22S of the gate layer 22. Note that while FIG. 3 shows the first protrusion 66A, the same applies to the second protrusion 66B.

[0040] The depth D1 of the trench 50, the radius of curvature R1 of the curved surface 56, and the protrusion width W2 of the protrusion 66 can be set to values ​​that, by combining these parameters, can alleviate local electric field concentration in the gate layer 22. For example, the values ​​of the depth D1, the radius of curvature R1, and the protrusion width W2 are selected so as to obtain a higher electric field alleviation effect than when a typical gate layer without a trench structure is used. The electric field alleviation effect when a gate layer 22 having a trench structure (trench 50 including the curved surface 56) is used will be described later.

[0041] In one example, the depth D1 may be, for example, 10 nm or more and 50 nm or less, the radius of curvature R1 may be, for example, 5 nm or more and 30 nm or less, and the protrusion width W2 may be, for example, more than 0 and 100 nm or less. However, the depth D1, the radius of curvature R1, and the protrusion width W2 are not necessarily limited to these ranges and may be set to other ranges as long as the electric field relaxation effect is obtained.

[0042] 4 shows a structure in which the protrusion width W2 of the protrusion 66 is 0 nm (i.e., the gate electrode 24 does not include the protrusion 66). In this manner, the gate electrode 24 does not need to include the protrusion 66. In this structure, the side surface 62S of the upper electrode portion 62 is flat and continuous with the outer surface 64S of the lower electrode portion 64 at the position of the trench opening end 52E (first end 52EA in FIG. 4). Therefore, the gate electrode 24 in FIG. 4 does not include the electrode end 24E of the gate electrode 24 in FIG. 3.

[0043] [Electric Field Relaxation Effect Obtained by Trench Structure] Next, the electric field relaxation effect obtained when using a gate layer 22 having a trench structure (trench 50 including curved surface 56) will be described.

[0044] 5 is a diagram showing the results of a simulation of the electric field distribution (equipotential lines) around the gate electrode 24 of the nitride semiconductor device 10 of FIG. 1. The structure of FIG. 5 corresponds to the structure of FIG. 3. The simulation results show the electric field distribution when a gate voltage of, for example, 10 V is applied to the gate electrode 24. As shown in FIG. 5, in the structure of the gate layer 22 having the trench 50, the electric field (equipotential lines) is concentrated in a region F1 of the curved surface 56 of the trench 50 (first curved surface 56A in FIG. 5).

[0045] FIG. 6 shows simulation results of the electric field distribution (equipotential lines) around the gate electrode 240 of a typical nitride semiconductor device 100 including a gate layer 220 without a trench structure. The structure in FIG. 6 is shown as a comparative example with the structure in FIG. 5 . The gate layer 220 includes a flat upper surface 220S and does not include a trench 50 as shown in FIG. 5 . The gate electrode 240 is provided on the upper surface 220S of the gate layer 220 and includes an electrode end 240E (first electrode end 240EA in FIG. 6 ) that contacts the upper surface 220S. As shown in FIG. 6 , in the gate layer 220 structure without a trench structure, the electric field (equipotential lines) is locally concentrated in a region F2 of the gate layer 220 near the electrode end 240E of the gate electrode 240.

[0046] 6, in which the electric field is locally concentrated in region F2 of gate layer 220 (near electrode end 240E), in the structure of Fig. 5, there is almost no electric field concentration in the region of gate layer 22 near electrode end 24E, and the electric field is concentrated in a wider region F1 of curved surface 56. Therefore, in the structure of Fig. 5, the electric field applied to gate layer 22 is relaxed compared to the structure of Fig. 6.

[0047] Fig. 7 is a graph showing the gate breakdown voltage characteristics of the nitride semiconductor device 10 of Fig. 1 and the nitride semiconductor device 100 of Fig. 6. In Fig. 7, a solid line graph 10L1 shows the gate breakdown voltage characteristics of the nitride semiconductor device 10, and a dashed line graph 100L1 shows the gate breakdown voltage characteristics of the nitride semiconductor device 100. The horizontal axis represents the gate voltage Vg, and the vertical axis represents the gate current Ig.

[0048] As shown by graph 100L1, in the nitride semiconductor device 100 of FIG. 6 (gate layer 220 without a trench structure), breakdown occurs when the gate voltage Vg is approximately 13 V. In contrast, as shown by graph 10L1, in the nitride semiconductor device 100 of FIG. 1 (gate layer 22 having trench 50 including curved surface 56), although the gate current Ig increases as the gate voltage Vg increases, no clear breakdown is observed. Furthermore, the rate of increase in gate current Ig also decreases. Therefore, the nitride semiconductor device 10 of FIG. 1 has improved gate breakdown characteristics compared to the nitride semiconductor device 100 of FIG. 6.

[0049] Fig. 8 is a graph showing the maximum electric field strength of the nitride semiconductor device 10 of Fig. 1 and the maximum electric field strength of the nitride semiconductor device 100 of Fig. 6. In Fig. 8, a solid line graph 10L2 shows the maximum electric field strength of the nitride semiconductor device 10, and a dashed line graph 100L2 shows the maximum electric field strength of the nitride semiconductor device 100. Note that the maximum electric field strength used in the present disclosure refers to the electric field strength at the point where the maximum electric field is applied.

[0050] The two graphs 10L2 and 100L2 show that the maximum electric field strength (i.e., the maximum applied electric field) is reduced in the nitride semiconductor device 10 of Figure 1 compared to the nitride semiconductor device 100 of Figure 6. As described above, in the nitride semiconductor device 100 of Figure 6, the maximum electric field is applied to region F2 (near the electrode end 240E) of the gate layer 220 where the electric field is locally concentrated. Therefore, graph 100L2 shows the electric field strength in region F2 (near the electrode end 240E).

[0051] In contrast, in the nitride semiconductor device 10 of FIG. 1 , the maximum electric field is applied to region F1 of the curved surface 56 (see FIG. 5 ). Therefore, graph 10L2 shows the electric field strength in region F1 of the curved surface 56. In the nitride semiconductor device 10, the maximum electric field is applied to region F1 of the curved surface 56, dispersing the electric field acting on the gate layer 22 and mitigating localized electric field concentration. As a result, the maximum electric field strength is reduced in the nitride semiconductor device 10 of FIG. 1 . For example, when the gate voltage Vg is 10 V, the maximum electric field applied to the nitride semiconductor device 100 (region F2) is approximately 5.69, while the maximum electric field applied to the nitride semiconductor device 10 (region F1) is approximately 4.50. Therefore, an electric field mitigation effect is achieved.

[0052] [Relationship between gate electrode protrusion width, trench depth, and maximum electric field strength] Figure 9 is a graph showing the relationship between the protrusion width W2 (see Figure 3) of the protrusion portion 66 of the gate electrode 24, the depth D1 (see Figure 3) of the trench 50, and the maximum electric field strength (maximum electric field applied to the curved surface 56) in the nitride semiconductor device 10 of Figure 1.

[0053] The example of Figure 9 shows the relationship between the protrusion width W2 of the protrusion 66 and the maximum electric field applied to the curved surface 56 for three trenches 50 having depths D1 of 10 nm, 30 nm, and 50 nm, respectively. The gate voltage Vg is, for example, 10 V. The protrusion width W2 is also varied, for example, between 0 nm, 25 nm, 50 nm, 75 nm, 100 nm, 200 nm, and 250 nm. The reference value Ref indicates the maximum electric field strength of the nitride semiconductor device 100 of Figure 6, i.e., the maximum electric field (approximately 5.69) applied to the region F2 near the electrode end 240E.

[0054] 9 , when the depth D1 of the trench 50 is 10 nm, the maximum electric field strength is lower than the reference value Ref when the protrusion width W2 is 100 nm or less. On the other hand, when the depth D1 of the trench 50 is 30 nm and 50 nm, the maximum electric field strength is lower than the reference value Ref regardless of the protrusion width W2. In other words, when the protrusion width W2 is 100 nm or less, the maximum electric field strength is lower than the reference value Ref regardless of the depth D1 of the trench 50. Therefore, when the gate electrode 24 includes the protrusion 66, the electric field relaxation effect is exerted when the protrusion width W2 is greater than 0 and equal to or less than 100 nm and the depth D1 is equal to or greater than 10 nm and equal to or less than 50 nm.

[0055] Here, the graph in Figure 9 shows that the smaller the protrusion width W2, the greater the electric field relaxation effect. This is because, as the protrusion width W2 increases, the distance between the electrode end 24E and the curved surface 56 increases, making it difficult to sufficiently relax the electric field concentration near the electrode end 24E. Furthermore, when the depth D1 is small, for example, when the depth D1 is 10 nm, the electric field relaxation effect is smaller than when the depth D1 is 30 nm or 50 nm. This is because the effect of dispersing the electric field over a wide area using the curved surface 56 of the trench 50 is reduced. Therefore, the depth D1 is more preferably 30 nm or more and 50 nm or less.

[0056] Furthermore, when the protrusion width W2 is 0 nm, i.e., when the gate electrode 24 does not include the protrusion 66, the maximum electric field strength is lowest regardless of whether the depth D1 of the trench 50 is 10 nm, 30 nm, or 50 nm. Therefore, the maximum electric field relaxation effect can be obtained by combining the structure of the gate electrode 24 shown in FIG. 4 described above with the trench structure of the gate layer 22. Therefore, it is more desirable for the gate electrode 24 to have the structure shown in FIG. 4 than the structure shown in FIG. 5.

[0057] [Relationship between gate electrode protrusion width, curvature of curved surface, and maximum electric field strength] Figure 10 is a graph showing the relationship between the protrusion width W2 (see Figure 3) of the protrusion portion 66 of the gate electrode 24, the curvature radius R1 (see Figure 3) of the curved surface 56, and the maximum electric field strength (maximum electric field applied to the curved surface 56) in the nitride semiconductor device 10 of Figure 1.

[0058] The example of Figure 10 shows the relationship between the protrusion width W2 of the protrusion 66 and the maximum electric field applied to the curved surface 56 for four trenches 50, each having a curvature radius R1 of 5 nm, 10 nm, 20 nm, and 30 nm. The gate voltage Vg is, for example, 10 V. The protrusion width W2 is varied, for example, between 0 nm, 50 nm, and 100 nm. As in Figure 9, the reference value Ref indicates the maximum electric field strength of the nitride semiconductor device 100 of Figure 6, i.e., the maximum electric field (approximately 5.69) applied to the region F2 near the electrode end 240E.

[0059] As shown in Figure 10, when the curvature radius R1 is 5 nm, the maximum electric field strength is lower than the reference value Ref when the protrusion width W2 is 40 nm or less. On the other hand, when the curvature radius R1 is 10 nm, 20 nm, or 30 nm, the maximum electric field strength is lower than the reference value Ref regardless of the protrusion width W2. Therefore, when the gate electrode 24 includes the protrusion 66, the electric field relaxation effect is exerted when the protrusion width W2 is greater than 0 and less than or equal to 100 nm and the curvature radius R1 is 10 nm or greater and less than or equal to 30 nm. Alternatively, when the gate electrode 24 includes the protrusion 66, the electric field relaxation effect is exerted when the protrusion width W2 is greater than 0 and less than or equal to 40 nm and the curvature radius R1 is 5 nm or greater and less than or equal to 30 nm.

[0060] 10 also shows that the smaller the protrusion width W2, the greater the electric field relaxation effect. This is because, as described above, as the protrusion width W2 increases, the distance between the electrode end 24E and the curved surface 56 increases, making it difficult to fully relax the electric field concentration near the electrode end 24E. Furthermore, when the curvature radius R1 is small, for example, when the curvature radius R1 is 5 nm, the electric field relaxation effect is smaller than when the curvature radius R1 is 10 nm, 20 nm, or 30 nm. This is because a smaller curvature of the curved surface 56 increases the electric field concentration on the curved surface 56. Therefore, the curvature radius R1 is more preferably 10 nm or more and 30 nm or less.

[0061] [Functions of Nitride Semiconductor Device] Next, the functions of the nitride semiconductor device 10 will be described. The gate layer 22 of the nitride semiconductor device 10 includes a trench 50 recessed in the upper surface 22S of the gate layer 22 in a region in contact with the gate electrode 24. The trench 50 includes a curved surface 56 that curves from the trench bottom surface 54 toward the trench opening end 52E. In this structure, the electric field is concentrated over a wider area of ​​the curved surface 56 of the trench 50, thereby suppressing local electric field concentration in the gate layer 22 near the electrode end 24E of the gate electrode 24. As a result, the electric field applied to the gate layer 22 is alleviated. In particular, in the structure of FIG. 4 in which the gate electrode 24 does not include the protrusion 66, the gate electrode 24 does not include the electrode end 24E that contacts the upper surface 22S of the gate layer 22. This further alleviates the electric field applied to the gate layer 22.

[0062] The nitride semiconductor device 10 of the first embodiment has the following advantages. (1-1) The gate layer 22 has a trench 50 including a curved surface 56. With this structure, the electric field can be concentrated on a wider area of ​​the curved surface 56 of the trench 50. This makes it possible to suppress local electric field concentration in a portion of the gate layer 22 near the electrode end 24E of the gate electrode 24, thereby mitigating the electric field (maximum electric field strength) applied to the gate layer 22. As a result, crystal defects and therefore crystal destruction in the gate layer that may be caused by local electric field concentration can be suppressed, and a decrease in gate breakdown voltage can be suppressed.

[0063] (1-2) The trench width W1 of the trench 50 is equal to or less than the gate electrode length L1 of the gate electrode 24 (see FIG. 2). In this structure, a reduction in the area where the gate electrode 24 contacts the gate layer 22 can be suppressed, and the ability to transmit a gate signal from the gate electrode 24 to the gate layer 22 can be favorably maintained.

[0064] (1-3) The gate electrode 24 includes a lower electrode portion 64 that fills the trench 50 and an upper electrode portion 62 that is formed integrally with the lower electrode portion 64 and is located above the upper surface of the gate layer 22. In this case, the gate electrode 24 may be configured so that the side surface 62S of the upper electrode portion 62 is flat and continuous with the outer surface 64S of the lower electrode portion 64 at the trench opening edge 52E (see FIG. 4). In this structure, the gate electrode 24 does not include a protrusion 66 (see FIG. 3) or an electrode end portion 24E (see FIG. 3). By combining such a gate electrode 24 with a gate layer 22 having a trench 50 that includes a curved surface 56, the electric field applied to the gate layer 22 can be further reduced.

[0065] (1-4) Alternatively, the upper electrode portion 62 may include a protrusion 66 that protrudes laterally from the trench opening end 52E along the upper surface 22S of the gate layer 22 (see FIG. 3). Even in such a gate electrode 24 structure, the electric field applied to the gate layer 22 can be alleviated by using the gate layer 22 having the trench 50 including the curved surface 56.

[0066] (1-5) The protrusion 66 may protrude laterally from the trench opening edge 52E along the upper surface 22S of the gate layer 22 with a protrusion width W2 that is equal to or less than the depth D1 of the trench 50. If the protrusion width W2 is large, the distance between the electrode end 24E and the curved surface 56 increases, which may prevent a sufficient effect of alleviating the electric field concentration near the electrode end 24E. By satisfying the relationship W2≦D1, the protrusion width W2 is limited according to the depth D1, and therefore the electric field alleviation effect can be maintained satisfactorily.

[0067] (1-6) The protrusion width W2 of the protrusion 66 may be greater than 0 nm and less than or equal to 100 nm. In this case, for example, the electric field relaxation effect can be achieved by setting the depth D1 of the trench 50 to 10 nm or greater and 50 nm or less (see FIG. 9). Furthermore, for example, the electric field relaxation effect can be achieved by setting the radius of curvature R1 of the curved surface 56 to 10 nm or greater and 30 nm or less (see FIG. 10). Note that, as shown in FIGS. 9 and 10, the electric field relaxation effect is maximized when there is no protrusion 66 (i.e., the protrusion width W2 is 0 nm), the depth D1 of the trench 50 is 50 nm, and the radius of curvature R1 of the curved surface 56 is 30 nm.

[0068] (1-7) The electron transit layer 16 may be a GaN layer. In this case, the electron supply layer 18 may be an AlGaN layer. The gate layer 22 may be a GaN layer containing acceptor-type impurities. With this structure, the electric field (maximum electric field strength) applied to the gate layer 22 in a normally-off GaN-HEMT can be alleviated, thereby suppressing a decrease in the gate breakdown voltage.

[0069] 11 to 13 are schematic cross-sectional views of an exemplary nitride semiconductor device 10 according to a second embodiment. In FIGS. 11 to 13, the same components as those in the nitride semiconductor device 10 according to the first embodiment are denoted by the same reference numerals. In the following, a description of the same components as those in the first embodiment will be omitted, and only components different from those in the first embodiment will be described.

[0070] In the second embodiment, the trench 50 includes a trench wall surface 70 connecting the trench opening end 52E and the curved surface 56. For example, as shown in FIG. 11 , the trench wall surface 70 includes a vertical surface 72 that is perpendicular to the upper surface 22S of the gate layer 22.

[0071] Alternatively, as shown in FIGS. 12 and 13 , the trench wall 70 includes an inclined surface 74 inclined relative to the upper surface 22S of the gate layer 22. For example, in FIG. 12 , the inclined surface 74 has an inclination angle of 60°, while in FIG. 13 , the inclined surface 74 has a gentler inclination angle of 30°. The inclination angle of the inclined surface 74 may be selected arbitrarily between 0° and 90°, but is preferably between 30° and 60°. Also, as shown in FIGS. 12 and 13 , the trench wall 70 may include a second curved surface 76 in addition to the inclined surface 74. The second curved surface 76 connects the inclined surface 74 to the trench opening end 52E. The second curved surface 76 may also have the effect of dispersing the electric field applied to the gate layer 22 and alleviating local electric field concentration. Alternatively, the trench wall 70 may include only the inclined surface 74.

[0072] By including a trench wall surface 70 between the trench opening end 52E and the curved surface 56, it becomes easier to form the depth D1 (see Figure 3) of the trench 50 and the radius of curvature R1 (see Figure 3) of the curved surface 56 to the desired values.

[0073] 12 , when the trench wall surface 70 includes an inclined surface 74, the protrusion width W2 of the protrusion 66 may be formed to be equal to or less than the distance W3 across the curved surface 56 from the connection point P between the curved surface 56 and the trench bottom surface 54 to the trench opening edge 52E in a plan view. Although not shown in detail, the trench 50 of FIG. 13 may also be formed to satisfy the relationship W2≦W3. Furthermore, the trench 50 of FIG. 11 or the trench 50 of the first embodiment may also be formed to satisfy the relationship W2≦W3. By limiting the size of the protrusion width W2 by the distance W3 in this manner, the electric field relaxation effect can be enhanced.

[0074] Table 1 below shows an example of measurements of the maximum electric field applied to the curved surface 56 when the protrusion width W2 of the protrusion 66 and the depth D1 of the trench 50 are changed in the trench 50 of Figure 11, which includes the vertical surface 72 as the trench wall surface 70. Here, the gate voltage is set to, for example, 10 V, the protrusion width W2 is changed between 0 nm, 50 nm, and 100 nm, and the depth D1 is changed between 10 nm, 30 nm, and 50 nm. The radius of curvature R1 of the curved surface 56 is, for example, 5 nm.

[0075] Table 2 shows an example of measurements of the maximum electric field applied to the curved surface 56 when the protrusion width W2 of the protrusion 66 and the depth D1 of the trench 50 are changed under the same conditions as in Table 1 for the trench 50 of Figure 12, which includes an inclined surface 74 with an inclination angle of 60° as the trench wall surface 70.

[0076] Table 3 shows an example of measurements of the maximum electric field applied to the curved surface 56 when the protrusion width W2 of the protrusion 66 and the depth D1 of the trench 50 are changed under the same conditions as in Table 1 for the trench 50 of Figure 13, which includes an inclined surface 74 with an inclination angle of 30° as the trench wall surface 70.

[0077] When the maximum electric field (approximately 5.69) measured in region F2 near electrode end 240 of nitride semiconductor device 100 in FIG. 6 , which does not have a trench structure, is taken as a reference value Ref and compared, the maximum electric fields shown in Tables 1 to 3 are all lower than reference value Ref when protrusion width W2 is 0 nm. Furthermore, depending on the combination of protrusion width W2 and depth D1, the maximum electric field becomes lower than reference value Ref. Furthermore, the maximum electric field tends to be lower when inclined surface 74 is compared to when inclined surface 72 is vertical, and also tends to be lower when inclination angle of inclined surface 74 is 30° compared to when inclination angle of inclined surface 74 is 60°.

[0078] Therefore, the nitride semiconductor device 10 of the second embodiment also provides the same advantages as the first embodiment. [Modifications] The above-described embodiments can be modified as follows. Furthermore, the above-described embodiments and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0079] In the above embodiments, the nitride semiconductor device 10 is configured as a normally-off nitride semiconductor HEMT. However, it may be configured as a normally-on nitride semiconductor HEMT.

[0080] In the above-described embodiments, the nitride semiconductor device 10 is configured as a HEMT using gallium nitride, but may be configured as a HEMT using other group III nitride semiconductors. In the above-described second embodiment, similar to the first embodiment, the radius of curvature R1 of the curved surface 56 can also be changed as appropriate.

[0081] The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Therefore, the phrase "a first layer is formed on a second layer" means that in some embodiments, the first layer may be in contact with the second layer and disposed directly on the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which another layer is formed between the first and second layers. For example, the above-described embodiments in which the electron supply layer 18 is formed on the electron transit layer 16 also include a structure in which an intermediate layer (e.g., a spacer layer or other layer) is located between the electron supply layer 18 and the electron transit layer 16 to stably form the 2DEG 20.

[0082] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0083] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "forward," "rearward," "sideways," "left," "right," "front," "rear," etc., used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations can be envisioned in this disclosure, and therefore these directional terms should not be interpreted narrowly.

[0084] [Notes] The technical ideas that can be understood from the above-described embodiments and modifications are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each note are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each note should not be limited to the components indicated by the reference numerals.

[0085] (Appendix A1) A semiconductor device comprising: an electron transit layer (16) made of a nitride semiconductor; an electron supply layer (18) arranged on the electron transit layer (16) to generate a two-dimensional electron gas (20) in the electron transit layer (16), the electron supply layer (18) being made of a nitride semiconductor having a band gap larger than that of the electron transit layer (16); a gate layer (22) arranged on the electron supply layer (18) and made of a nitride semiconductor containing acceptor-type impurities; a gate electrode (24) in contact with the gate layer (22); and a source electrode (32) and a drain electrode (34) electrically connected to the two-dimensional electron gas (20), wherein the gate layer (22) includes a trench (50) recessed in an upper surface (22S) of the gate layer (22) in a region in contact with the gate electrode (24), the trench (50) having: a trench opening end (52E); a trench bottom surface (54); and a curved surface (56:56A; 56B) that is continuous with the trench bottom surface (54) and curves from the trench bottom surface (54) toward the trench opening end (52E).

[0086] (Appendix A2) The nitride semiconductor device (10) according to Appendix A1, wherein the trench opening end (52E) includes a first end (52EA) and a second end (52EB) facing each other in a first direction, the trench (50) has a trench width (W1) corresponding to a distance between the first end (52EA) and the second end (52EB) in the first direction, the gate electrode (24) has a gate electrode length (L1) in the first direction, and the trench width (W1) is equal to or less than the gate electrode length (L1).

[0087] (Appendix A3) The nitride semiconductor device (10) according to Appendix A1 or A2, wherein the gate electrode (24) includes: a lower electrode portion (64) filling the trench (50); and an upper electrode portion (62) formed integrally with the lower electrode portion (64) and positioned above an upper surface of the gate layer (22), and the upper electrode portion (62) includes a side surface (62S) that is flat and continuous with an outer surface (64S) of the lower electrode portion (64) at the position of the trench opening end (52E).

[0088] (Appendix A4) The nitride semiconductor device (10) according to Appendix A1 or A2, wherein the gate electrode (24) includes: a lower electrode portion (64) filling the trench (50); and an upper electrode portion (62) formed integrally with the lower electrode portion (64) and positioned above an upper surface of the gate layer (22), and the upper electrode portion (62) includes protrusions (66:66A; 66B) protruding laterally from the trench opening end (52E) along the upper surface of the gate layer (22).

[0089] (Appendix A5) The nitride semiconductor device (10) according to Appendix A4, wherein the protrusion (66:66A; 66B) protrudes laterally from the trench opening end (52E) along the upper surface of the gate layer (22) with a protrusion width (W2) that is equal to or less than the depth (D1) of the trench (50).

[0090] (Appendix A6) The nitride semiconductor device (10) according to Appendix A5, wherein the protrusion width (W2) is equal to or less than a distance (W3) across the curved surfaces (56:56A; 56B) from a connection point (P) between the curved surfaces (56:56A; 56B) and the trench bottom surface (54) to the trench opening end (52E) in a plan view.

[0091] (Appendix A7) The nitride semiconductor device (10) according to Appendix A4, wherein the protrusion (66:66A; 66B) protrudes laterally from the trench opening end (52E) along the upper surface of the gate layer (22) with a protrusion width (W2) greater than 0 nm and not greater than 100 nm.

[0092] (Appendix A8) The nitride semiconductor device (10) according to any one of Appendices A1 to A6, wherein the trench (50) includes a trench wall surface (70) connecting the trench opening end (52E) and the curved surface (56:56A; 56B).

[0093] (Appendix A9) The nitride semiconductor device (10) according to Appendix A8, wherein the trench wall (70) includes an inclined surface (74).

[0094] (Appendix A10) The nitride semiconductor device (10) according to appendix A9, wherein the inclined surface (74) has an inclination angle of 30° or more and 60° or less.

[0095] (Appendix A11) The nitride semiconductor device (10) according to appendix A9 or A10, wherein the trench wall (70) further includes a second curved surface (76) between the inclined surface (74) and the trench opening end (52E).

[0096] (Appendix A12) The nitride semiconductor device (10) according to any one of Appendices A8 to A10, wherein the trench wall (70) includes a vertical surface (72).

[0097] (Appendix A13) The nitride semiconductor device (10) according to Appendix A12, wherein the trench wall (70) further includes a second curved surface (76) between the vertical surface (72) and the trench opening end (52E).

[0098] (Appendix A14) The nitride semiconductor device (10) according to any one of Appendices A1 to A13, wherein the trench (50) has a depth of 10 nm or more and 50 nm or less.

[0099] (Appendix A15) The nitride semiconductor device (10) according to any one of Appendices A1 to A14, wherein the curved surface (56: 56A; 56B) has a radius of curvature (R1) of 10 nm or more and 30 nm or less.

[0100] (Appendix A16) The nitride semiconductor device (10) according to any one of Appendices A1 to A15, wherein the electron transit layer (16) is a GaN layer, the electron supply layer (18) is an AlGaN layer, and the gate layer (22) is a GaN layer containing the acceptor-type impurity.

[0101] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0102] REFERENCE SIGNS LIST 10...Nitride semiconductor device 12...Substrate 14...Buffer layer 16...Electron transit layer 18...Electron supply layer 20...Two-dimensional electron gas (2DEG) 22...Gate layer 22S...Upper surface of gate layer 24...Gate electrode 32...Source electrode 34...Drain electrode 50...Trench 52E...Trench opening end 52EA...First end 52EB...Second end 54...Trench bottom surface 56...Curved surface 56A...First curved surface 56B...Second curved surface 62...Upper electrode portion 62S...Side surface 64...Lower electrode portion 64S...Outer surface 66...Protrusion 66A...First protrusion 66B...Second protrusion 70...Trench wall surface 72...Vertical surface 74...Inclined surface W1...Trunk width W2...Protrusion width L1...Gate electrode length D1...Trench depth R1...curvature radius

Claims

1. an electron transit layer made of a nitride semiconductor; an electron supply layer that is disposed on the electron transit layer so as to generate a two-dimensional electron gas in the electron transit layer and is made of a nitride semiconductor having a larger band gap than that of the electron transit layer; a gate layer disposed on the electron supply layer and made of a nitride semiconductor containing an acceptor-type impurity; a gate electrode in contact with the gate layer; a source electrode and a drain electrode electrically connected to the two-dimensional electron gas; the gate layer includes a trench recessed into an upper surface of the gate layer in a region in contact with the gate electrode; The trench is A trench opening end; The bottom of the trench; a curved surface that is continuous with the bottom surface of the trench and curves from the bottom surface of the trench toward an opening end of the trench; 2. A nitride semiconductor device comprising:

2. the trench opening end includes a first end and a second end opposed to each other in a first direction; the trench has a trench width corresponding to a distance between the first end and the second end in the first direction; the gate electrode has a gate electrode length in the first direction, The nitride semiconductor device according to claim 1 , wherein the trench width is equal to or smaller than the gate electrode length.

3. The gate electrode is a lower electrode portion filling the trench; an upper electrode portion formed integrally with the lower electrode portion and located above an upper surface of the gate layer; 3. The nitride semiconductor device according to claim 1, wherein said upper electrode portion includes a side surface that is flat and continuous with an outer surface of said lower electrode portion at the position of an opening end of said trench.

4. The gate electrode is a lower electrode portion filling the trench; an upper electrode portion formed integrally with the lower electrode portion and located above an upper surface of the gate layer; 3. The nitride semiconductor device according to claim 1, wherein said upper electrode portion includes a protruding portion protruding laterally from an opening end of said trench along an upper surface of said gate layer.

5. The nitride semiconductor device according to claim 4 , wherein said protrusion protrudes laterally from an opening end of said trench along an upper surface of said gate layer with a protrusion width equal to or smaller than a depth of said trench.

6. The nitride semiconductor device according to claim 4 , wherein said protrusion protrudes laterally from an opening end of said trench along an upper surface of said gate layer with a protrusion width greater than 0 nm and not greater than 100 nm.

7. The nitride semiconductor device according to claim 1 , wherein said trench includes a trench wall surface connecting said trench opening end and said curved surface.

8. The nitride semiconductor device according to claim 7 , wherein said trench wall surface includes an inclined surface.

9. The nitride semiconductor device according to claim 8 , wherein said inclined surface has an inclination angle of 30° or more and 60° or less.

10. The nitride semiconductor device according to claim 7 , wherein said trench wall surface includes a vertical surface.

11. The nitride semiconductor device according to claim 1 , wherein the trench has a depth of not less than 10 nm and not more than 50 nm.

12. The nitride semiconductor device according to claim 1 , wherein said curved surface has a radius of curvature of not less than 10 nm and not more than 30 nm.

13. the electron transport layer is a GaN layer, The electron supply layer is an AlGaN layer.

3. The nitride semiconductor device according to claim 1, wherein said gate layer is a GaN layer containing said acceptor-type impurities.