Nitride semiconductor device

Abstract

This nitride semiconductor device comprises: an electron transit layer; an electron supply layer that is formed on the electron transit layer and that has a band gap which is larger than that of the electron transit layer; a dielectric layer that is formed on the electron supply layer; and an electrode that has a contact part which is in electrical contact with the electron supply layer via at least an opening passing through the dielectric layer. The contact part has: an inclined surface that is inclined so as to decrease in width toward the electron transit layer; a tip surface that is in contact with the bottom face of the opening; and a curved surface that is provided between the tip surface and the inclined surface and that is curved so as to protrude toward the electron transit layer.

Description

nitride semiconductor devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] Currently, commercialization of high electron mobility transistors (HEMTs) using nitride semiconductors is progressing (see, for example, Patent Document 1). For example, a HEMT includes an electron transit layer made of a GaN layer, an electron supply layer made of an AlGaN layer formed on the electron transit layer, a gate layer made of a p-type GaN layer formed on the electron supply layer, a gate electrode formed on the gate layer, and a passivation layer covering the electron supply layer, gate layer, and gate electrode. A high concentration of two-dimensional electron gas (2DEG) is generated at the interface between the electron transit layer and the electron supply layer, closer to the electron transit layer. The passivation layer has source and drain openings exposing the electron supply layer. The HEMT further includes a source electrode in ohmic contact with the 2DEG via the electron supply layer exposed by the source opening, and a drain electrode in ohmic contact with the 2DEG via the electron supply layer exposed by the drain opening.

[0003] Japanese Patent Application Laid-Open No. 2017-73506

[0004] In a structure in which the source and drain electrodes are in ohmic contact with the 2DEG, it is desirable to suppress an increase in the contact resistance between these electrodes and the 2DEG. This is not limited to HEMTs, but is also desirable in other semiconductor devices such as diodes that use nitride semiconductors.

[0005] A nitride semiconductor device according to one aspect of the present disclosure includes an electron transit layer, an electron supply layer formed on the electron transit layer and having a band gap larger than that of the electron transit layer, a dielectric layer formed on the electron supply layer, and an electrode having a contact portion in electrical contact with the electron supply layer through at least an opening that penetrates the dielectric layer, wherein the contact portion has an inclined surface that is inclined so as to narrow toward the electron transit layer, a tip surface that is in contact with a bottom surface of the opening, and a curved surface that is provided between the tip surface and the inclined surface and is curved so as to be convex toward the electron transit layer.

[0006] According to the nitride semiconductor device of the present disclosure, an increase in the contact resistance between the electrode and the 2DEG can be suppressed.

[0007] FIG. 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a first embodiment. FIG. 2 is a partially enlarged cross-sectional view of the nitride semiconductor device of FIG. 1. FIG. 3 is a schematic cross-sectional view showing an exemplary manufacturing process of the nitride semiconductor device of FIG. 1. FIG. 4 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 3. FIG. 5 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 4. FIG. 6 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 5. FIG. 7 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 6. FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 7. FIG. 9 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a comparative example. FIG. 10 is a graph showing the relationship between the position of the tip facet of the electrode contact portion and the contact resistance. FIG. 11 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a second embodiment. FIG. 12 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a third embodiment. FIG. 13 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a fourth embodiment. FIG. 14 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a fifth embodiment. FIG. 15 is a schematic plan view showing an exemplary formation pattern of the nitride semiconductor device of FIG. 14. 16 and 17 are schematic cross-sectional views of nitride semiconductor devices according to modifications.

[0008] Hereinafter, several embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] First Embodiment (Configuration of Nitride Semiconductor Device) The configuration of a nitride semiconductor device 10 according to a first embodiment will be described with reference to FIGS. 1 and 2. FIG.

[0011] FIG. 1 shows a schematic cross-sectional structure of an exemplary nitride semiconductor device 10 according to a first embodiment. The term "plan view" used in the present disclosure refers to viewing the nitride semiconductor device 10 in the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1. For convenience, the +Z direction is defined as up, the −Z direction as down, the +X direction as right, and the −X direction as left in the nitride semiconductor device 10 shown in FIG. 1. Unless explicitly stated otherwise, the "plan view" refers to viewing the nitride semiconductor device 10 from above along the Z-axis.

[0012] The nitride semiconductor device 10 uses a III-V group semiconductor. In the first embodiment, a III-V group nitride semiconductor is used as the III-V group semiconductor. A III-V group nitride semiconductor is a semiconductor that uses nitrogen as a group V element in a III-V group semiconductor, and typical examples include gallium nitride (GaN), aluminum nitride (AlN), and indium nitride (InN). In general, Al ｘ In ｙ Ga １－ｘ－ｙ N (0≦x≦1, 0≦y≦1, 0≦x+y≦1).

[0013] The nitride semiconductor device 10 includes a substrate 12, a buffer layer 14 formed on the substrate 12, an electron transit layer 16 formed on the buffer layer 14, and an electron supply layer 18 formed on the electron transit layer 16.

[0014] The substrate 12 may be, for example, a silicon (Si) substrate. Alternatively, instead of a Si substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a sapphire substrate may be used. The thickness of the substrate 12 may be, for example, 200 μm or more and 1500 μm or less. In the following description, unless explicitly stated otherwise, the thickness refers to the dimension along the Z-axis direction in FIG. 1 .

[0015] The buffer layer 14 is located between the substrate 12 and the electron transit layer 16 and may be composed of any material that can reduce the lattice mismatch between the substrate 12 and the electron transit layer 16. The buffer layer 14 may also include one or more nitride semiconductor layers. The buffer layer 14 may include, for example, at least one of an AlN layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 14 may be composed of a single AlN film, a single AlGaN film, a film having an AlGaN / GaN superlattice structure, a film having an AlN / AlGaN superlattice structure, or a film having an AlN / GaN superlattice structure.

[0016] In one example, the buffer layer 14 may include a first buffer layer that is an AlN layer formed on the substrate 12, and a second buffer layer that is an AlGaN layer formed on the AlN layer (first buffer layer). The first buffer layer may be an AlN layer having a thickness of, for example, 200 nm, and the second buffer layer may be a graded AlGaN layer having a thickness of, for example, 300 nm. Note that, in order to suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating except for the surface region. In this case, the impurity may be, for example, carbon (C) or iron (Fe). The impurity concentration may be, for example, 4×10 １６ cm －３The thickness of the buffer layer 14 may be greater than 500 nm. In one example, the thickness of the buffer layer 14 is 1500 nm.

[0017] The electron transit layer 16 is made of a nitride semiconductor. The electron transit layer 16 may be, for example, a GaN layer. The thickness of the electron transit layer 16 may be, for example, 0.5 μm or more and 2 μm or less. In one example, the thickness of the electron transit layer 16 is 1 μm. The electron transit layer 16 includes a front surface 16A and a back surface 16B opposite to the front surface 16A. The back surface 16B is in contact with the buffer layer 14. The front surface 16A is in contact with the electron supply layer 18.

[0018] In order to suppress leakage current in the electron transit layer 16, an impurity may be introduced into a part of the electron transit layer 16 to make the electron transit layer 16 semi-insulating except for the surface layer region. In this case, the impurity may be, for example, C. The impurity concentration may be, for example, 4×10 １６ cm －３ or more. That is, the electron transit layer 16 may include a plurality of GaN layers with different impurity concentrations, for example, a C-doped GaN layer and a non-doped GaN layer. In this case, the C-doped GaN layer is formed on the buffer layer 14. The C-doped GaN layer may have a thickness of 0.5 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer may be 5×10 １７ cm －３ 9x10 or more １９ cm －３ The undoped GaN layer is formed on the C-doped GaN layer. The undoped GaN layer may have a thickness of 0.05 μm or more and 0.4 μm or less. The undoped GaN layer is in contact with the electron supply layer 18. In one example, the electron transit layer 16 includes a C-doped GaN layer having a thickness of 0.9 μm and an undoped GaN layer having a thickness of 0.1 μm. The C concentration in the C-doped GaN layer is about 1×10 １８ cm －３ is.

[0019] The electron supply layer 18 is made of a nitride semiconductor having a larger band gap than the electron transit layer 16. The electron supply layer 18 may be, for example, an AlGaN layer. In nitride semiconductors, the higher the Al composition, the larger the band gap. Therefore, the electron supply layer 18, which is an AlGaN layer, has a larger band gap than the electron transit layer 16, which is a GaN layer. In one example, the electron supply layer 18 is made of Al ｘ Ga １－ｘ In other words, the electron supply layer 18 is made of Al ｘ Ga １－ｘ The electron supply layer 18 can be said to be an N layer. x is 0<x<0.4, preferably 0.1≦x≦0.3, and more preferably 0.2≦x≦0.3. ｘ Ga １－ｘ The range of x in the N layers can be changed arbitrarily.

[0020] The electron supply layer 18 includes a front surface 18A and a back surface 18B opposite to the front surface 18A. The back surface 18B is in contact with the electron transit layer 16. The front surface 18A is in contact with the dielectric layer 22. The electron supply layer 18 may have a thickness of, for example, 5 nm or more and 20 nm or less. In one example, the thickness of the electron supply layer 18 is about 10 nm.

[0021] The electron transit layer 16 and the electron supply layer 18 have different lattice constants in the bulk region. Therefore, the electron transit layer 16 and the electron supply layer 18 form a lattice-mismatched junction. Due to spontaneous polarization of the electron transit layer 16 and the electron supply layer 18 and piezoelectric polarization caused by compressive stress on the heterojunction of the electron transit layer 16, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 becomes lower than the Fermi level. As a result, two-dimensional electron gas (2DEG) 20 spreads within the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 (for example, at a distance of about several nanometers from the interface). The concentration of the 2DEG 20 is not particularly limited, but may be, for example, 1×10 １３ cm －２ That's about it.

[0022] The nitride semiconductor device 10 further includes a dielectric layer 22, an insulating layer 24, and an electrode 30. The dielectric layer 22 is formed on the electron supply layer 18. It can also be said that the dielectric layer 22 covers the electron supply layer 18. The dielectric layer 22 is made of, for example, silicon nitride (SiN), silicon dioxide (SiO ２ ), silicon oxynitride (SiON), alumina (Al ２ O ３ The dielectric layer 22 may be made of a material containing one of silicon nitride (SiN), aluminum nitride (AlN), and aluminum oxynitride (AlON). In one example, the dielectric layer 22 is made of a material containing silicon nitride (SiN). The dielectric layer 22 can also be considered a passivation layer. The thickness of the dielectric layer 22 is thicker than the thickness of the electron supply layer 18. In one example, the thickness of the dielectric layer 22 is about 100 nm. The thickness of the dielectric layer 22 can be changed as desired.

[0023] The electrode 30 has a contact portion 32 that is in electrical contact with the electron supply layer 18 through at least an opening 50 that penetrates the dielectric layer 22 , and a wiring portion 34 formed on the dielectric layer 22 .

[0024] The contact portion 32 is in ohmic contact with the 2DEG 20 through the opening 50. Therefore, the electrode 30 can also be said to be an ohmic electrode. The wiring portion 34 is formed so as to protrude from the opening 50 in the width direction of the electrode 30 (the X-axis direction in FIG. 1 ). The wiring portion 34 is located inside the outer peripheries (not shown) of the dielectric layer 22, the electron supply layer 18, etc. in a plan view.

[0025] A recess 36 recessed toward the electron supply layer 18 is formed in a portion of the wiring portion 34 corresponding to the contact portion 32. A bottom surface 36A of the recess 36 is located on the opposite side of the dielectric layer 22 from the electron supply layer 18. The recess 36 is formed at a position overlapping with the opening 50 in a plan view.

[0026] The electrode 30 has an electrode layer 40, a first barrier layer 42, and a second barrier layer 44. The electrode 30 has a laminated structure of the electrode layer 40, the first barrier layer 42, and the second barrier layer 44. The contact section 32 is composed of only the electrode layer 40. The wiring section 34 is composed of a laminated structure of the electrode layer 40, the first barrier layer 42, and the second barrier layer 44.

[0027] The first barrier layer 42 is formed on the dielectric layer 22. The first barrier layer 42 may be made of a material containing any one of titanium nitride (TiN), tungsten silicon nitride (WSiN), and tungsten nitride (WN). In one example, the first barrier layer 42 is made of a material containing TiN. The thickness of the first barrier layer 42 is thinner than the thickness of the dielectric layer 22. In one example, the thickness of the first barrier layer 42 is about 50 nm.

[0028] The electrode layer 40 includes a portion formed on the first barrier layer 42. The electrode layer 40 includes a portion provided between the first barrier layer 42 and the second barrier layer 44. Therefore, the first barrier layer 42 can be said to be interposed between the dielectric layer 22 and the electrode layer 40. The electrode layer 40 includes at least Ti and Al. The electrode layer 40 may include, for example, AlCu and Ti. The electrode layer 40 is composed of one or more metal layers. In one example, the electrode layer 40 has a stacked structure of a first metal layer, a second metal layer, and a third metal layer. The first metal layer is formed of a material containing, for example, Ti. The thickness of the first metal layer is approximately 20 nm. The second metal layer is formed on the first metal layer. The second metal layer is formed of a material containing AlCu. The second metal layer is, for example, an alloy of Al with approximately 1% or less of Cu added. The thickness of the second metal layer is approximately 200 nm. The third metal layer is formed on the second metal layer. The third metal layer is formed of a material containing Ti. Thus, the electrode layer 40 contains at least Ti, Al, and Cu. Therefore, it can be said that the electrode 30 contains at least Ti, Al, and Cu. The thickness of the third metal layer is approximately 20 nm. Thus, the thickness of the electrode layer 40 is thicker than the thickness of the first barrier layer 42 and the thickness of the dielectric layer 22.

[0029] The second barrier layer 44 is provided on the side of the interconnection portion 34 opposite to the first barrier layer 42. The second barrier layer 44 is formed along the recess 36 of the interconnection portion 34. The second barrier layer 44 may be made of a material containing any of TiN, WSiN, and WN. In one example, the second barrier layer 44 is made of a material containing TiN. That is, the second barrier layer 44 is made of the same material as the first barrier layer 42. The thickness of the second barrier layer 44 is equal to the thickness of the first barrier layer 42, for example. In one example, the thickness of the second barrier layer 44 is approximately 50 nm. Here, as shown in FIG. 1 , the thickness of the second barrier layer 44 varies. The thickness of the portion of the second barrier layer 44 that overlaps with the first barrier layer 42 in a plan view is approximately 50 nm.

[0030] As shown in FIG. 1 , the outer surface 34A of the wiring portion 34 is inclined in the Z-axis direction so that its width narrows with increasing distance from the dielectric layer 22. More specifically, the outer surface 42A of the first barrier layer 42, the outer surface 40A of the electrode layer 40 in the wiring portion 34, and the outer surface 44A of the second barrier layer 44 are each inclined in the Z-axis direction so that their width narrows with increasing distance from the dielectric layer 22. The inclination angle of the outer surface 42A of the first barrier layer 42 with respect to the Z-axis direction is equal to the inclination angle of the outer surface 40A of the electrode layer 40 with respect to the Z-axis direction. Furthermore, the outer surface 42A and the outer surface 40A are continuous and flush with each other. The inclination angle of the second barrier layer 44 with respect to the Z-axis direction is greater than the inclination angle of the outer surface 40A of the electrode layer 40 with respect to the Z-axis direction.

[0031] The insulating layer 24 is formed so as to cover the wiring portion 34 of the electrode 30 and the portion of the dielectric layer 22 exposed from the electrode 30. Therefore, the insulating layer 24 is formed on the second barrier layer 44. The insulating layer 24 is also in contact with the outer surface 40A of the electrode layer 40 in the wiring portion 34, the outer surface 42A of the first barrier layer 42, the outer surface 44A of the second barrier layer 44, and the surface 22A of the dielectric layer 22. The insulating layer 24 is made of, for example, SiO ２ The material constituting the insulating layer 24 can be changed arbitrarily, and may be, for example, SiON or SiN.

[0032] In the first embodiment, the length L2 of the wiring portion 34 in the X-axis direction is at least twice the length L1 of the tip end 32P of the contact portion 32 in the X-axis direction. Here, the length L2 of the wiring portion 34 in the X-axis direction indicates the maximum length of the wiring portion 34 in the X-axis direction. In other words, the length L2 can be defined by the length in the X-axis direction of the portion of the outer surface 42A of the first barrier layer 42 that contacts the dielectric layer 22. Furthermore, the length L1 in the X-axis direction of the tip end 32P of the contact portion 32 can be defined by the width of the contact portion 32 at the interface between the dielectric layer 22 and the electron supply layer 18 in the Z-axis direction.

[0033] 1 and 2, a detailed configuration of the opening 50 and the contact portion 32 of the electrode 30 provided in the opening 50 will be described. Fig. 2 shows an enlarged view of a portion of the opening 50 and the contact portion 32 in Fig. 1.

[0034] 1 , in the first embodiment, the opening 50 penetrates the dielectric layer 22 and is also formed in at least a part of the electron supply layer 18. More specifically, the opening 50 has a through portion 52 that penetrates the dielectric layer 22 and a recess portion 54 that is continuous with the through portion 52 and is provided in the electron supply layer 18.

[0035] The contact portion 32 is formed from the electrode layer 40, and since the contact portion 32 penetrates the first barrier layer 42, the opening 50 has a barrier-side penetrating portion 56 that penetrates the first barrier layer 42. That is, in the first embodiment, the contact portion 32 penetrates both the first barrier layer 42 and the dielectric layer 22. On the other hand, the contact portion 32 does not penetrate the electron supply layer 18.

[0036] 2, the barrier-side through-portion 56 is configured by an inner surface 42B that constitutes an opening formed in the first barrier layer 42. The inner surface 42B is inclined so that the opening width of the barrier-side through-portion 56 narrows toward the electron transit layer 16. Here, the opening width of the barrier-side through-portion 56 can be defined by the size of the barrier-side through-portion 56 in the X-axis direction.

[0037] The through portion 52 is configured by an inner surface 22B that constitutes an opening formed in the dielectric layer 22. The inner surface 22B is inclined so that the width of the through portion 52 narrows toward the electron transit layer 16. Here, the opening width of the through portion 52 can be defined by the size of the through portion 52 in the X-axis direction. In the first embodiment, the inclination angle of the inner surface 22B with respect to the Z-axis direction is equal to the inclination angle of the inner surface 42B of the first barrier layer 42 with respect to the Z-axis direction. The inner surface 22B and the inner surface 42B are continuous and flush with each other.

[0038] The recess portion 54 includes a recess bottom surface 18C formed in the electron supply layer 18 and curved recess surfaces 18D formed at both ends of the recess bottom surface 18C in the X-axis direction. The recess portion 54 also includes an inclined recess surface 18E that is continuous with the curved recess surface 18D on the side opposite to the recess bottom surface 18C.

[0039] The recess bottom surface 18C is located closer to the back surface 18B than the front surface 18A of the electron supply layer 18. In the first embodiment, the recess bottom surface 18C is located closer to the back surface 18B than the center in the thickness direction (Z-axis direction) of the electron supply layer 18. The recess bottom surface 18C extends along the X-axis direction. The recess bottom surface 18C forms the bottom surface of the opening 50.

[0040] The recess curved surface 18D is curved so as to be recessed toward the electron transit layer 16. In other words, the center of curvature of the recess curved surface 18D is located on the dielectric layer 22 side with respect to the recess bottom surface 18C.

[0041] The recess inclined surface 18E is inclined such that the opening width of the opening 50 narrows toward the recess curved surface 18D. Here, the opening width of the opening 50 can be defined by the size of the opening 50 in the X-axis direction. In the first embodiment, the inclination angle of the recess inclined surface 18E with respect to the Z-axis direction is equal to the inclination angle of the inner surface 22B of the dielectric layer 22 with respect to the Z-axis direction. The recess inclined surface 18E and the inner surface 22B are continuous and flush with each other. In one example, both the inclination angle of the recess inclined surface 18E with respect to the Z-axis direction and the inclination angle of the inner surface 22B of the dielectric layer 22 with respect to the Z-axis direction are between 10° and 20°. In the first embodiment, both the inclination angle of the recess inclined surface 18E with respect to the Z-axis direction and the inclination angle of the inner surface 22B of the dielectric layer 22 with respect to the Z-axis direction are 15°.

[0042] The contact portion 32 of the electrode 30 is embedded in the opening 50. The contact portion 32 is a portion of the electrode 30 that is closer to the electron transit layer 16 than the surface 42C of the first barrier layer 42. The contact portion 32 includes an inclined surface 32A that is inclined so that its width narrows toward the electron transit layer 16, a tip surface 32B that is in contact with the recess bottom surface 18C that serves as the bottom surface of the opening 50, and a curved surface 32C that is provided between the tip surface 32B and the inclined surface 32A.

[0043] The inclined surface 32A includes a first portion 32AA in contact with the dielectric layer 22 and a second portion 32AB in contact with the electron supply layer 18. The inclined surface 32A also includes a third portion 32AC in contact with the first barrier layer 42.

[0044] The first portion 32AA is in contact with the inner surface 22B of the dielectric layer 22 that constitutes the through portion 52. In the first embodiment, the first portion 32AA is in contact with the entire inner surface 22B. Therefore, the inclination angle of the first portion 32AA with respect to the Z-axis direction is equal to the inclination angle of the inner surface 22B with respect to the Z-axis direction.

[0045] The second portion 32AB contacts the recess inclined surface 18E of the electron supply layer 18 that constitutes the recess portion 54. In the first embodiment, the second portion 32AB contacts the entire recess inclined surface 18E. Therefore, the inclination angle of the second portion 32AB with respect to the Z-axis direction is equal to the inclination angle of the recess inclined surface 18E with respect to the Z-axis direction. The inclination angle of the first portion 32AA with respect to the Z-axis direction and the inclination angle of the second portion 32AB with respect to the Z-axis direction are equal to each other. In one example, both the inclination angle of the first portion 32AA with respect to the Z-axis direction and the inclination angle of the second portion 32AB with respect to the Z-axis direction are equal to or greater than 10° and equal to or less than 20°. In the first embodiment, both the inclination angle of the first portion 32AA with respect to the Z-axis direction and the inclination angle of the second portion 32AB with respect to the Z-axis direction are 15°. In the first embodiment, the first portion 32AA and the second portion 32AB are continuous and flush with each other. That is, the boundary between the first portion 32AA and the second portion 32AB and the boundary between the second portion 32AB and the first portion 32AA are not misaligned with each other in the X-axis direction. In other words, no step is formed between the first portion 32AA and the second portion 32AB.

[0046] The third portion 32AC is in contact with the inner surface 42B of the first barrier layer 42, which constitutes the barrier-side penetration portion 56. In the first embodiment, the third portion 32AC is in contact with the entire inner surface 42B. Therefore, the inclination angle of the third portion 32AC with respect to the Z-axis direction is equal to the inclination angle of the inner surface 42B with respect to the Z-axis direction. The inclination angle of the first portion 32AA with respect to the Z-axis direction and the inclination angle of the third portion 32AC with respect to the Z-axis direction are also equal to each other. In the first embodiment, the first portion 32AA and the third portion 32AC are continuous and flush with each other. That is, the boundary portion of the first portion 32AA with the third portion 32AC and the boundary portion of the third portion 32AC with the first portion 32AA are not misaligned with each other in the X-axis direction. In other words, no step is formed between the first portion 32AA and the third portion 32AC.

[0047] The tip surface 32B of the contact portion 32 extends along the X-axis direction. In the first embodiment, the tip surface 32B is in contact with the electron supply layer 18. More specifically, the tip surface 32B is in contact with a recess bottom surface 18C (the bottom surface of the opening 50) of the electron supply layer 18. Because the recess bottom surface 18C is located closer to the back surface 18B than the center of the electron supply layer 18 in the thickness direction, the tip surface 32B is located closer to the electron transit layer 16 than the center of the electron supply layer 18 in the thickness direction.

[0048] The curved surface 32C of the contact portion 32 is curved so as to be convex toward the electron transit layer 16. In other words, the center of curvature of the curved surface 32C is located closer to the dielectric layer 22 than the tip surface 32B. In the first embodiment, the curved surface 32C is located between the front surface 18A and the back surface 18B of the electron supply layer 18 in the Z-axis direction. The curved surface 32C is in contact with the electron supply layer 18. More specifically, the curved surface 32C is in contact with the recess curved surface 18D of the electron supply layer 18. The curvature of the curved surface 32C is equal to the curvature of the recess curved surface 18D.

[0049] The arc length of the curved surface 32C is longer than the arc length of the connection portion 38 between the contact portion 32 and the wiring portion 34 in the electrode layer 40. More specifically, the connection portion 38 is formed in a curved, concave shape recessed toward the recess 36 (see FIG. 1 ) of the wiring portion 34. In other words, the first barrier layer 42 includes a barrier-side curved surface 42D formed between the inner surface 42B constituting the barrier-side through portion 56 of the first barrier layer 42 and the surface 42C of the first barrier layer 42. The barrier-side curved surface 42D is a portion unintentionally formed during the process of forming the barrier-side through portion 56 in the first barrier layer 42, for example, by dry etching. Because the connection portion 38 is in contact with the barrier-side curved surface 42D, the arc length of the connection portion 38 is equal to the arc length of the barrier-side curved surface 42D. Therefore, it can be said that the arc length of the curved surface 32C is longer than the arc length of the unintentionally formed barrier-side curved surface 42D.

[0050] (Method of Manufacturing Semiconductor Device) A method of manufacturing the nitride semiconductor device 10 of the first embodiment will be described with reference to Figures 3 to 8. Figures 3 to 8 are schematic cross-sectional views showing exemplary manufacturing steps for the nitride semiconductor device 10. For ease of understanding, members that will become the final components of the nitride semiconductor device 10 are designated by the same reference numerals as in Figure 1.

[0051] As shown in FIG. 3, the method for manufacturing the nitride semiconductor device 10 includes forming a buffer layer 14, an electron transit layer 16, and an electron supply layer 18 on a substrate 12, which is, for example, a Si substrate with a <111> plane orientation.

[0052] The buffer layer 14, the electron transit layer 16, and the electron supply layer 18 can be epitaxially grown using a metal organic chemical vapor deposition (MOCVD) method.

[0053] Although detailed illustration is omitted, in one example, the buffer layer 14 is a multi-layer buffer layer, in which an AlN layer (first buffer layer) is formed on the substrate 12, and then a graded AlGaN layer (second buffer layer) is formed on the AlN layer. The graded AlGaN layer is formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25%, in that order from the side closest to the AlN layer.

[0054] Next, a GaN layer is formed on the buffer layer 14 as the electron transit layer 16, and an AlGaN layer is formed on the electron transit layer 16 as the electron supply layer 18. Therefore, the electron supply layer 18 has a larger band gap than the electron transit layer 16. The thickness of the buffer layer 14 is, for example, 1.5 μm, the thickness of the electron transit layer 16 is, for example, 1 μm, and the thickness of the electron supply layer 18 is, for example, 10 nm.

[0055] The method for manufacturing the nitride semiconductor device 10 includes forming a dielectric layer 22 on the electron supply layer 18. In one example, the dielectric layer 22 is a SiN layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method. Alternatively, the dielectric layer 22 may be formed by a low-pressure chemical vapor deposition (LPCVD) method. The thickness of the dielectric layer 22 is, for example, 100 nm.

[0056] The method for manufacturing the nitride semiconductor device 10 includes forming a first barrier layer 42 on the dielectric layer 22. The first barrier layer 42 is a TiN layer formed by sputtering. The first barrier layer 42 has a thickness of 50 nm. The first barrier layer 42 may be made of WSiN or WN.

[0057] 4 , the manufacturing method of the nitride semiconductor device 10 includes forming the barrier-side penetrating portion 56 in the first barrier layer 42. More specifically, first, a mask 60 including an opening 62 is formed. Specifically, a photoresist is formed on the first barrier layer 42. Next, the photoresist is patterned so that a portion of the first barrier layer 42 is exposed from the photoresist. This forms the mask 60 including the opening 62. The opening 62 is formed in a tapered shape such that the opening width of the opening 62 narrows toward the first barrier layer 42.

[0058] Subsequently, etching (e.g., dry etching) using this mask 60 removes the first barrier layer 42 at a position corresponding to the opening 62. This etching forms a barrier-side through portion 56 at a position corresponding to the opening 62. Because the opening 62 is tapered, the inner surface 42B of the first barrier layer 42 that constitutes the barrier-side through portion 56 is similarly formed as an inclined surface such that the opening width of the barrier-side through portion 56 narrows toward the dielectric layer 22. Here, the formation of the barrier-side through portion 56 exposes the dielectric layer 22.

[0059] As shown in FIG. 5 , the manufacturing method for the nitride semiconductor device 10 includes forming a through-hole 52 in the dielectric layer 22. More specifically, the dielectric layer 22 is removed at a position corresponding to the opening 62 by etching (e.g., dry etching) using a mask 60. The etching conditions are set so as not to damage the electron supply layer 18 due to etching. In one example, the bias power used when forming the through-hole 52 in the dielectric layer 22 is lower than the bias power used when forming the barrier-side through-hole 56 in the first barrier layer 42. Furthermore, since the opening 62 is tapered, the inner surface 22B of the dielectric layer 22 that constitutes the through-hole 52 is formed as an inclined surface such that the opening width of the through-hole 52 narrows toward the electron supply layer 18. Furthermore, since a common mask 60 is used, the inclination angle of the inner surface 42B of the first barrier layer 42 with respect to the Z-axis direction and the inclination angle of the inner surface 22B of the dielectric layer 22 with respect to the Z-axis direction are equal to each other. Furthermore, the inner surface 42B and the inner surface 22B are continuous and flush with each other. Here, the formation of the through portion 52 exposes the electron supply layer 18 .

[0060] As shown in FIG. 6 , the manufacturing method for the nitride semiconductor device 10 includes forming a recess 54 in the electron supply layer 18. More specifically, a portion of the electron supply layer 18 at a position corresponding to the opening 62 is removed by etching (e.g., dry etching) using a mask 60. The etching conditions are set to form the recess 54, i.e., the recess bottom surface 18C, the recess curved surface 18D, and the recess inclined surface 18E. Because the opening 62 is tapered, the recess inclined surface 18E is formed as an inclined surface such that the width of the recess 54 narrows toward the electron transit layer 16. Because a common mask 60 is used, the inclination angle of the recess inclined surface 18E relative to the Z-axis direction is equal to the inclination angle of the inner surface 22B of the dielectric layer 22 relative to the Z-axis direction. The recess inclined surface 18E and the inner surface 22B are continuous and flush with each other. Here, the inclination angles of the recess inclined surface 18E and the inner side surfaces 22B, 42B with respect to the Z-axis direction are each 10° to 20°, inclusive, and are 15° in the first embodiment. Through the above steps, the opening 50 is formed. Then, after the opening 50 is formed, the mask 60 is removed.

[0061] 7, the method for manufacturing the nitride semiconductor device 10 includes forming the electrode layer 40 and the second barrier layer 44. Both the electrode layer 40 and the second barrier layer 44 are formed by sputtering.

[0062] More specifically, as shown in FIG. 7 , a first metal layer is first formed in contact with the surface 42C and inner surface 42B of the first barrier layer 42, the inner surface 22B of the dielectric layer 22, the recess inclined surface 18E, the recess curved surface 18D, and the recess bottom surface 18C of the electron supply layer 18. The first metal layer is formed of a material containing Ti, for example. The thickness of the first metal layer is 20 nm. Next, a second metal layer is formed on the first metal layer. The second metal layer is formed of a material containing AlCu. The second metal layer is, for example, an alloy of Al with Cu added at approximately 1% or less. The thickness of the second metal layer is 200 nm. Next, a third metal layer is formed on the second metal layer. The third metal layer is formed of a material containing Ti. The thickness of the third metal layer is approximately 20 nm.

[0063] Next, a second barrier layer 44 is formed on the third metal layer. The second barrier layer 44 is a TiN layer formed by sputtering. The thickness of the second barrier layer 44 is 50 nm. Through the above steps, the contact portion 32 of the electrode 30 is formed. The second barrier layer 44 may be WSiN or WN.

[0064] Next, a mask 64 is formed on the second barrier layer 44. Specifically, a photoresist is formed on the second barrier layer 44. Subsequently, the photoresist is patterned so that a portion of the second barrier layer 44 is exposed from the photoresist. The mask 64 is patterned to include an inclined surface 66 that is inclined so that its width increases toward the second barrier layer 44.

[0065] As shown in FIG. 8 , the manufacturing method of the nitride semiconductor device 10 includes patterning each of the first barrier layer 42, the electrode layer 40, and the second barrier layer 44. More specifically, the second barrier layer 44 exposed from the mask 64 is removed by etching (e.g., dry etching) using a mask 64. As a result, the electrode layer 40 is exposed from the mask 64. Subsequently, the electrode layer 40 exposed from the mask 64 is removed by dry etching. As a result, the first barrier layer 42 is exposed from the mask 64. Subsequently, the first barrier layer 42 exposed from the mask 64 is removed by dry etching. Here, because the mask 64 includes an inclined surface 66, the outer surface 44A of the second barrier layer 44, the outer surface 40A of the electrode layer 40, and the outer surface 42A of the first barrier layer 42 are each formed as an inclined surface. As a result, the wiring portion 34 of the electrode 30 is formed.

[0066] The manufacturing method of the nitride semiconductor device 10 includes a heat treatment. More specifically, the heat treatment is performed at a temperature that achieves good ohmic contact between the contact portion 32 of the electrode 30 and the 2DEG 20 (see FIG. 1 ) via the electron supply layer 18. That is, the heat treatment forms ohmic contact between the contact portion 32 and the 2DEG 20 via the electron supply layer 18. More specifically, nitrogen (N) in the electron supply layer 18 made of AlGaN bonds with Ti in the contact portion 32, resulting in a state in which N is removed from the crystal of the electron supply layer 18, i.e., a state in which vacancies are formed. In this state, the electron supply layer 18 becomes n-type. Furthermore, Al, which has a low Schottky barrier with respect to the n-type electron supply layer 18, diffuses at the interface between the electron supply layer 18 and the contact portion 32, thereby reducing contact resistance. On the other hand, the wiring portion 34 has the first barrier layer 42 and the second barrier layer 44 formed thereon, and the first barrier layer 42 and the second barrier layer 44 are formed from high-melting-point metals such as TiN, WSiN, and WN, so that mutual reaction between the electrode layer 40 and the dielectric layer 22 and the insulating layer 24 is unlikely to occur. This prevents Al from diffusing into the dielectric layer 22 and the insulating layer 24. The temperature of the heat treatment is set appropriately depending on the material of the electrode 30. The electrode 30 is formed through the above steps.

[0067] Next, although not shown, the method for manufacturing the nitride semiconductor device 10 includes forming the insulating layer 24. In one example, the insulating layer 24 is a SiO.sub.2 layer formed by PECVD. ２ The insulating layer 24 may be formed by the LPCVD method. Through the above steps, the nitride semiconductor device 10 is manufactured.

[0068] (Function) The function of the nitride semiconductor device 10 of the first embodiment will be described. FIG. 9 shows a schematic cross-sectional structure of a nitride semiconductor device of a comparative example (hereinafter, "comparative nitride semiconductor device 10X"). The comparative nitride semiconductor device 10X differs from the nitride semiconductor device 10 of the first embodiment (see FIG. 1) in the configuration of the opening and the electrode contact portion. In the following description, the opening of the comparative nitride semiconductor device 10X will be referred to as "opening 50X" and the contact portion will be referred to as "contact portion 32X." Furthermore, in the comparative nitride semiconductor device 10X, the same components as those in the nitride semiconductor device 10 of the first embodiment will be described using the same reference numerals.

[0069] 9 , the opening 50X penetrates the dielectric layer 22 to expose the electron supply layer 18. The inner surface 22B of the dielectric layer 22 extends along the Z-axis direction. In the comparative nitride semiconductor device 10X, the recess 54 (see FIG. 2 ) is not formed in the electron supply layer 18. In other words, the surface 18A of the electron supply layer 18 forms the bottom surface of the opening 50X.

[0070] The contact portion 32X is provided within the opening 50X. An outer surface 32XA of the contact portion 32X is in contact with the inner surface 22B of the dielectric layer 22. In other words, the outer surface 32XA extends along the Z-axis direction. A tip surface 32XB of the contact portion 32X is in contact with the surface 18A of the electron supply layer 18. In this manner, a corner portion 32XC is formed by the tip surface 32XB and the outer surface 32XA of the contact portion 32X.

[0071] Incidentally, a heat treatment is performed to form an ohmic contact between the contact portion 32X and the 2DEG 20 via the electron supply layer 18. At this time, stress is generated in the contact portion 32X due to the difference in thermal expansion between the contact portion 32X and the dielectric layer 22 and the electron supply layer 18. The stress is particularly large at the corner portion 32XC.

[0072] As a result, the contact portion 32X may be deformed, and a void (air gap) VX may occur between the tip surface 32XB of the contact portion 32X and the surface 18A of the electron supply layer 18. This increases the contact resistance between the contact portion 32X and the 2DEG 20 via the electron supply layer 18.

[0073] As shown in FIG. 1 , in the nitride semiconductor device 10 of the first embodiment, the contact portion 32 includes an inclined surface 32A that narrows toward the tip surface 32B and a curved surface 32C provided between the inclined surface 32A and the tip surface 32B. Therefore, when heat treatment is performed, the force of expansion of the contact portion 32 is dispersed by both the inclined surface 32A and the curved surface 32C. This reduces stress generated in the contact portion 32. This suppresses deformation of the contact portion 32, thereby suppressing the generation of voids VX between the tip surface 32B of the contact portion 32 and the electron supply layer 18. This suppresses an increase in contact resistance between the contact portion 32 and the 2DEG 20 via the electron supply layer 18.

[0074] 10 is a graph showing the relationship between the position of the tip surface 32B of the contact portion 32 in the Z-axis direction and the contact resistance. The horizontal axis represents the position of the tip surface 32B of the contact portion 32 in the Z-axis direction, and the vertical axis represents the magnitude of the contact resistance (Ω-mm). The range of "0 nm" to "10 nm" on the horizontal axis represents the range in the Z-axis direction in which the electron supply layer 18 is formed, with "0 nm" representing the position of the back surface 18B of the electron supply layer 18 and "10 nm" representing the position of the front surface 18A of the electron supply layer 18. Therefore, "5 nm" represents the center of the electron supply layer 18 in the Z-axis direction. The negative range on the horizontal axis represents the range in the Z-axis direction in which the electron transit layer 16 is formed. In other words, the negative range on the horizontal axis indicates that the contact portion 32 penetrates the electron supply layer 18 and contacts the electron transit layer 16.

[0075] 10 , when the tip surface 32B of the contact portion 32 is located even slightly closer to the back surface 18B of the electron supply layer 18 than the front surface 18A, the contact resistance drops sharply. In other words, when the recess 54 of the opening 50 is formed in the electron supply layer 18, the contact resistance drops sharply. In other words, when the recess 54 is not formed in the electron supply layer 18, the contact resistance increases.

[0076] Generally, fluorine is used as a reactive gas when forming the through-hole 52 in the dielectric layer 22 by dry etching. It is believed that this fluorine remains on the surface 18A of the electron supply layer 18, increasing the contact resistance.

[0077] On the other hand, when a recess 54 is formed in the electron supply layer 18, the contact resistance is reduced because the remaining fluorine is removed along with the surface 18A of the electron supply layer 18 during the formation of the recess 54. In the first embodiment, the opening 50 has the recess 54 formed in the electron supply layer 18. The tip surface 32B of the contact portion 32 is in contact with the recess bottom surface 18C of the recess 54. This reduces the contact resistance.

[0078] 10 , the contact resistance is particularly reduced when the tip surface 32B of the contact portion 32 is positioned in the range of 0 nm or more and less than 3 nm. For example, when the tip surface 32B of the contact portion 32 is positioned in the range of 1.5 nm or more and 3 nm or less, the contact resistance decreases as the tip surface 32B of the contact portion 32 approaches the 1.5 nm position. On the other hand, the contact resistance increases as the tip surface 32B of the contact portion 32 approaches the electron transit layer 16 from the 1.5 nm position. The contact resistance when the tip surface 32B of the contact portion 32 is positioned at 0 nm is approximately equal to the contact resistance at the 5 nm position. Thus, the contact resistance is minimum when the tip surface 32B of the contact portion 32 is positioned at 1.5 nm.

[0079] (Effects) The nitride semiconductor device 10 of the first embodiment has the following effects: (1-1) The nitride semiconductor device 10 includes an electron transit layer 16, an electron supply layer 18 formed on the electron transit layer 16 and having a band gap larger than that of the electron transit layer 16, a dielectric layer 22 formed on the electron supply layer 18, and an electrode 30 having a contact portion 32 in electrical contact with the electron supply layer 18 through at least an opening 50 that penetrates the dielectric layer 22. The contact portion 32 has an inclined surface 32A that is inclined so as to narrow toward the electron transit layer 16, a tip surface 32B that is in contact with the bottom surface of the opening 50, and a curved surface 32C that is provided between the tip surface 32B and the inclined surface 32A and is curved so as to be convex toward the electron transit layer 16.

[0080] According to this configuration, the inclined surface 32A and the curved surface 32C of the contact portion 32 reduce stress generated in the electrode 30 during heat treatment in the manufacturing process of the nitride semiconductor device 10. This makes it possible to suppress the generation of voids VX between the contact portion 32 and the electron supply layer 18. Therefore, it is possible to suppress an increase in contact resistance between the electrode 30 (contact portion 32) and the 2DEG 20 via the electron supply layer 18. Since the generation of voids VX is suppressed in this way, a stable ohmic contact structure with low contact resistance between the electrode 30 and the 2DEG 20 can be achieved.

[0081] (1-2) The opening 50 has a through portion 52 that penetrates the dielectric layer 22 and a recess portion 54 that is continuous with the through portion 52 and is provided in the electron supply layer 18. The opening 50 penetrates the dielectric layer 22 and is formed in at least a part of the electron supply layer 18. The inclined surface 32A of the contact portion 32 includes a first portion 32AA that is in contact with the dielectric layer 22 and a second portion 32AB that is in contact with the electron supply layer 18. The curved surface 32C of the contact portion 32 is in contact with the electron supply layer 18.

[0082] According to this configuration, even if fluorine used in dry etching the dielectric layer 22 remains on the surface 18A of the electron supply layer 18, the fluorine is removed when the recess 54 is formed in the electron supply layer 18. This reduces the contact resistance between the contact portion 32 and the 2DEG 20 via the electron supply layer 18.

[0083] (1-3) The tip surface 32B of the contact portion 32 is located closer to the electron transit layer 16 than the center of the electron supply layer 18 in the thickness direction (Z direction) of the electron supply layer 18. According to this configuration, as shown in the graph of Fig. 10, when the tip surface 32B of the contact portion 32 is located closer to the electron transit layer 16 than the center of the electron supply layer 18 in the Z axis direction, the contact resistance between the contact portion 32 and the 2DEG 20 via the electron supply layer 18 can be further reduced.

[0084] (1-4) The inclination angle of the first portion 32AA of the inclined surface 32A of the contact portion 32 relative to the thickness direction (Z-axis direction) of the electron transit layer 16 is equal to the inclination angle of the second portion 32AB relative to the Z-axis direction.

[0085] According to this configuration, because the inclination angles are equal to each other, the thermal expansion force of the contact portion 32 is dispersed at the inner surface 22B of the dielectric layer 22 and the inclined recess surface 18E of the electron supply layer 18 during heat treatment in the manufacturing process of the nitride semiconductor device 10, and this disperses the force to less affect each other. This reduces stress generated in the contact portion 32 due to the reaction force from the dielectric layer 22 and the electron supply layer 18 to the contact portion 32. Therefore, it is possible to suppress the generation of voids VX between the contact portion 32 and the electron supply layer 18, thereby suppressing an increase in contact resistance between the electrode 30 (contact portion 32) and the 2DEG 20 via the electron supply layer 18.

[0086] (1-5) The inclination angle of the first portion 32AA of the inclined surface 32A with respect to the Z-axis direction and the inclination angle of the second portion 32AB with respect to the Z-axis direction are both 10° or more and 20° or less. In other words, the inclination angle of the inner surface 22B of the dielectric layer 22 with respect to the Z-axis direction and the inclination angle of the recess inclined surface 18E of the recess portion 54 with respect to the Z-axis direction are both 10° or more and 20° or less.

[0087] According to this configuration, the inclination angle is 10° or more and 20° or less, which makes it possible to prevent a microtrench shape from being formed between recess inclined surface 18E and recess bottom surface 18C. Therefore, a curved surface 32C is formed between inclined surface 32A and tip surface 32B of contact portion 32 in contact with recess 54. This makes it possible to reduce stress generated in electrode 30 during heat treatment in the manufacturing process of nitride semiconductor device 10.

[0088] (1-6) The first portion 32AA and the second portion 32AB of the inclined surface 32A of the contact portion 32 are continuous and flush with each other. Compared to a configuration in which a step is formed between the first portion 32AA and the second portion 32AB, this configuration eliminates stress that occurs in the contact portion 32 due to the step, thereby reducing stress that occurs in the contact portion 32.

[0089] (1-7) The electrode 30 has a wiring portion 34 provided on the dielectric layer 22. The length L2 of the wiring portion 34 in the width direction (X-axis direction) is at least twice the length L1 of the tip end 32P of the contact portion 32 in the width direction.

[0090] This configuration can increase the heat capacity of the electrode 30 including the wiring portion 34 and the contact portion 32. This can reduce stress that occurs in the electrode 30 during heat treatment in the manufacturing process of the nitride semiconductor device 10.

[0091] (1-8) The wiring portion 34 includes a first barrier layer 42 in contact with the dielectric layer 22. With this configuration, the wiring portion 34 and the dielectric layer 22 are separated by the first barrier layer 42, and therefore, diffusion of Al into the dielectric layer 22 due to mutual reaction between the Al component contained in the electrode 30 and the Si component contained in the dielectric layer 22 can be suppressed.

[0092] (1-9) The first barrier layer 42 contains any one of TiN, WSiN, and WN. This configuration can prevent Al contained in the electrode 30 from diffusing into the dielectric layer 22. Note that the same effect can be obtained even if the first barrier layer 42 has a structure in which multiple layers containing any one of TiN, WSiN, and WN are stacked.

[0093] (1-10) The wiring portion 34 includes a second barrier layer 44 provided on the opposite side to the first barrier layer 42. With this configuration, the wiring portion 34 and the insulating layer 24 are separated by the second barrier layer 44, so that it is possible to suppress diffusion of Al into the insulating layer 24 due to mutual reaction between the Al component contained in the electrode 30 and the Si component contained in the insulating layer 24.

[0094] (1-11) The second barrier layer 44 contains any one of TiN, WSiN, and WN. This configuration can prevent Al contained in the electrode 30 from diffusing into the insulating layer 24. Note that the same effect can be obtained even if the second barrier layer 44 has a structure in which multiple layers containing any one of TiN, WSiN, and WN are stacked.

[0095] (1-12) The electrode layer 40 contains at least Ti, Al, and Cu. According to this configuration, when the electrode layer 40 contains Ti, Ti extracts nitrogen (N) from the electron supply layer 18 formed of AlGaN, thereby forming vacancies in the electron supply layer 18. Because the vacancies exhibit n-type conductivity, the contact resistance of the electrode 30 to the 2DEG 20 can be reduced.

[0096] When the electrode layer 40 contains Al, Al has a low Schottky barrier with the electron supply layer 18 formed of AlGaN. In addition, Al diffuses into the recess 54 of the electron supply layer 18 during heat treatment in the manufacturing process of the nitride semiconductor device 10, thereby reducing contact resistance. Furthermore, by adding about 1% or less of Cu, which has a larger atomic number than Al, to Al, electromigration is less likely to occur when a large current flows through the electrode 30.

[0097] (1-13) The electron supply layer 18 is Al ｘ Ga １－ｘ N layer (0.2≦x≦0.3). With this configuration, when the Al composition ratio is 0.2 or more and 0.3 or less, a recess portion 54 including the recess inclined surface 18E, the recess curved surface 18D, and the recess bottom surface 18C can be formed in the electron supply layer 18. Therefore, an increase in contact resistance between the electrode 30 (contact portion 32) and the 2DEG 20 via the electron supply layer 18 can be suppressed.

[0098] (1-14) The arc length of the curved surface 32C of the contact portion 32 is longer than the arc length of the connection portion 38 (see FIG. 2) between the contact portion 32 and the wiring portion 34. This configuration enhances the effect of reducing stress generated in the electrode 30 by the curved surface 32C.

[0099] Second Embodiment The configuration of a nitride semiconductor device 10 of a second embodiment will be described with reference to Figure 11. The nitride semiconductor device 10 of the second embodiment differs from the nitride semiconductor device 10 of the first embodiment mainly in the configurations of the opening 50 and the contact portion 32 of the electrode 30. Below, differences from the nitride semiconductor device 10 of the first embodiment will be described in detail, and components common to the nitride semiconductor device 10 of the first embodiment will be denoted by the same reference numerals and will not be described again.

[0100] As shown in FIG. 11 , in the second embodiment, the opening 50 is provided so as to expose the surface 18A of the electron supply layer 18. That is, in the second embodiment, the inner surface 22B of the dielectric layer 22 constituting the through portion 52 and the recessed slope 18E of the electron supply layer 18 on which the recess 54 is provided are not flush with each other. The edge of the inner surface 22B of the dielectric layer 22 that contacts the surface 18A of the electron supply layer 18 is located further outward in the X-axis direction than the edge of the recessed slope 18E of the electron supply layer 18 that contacts the surface 18A of the electron supply layer 18. Therefore, the surface 18A of the electron supply layer 18 is provided between the inner surface 22B of the dielectric layer 22 and the recessed slope 18E. That is, the surface 18A of the electron supply layer 18 provided between the inner surface 22B of the dielectric layer 22 and the recessed slope 18E connects the inner surface 22B of the dielectric layer 22 and the recessed slope 18E. In the second embodiment, the width of the through portion 52 is wider than the width of the through portion 52 in the first embodiment. Note that the inclination angle of the inner surface 22B of the dielectric layer 22 with respect to the Z-axis direction and the inclination angle of the recess inclined surface 18E with respect to the Z-axis direction in the second embodiment are the same as those in the first embodiment.

[0101] The contact portion 32 of the electrode 30 includes a step portion 39 provided between a first portion 32AA and a second portion 32AB of the inclined surface 32A. The step portion 39 contacts the surface 18A of the electron supply layer 18 that contacts the dielectric layer 22. More specifically, the step portion 39 includes a step surface 39A that faces the surface 18A of the electron supply layer 18. The step surface 39A is formed in a flat shape parallel to the XY plane. The step surface 39A contacts the surface 18A of the electron supply layer 18. The tip surface 32B and the curved surface 32C of the contact portion 32 are similar to the tip surface 32B and the curved surface 32C of the first embodiment.

[0102] Next, a method for manufacturing the nitride semiconductor device 10 will be described. Differences from the method for manufacturing the nitride semiconductor device 10 of the first embodiment will be described below. The method for manufacturing the nitride semiconductor device 10 of the second embodiment differs in the method for forming the recess 54 in the electron supply layer 18. More specifically, a mask (not shown) is first formed on the electron supply layer 18 exposed by the through-hole 52 in the dielectric layer 22. This mask is formed using photoresist and patterning, similar to the mask 60 (see FIG. 5 ). The mask has an opening narrower than the through-hole 52. The opening exposes the electron supply layer 18. Subsequently, a portion of the electron supply layer 18 at a position corresponding to the opening in the mask is removed by etching (e.g., dry etching) using the mask. At this time, as in the first embodiment, etching conditions are set so as to form the recess 54, i.e., the recess bottom surface 18C, the recess curved surface 18D, and the recess inclined surface 18E. Furthermore, because the opening (not shown) of the mask is tapered, the recess inclined surface 18E is formed as an inclined surface such that the width of the recess 54 narrows toward the electron transit layer 16. Furthermore, by using the same formation conditions for the masks used to etch the dielectric layer 22 and the electron supply layer 18, it is possible to make the inclination angle of the recess inclined surface 18E relative to the Z-axis direction equal to the inclination angle of the inner surface 22B of the dielectric layer 22 relative to the Z-axis direction. The inclination angles of the recess inclined surface 18E and the inner surfaces 22B and 42B relative to the Z-axis direction are between 10° and 20°, inclusive, and are, for example, 15°. After the recess 54 is formed, the mask is removed.

[0103] (Effects) According to the nitride semiconductor device 10 of the second embodiment, in addition to the effects (1-1) to (1-5) and (1-7) to (1-14) of the first embodiment, the following effects can be obtained.

[0104] (2-1) The contact portion 32 includes a step portion 39 provided between the first portion 32AA and the second portion 32AB of the inclined surface 32A. The step portion 39 is in contact with the surface 18A of the electron supply layer 18 that is in contact with the dielectric layer 22.

[0105] This configuration increases the contact area between the contact portion 32 and the electron supply layer 18. Therefore, a large current can be supplied with low resistance from the contact portion 32 to the electron supply layer 18. Such an ohmic contact structure can reduce power consumption when the nitride semiconductor device 10 is applied to a power device, for example.

[0106] 12 , the configuration of a nitride semiconductor device 10 of the third embodiment will be described. The nitride semiconductor device 10 of the third embodiment differs from the nitride semiconductor device 10 of the first embodiment mainly in the configurations of the opening 50 and the contact portion 32 of the electrode 30. Below, differences from the nitride semiconductor device 10 of the first embodiment will be described in detail, and components common to the nitride semiconductor device 10 of the first embodiment will be denoted by the same reference numerals and will not be described again.

[0107] 12 , in the third embodiment, the opening 50 does not have the recess portion 54 (see FIG. 1 ). That is, the opening 50 has a barrier-side penetrating portion 56 and a penetrating portion 52. The bottom surface of the opening 50 is formed by the surface 18A of the electron supply layer 18.

[0108] The third embodiment also differs in the shape of the through portion 52. More specifically, the inner surface 22B of the dielectric layer 22 constituting the through portion 52 includes a dielectric-side inclined surface 22BA and a dielectric-side curved surface 22BB provided between the dielectric-side inclined surface 22BA and the surface 18A of the electron supply layer 18.

[0109] The dielectric-side inclined surface 22BA is continuous and flush with the inner surface 42B of the first barrier layer 42 that constitutes the barrier-side penetration portion 56. The inclination angle of the dielectric-side inclined surface 22BA with respect to the Z-axis direction is equal to the inclination angle of the inner surface 42B with respect to the Z-axis direction. Similar to the first embodiment, these inclination angles are 10° to 20°, inclusive, and are 15° in one example.

[0110] The dielectric-side curved surface 22BB is curved so as to be convex toward the electron supply layer 18. The shape of the dielectric-side curved surface 22BB is similar to the shape of the recess curved surface 18D in the first embodiment. The arc length of the dielectric-side curved surface 22BB is longer than the arc length of the connection portion 38 (see FIG. 2 ) between the contact portion 32 and the wiring portion 34.

[0111] The tip surface 32B of the contact portion 32 of the electrode 30 is flush with the upper surface of the electron supply layer 18 (surface 18A of the electron supply layer 18) that is in contact with the dielectric layer 22. The tip surface 32B is in contact with the surface 18A of the electron supply layer 18.

[0112] The inclined surface 32A of the contact portion 32 does not have a second portion 32AB. That is, the inclined surface 32A has a first portion 32AA and a third portion 32AC. The curved surface 32C is located closer to the first barrier layer 42 than the surface 18A of the electron supply layer 18. In the third embodiment, the curved surface 32C is in contact with the dielectric layer 22. More specifically, the curved surface 32C is in contact with the dielectric-side curved surface 22BB. Therefore, the arc length of the curved surface 32C is longer than the arc length of the connection portion 38 (see FIG. 2 ).

[0113] In the third embodiment, the tip end 32P of the contact portion 32 is configured by a tip surface 32B and a curved surface 32C. The relationship between the widthwise length (X-axis direction) of the wiring portion 34 and the widthwise length of the tip end 32P of the contact portion 32 is the same as in the first embodiment.

[0114] (Effects) According to the nitride semiconductor device 10 of the third embodiment, in addition to the effects (1-1) and (1-7) to (1-14) of the first embodiment, the following effects can be obtained.

[0115] (3-1) The tip surface 32B of the contact portion 32 and the surface 18A of the electron supply layer 18 that contacts the dielectric layer 22 are flush with each other. The curved surface 32C contacts the dielectric layer 22. With this configuration, the inclined surface 32A (first portion 32AA) and the curved surface 32C of the contact portion 32 reduce stress in the electrode 30 during heat treatment in the manufacturing process of the nitride semiconductor device 10. This suppresses the generation of voids VX between the tip surface 32B and the electron supply layer 18. Therefore, an increase in contact resistance between the electrode 30 (contact portion 32) and the 2DEG 20 via the electron supply layer 18 can be suppressed. Because the generation of voids VX is suppressed, a stable, low-contact-resistance ohmic contact structure between the electrode 30 and the 2DEG 20 can be achieved.

[0116] 13, the configuration of a nitride semiconductor device 10 according to a fourth embodiment will be described. The nitride semiconductor device 10 according to the fourth embodiment differs from the nitride semiconductor device 10 according to the first embodiment mainly in the configuration of the contact portion 32 of the electrode 30. Below, differences from the nitride semiconductor device 10 according to the first embodiment will be described in detail, and components common to the nitride semiconductor device 10 according to the first embodiment will be denoted by the same reference numerals and will not be described again.

[0117] 13 , in the fourth embodiment, the opening 50 penetrates through both the dielectric layer 22 and the electron supply layer 18. The opening 50 is also formed in at least a part of the electron transit layer 16. In the fourth embodiment, the through portion 52 of the opening 50 penetrates through both the dielectric layer 22 and the electron supply layer 18. A recess 54 continuous with the through portion 52 is provided in the electron transit layer 16.

[0118] The through portion 52 includes a first through portion 52A that penetrates the dielectric layer 22 and a second through portion 52B that penetrates the electron supply layer 18. The first through portion 52A has the same configuration as the through portion 52 of the first embodiment (see FIG. 1 ). The relationship between the inner surface 22B of the dielectric layer 22 that constitutes the first through portion 52A and the inner surface 42B of the first barrier layer 42 that constitutes the barrier-side through portion 56 is the same as in the first embodiment.

[0119] The second through portion 52B is configured with an inner surface 18F that constitutes an opening formed in the electron supply layer 18. The inner surface 18F is inclined so that the opening width of the second through portion 52B narrows toward the buffer layer 14 (see FIG. 1 ). Here, the opening width of the second through portion 52B can be defined by the size of the second through portion 52B in the X-axis direction. In the fourth embodiment, the inclination angle of the inner surface 18F with respect to the Z-axis direction is equal to the inclination angle of the inner surface 22B of the dielectric layer 22 with respect to the Z-axis direction. The inner surface 18F and the inner surface 22B are continuous and flush with each other. As in the first embodiment, both the inclination angle of the inner surface 18F with respect to the Z-axis direction and the inclination angle of the inner surface 22B of the dielectric layer 22 with respect to the Z-axis direction are 10° to 20°, inclusive, and are 15° in one example.

[0120] The recess 54 includes a recess bottom surface 16C formed in the electron transit layer 16 and curved recess surfaces 16D formed on both ends of the recess bottom surface 16C in the X-axis direction. In other words, unlike the first embodiment, the recess 54 does not include an inclined recess surface. The recess bottom surface 16C can also be considered to be the bottom surface of the electron transit layer 16 that comes into contact with the tip surface 32B of the contact portion 32.

[0121] The recess bottom surface 16C is located closer to the front surface 16A than the back surface 16B of the electron transit layer 16. In the first embodiment, the recess bottom surface 16C is located closer to the front surface 16A than the center of the electron transit layer 16 in the thickness direction (Z-axis direction). In one example, the distance between the front surface 16A of the electron transit layer 16 and the recess bottom surface 16C in the Z-axis direction, i.e., the depth of the recess portion 54, is 20 nm or less. The recess bottom surface 16C extends along the X-axis direction. The recess bottom surface 16C forms the bottom surface of the opening 50.

[0122] The recess curved surface 16D is curved so as to be convex toward the buffer layer 14. That is, the center of curvature of the recess curved surface 16D is located on the electron supply layer 18 side of the recess bottom surface 16C. The shape of the recess curved surface 16D is similar to the shape of the recess curved surface 18D (see FIG. 1 ) of the first embodiment. The arc length of the recess curved surface 16D is longer than the arc length of the connection portion 38 (see FIG. 2 ) between the contact portion 32 and the wiring portion 34.

[0123] The contact portion 32 of the electrode 30 penetrates the dielectric layer 22 and the electron supply layer 18 through the opening 50. The contact portion 32 reaches the electron transit layer 16. In the fourth embodiment, the inclined surface 32A of the contact portion 32 includes a first portion 32AA in contact with the dielectric layer 22 and a second portion 32AB in contact with the electron supply layer 18. The inclined surface 32A also includes a third portion 32AC in contact with the first barrier layer 42.

[0124] The configuration of the first portion 32AA in the fourth embodiment is the same as that of the first portion 32AA in the first embodiment. Unlike the second portion 32AB in the first embodiment, the second portion 32AB in the fourth embodiment contacts the entire inner surface 18F of the electron supply layer 18. The first portion 32AA and the second portion 32AB are continuous and flush with each other. The inclination angle of the first portion 32AA with respect to the Z-axis direction and the inclination angle of the second portion 32AB with respect to the Z-axis direction are equal to each other. Both the inclination angle of the first portion 32AA with respect to the Z-axis direction and the inclination angle of the second portion 32AB with respect to the Z-axis direction are 10° or more and 20° or less. In the fourth embodiment, both the inclination angle of the first portion 32AA with respect to the Z-axis direction and the inclination angle of the second portion 32AB with respect to the Z-axis direction are 15°.

[0125] The curved surface 32C of the contact portion 32 is in contact with at least the electron transit layer 16. That is, in the fourth embodiment, the curved surface 32C is located closer to the buffer layer 14 than the rear surface 18B of the electron supply layer 18. The arc length of the curved surface 32C is longer than the arc length of the connection portion 38 between the contact portion 32 and the wiring portion 34, as in the first embodiment.

[0126] In the fourth embodiment, the tip portion 32P of the contact portion 32 is composed of a tip surface 32B and a curved surface 32C. That is, the tip portion 32P fills the recess portion 54 provided in the electron transit layer 16. The relationship between the width direction (X-axis direction) of the wiring portion 34 and the width direction length of the tip portion 32P of the contact portion 32 is the same as in the first embodiment.

[0127] In the fourth embodiment, the entire curved surface 32C is in contact with the electron transit layer 16, but this is not limiting. For example, a portion of the curved surface 32C may be in contact with the electron supply layer 18. In this case, a recessed curved surface is formed in a portion of the electron supply layer 18. In other words, the recessed curved surface is formed in both the electron supply layer 18 and the electron transit layer 16.

[0128] (Effects) The nitride semiconductor device 10 of the fourth embodiment has the following effects. (4-1) The opening 50 has a through portion 52 that penetrates both the dielectric layer 22 and the electron supply layer 18, and a recess portion 54 that is continuous with the through portion 52 and is provided in the electron transit layer 16. The opening 50 penetrates both the dielectric layer 22 and the electron supply layer 18 and is also formed in at least a portion of the electron transit layer 16. The contact portion 32 penetrates the dielectric layer 22 and the electron supply layer 18 through the opening 50 to reach the electron transit layer 16. The inclined surface 32A of the contact portion 32 includes a first portion 32AA that contacts the dielectric layer 22 and a second portion 32AB that contacts the electron supply layer 18. The curved surface 32C of the contact portion 32 contacts at least the electron transit layer 16.

[0129] According to this configuration, the inclined surface 32A and the curved surface 32C of the contact portion 32 reduce stress generated in the electrode 30 during heat treatment in the manufacturing process of the nitride semiconductor device 10. This makes it possible to suppress the generation of voids VX between the tip surface 32B and the electron transit layer 16. This prevents an increase in contact resistance between the electrode 30 (contact portion 32) and the 2DEG 20. Because the generation of voids VX is suppressed in this way, a stable ohmic contact structure with low contact resistance between the electrode 30 and the 2DEG 20 can be achieved.

[0130] (4-2) The electron transit layer 16 includes a surface 16A in contact with the electron supply layer 18 and a recess bottom surface 16C serving as a bottom surface in contact with the tip surface 32B of the contact portion 32. The distance between the surface 16A of the electron transit layer 16 and the recess bottom surface 16C in the thickness direction (Z-axis direction) of the electron transit layer 16 is 20 nm or less.

[0131] 10, the contact resistance is small when the tip surface 32B of the contact portion 32 is located less than 20 nm from the surface 16A of the electron transit layer 16. Therefore, the contact resistance can be reduced by setting the distance between the surface 16A of the electron transit layer 16 and the recess bottom surface 16C to 20 nm or less.

[0132] Furthermore, for example, if the electron supply layer 18 is thin, it is difficult to form the recess 54 in the electron supply layer 18, but the recess 54 can be easily formed by forming the recess 54 in the electron transit layer 16. Therefore, the manufacturing process of the nitride semiconductor device 10 can be stabilized.

[0133] Fifth Embodiment The configuration of a nitride semiconductor device 10 according to a fifth embodiment will be described with reference to Figures 14 and 15. The nitride semiconductor device 10 according to the fifth embodiment differs from the nitride semiconductor device 10 according to the first embodiment in that it is configured as a high electron mobility transistor (HEMT). Below, differences from the nitride semiconductor device 10 according to the first embodiment will be described in detail, and components common to the nitride semiconductor device 10 according to the first embodiment will be denoted by the same reference numerals and will not be described again.

[0134] 14 , in the fifth embodiment, the nitride semiconductor device 10 includes a gate layer 70 formed on the electron supply layer 18, and a gate electrode 72 formed on the gate layer 70. The nitride semiconductor device 10 further includes a source electrode 74 and a drain electrode 76.

[0135] The gate layer 70 has a band gap smaller than that of the electron supply layer 18 and is made of a nitride semiconductor containing acceptor-type impurities. The gate layer 70 can be made of any material having a band gap smaller than that of the electron supply layer 18, which is, for example, an AlGaN layer. In one example, the gate layer 70 is a GaN layer doped with acceptor-type impurities (p-type GaN layer). The acceptor-type impurities can include at least one of zinc (Zn), magnesium (Mg), and C. The maximum concentration of the acceptor-type impurities in the gate layer 70 is, for example, 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The following is the result.

[0136] As described above, the energy levels of the electron transit layer 16 and the electron supply layer 18 are raised by including acceptor-type impurities in the gate layer 70. Therefore, in the region immediately below the gate layer 70, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. Therefore, at zero bias when no voltage is applied to the gate electrode 72, no 2DEG 20 is formed in the region of the electron transit layer 16 immediately below the gate layer 70. On the other hand, 2DEG 20 is formed in the region of the electron transit layer 16 other than the region immediately below the gate layer 70.

[0137] In this way, the presence of the gate layer 70 doped with acceptor-type impurities depletes the 2DEG 20 in the region directly below the gate layer 70. As a result, normally-off operation is achieved in the nitride semiconductor device 10. When an appropriate on-voltage is applied to the gate electrode 72, a channel is formed by the 2DEG 20 in the electron transit layer 16 in the region directly below the gate electrode 72, thereby establishing conduction between the source and the drain.

[0138] The gate electrode 72 is composed of one or more metal layers. One example of the gate electrode 72 is a TiN layer. Alternatively, the gate electrode 72 may be composed of a first metal layer made of a material containing Ti and a second metal layer made of a material containing TiN and stacked on the first metal layer. The thickness of the gate electrode 72 may be, for example, 50 nm or more and 200 nm or less. The gate electrode 72 can form a Schottky junction with the gate layer 70.

[0139] In the fifth embodiment, the dielectric layer 22 covers the electron supply layer 18, the gate layer 70, and the gate electrode 72. In addition, in the fifth embodiment, the opening 50 includes a source opening 50A and a drain opening 50B. Each of the source opening 50A and the drain opening 50B is separated from the gate layer 70. The gate layer 70 is located between the source opening 50A and the drain opening 50B in the X-axis direction. More specifically, the gate layer 70 is located between the source opening 50A and the drain opening 50B and closer to the source opening 50A than the drain opening 50B. The configurations of the source opening 50A and the drain opening 50B are similar to the configuration of the opening 50 in the first embodiment.

[0140] In the fifth embodiment, a plurality of electrodes 30 are provided, each constituting a source electrode 74 and a drain electrode 76. The source electrode 74 is electrically connected to the electron supply layer 18 through the source opening 50A. The source electrode 74 includes a contact portion 74A and a field plate portion 74B continuous with the contact portion 74A. The contact portion 74A is a portion embedded in the source opening 50A. That is, the contact portion 74A corresponds to the contact portion 32 of the electrode 30. Therefore, the configuration of the contact portion 74A is the same as the configuration of the contact portion 32. The field plate portion 74B covers the dielectric layer 22 and includes an end portion 74C located between the drain opening 50B and the gate layer 70 in the X-axis direction in a plan view. The field plate portion 74B is separated from the drain electrode 76 formed in the drain opening 50B. The field plate portion 74B extends along the surface 22A of the dielectric layer 22 from the contact portion 74A to the end portion 74C toward the drain electrode 76. The field plate portion 74B serves to alleviate electric field concentration near the end of the gate electrode 72 when there is no gate voltage applied to the gate electrode 72 (zero bias). Although the shape is different, the field plate portion 74B corresponds to the wiring portion 34 of the electrode 30. Therefore, the field plate portion 74B has a layered structure of the electrode layer 40, the first barrier layer 42, and the second barrier layer 44.

[0141] The drain electrode 76 is electrically connected to the electron supply layer 18 through the drain opening 50B. The drain electrode 76 includes a contact portion 76A and a wiring portion 76B continuous with the contact portion 76A. The contact portion 76A is a portion embedded in the drain opening 50B. That is, the contact portion 76A corresponds to the contact portion 32 of the electrode 30. Therefore, the configuration of the contact portion 76A is the same as the configuration of the contact portion 32. Furthermore, the wiring portion 76B corresponds to the wiring portion 34 of the electrode 30. Therefore, the wiring portion 76B has a stacked structure of the electrode layer 40, the first barrier layer 42, and the second barrier layer 44.

[0142] The electrode layer 40 of both the source electrode 74 and the drain electrode 76 is composed of one or more metal layers (e.g., Ti, Al, TiN, etc.). The source electrode 74 and the drain electrode 76 are in contact with the electron supply layer 18 through the source opening 50A and the drain opening 50B, respectively. As a result, both the source electrode 74 and the drain electrode 76 are in ohmic contact with the 2DEG 20. The insulating layer 24 is formed to cover both the source electrode 74 and the drain electrode 76.

[0143] 15 shows a planar structure of an exemplary formation pattern 100 of the nitride semiconductor device 10 according to the fifth embodiment. For ease of understanding, components in FIG. 15 that are similar to those in FIG. 14 are denoted by the same reference numerals. The drain electrode 76, the source electrode 74, and the dielectric layer 22 are depicted as being transparent so that the underlying components (e.g., the gate layer 70) can be seen. Only the outer edges of the source electrode 74 and the drain electrode 76 are depicted with dashed lines. Only the source opening 50A and the drain opening 50B of the dielectric layer 22 are depicted.

[0144] 15, the formation pattern 100 includes an active region 102 that contributes to the transistor operation and an inactive region 104 that does not contribute to the transistor operation. The active region 102 is a region through which a current flows between the source and the drain when a voltage is applied to the gate electrode 72.

[0145] In the active region 102, multiple nitride semiconductor devices (four in the example of FIG. 15 ) are continuously formed along the X-axis direction. Each of the nitride semiconductor devices shown in FIG. 15 corresponds to the nitride semiconductor device 10 in FIG. 14 . That is, the cross-sectional view shown in FIG. 14 corresponds to an enlarged portion of the cross section of the formation pattern 100 in the active region 102, where one nitride semiconductor device (including a gate electrode and associated source and drain electrodes) is present. In the active region 102, the field plate portion 74B of the source electrode 74 includes an end portion 74C located between the drain opening 50B and the gate layer 70. A drain electrode 76 is formed in the active region 102. On the other hand, the drain electrode 76 is not formed in the non-active region 104. As shown in FIG. 15 , the source electrode 74, the gate layer 70, and the gate electrode 72 are continuously formed along the Y-axis direction across the active region 102 and the non-active region 104.

[0146] (Function) The function of the nitride semiconductor device 10 of the fifth embodiment will be described. The breakdown field of a group III nitride semiconductor is approximately ten times larger than that of Si. This makes it a suitable material for small, low-resistance nitride semiconductor devices. In a HEMT using this group III nitride semiconductor, a high-concentration 2DEG 20 is formed, thereby reducing the channel resistance and access resistance. Here, the channel resistance is the resistance directly below the gate layer 70, and the access resistance is the resistance between the gate and source and between the gate and drain.

[0147] In order to realize a HEMT with stable low resistance, it is considered to reduce the contact resistance between the source electrode 74 and the drain electrode 76, which becomes parasitic resistance, and the 2DEG 20 via the electron supply layer 18. Therefore, in the fifth embodiment, the contact structure between the source electrode 74 and the electron supply layer 18 and the contact structure between the drain electrode 76 and the electron supply layer 18 are configured in the same manner as the contact structure between the contact portion 32 of the electrode 30 and the electron supply layer 18 in the first embodiment. This makes it possible to suppress an increase in contact resistance caused by voids VX (see FIG. 5 ). Therefore, a HEMT with stable low resistance can be realized.

[0148] Furthermore, the recesses 54 in both the source opening 50A and the drain opening 50B provided in the electron supply layer 18 can further reduce the contact resistance between the source electrode 74 and the drain electrode 76 and the 2DEG 20 via the electron supply layer 18. Therefore, a HEMT with even lower resistance can be realized.

[0149] (Effects) The nitride semiconductor device 10 of the fifth embodiment has the following effects. (5-1) The opening 50 includes a source opening 50A and a drain opening 50B. The nitride semiconductor device 10 includes a gate electrode 72 provided on the electron supply layer 18 and covered with a dielectric layer 22, a source electrode 74 electrically connected to the electron supply layer 18 through the source opening 50A, and a drain electrode 76 electrically connected to the electron supply layer 18 through the drain opening 50B. At least one electrode 30 is provided, and constitutes at least one of the source electrode 74 and the drain electrode 76.

[0150] According to this configuration, the electrode 30 constitutes the source electrode 74, thereby reducing the contact resistance between the source electrode 74 and the 2DEG 20 via the electron supply layer 18. Furthermore, the electrode 30 constitutes the drain electrode 76, thereby reducing the contact resistance between the drain electrode 76 and the 2DEG 20 via the electron supply layer 18. Therefore, a low-resistance HEMT can be realized.

[0151] (5-2) The source opening 50A, the drain opening 50B, and the gate electrode 72 are spaced apart from each other. The source opening 50A is located on the opposite side of the gate electrode 72 from the drain opening 50B. The source electrode 74 includes a field plate portion 74B that extends from the source opening 50A to a position closer to the drain opening 50B than the gate electrode 72.

[0152] With this configuration, the field plate portion 74B can alleviate electric field concentration near the end of the gate electrode 72 at zero bias when no gate voltage is applied to the gate electrode 72. Furthermore, when a high voltage is applied to the drain electrode 76, electric field concentration can be alleviated at one of the ends of the gate layer 70 in the X-axis direction that is closer to the drain electrode 76.

[0153] (5-3) The nitride semiconductor device 10 includes a gate layer 70 provided on the electron supply layer 18 and made of a semiconductor having a smaller band gap than the electron supply layer 18. A gate electrode 72 is disposed on the gate layer 70.

[0154] With this configuration, the gate layer 70 can deplete the 2DEG 20 directly below the gate layer 70. This allows a normally-off HEMT to be realized. Such a HEMT is suitable for power devices that require high safety.

[0155] (5-4) The electron supply layer 18 is Al ｘ Ga １－ｘ N layer (0.2≦x≦0.3). With this configuration, when the Al composition ratio is 0.2 or more and 0.3 or less, a recess portion 54 including the recess inclined surface 18E, the recess curved surface 18D, and the recess bottom surface 18C can be formed in the electron supply layer 18. This makes it possible to suppress an increase in contact resistance between the electrode 30 (contact portion 32) and the 2DEG 20 via the electron supply layer 18. Therefore, a HEMT with stable low resistance can be realized.

[0156] [Modifications] The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0157] 16, the contact portion 32 may have a curved surface 39B provided between the step portion 39 and the first portion 32AA of the inclined surface 32A. The curved surface 39B has the same configuration as, for example, the curved surface 32C. The arc length of the curved surface 39B is equal to the arc length of the curved surface 32C.

[0158] In the fifth embodiment, the electrode 30 may constitute the source electrode 74 but may not constitute the drain electrode 76. In other words, the contact portion 74A of the source electrode 74 may correspond to the contact portion 32 of the electrode 30, while the contact portion 76A of the drain electrode 76 may not correspond to the contact portion 32 of the electrode 30. In this case, the contact portion 76A does not have the inclined surface 32A and the curved surface 32C as the contact portion 32 does.

[0159] Alternatively, the electrode 30 may constitute the drain electrode 76 but not the source electrode 74. In this case, the contact portion 74A of the source electrode 74 does not have the inclined surface 32A and the curved surface 32C like the contact portion 32 of the electrode 30.

[0160] In the fifth embodiment, the configuration of at least one of the source electrode 74 and the drain electrode 76 may be changed to any one of the configurations of the electrodes 30 in the second to fourth embodiments. The configuration of the contact portion 32 of the electrode 30 corresponding to the source electrode 74 and the configuration of the contact portion 32 of the electrode 30 corresponding to the drain electrode 76 may be different from each other.

[0161] In the first and second embodiments, the position of the tip surface 32B of the contact portion 32 in the Z-axis direction can be changed as desired within the thickness range of the electron supply layer 18. In one example, as shown in Fig. 17 , the tip surface 32B of the contact portion 32 may be in contact with the surface 16A of the electron transit layer 16. In other words, the contact portion 32 may penetrate the electron supply layer 18. On the other hand, the contact portion 32 does not penetrate into the electron transit layer 16 in the Z-axis direction.

[0162] In the first and second embodiments, the recess slope 18E may be omitted from the recess portion 54. In the fourth embodiment, the recess portion 54 may have a recess slope. The recess slope is provided in the electron transit layer 16. The recess slope is sloped so that the opening width of the opening 50 narrows toward the recess curved surface 16D. Here, the opening width of the opening 50 can be defined by the size of the opening 50 in the X-axis direction. The slope angle of the recess slope with respect to the Z-axis direction is equal to the slope angle of the inner surface 18F of the electron supply layer 18 with respect to the Z-axis direction. The recess slope and the inner surface 18F are continuous and flush with each other.

[0163] In the fifth embodiment, the gate layer 70 may be omitted. In this case, the gate electrode 72 is formed on the electron supply layer 18. This makes the nitride semiconductor device 10 normally on.

[0164] In each embodiment, the first barrier layer 42 may be omitted. In each embodiment, the second barrier layer 44 may be omitted. In each embodiment, the insulating layer 24 may be omitted.

[0165] In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B." The term "on" as used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Therefore, the expression "a first layer is formed on a second layer" means that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers. For example, the above embodiments in which the electron supply layer 18 is formed on the electron transit layer 16 also include a structure in which an intermediate layer is located between the electron supply layer 18 and the electron transit layer 16 to stably form the 2DEG 20.

[0166] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0167] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "forward," "rearward," "sideways," "left," "right," "front," "rear," etc., used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0168] [Notes] The technical ideas that can be understood from the above-described embodiments and modifications are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each note are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each note should not be limited to the components indicated by the reference numerals.

[0169] (Supplementary Note 1) A nitride semiconductor device (10) comprising: an electron transit layer (16); an electron supply layer (18) formed on the electron transit layer (16) and having a band gap larger than that of the electron transit layer (16); a dielectric layer (22) formed on the electron supply layer (18); and an electrode (30) having a contact portion (32) in electrical contact with the electron supply layer (18) via an opening (50) penetrating at least the dielectric layer (22), wherein the contact portion (32) has an inclined surface (32A) inclined so as to narrow toward the electron transit layer (16), a tip surface (32B) in contact with a bottom surface of the opening (50), and a curved surface (32C) provided between the tip surface (32B) and the inclined surface (32A) and curved so as to be convex toward the electron transit layer (16).

[0170] (Supplementary Note 2) The nitride semiconductor device according to Supplementary Note 1, wherein the opening (50) has a through portion (52) penetrating the dielectric layer (22) and a recess portion (54) continuous with the through portion (52) and provided in the electron supply layer (18), the opening (50) also penetrating the dielectric layer (22) and being formed in at least a part of the electron supply layer (18), the inclined surface (32A) including a first portion (32AA) in contact with the dielectric layer (22) and a second portion (32AB) in contact with the electron supply layer (18), and the curved surface (32C) in contact with the electron supply layer (18).

[0171] (Supplementary Note 3) The nitride semiconductor device according to Supplementary Note 2, wherein the tip surface (32B) is in contact with the electron supply layer (18).

[0172] (Supplementary Note 4) The nitride semiconductor device according to Supplementary Note 3, wherein the tip surface (32B) is provided closer to the electron transit layer (16) than a center of the electron supply layer (18) in a thickness direction (Z-axis direction) of the electron supply layer (18).

[0173] (Supplementary Note 5) The opening (50) has a through portion (52) that penetrates both the dielectric layer (22) and the electron supply layer (18), and a recess portion (54) that is continuous with the through portion (52) and is provided in the electron transit layer (16), the opening (50) penetrates both the dielectric layer (22) and the electron supply layer (18) and is also formed in at least a portion of the electron transit layer (16), the contact portion (32) penetrates the dielectric layer (22) and the electron supply layer (18) via the opening (50) and reaches the electron transit layer (16), the inclined surface (32A) includes a first portion (32AA) that contacts the dielectric layer (22) and a second portion (32AB) that contacts the electron supply layer (18), and the curved surface (32C) contacts at least the electron transit layer (16). 2. The nitride semiconductor device according to claim 1.

[0174] (Supplementary Note 6) The nitride semiconductor device according to Supplementary Note 5, wherein the electron transit layer (16) includes a surface (16A) in contact with the electron supply layer (18) and a bottom surface (16C) in contact with the tip surface (32B), and a distance between the surface (16A) of the electron transit layer (16) and the bottom surface (16C) of the electron transit layer (16) in a thickness direction (Z-axis direction) of the electron transit layer (16) is 20 nm or less.

[0175] (Supplementary Note 7) The nitride semiconductor device according to any one of Supplementary Notes 2 to 6, wherein an inclination angle of the first portion (32AA) with respect to a thickness direction (Z-axis direction) of the electron transit layer (16) and an inclination angle of the second portion (32AB) with respect to the thickness direction (Z-axis direction) of the electron transit layer (16) are equal to each other.

[0176] (Supplementary Note 8) The nitride semiconductor device according to Supplementary Note 7, wherein both an inclination angle of the first portion (32AA) with respect to a thickness direction (Z-axis direction) of the electron transit layer (16) and an inclination angle of the second portion (32AB) with respect to the thickness direction (Z-axis direction) of the electron transit layer (16) are 10° or more and 20° or less.

[0177] (Supplementary Note 9) The nitride semiconductor device according to any one of Supplementary Notes 2 to 8, wherein the first portion (32AA) and the second portion (32AB) are continuous and flush with each other.

[0178] (Supplementary Note 10) The nitride semiconductor device according to any one of Supplementary Notes 2 to 8, wherein the contact portion (32) includes a step portion (39) provided between the first portion (32AA) and the second portion (32AB), and the step portion (39) is in contact with a surface (18A) of the electron supply layer (18) that is in contact with the dielectric layer (22).

[0179] (Supplementary Note 11) The nitride semiconductor device according to Supplementary Note 1, wherein the tip surface (32B) and a surface (18A) of the electron supply layer (18) that contacts the dielectric layer (22) are flush with each other.

[0180] (Supplementary Note 12) The nitride semiconductor device according to any one of Supplementary Notes 1 to 11, wherein the electrode (30) has a wiring portion (34) provided on the dielectric layer (22), and a length (L2) in a width direction (X-axis direction) of the wiring portion (34) is at least twice the length (L1) in the width direction (X-axis direction) of a tip portion (32P) of the contact portion (32).

[0181] (Supplementary Note 13) The nitride semiconductor device according to any one of Supplementary Notes 1 to 12, wherein the electrode (30) includes an electrode layer (40), and the electrode layer (40) includes at least Ti, Al, and Cu.

[0182] (Supplementary Note 14) The nitride semiconductor device according to Supplementary Note 13, wherein the electrode (30) has a wiring portion (34) provided on the dielectric layer (22), the wiring portion (34) includes a first barrier layer (42) in contact with the dielectric layer (22), and the electrode layer (40) includes a portion provided on the first barrier layer (42).

[0183] (Supplementary Note 15) The nitride semiconductor device according to Supplementary Note 14, wherein the first barrier layer (42) contains any one of TiN, WSiN, and WN.

[0184] (Supplementary Note 16) The nitride semiconductor device according to Supplementary Note 14 or 15, wherein the wiring portion (34) includes a second barrier layer (44) provided on the electrode layer (40) on the opposite side to the first barrier layer (42).

[0185] (Supplementary Note 17) The nitride semiconductor device according to Supplementary Note 16, wherein the second barrier layer (44) contains any one of TiN, WSiN, and WN.

[0186] (Supplementary Note 18) The nitride semiconductor device according to any one of Supplementary Notes 1 to 17, wherein the opening (50) includes a source opening (50A) and a drain opening (50B), and the nitride semiconductor device comprises: a gate electrode (72) provided on the electron supply layer (18) and covered with the dielectric layer (22); a source electrode (74) electrically connected to the electron supply layer (18) through the source opening (50A); and a drain electrode (76) electrically connected to the electron supply layer (18) through the drain opening (50B), and at least one electrode (30) is provided and constitutes at least one of the source electrode (74) and the drain electrode (76).

[0187] (Supplementary Note 19) The nitride semiconductor device according to Supplementary Note 18, wherein the source opening (50A), the drain opening (50B), and the gate electrode (72) are arranged spaced apart from each other, the source opening (50A) is arranged on the opposite side of the gate electrode (72) from the drain opening (50B), and the source electrode (74) includes a field plate portion (74B) extending from the source opening (50A) to a position closer to the drain opening (50B) than the gate electrode (72).

[0188] (Supplementary Note 20) The nitride semiconductor device according to Supplementary Note 18 or 19, further comprising: a gate layer (70) provided on the electron supply layer (18) and made of a semiconductor having a band gap smaller than that of the electron supply layer (18), and the gate electrode (72) is disposed on the gate layer (70).

[0189] (Appendix 21) The electron supply layer (18) is Al ｘ Ga １－ｘ The nitride semiconductor device according to any one of appendices 1 to 20, wherein the nitride semiconductor layer is an N layer (0.2≦x≦0.3).

[0190] (Supplementary Note 22) The nitride semiconductor device according to any one of Supplementary Notes 13 to 17, wherein the contact portion (32) is constituted only by the electrode layer (40).

[0191] (Supplementary Note 23) The nitride semiconductor device according to Supplementary Note 10, wherein the contact portion (32) has a curved surface (39B) provided between the step portion (39) and the first portion (32AA) of the inclined surface (32A).

[0192] (Supplementary Note 24) The nitride semiconductor device according to Supplementary Note 1, wherein the opening (50) has a through portion (52) that passes through both the dielectric layer (22) and the electron supply layer (18), and a recess portion (54) that is continuous with the through portion (52) and is provided in the electron supply layer (18), the opening (50) passes through both the dielectric layer (22) and the electron supply layer (18), the contact portion (32) passes through the dielectric layer (22) and the electron supply layer (18) via the opening (50), the inclined surface (32A) includes a first portion (32AA) that is in contact with the dielectric layer (22) and a second portion (32AB) that is in contact with the electron supply layer (18), and the tip surface (32B) is in contact with a surface (16A) of the electron transit layer (16) that is in contact with the electron supply layer (18).

[0193] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0194] DESCRIPTION OF SYMBOLS 10...Nitride semiconductor device 12...Substrate 14...Buffer layer 16...Electron transit layer 16A...Front surface 16B...Back surface 16C...Recess bottom surface 16D...Curved recess surface 18...Electron supply layer 18A...Front surface 18B...Back surface 18C...Recess bottom surface 18D...Curved recess surface 18E...Curved recess surface 18F...Inner surface 20...2DEG 22...Dielectric layer 22A...Front surface 22B...Inner surface 22BA...Dielectric-side inclined surface 22BB...Curved dielectric-side surface 24...Insulating layer 30...Electrode 32...Contact portion 32A...Inclined surface 32AA...First portion 32AB...Second portion 32AC...Third portion 32B...Tip surface 32C...Curved surface 32P...Tip portion 34...Wiring portion 34A...Outer surface 36...Recess 36A...bottom surface 38...connection portion 39...step portion 39A...step surface 39B...curved surface 40...electrode layer 40A...outer surface 42...first barrier layer 42A...outer surface 42B...inner surface 42C...surface 42D...barrier-side curved surface 44...second barrier layer 44A...outer surface 50...opening 50A...source opening 50B...drain opening 52...through portion 52A...first through portion 52B...second through portion 54...recess portion 56...barrier-side through portion 60...mask 62...opening 64...mask 66...inclined surface 70...gate layer 72...gate electrode 74...source electrode 74A...contact portion 74B...field plate portion 74C...end portion 76...drain electrode 76A...contact portion 76B...wiring portion 100...forming pattern 102... Active region 104... Inactive region L1... Length of tip of contact portion L2... Length of wiring portion 10X... Comparative nitride semiconductor device 50X... Opening 32X... Contact portion 32XA... Outer surface 32XB... Tip surface 32XC... Corner portion VX... Void

Claims

1. An electron transport layer; an electron supply layer formed on the electron transit layer and having a band gap larger than that of the electron transit layer; a dielectric layer formed on the electron supply layer; an electrode having a contact portion electrically contacting the electron supply layer through at least an opening penetrating the dielectric layer; Equipped with The contact portion is an inclined surface that is inclined so that its width becomes narrower toward the electron transit layer; a tip surface in contact with a bottom surface of the opening; a curved surface provided between the tip surface and the inclined surface and curved so as to be convex toward the electron transit layer; The nitride semiconductor device has

2. The opening is a through portion penetrating the dielectric layer; a recess portion provided in the electron supply layer and continuous with the through portion; the opening is formed through the dielectric layer and also in at least a part of the electron supply layer; The inclined surface is a first portion in contact with the dielectric layer; a second portion in contact with the electron supply layer; Including, The curved surface is in contact with the electron supply layer. The nitride semiconductor device according to claim 1 .

3. The tip surface is in contact with the electron supply layer. The nitride semiconductor device according to claim 2 .

4. The tip surface is provided closer to the electron transit layer than the center of the electron supply layer in the thickness direction of the electron supply layer. The nitride semiconductor device according to claim 3 .

5. The opening is a through portion that penetrates both the dielectric layer and the electron supply layer; a recess portion provided in the electron transit layer and continuous with the through portion; the opening is formed through both the dielectric layer and the electron supply layer and also in at least a part of the electron transit layer, the contact portion penetrates the dielectric layer and the electron supply layer through the opening to reach the electron transit layer, The inclined surface is a first portion in contact with the dielectric layer; a second portion in contact with the electron supply layer; Including, The curved surface is in contact with at least the electron transport layer. The nitride semiconductor device according to claim 1 .

6. the electron transit layer includes a surface in contact with the electron supply layer and a bottom surface in contact with the tip surface, The distance between the surface of the electron transport layer and the bottom surface of the electron transport layer in the thickness direction of the electron transport layer is 20 nm or less. The nitride semiconductor device according to claim 5 .

7. The inclination angle of the first portion with respect to the thickness direction of the electron transit layer and the inclination angle of the second portion with respect to the thickness direction of the electron transit layer are equal to each other. The nitride semiconductor device according to any one of claims 2 to 6.

8. Both the inclination angle of the first portion with respect to the thickness direction of the electron transit layer and the inclination angle of the second portion with respect to the thickness direction of the electron transit layer are 10° or more and 20° or less. The nitride semiconductor device according to claim 7 .

9. The first portion and the second portion are continuous and flush with each other. The nitride semiconductor device according to any one of claims 2 to 6.

10. the contact portion includes a step portion provided between the first portion and the second portion, The step portion is in contact with a surface of the electron supply layer that is in contact with the dielectric layer. The nitride semiconductor device according to any one of claims 2 to 6.

11. The tip surface and a surface of the electron supply layer that is in contact with the dielectric layer are flush with each other. The nitride semiconductor device according to claim 1 .

12. The electrode has a wiring portion provided on the dielectric layer, The width of the wiring portion is at least twice the width of the tip of the contact portion. The nitride semiconductor device according to any one of claims 1 to 6.

13. The electrode includes an electrode layer, The electrode layer includes at least Ti, Al, and Cu. The nitride semiconductor device according to any one of claims 1 to 6.

14. The electrode has a wiring portion provided on the dielectric layer, the wiring portion includes a first barrier layer in contact with the dielectric layer, The electrode layer includes a portion provided on the first barrier layer. The nitride semiconductor device according to claim 13.

15. The first barrier layer includes any one of TiN, WSiN, and WN. The nitride semiconductor device according to claim 14.

16. The wiring portion includes a second barrier layer provided on the opposite side of the electrode layer from the first barrier layer. The nitride semiconductor device according to claim 14.

17. The second barrier layer includes any one of TiN, WSiN, and WN. The nitride semiconductor device according to claim 16.

18. the openings include a source opening and a drain opening; a gate electrode provided on the electron supply layer and covered with the dielectric layer; a source electrode electrically connected to the electron supply layer through the source opening; a drain electrode electrically connected to the electron supply layer through the drain opening; Equipped with At least one electrode is provided, and constitutes at least one of the source electrode and the drain electrode. The nitride semiconductor device according to any one of claims 1 to 6.

19. the source opening, the drain opening, and the gate electrode are spaced apart from one another; the source opening is disposed on an opposite side of the gate electrode from the drain opening, The source electrode includes a field plate portion extending from the source opening to a position closer to the drain opening than the gate electrode. The nitride semiconductor device according to claim 18.

20. a gate layer provided on the electron supply layer and made of a semiconductor having a band gap smaller than that of the electron supply layer; The gate electrode is disposed on the gate layer. The nitride semiconductor device according to claim 18.

21. The electron supply layer is Al ｘ G １－ｘ N layers (0.2≦x≦0.3). The nitride semiconductor device according to any one of claims 1 to 6.