Semiconductor module

Abstract

This semiconductor module includes an IGBT device and a MISFET device that constitutes a parallel circuit with the IGBT device. The semiconductor module generates a drain current of the MISFET device in a voltage range lower than the built-in voltage of the IGBT device, and generates a collector current of the IGBT device and a drain current of the MISFET in a voltage range higher than or equal to the built-in voltage.

Description

Semiconductor Module

[0001] This application claims priority from Japanese Patent Application No. 2022-061318 filed on March 31, 2022, the entire content of which is incorporated herein by reference. The present invention relates to a semiconductor module including an IGBT device and a MISFET device that forms a parallel circuit with the IGBT device.

[0002] Patent Document 1 discloses a power transistor drive device having a parallel circuit including an insulated gate bipolar transistor and a field effect transistor, in which the field effect transistor is controlled to be in an on state after the insulated gate bipolar transistor is controlled to be in an on state.

[0003] US Patent Application Publication No. 2018 / 0138904

[0004] One embodiment provides a semiconductor module capable of improving electrical characteristics.

[0005] One embodiment provides a semiconductor module including an IGBT device and a MISFET device that forms a parallel circuit with the IGBT device, generating a drain current of the MISFET device in a voltage range that is less than a built-in voltage of the IGBT device, and generating a collector current of the IGBT device and a drain current of the MISFET device in a voltage range that is equal to or greater than the built-in voltage.

[0006] The above and other objects, features, and advantages will become apparent from the following description of the embodiments with reference to the accompanying drawings.

[0007] FIG. 1 is a circuit diagram showing the electrical structure of a semiconductor module according to an embodiment. FIG. 2 is a graph showing electrical characteristics of the semiconductor module shown in FIG. 1. FIG. 3 is a plan view showing an example configuration of an IGBT device incorporated in the semiconductor module shown in FIG. 1. FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 3. FIG. 5 is a plan view showing an example layout of the first chip shown in FIG. 3. FIG. 6 is a cross-sectional view showing a main portion of the first active region shown in FIG. 5. FIG. 7 is a plan view showing an example configuration of a MISFET device incorporated in the semiconductor module shown in FIG. 1. FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII in FIG. 7. FIG. 9 is a plan view showing an example layout of the second chip shown in FIG. 7. FIG. 10 is a cross-sectional view showing a main portion of the second active region shown in FIG. 7. FIG. 11A is a graph showing current-voltage characteristics according to a first adjustment example of the semiconductor module shown in FIG. 1. FIG. 11B is a graph showing current-voltage characteristics according to a second adjustment example of the semiconductor module shown in FIG. 1. 11C is a graph showing current-voltage characteristics according to a third adjustment example of the semiconductor module shown in FIG. 1. FIG. 12 is a perspective view showing one configuration example of a semiconductor module. FIG. 13 is a plan view showing the internal structure of the semiconductor module shown in FIG. 12. FIG. 14 is a plan view showing another configuration example of a semiconductor module. FIG. 15 is a plan view showing another configuration example of a semiconductor module. FIG. 16 is a cross-sectional view showing another configuration example of an IGBT device. FIG. 17 is a cross-sectional view showing another configuration example of a MISFET device. FIG. 18 is a cross-sectional view showing another configuration example of a MISFET device. FIG. 19 is a cross-sectional view showing another configuration example of a MISFET device. FIG. 20 is a cross-sectional view showing another configuration example of a MISFET device.

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0009] When the phrase "substantially equal" is used in a description in which a comparison target is present, this phrase includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not attached with the intent of limiting the names of each structure.

[0010] 1 is a circuit diagram showing the electrical structure of a semiconductor module 1 according to one embodiment. Referring to FIG. 1, the semiconductor module 1 includes an insulated gate bipolar transistor (IGBT) device 2 and a metal semiconductor field effect transistor (MISFET) device 3 that configures a parallel switching circuit together with the IGBT device 2.

[0011] The IGBT device 2 is a first semiconductor switching device (first semiconductor device) of a bipolar type having an IGBT, and includes a collector C, an emitter E, and a first gate G1. The MISFET device 3 is a second semiconductor switching device (second semiconductor device) of a unipolar type having a MISFET, and includes a drain D, a source S, and a second gate G2.

[0012] The drain D of the MISFET device 3 is electrically connected to the collector C of the IGBT device 2. The source S of the MISFET device 3 is electrically connected to the emitter E of the IGBT device 2. The second gate G2 of the MISFET device 3 is electrically connected to the first gate G1 of the IGBT device 2.

[0013] The first gate G1 of the IGBT device 2 and the second gate G2 of the MISFET device 3 are electrically connected to a gate drive circuit GD, and a gate signal from the gate drive circuit GD is input to the first gate G1 and the second gate G2. That is, the MISFET device 3 is controlled simultaneously with the IGBT device 2. The IGBT device 2 generates a collector current Ice in response to the gate signal, and the MISFET device 3 generates a drain current Ids in response to the gate signal.

[0014] The gate drive circuit GD may be a gate driver IC. Although the semiconductor module 1 is shown electrically connected to the gate drive circuit GD in Fig. 1, the semiconductor module 1 may include the gate drive circuit GD as one of its components.

[0015] Fig. 2 is a graph showing the electrical characteristics of the semiconductor module 1 shown in Fig. 1. In Fig. 2, the vertical axis represents the collector current Ice (drain current Ids), and the horizontal axis represents the collector voltage Vce (drain voltage Vds). Fig. 2 also shows the characteristics of the output current IO of the semiconductor module 1. The output current IO is the sum of the collector current Ice and the drain current Ids.

[0016] 2 , the semiconductor module 1 generates an output current IO consisting of only the drain current Ids of the MISFET device 3 in a voltage range below the built-in voltage Vbi of the IGBT device 2. On the other hand, the semiconductor module 1 generates an output current IO including the drain current Ids of the MISFET device 3 and the collector current Ice of the IGBT device 2 in a voltage range equal to or higher than the built-in voltage Vbi of the IGBT device 2.

[0017] Since the IGBT device 2 is a bipolar semiconductor switching device, it has a relatively large loss in the low current region below the built-in voltage Vbi and a relatively small loss in the high current region above the built-in voltage Vbi. The loss reduction effect in the high current region of the IGBT device 2 is due to the conductivity modulation effect.

[0018] On the other hand, the MISFET device 3 is a unipolar semiconductor switching device different from the IGBT device 2, and therefore does not have a built-in voltage Vbi and does not exhibit a conductivity modulation effect. The MISFET device 3 has a relatively small loss in the low current region and a relatively large loss in the high current region. The loss in the high current region of the MISFET device 3 can be improved by increasing the size of the MISFET device 3, but this causes problems such as cost and layout changes.

[0019] According to the semiconductor module 1, the drain current Ids of the MISFET device 3 is used in the low current region, thereby reducing loss in the IGBT device 2 in the low current region. Also, the collector current Ice of the IGBT device 2 and the drain current Ids of the MISFET device 3 are used in the high current region, thereby reducing loss in the MISFET device 3 in the high current region.

[0020] Therefore, the semiconductor module 1 can reduce losses in both the low current region and the high current region without increasing the size of the MISFET device 3. This makes it possible to provide a semiconductor module 1 that can improve electrical characteristics. Below, examples of the IGBT device 2 incorporated in the semiconductor module 1 and examples of the MISFET device 3 incorporated in the semiconductor module 1 will be described.

[0021] Fig. 3 is a plan view showing a configuration example of the IGBT device 2 incorporated in the semiconductor module 1 shown in Fig. 1. Fig. 4 is a schematic cross-sectional view taken along line IV-IV shown in Fig. 3. Fig. 5 is a plan view showing an example of the layout within the first chip 10 shown in Fig. 3. Fig. 6 is a cross-sectional view showing a main part of the first active region 17 shown in Fig. 5.

[0022] The IGBT device 2 has a first breakdown voltage VB1. The first breakdown voltage VB1 is a reverse voltage at which reverse voltage breakdown (avalanche breakdown) begins. For example, the first breakdown voltage VB1 may be 500 V or higher and 1500 V or lower. The first breakdown voltage VB1 may have a value belonging to any one of the following ranges: 500 V or higher and 750 V or lower, 750 V or higher and 1000 V or lower, 1000 V or higher and 1250 V or lower, and 1250 V or higher and 1500 V or lower. For example, the first breakdown voltage VB1 may be 500 V or higher and 700 V or lower, or 1100 V or higher and 1300 V or lower.

[0023] 3 to 6, in this embodiment, the IGBT device 2 includes a first chip 10 having a hexahedral shape (specifically, a rectangular parallelepiped shape). The first chip 10 is a Si chip made of single crystal silicon (Si). In other words, the IGBT device 2 is a "Si-IGBT device." The first chip 10 has a single-layer structure made of a Si substrate.

[0024] The first chip 10 has a first chip thickness T1. The first chip thickness T1 may be 50 μm or more and 200 μm or less. The first chip thickness T1 may be a value belonging to any one of the following ranges: 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, and 175 μm or more and 200 μm or less.

[0025] For example, the first chip thickness T1 may be 60 μm or more and 90 μm or less when the first breakdown voltage VB1 is 500 V or more and 700 V or less. For example, when the first breakdown voltage VB1 is 1100 V or more and 1300 V or less, the first chip thickness T1 may be 120 μm or more and 160 μm or less.

[0026] The first chip 10 has a first main surface 11 on one side, a second main surface 12 on the other side, and first to fourth side surfaces 13A to 13D connecting the first main surface 11 and the second main surface 12. The first main surface 11 and the second main surface 12 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the first chip 10. Of course, the first main surface 11 and the second main surface 12 may be formed in a square shape in a plan view.

[0027] The first side surface 13A and the second side surface 13B extend in a first direction X along the first main surface 11 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The first side surface 13A and the second side surface 13B form long sides of the first chip 10. The third side surface 13C and the fourth side surface 13D extend in the second direction Y and face the first direction X. The third side surface 13C and the fourth side surface 13D form short sides of the first chip 10.

[0028] Each of the first to fourth side surfaces 13A to 13D may have a length of 0.1 mm to 20 mm in plan view. The length of each of the first to fourth side surfaces 13A to 13D may have a value that falls within any one of the ranges of 0.1 mm to 1 mm, 1 mm to 2.5 mm, 2.5 mm to 5 mm, 5 mm to 7.5 mm, 7.5 mm to 10 mm, 10 mm to 12.5 mm, 12.5 mm to 15 mm, 15 mm to 17.5 mm, and 17.5 mm to 20 mm.

[0029] The first chip 10 has a first chip area S1 in plan view, which is the product of the length of the first side surface 13A and the length of the third side surface 13C (i.e., the product of the length of the second side surface 13B and the length of the fourth side surface 13D).

[0030] The IGBT device 2 includes an n-type (first conductivity type) semiconductor region 14 formed inside the first chip 10. The semiconductor region 14 is formed throughout the interior of the first chip 10. In this embodiment, the first chip 10 is made of an n-type Si chip, and the semiconductor region 14 is formed using the Si chip.

[0031] The IGBT device 2 includes an n-type buffer region 15 formed in a surface layer portion of the second main surface 12. In this embodiment, the buffer region 15 is formed in a layer shape extending along the second main surface 12 over the entire area of ​​the second main surface 12, and is exposed from the first to fourth side surfaces 13A to 13D. The buffer region 15 has a higher n-type impurity concentration than the semiconductor region 14. The presence or absence of the buffer region 15 is optional, and a configuration without the buffer region 15 may also be employed.

[0032] The IGBT device 2 includes a p-type (second conductivity type) collector region 16 formed in a surface layer portion of the second main surface 12. In this embodiment, the collector region 16 is formed in a surface layer portion on the second main surface 12 side of the buffer region 15. The collector region 16 is formed in a layer shape extending along the second main surface 12 over the entire area of ​​the second main surface 12, and is exposed from the second main surface 12 and the first to fourth side surfaces 13A to 13D.

[0033] The IGBT device 2 includes a first active region 17 provided on the first main surface 11 of the first chip 10. The first active region 17 includes an IGBT structure 18 and is a region that generates a collector current Ice. The first active region 17 has a first active area SA1 in a plan view.

[0034] For example, when a polygonal region (see the two-dot chain line in FIG. 3 ) is defined to encompass the IGBT structure 18 in a plan view, the first active area SA1 is defined by the planar area of ​​the polygonal region. When a plurality of first active regions 17 are provided, the first active area SA1 is defined by the total planar area of ​​the plurality of first active regions 17.

[0035] The first active area SA1 may take various values ​​depending on the first chip area S1. The first active area SA1 may be 30% or more and less than 100% of the first chip area S1. The first active area SA1 may have a value belonging to any one of the following ranges of 30% or more and 40% or less, 40% or more and 50% or less, 50% or more and 60% or less, 60% or more and 70% or less, 70% or more and 80% or less, 80% or more and 90% or less, and 90% or more and less than 100% of the first chip area S1.

[0036] The IGBT structure 18 includes a p-type base region 19 formed in a surface layer portion of the first main surface 11 in the first active region 17. The base region 19 may also be referred to as a "channel region." The base region 19 is formed in a layer shape extending along the first main surface 11 throughout the first active region 17.

[0037] The IGBT structure 18 includes a plurality of first trench structures 20 formed in the first main surface 11 in the first active region 17. A gate potential Vg is applied to the plurality of first trench structures 20. The plurality of first trench structures 20 control inversion and non-inversion of the channel. In other words, the IGBT structure 18 is of a trench gate type. The first trench structures 20 may also be referred to as a "first trench gate structure."

[0038] The multiple first trench structures 20 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. The multiple first trench structures 20 are formed in the first main surface 11 so as to penetrate the base region 19 and reach the semiconductor region 14.

[0039] The depth of each first trench structure 20 may be 0.5 μm or more and 10 μm or less. The depth of each first trench structure 20 may have a value belonging to any one of the ranges of 0.5 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, and 7.5 μm or more and 10 μm or less. The depth of each first trench structure 20 is preferably 4 μm or more and 8 μm or less.

[0040] Each first trench structure 20 includes a first trench 21, a first insulating film 22, and a first buried electrode 23. The first trench 21 is formed in the first main surface 11 and defines the wall surface of the first trench structure 20. The first insulating film 22 coats the wall surface of the first trench 21 in a film-like manner. The first insulating film 22 may include a silicon oxide film. The first buried electrode 23 is buried in the first trench 21 with the first insulating film 22 sandwiched therebetween. In this embodiment, the first buried electrode 23 includes conductive polysilicon.

[0041] The IGBT structure 18 includes a plurality of n-type emitter regions 24 formed in regions along the plurality of first trench structures 20 in a surface layer portion of the base region 19. Each emitter region 24 has a higher n-type impurity concentration than the semiconductor region 14. Each emitter region 24 is formed in a region between two adjacent first trench structures 20 in the surface layer portion of the base region 19. Each emitter region 24, together with the semiconductor region 14, forms a channel of the IGBT in the base region 19.

[0042] The IGBT structure 18 includes a plurality of contact holes 25 formed in the first main surface 11 to expose a plurality of emitter regions 24. Each contact hole 25 is formed in a region between two adjacent first trench structures 20. Each contact hole 25 is formed at an interval from the bottom of the base region 19 toward the first main surface 11. Each contact hole 25 may penetrate the emitter region 24, or may be formed at an interval from the bottom of the emitter region 24 toward the first main surface 11. Each contact hole 25 is formed in a strip shape extending along the first trench structure 20 in a plan view.

[0043] The IGBT structure 18 includes a plurality of p-type first contact regions 26 formed in a surface layer portion of the base region 19 in a region different from the emitter region 24. Each of the first contact regions 26 has a higher p-type impurity concentration than the base region 19. Each of the first contact regions 26 is formed in a region along the wall surface of the corresponding contact hole 25. Each of the first contact regions 26 is formed in a strip shape extending along the corresponding contact hole 25 in a plan view. The bottom of each of the first contact regions 26 is formed in a region between the bottom of the base region 19 and the bottom wall of the corresponding contact hole 25.

[0044] The IGBT device 2 includes a first interlayer insulating film 27 covering the first main surface 11. In this embodiment, the first interlayer insulating film 27 includes a first lower insulating film 28 and a first upper insulating film 29. The first lower insulating film 28 is connected to the first insulating film 22 and covers the first main surface 11 so as to expose the first buried electrodes 23. The first lower insulating film 28 may include a silicon oxide film. The first upper insulating film 29 covers the first lower insulating film 28 so as to cover the multiple first trench structures 20. The first upper insulating film 29 may include a silicon oxide film. The first upper insulating film 29 is thicker than the first lower insulating film 28.

[0045] The first interlayer insulating film 27 includes a plurality of emitter openings 30 that expose the plurality of emitter regions 24. The plurality of emitter openings 30 are formed in a one-to-one correspondence with the plurality of contact holes 25 so as to communicate with the plurality of contact holes 25. The plurality of emitter openings 30 are formed in a strip shape extending along the plurality of contact holes 25.

[0046] The IGBT device 2 includes a plurality of contact electrodes 31 embedded in the first interlayer insulating film 27. The plurality of contact electrodes 31 are embedded in a plurality of emitter openings 30. Each contact electrode 31 extends from the emitter opening 30 into a contact hole 25, and is electrically connected to the emitter region 24 and the first contact region 26 within the contact hole 25.

[0047] The IGBT device 2 includes a first gate electrode 32 disposed on the first interlayer insulating film 27. A gate potential Vg is applied to the first gate electrode 32 from the outside. The first gate electrode 32 is disposed in a region along the center of the third side surface 13C in a plan view. The first gate electrode 32 may be disposed in any location. For example, the first gate electrode 32 may be disposed in a region along a corner of the first chip 10 or in the center of the first chip 10 in a plan view.

[0048] The first gate electrode 32 faces a region outside the first active region 17 with the first interlayer insulating film 27 interposed therebetween. Of course, the first gate electrode 32 may face the first active region 17 (i.e., the plurality of first trench structures 20) with the first interlayer insulating film 27 interposed therebetween. The first gate electrode 32 is formed in a quadrangular shape in plan view. The first gate electrode 32 may also be formed in a circular or polygonal shape in plan view.

[0049] The first gate electrode 32 includes a conductive material different from that of the first buried electrode 23. The first gate electrode 32 may include at least one of a Ti-based metal film, an Al-based metal film, and a Cu-based metal film. The Ti-based metal film may include at least one of a Ti film and a TiN film (the same applies hereinafter in this specification).

[0050] The Al-based metal film may include at least one of a pure Al film (an Al film with a purity of 99% or more) and an Al alloy film (the same applies hereinafter in this specification). The Cu-based metal film may include at least one of a pure Cu film (a Cu film with a purity of 99% or more) and a Cu alloy film (the same applies hereinafter in this specification).

[0051] The Al alloy film and Cu alloy film may include at least one of an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film (the same applies hereinafter in this specification). In this embodiment, the gate electrode has a laminated structure including a Ti-based metal film and an Al-based metal film laminated in this order from the first interlayer insulating film 27 side. The first gate electrode 32 may be referred to as a "first gate metal."

[0052] The IGBT device 2 includes a first gate wiring 33 disposed on the first interlayer insulating film 27. The first gate wiring 33 is electrically connected to the first gate electrode 32 and the plurality of first trench structures 20, and transmits a gate potential Vg applied to the first gate electrode 32 to the plurality of first trench structures 20.

[0053] Specifically, the first gate wiring 33 is drawn out from the first gate electrode 32 onto the first interlayer insulating film 27 in a plan view, and extends in a strip shape along the first to third side surfaces 13A to 13C so as to intersect (specifically, orthogonally cross) both end portions of the plurality of first trench structures 20. The first gate wiring 33 penetrates the first interlayer insulating film 27 and is electrically connected to the plurality of first trench structures 20. The first gate wiring 33 contains the same conductive material as the first gate electrode 32.

[0054] The IGBT device 2 includes an emitter electrode 34 disposed on the first interlayer insulating film 27. An emitter potential Ve is applied to the emitter electrode 34 from the outside. The emitter electrode 34 is disposed on the first interlayer insulating film 27 in a region surrounded by the first gate electrode 32 and the first gate wiring 33 so as to cover the first active region 17.

[0055] The emitter electrode 34 faces the plurality of first trench structures 20 with the first interlayer insulating film 27 interposed therebetween, and penetrates the first interlayer insulating film 27 to be electrically connected to the plurality of emitter regions 24 and the plurality of first contact regions 26. Specifically, the emitter electrode 34 is electrically connected to the plurality of emitter regions 24 and the plurality of first contact regions 26 via a plurality of contact electrodes 31 that penetrate the first interlayer insulating film 27.

[0056] The emitter electrode 34 includes the same conductive material as the first gate electrode 32. The emitter electrode 34 may also be referred to as an "emitter metal." In this embodiment, the emitter electrode 34 includes a different conductive material from the plurality of contact electrodes 31. Of course, the emitter electrode 34 may also include the same conductive material as the plurality of contact electrodes 31. In this case, portions of the emitter electrode 34 located within the plurality of emitter openings 30 may be formed as the plurality of contact electrodes 31.

[0057] In this embodiment, the emitter electrode 34 has a planar shape that is approximately similar to the planar shape of the first active region 17. When the planar shape of the emitter electrode 34 is approximately similar to the planar shape of the first active region 17, the above-mentioned first active area SA1 may be defined by the planar area of ​​the emitter electrode 34.

[0058] The IGBT device 2 includes a collector electrode 35 covering the second main surface 12. A collector potential Vc is applied to the collector electrode 35. The collector electrode 35 forms ohmic contact with the collector region 16 exposed from the second main surface 12. The collector electrode 35 may cover the entire second main surface 12 so as to be continuous with the periphery of the first chip 10 (first to fourth side surfaces 13A to 13D).

[0059] Fig. 7 is a plan view showing a configuration example of the MISFET device 3 incorporated in the semiconductor module 1 shown in Fig. 1. Fig. 8 is a schematic cross-sectional view taken along line VIII-VIII shown in Fig. 7. Fig. 9 is a plan view showing an example of the layout within the second chip 40 shown in Fig. 7. Fig. 10 is a cross-sectional view showing a main part of the second active region 47 shown in Fig. 7.

[0060] The MISFET device 3 has a second breakdown voltage VB2. The second breakdown voltage VB2 is a reverse voltage at which reverse voltage breakdown (avalanche breakdown) begins. The second breakdown voltage VB2 is preferably equal to or greater than the first breakdown voltage VB1 of the IGBT device 2. It is particularly preferable that the second breakdown voltage VB2 be higher than the first breakdown voltage VB1. For example, the second breakdown voltage VB2 may be equal to or greater than 500 V and equal to or less than 3000 V.

[0061] The second breakdown voltage VB2 may have a value belonging to any one of the ranges of 500 V to 750 V, 750 V to 1000 V, 1000 V to 1250 V, 1250 V to 1500 V, 1500 V to 1750 V, 1750 V to 2000 V, 2000 V to 2250 V, 2250 V to 2500 V, 2500 V to 2750 V, and 2750 V to 3000 V. For example, the second breakdown voltage VB2 may be 500 V to 700 V or 1100 V to 1300 V.

[0062] 7 to 10, the MISFET device 3 includes a hexahedral (specifically, rectangular parallelepiped) second chip 40. The second chip 40 is made of a semiconductor single crystal different from that of the first chip 10. Specifically, the second chip 40 is made of a wide bandgap semiconductor chip made of a single crystal of a wide bandgap semiconductor.

[0063] In other words, the MISFET device 3 is a "wide bandgap semiconductor-MISFET device." A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si. Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).

[0064] In this embodiment, the second chip 40 is a SiC chip including a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the MISFET device 3 is a "SiC-MISFET device." The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the second chip 40 includes a 4H-SiC single crystal, but the second chip 40 may include other polytypes.

[0065] The second chip 40 has a second chip thickness T2. The second chip thickness T2 may be equal to or greater than the first chip thickness T1 of the IGBT device 2. The second chip thickness T2 may be less than the first chip thickness T1. The second chip thickness T2 may be approximately equal to the first chip thickness T1. The second chip thickness T2 may be equal to or greater than 25 μm and equal to or less than 200 μm.

[0066] The second chip thickness T2 may have a value belonging to any one of the ranges of 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, and 175 μm or more and 200 μm or less.

[0067] For example, when the value of the second breakdown voltage VB2 is 500 V or more and 700 V or less, the second chip thickness T2 may have a value belonging to any one of the ranges of 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, and 150 μm or more and 175 μm or less.

[0068] For example, when the value of the second breakdown voltage VB2 is 1100 V or more and 1300 V or less (3000 V or less), the second chip thickness T2 may have a value belonging to any one of the ranges of 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, and 175 μm or more and 200 μm or less.

[0069] For example, when the value of the second breakdown voltage VB2 is 1100 V or more and 1300 V or less (3000 V or less), the second chip thickness T2 may have a value belonging to any one of the ranges of 150 μm or more and 160 μm or less, 160 μm or more and 170 μm or less, and 170 μm or more and 180 μm or less.

[0070] The second chip 40 has a first main surface 41 on one side, a second main surface 42 on the other side, and first to fourth side surfaces 43A to 43D connecting the first main surface 41 and the second main surface 42. The first main surface 41 and the second main surface 42 are formed in a quadrangular shape (square in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the second chip 40. Of course, the first main surface 41 and the second main surface 42 may be formed in a rectangular shape in a plan view.

[0071] The first main surface 41 and the second main surface 42 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 41 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 42 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0072] The first main surface 41 and the second main surface 42 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be greater than 0° and not more than 10°. The off angle is preferably not more than 5°.

[0073] The first side surface 43A and the second side surface 43B extend in a first direction X along the first main surface 41 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 43C and the fourth side surface 43D extend in the second direction Y and face the first direction X. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0074] The first to fourth side surfaces 43A to 43D may each have a length of 0.1 mm to 20 mm in plan view. The lengths of the first to fourth side surfaces 43A to 43D may each have a value that belongs to any one of the following ranges: 0.1 mm to 1 mm, 1 mm to 2.5 mm, 2.5 mm to 5 mm, 5 mm to 7.5 mm, 7.5 mm to 10 mm, 10 mm to 12.5 mm, 12.5 mm to 15 mm, 15 mm to 17.5 mm, and 17.5 mm to 20 mm.

[0075] The second chip 40 has a second chip area S2 in plan view. The second chip area S2 is the product of the length of the first side surface 43A and the length of the third side surface 43C (i.e., the product of the length of the second side surface 43B and the length of the fourth side surface 43D). The second chip area S2 is preferably less than the first chip area S1 of the IGBT device 2.

[0076] It is particularly preferable that the second chip area S2 be 0.1 to 0.6 times the first chip area S1. In this case, the second chip area S2 may have a value that falls within any one of the following ranges: 0.1 to 0.2 times, 0.2 to 0.3 times, 0.3 to 0.4 times, 0.4 to 0.5 times, or 0.5 to 0.6 times the first chip area S1.

[0077] The MISFET device 3 includes an n-type first semiconductor region 44 formed in a region (surface layer portion) on the first main surface 41 side of the second chip 40. The first semiconductor region 44 is formed in a layer shape extending along the first main surface 41 and is exposed from the first main surface 41 and first to fourth side surfaces 43A to 43D. In this embodiment, the first semiconductor region 44 is made of an epitaxial layer of a wide bandgap semiconductor (SiC epitaxial layer).

[0078] The first semiconductor region 44 may have a thickness of 1 μm or more and 50 μm or less. The first semiconductor region 44 may have a value belonging to any one of the ranges of 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, and 40 μm or more and 50 μm or less. The thickness of the first semiconductor region 44 is preferably 15 μm or more and 25 μm or less.

[0079] The MISFET device 3 includes an n-type second semiconductor region 45 formed in a region (surface layer portion) on the second main surface 42 side of the second chip 40. The second semiconductor region 45 is formed in a layer shape extending along the second main surface 42 and is exposed from the second main surface 42 and first to fourth side surfaces 43A to 43D. The second semiconductor region 45 has a higher n-type impurity concentration than the first semiconductor region 44 and is electrically connected to the first semiconductor region 44. In this embodiment, the second semiconductor region 45 is made of a wide bandgap semiconductor single crystal substrate (SiC single crystal substrate).

[0080] That is, the second chip 40 has a layered structure including a substrate and an epitaxial layer. The second semiconductor region 45 may have a thickness of 1 μm to 200 μm. The second semiconductor region 45 may have a thickness in any one of the following ranges: 1 μm to 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, or 175 μm to 200 μm.

[0081] The thickness of the second semiconductor region 45 may be 5 μm or more. The thickness of the second semiconductor region 45 is preferably 10 μm or more. The thickness of the second semiconductor region 45 may be equal to or greater than the thickness of the first semiconductor region 44. The thickness of the second semiconductor region 45 may be less than the thickness of the first semiconductor region 44. The thickness of the second semiconductor region 45 may be approximately equal to the thickness of the first semiconductor region 44, and in this embodiment, the thickness of the second semiconductor region 45 is greater than the thickness of the first semiconductor region 44.

[0082] The MISFET device 3 includes a second active region 47 provided on the first main surface 41 of the second chip 40. The second active region 47 includes a MISFET structure 48 and is a region that generates a drain current Ids. The second active region 47 has a second active area SA2 in a plan view.

[0083] For example, when a polygonal region (see the two-dot chain line in FIG. 7 ) is defined to encompass the MISFET structure 48 in plan view, the second active area SA2 is defined by the plane area of ​​the polygonal region. When a plurality of second active regions 47 are provided, the second active area SA2 is defined by the total plane area of ​​the plurality of second active regions 47.

[0084] The second active area SA2 may take various values ​​depending on the second chip area S2. The second active area SA2 may be 30% or more and less than 100% of the second chip area S2. The second active area SA2 may have a value belonging to any one of the following ranges of 30% or more and 40% or less, 40% or more and 50% or less, 50% or more and 60% or less, 60% or more and 70% or less, 70% or more and 80% or less, 80% or more and 90% or less, and 90% or more and less than 100% of the second chip area S2.

[0085] The second active area SA2 is preferably smaller than the first active area SA1 of the IGBT device 2. The second active area SA2 is particularly preferably 0.1 to 0.6 times the first active area SA1. In this case, the second active area SA2 may have a value belonging to any one of the following ranges of 0.1 to 0.2 times, 0.2 to 0.3 times, 0.3 to 0.4 times, 0.4 to 0.5 times, and 0.5 to 0.6 times the first active area SA1.

[0086] The MISFET structure 48 includes a p-type body region 49 formed in a surface layer portion of the first major surface 41 in the second active region 47. The body region 49 may also be referred to as a "channel region." The body region 49 is formed in a layer shape extending along the first major surface 41 throughout the entire area of ​​the second active region 47.

[0087] The MISFET structure 48 includes a plurality of second trench structures 50 formed in the first main surface 41 in the second active region 47. A gate potential Vg of the IGBT device 2 is applied to the plurality of second trench structures 50. The plurality of second trench structures 50 control inversion and non-inversion of the channel. In other words, the MISFET structure 48 is of a trench gate type. The second trench structures 50 may also be referred to as a "second trench gate structure."

[0088] The second trench structures 50 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. The second trench structures 50 penetrate the body region 49 to reach the first semiconductor region 44, and are formed at intervals from the bottom of the first semiconductor region 44 toward the first main surface 41.

[0089] The plurality of second trench structures 50 are preferably shallower than the plurality of first trench structures 20 of the IGBT device 2. The depth of each second trench structure 50 may be 0.1 μm or more and 3 μm or less. The depth of each second trench structure 50 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The depth of each first trench structure 20 is preferably 0.5 μm or more and 1.5 μm or less.

[0090] Each second trench structure 50 includes a second trench 51, a second insulating film 52, and a second buried electrode 53. The second trench 51 is formed in the first main surface 41 and defines the wall surface of the second trench structure 50. The second insulating film 52 coats the wall surface of the second trench 51 in a film-like manner. The second insulating film 52 may include a silicon oxide film. The second buried electrode 53 is buried in the second trench 51 with the second insulating film 52 sandwiched therebetween. In this embodiment, the second buried electrode 53 includes conductive polysilicon.

[0091] The MISFET structure 48 includes a plurality of third trench structures 60 formed in the first main surface 41 in the second active region 47. The emitter potential Ve of the IGBT device 2 is applied to the plurality of third trench structures 60 as a source potential Vs. The third trench structures 60 may also be referred to as "trench source structures."

[0092] The plurality of third trench structures 60 are each disposed in a region between two adjacent second trench structures 50. The plurality of third trench structures 60 are arranged alternately with the plurality of second trench structures 50 in the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y. The plurality of third trench structures 60 penetrate the body region 49 to reach the first semiconductor region 44, and are formed at intervals from the bottom of the first semiconductor region 44 toward the first main surface 41.

[0093] Each third trench structure 60 has a depth equal to or greater than the depth of each second trench structure 50. In this embodiment, each third trench structure 60 is deeper than each second trench structure 50. The depth of each third trench structure 60 is preferably 1.5 to 3 times the depth of each second trench structure 50.

[0094] Each third trench structure 60 is preferably shallower than each first trench structure 20 of the IGBT device 2. The depth of each third trench structure 60 may be 0.5 μm or more and 5 μm or less. The depth of each third trench structure 60 may have a value belonging to any one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The depth of each third trench structure 60 is preferably 1 μm or more and 2.5 μm or less.

[0095] Each third trench structure 60 includes a third trench 61, a third insulating film 62, and a third buried electrode 63. The third trench 61 is formed in the first main surface 41 and defines the wall surface of the third trench structure 60. The third insulating film 62 coats the wall surface of the third trench 61 in a film-like manner. The third insulating film 62 may include a silicon oxide film. The third buried electrode 63 is buried in the third trench 61 with the third insulating film 62 sandwiched therebetween. In this embodiment, the third buried electrode 63 includes conductive polysilicon.

[0096] The MISFET structure 48 includes a plurality of n-type source regions 64 formed in regions along the plurality of second trench structures 50 in a surface layer portion of the body region 49. Each source region 64 has a higher n-type impurity concentration than the first semiconductor region 44. Each source region 64 is formed in a region between adjacent second trench structures 50 and third trench structures 60 in the surface layer portion of the body region 49. Each source region 64, together with the first semiconductor region 44, forms a channel of the MISFET in the body region 49.

[0097] The MISFET structure 48 includes a plurality of p-type well regions 65 formed in the second chip 40 in regions along the plurality of third trench structures 60. In this embodiment, the well regions 65 have a higher p-type impurity concentration than the body region 49. Of course, the p-type impurity concentration of the well regions 65 may be lower than that of the body region 49.

[0098] The multiple well regions 65 cover the wall surfaces of the third trench structure 60 in the second chip 40, and are electrically connected to the body region 49 in the surface portion of the first main surface 41. The multiple well regions 65 are formed at intervals from the bottom of the first semiconductor region 44 toward the first main surface 41, and face the second semiconductor region 45 with part of the first semiconductor region 44 in between. The multiple well regions 65 form pn junctions with the first semiconductor region 44.

[0099] The MISFET structure 48 includes a plurality of p-type second contact regions 66 formed in the plurality of well regions 65 and in regions along the plurality of third trench structures 60. The second contact regions 66 have a higher p-type impurity concentration than the body region 49. In this embodiment, the p-type impurity concentration of the second contact regions 66 is higher than that of the well region 65.

[0100] The second contact regions 66 cover the wall surfaces of the corresponding third trench structures 60 in the corresponding well regions 65. The second contact regions 66 are extended from the corresponding well regions 65 along the wall surfaces of the corresponding third trench structures 60 to the surface layer portions of the body region 49 and are exposed from the first main surface 41.

[0101] The MISFET device 3 includes a second interlayer insulating film 67 covering the first main surface 41. In this embodiment, the second interlayer insulating film 67 includes a second lower insulating film 68 and a second upper insulating film 69. The second lower insulating film 68 is connected to the second insulating film 52 and the third insulating film 62, and covers the first main surface 41 so as to expose the second buried electrode 53 and the third buried electrode 63.

[0102] The second lower insulating film 68 may include a silicon oxide film. The second upper insulating film 69 covers the second lower insulating film 68 so as to cover the plurality of second trench structures 50 and the plurality of third trench structures 60. The second upper insulating film 69 may include a silicon oxide film. The second upper insulating film 69 is thicker than the second lower insulating film 68.

[0103] The MISFET device 3 includes a second gate electrode 72 disposed on the second interlayer insulating film 67. A gate potential Vg of the IGBT device 2 is applied to the second gate electrode 72 from the outside. The second gate electrode 72 is disposed in a region along the center of the third side surface 43C in a plan view. The second gate electrode 72 may be disposed in any location. For example, the second gate electrode 72 may be disposed in a region along a corner of the second chip 40 or in the center of the second chip 40 in a plan view.

[0104] The second gate electrode 72 faces a region outside the second active region 47 with the second interlayer insulating film 67 sandwiched therebetween. Of course, the second gate electrode 72 may face the second active region 47 (i.e., the plurality of second trench structures 50 and the plurality of third trench structures 60) with the second interlayer insulating film 67 sandwiched therebetween. The second gate electrode 72 is formed in a quadrangular shape in plan view. The second gate electrode 72 may also be formed in a circular or polygonal shape in plan view.

[0105] The second gate electrode 72 includes a conductive material different from that of the second buried electrode 53. The second gate electrode 72 may include at least one of a Ti-based metal film, an Al-based metal film, and a Cu-based metal film. In this embodiment, the second gate electrode 72 has a layered structure including a Ti-based metal film and an Al-based metal film stacked in this order from the second interlayer insulating film 67 side. The second gate electrode 72 may also be referred to as a "second gate metal."

[0106] The MISFET device 3 includes a second gate wiring 73 disposed on the second interlayer insulating film 67. The second gate wiring 73 is electrically connected to the second gate electrode 72 and the plurality of second trench structures 50, and transmits the gate potential Vg applied to the second gate electrode 72 to the plurality of second trench structures 50.

[0107] Specifically, the second gate wiring 73 is drawn out from the second gate electrode 72 onto the second interlayer insulating film 67 in a plan view, and extends in a strip shape along the first to third side surfaces 43A to 43C so as to intersect (specifically, orthogonally intersect) both end portions of the plurality of second trench structures 50. The second gate wiring 73 penetrates the second interlayer insulating film 67 and is electrically connected to the plurality of second trench structures 50. The second gate wiring 73 contains the same conductive material as the second gate electrode 72.

[0108] The MISFET device 3 includes a source electrode 74 disposed on the second interlayer insulating film 67. The emitter potential Ve of the IGBT device 2 is applied to the source electrode 74 as a source potential Vs. The source electrode 74 is disposed on the second interlayer insulating film 67 in a region surrounded by the second gate electrode 72 and the second gate wiring 73 so as to cover the second active region 47. The source electrode 74 faces the second trench structures 50 with the second interlayer insulating film 67 in between, and penetrates the second interlayer insulating film 67 to be electrically connected to the third trench structures 60, the source regions 64, and the second contact regions 66.

[0109] The source electrode 74 includes the same conductive material as the second gate electrode 72. The source electrode 74 may also be referred to as a "source metal." In this embodiment, the source electrode 74 has a planar shape that is approximately similar to the planar shape of the second active region 47. When the planar shape of the source electrode 74 is approximately similar to the planar shape of the second active region 47, the second active area SA2 described above may be defined by the planar area of ​​the source electrode 74.

[0110] The MISFET device 3 includes a drain electrode 75 covering the second main surface 42. The drain electrode 75 is applied with the collector potential Vc of the IGBT device 2 as a drain potential Vd. The drain electrode 75 forms an ohmic contact with the second semiconductor region 45 exposed from the second main surface 42. The drain electrode 75 may cover the entire second main surface 42 so as to be continuous with the periphery (first to fourth side surfaces 43A to 43D) of the second chip 40.

[0111] Hereinafter, a specific example of adjusting the output current IO that can appropriately suppress losses in both the low current region and the high current region in the semiconductor module 1 will be described. The output current IO of the semiconductor module 1 is adjusted by adjusting the chip area ratio S2 / S1 of the second chip area S2 of the MISFET device 3 to the first chip area S1 of the IGBT device 2. In other words, the output current IO is adjusted by adjusting the active area ratio SA2 / SA1 of the second active area SA2 of the MISFET device 3 to the first active area SA1 of the IGBT device 2.

[0112] When the second chip area S2 (second active area SA2) of the MISFET device 3 is equal to or larger than the first chip area S1 (first active area SA1) of the IGBT device 2, the current generation capability improves accordingly, and the loss of the MISFET device 3 in the high current region increases. For example, when the MISFET device 3 generates a drain current Ids close to the maximum rated value of the collector current Ice of the IGBT device 2, the loss of the MISFET device 3 in the high current region becomes extremely high. In these cases, there is little benefit in connecting the MISFET device 3 in parallel with the IGBT device 2.

[0113] For example, the semiconductor module 1 can be incorporated into an inverter, a DC / DC converter, or a PFC (power factor correction) circuit. In the case of an inverter, a collector current Ice of 20% to 40% of the maximum rated value is generally used. In the case of a DC / DC converter or a PFC circuit, a collector current Ice of 30% to 50% of the maximum rated value is generally used.

[0114] Since the MISFET device 3 is intended for use in a low current region, it is required to efficiently generate a drain current Ids in an even lower current range than the above current range, and therefore there is little benefit in increasing the second chip area S2 (second active area SA2) of the MISFET device 3.

[0115] Therefore, in order to limit the current generating capacity of the MISFET device 3, it is preferable that the second chip area S2 (second active area SA2) of the MISFET device 3 is set to be less than the first chip area S1 (first active area SA1) of the IGBT device 2. It is particularly preferable that the chip area ratio S2 / S1 (active area ratio SA2 / SA1) be 0.1 or more and 0.6 or less.

[0116] Furthermore, since the MISFET device 3 is intended for use in a low current region, it is required to be smaller than the IGBT device 2, while since the MISFET device 3 is connected in parallel to the IGBT device 2, which is intended for use in high current operation, it is required to have a breakdown voltage that is higher than that of the IGBT device 2.

[0117] In this embodiment, the MISFET device 3 has a second breakdown voltage VB2 that is equal to or higher than the first breakdown voltage VB1 of the IGBT device 2. The MISFET device 3 that satisfies the conditions of being small and having a high breakdown voltage is achieved by employing a second chip 40 made of a wide bandgap semiconductor (made of SiC in this embodiment).

[0118] Fig. 11A is a graph showing current-voltage characteristics according to a first adjustment example of the semiconductor module 1 shown in Fig. 1. Fig. 11B is a graph showing current-voltage characteristics according to a second adjustment example of the semiconductor module 1 shown in Fig. 1. Fig. 11C is a graph showing current-voltage characteristics according to a third adjustment example of the semiconductor module 1 shown in Fig. 1. In Figs. 11A to 11C, the vertical axis represents the collector current Ice (drain current Ids), and the horizontal axis represents the collector voltage Vce (drain voltage Vds).

[0119] 11A to 11C show a first characteristic C1, a second characteristic C2, and a third characteristic C3, respectively. The first characteristic C1 shows the individual collector current Ice when the IGBT device 2 is used alone. The second characteristic C2 shows the individual drain current Ids when the MISFET device 3 is used alone. The third characteristic C3 shows the output current IO when a parallel switching circuit including the IGBT device 2 and the MISFET device 3 is used. The output current IO is the sum of the individual collector current Ice and the individual drain current Ids.

[0120] 11A shows the first to third characteristics C1 to C3 when the chip area ratio S2 / S1 (active area ratio SA2 / SA1) is adjusted to 0.1. FIG. 11B shows the first to third characteristics C1 to C3 when the chip area ratio S2 / S1 (active area ratio SA2 / SA1) is adjusted to 0.3. FIG. 11C shows the first to third characteristics C1 to C3 when the chip area ratio S2 / S1 (active area ratio SA2 / SA1) is adjusted to 0.6.

[0121] Referring to Figures 11A to 11C, the individual drain current Ids (individual collector current Ice) at the intersection P of the first characteristic C1 and the second characteristic C2 is set to a first current value A, and the individual drain current Ids when the built-in voltage Vbi is applied (specifically, when a drain voltage Vds equal to the built-in voltage Vbi is applied) is set to a second current value B (B < A).

[0122] In this case, the current ratio A / B of the first current value A to the second current value B is preferably greater than 1 and less than or equal to 3 (1<A / B≦3). The current ratio A / B may have a value belonging to any one of the following ranges: greater than 1 and less than or equal to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. It is particularly preferable that the current ratio A / B be greater than or equal to 1.1 and less than or equal to 2.6.

[0123] The difference value (A-B) between the first current value A and the second current value B is preferably 0.5 A or more and 30 A or less. The difference value (A-B) may have a value belonging to any one of the ranges of 0.5 A or more and 1 A or less, 1 A or more and 5 A or less, 5 A or more and 10 A or less, 10 A or more and 15 A or less, 15 A or more and 20 A or less, 20 A or more and 25 A or less, and 25 A or more and 30 A or less.

[0124] The slope of the line connecting the first current value A and the second current value B is preferably greater than 1 and not greater than 30. The slope of the line connecting the first current value A and the second current value B may have a value belonging to any one of the following ranges: greater than 1 and not greater than 5, 5 to 10, 10 to 15, 15 to 20, 20 to 25, and 25 to 30.

[0125] 11A, the first current value A is adjusted to 4.2 A, and the second current value B is adjusted to 3.3 A. The built-in voltage Vbi is 0.6 V, and the collector voltage Vce (drain voltage Vds) at the intersection P is 0.9 V. The current ratio A / B is 1.27. The difference (A-B) between the first current value A and the second current value B is 0.9 A. The slope of the line connecting the first current value A and the second current value B is 3.

[0126] In Figure 11B, the first current value A is adjusted to 16 A, and the second current value B is adjusted to 10.7 A. The built-in voltage Vbi is 0.6 V, and the collector voltage Vce (drain voltage Vds) at intersection P is 1.16 V. The current ratio A / B is 1.5. The difference (A-B) between the first current value A and the second current value B is 5.3 A. The slope of the line connecting the first current value A and the second current value B is 9.46.

[0127] In Figure 11C, the first current value A is adjusted to 46 A, and the second current value B is adjusted to 22.8 A. The built-in voltage Vbi is 0.6 V, and the collector voltage Vce (drain voltage Vds) at intersection P is 1.7 V. The current ratio A / B is 2.02. The difference (A-B) between the first current value A and the second current value B is 23.2 A. The slope of the line connecting the first current value A and the second current value B is 21.1.

[0128] As described above, the semiconductor module 1 includes the IGBT device 2 and the MISFET device 3. The MISFET device 3 forms a parallel circuit together with the IGBT device 2. In this structure, the semiconductor module 1 generates a drain current Ids of the MISFET device 3 in a voltage range below the built-in voltage Vbi of the IGBT device 2, and generates a collector current Ice of the IGBT device 2 and a drain current Ids of the MISFET device 3 in a voltage range equal to or higher than the built-in voltage Vbi.

[0129] According to this structure, the drain current Ids of the MISFET device 3 is used in the low current region, thereby reducing loss in the IGBT device 2 in the low current region. Also, the collector current Ice of the IGBT device 2 and the drain current Ids of the MISFET device 3 are used in the high current region, thereby reducing loss in the MISFET device 3 in the high current region. Therefore, it is possible to provide a semiconductor module 1 that can improve electrical characteristics.

[0130] Preferably, the IGBT device 2 has a first breakdown voltage VB1, and the MISFET device 3 has a second breakdown voltage VB2 equal to or greater than the first breakdown voltage VB1. This structure allows the MISFET device 3, which is designed for use in low-voltage, low-current environments, to be used appropriately in combination with the IGBT device 2, which is designed for use in high-voltage, high-current environments. The first breakdown voltage VB1 may be 500 V or greater and 1500 V or less. The second breakdown voltage VB2 may be 500 V or greater and 3000 V or less.

[0131] The IGBT device 2 preferably includes a first chip 10 made of Si. This structure allows the use of a relatively inexpensive IGBT device 2. The MISFET device 3 preferably includes a second chip 40 made of a wide bandgap semiconductor. The wide bandgap semiconductor allows the second chip 40 to be easily miniaturized and have a high breakdown voltage at the same time. Therefore, a high-breakdown-voltage MISFET device 3 suitable for the usage environment of the IGBT device 2 can be easily realized. It is particularly preferable that the wide bandgap semiconductor is SiC.

[0132] Preferably, the first chip 10 has a first chip area S1, and the second chip 40 has a second chip area S2 smaller than the first chip area S1. This structure limits the current generation capability of the MISFET device 3, thereby appropriately reducing the loss of the MISFET device 3 in the low current region. It is particularly preferable that the second chip area S2 be 0.1 to 0.6 times the first chip area S1. The second chip 40 may be thinner than the first chip 10. The second chip 40 may be thicker than the first chip 10.

[0133] With regard to the first characteristic C1 indicating the individual collector current Ice of the IGBT device 2 alone and the second characteristic C2 indicating the individual drain current Ids of the MISFET device 3 alone, when the individual drain current Ids (individual collector current Ice) at the intersection P of the first characteristic C1 and the second characteristic C2 is set to a first current value A and the individual drain current Ids when the built-in voltage Vbi is applied is set to a second current value B (B<A), it is preferable that the current ratio A / B of the first current value A to the second current value B be greater than 1 and equal to or less than 3 (1<A / B≦3). With this structure, it is possible to appropriately reduce losses in both the low current region and the high current region.

[0134] The semiconductor module 1 may have any configuration as long as it can configure a parallel switching circuit of the IGBT devices 2 and the MISFET devices 3, and is not limited to a specific configuration. Examples of the configuration of the semiconductor module 1 are shown below. Fig. 12 is a perspective view showing one configuration example of the semiconductor module 1. Fig. 13 is a plan view showing the internal structure of the semiconductor module 1 shown in Fig. 12.

[0135] 12 and 13, semiconductor module 1 has a TO-220 package configuration in this embodiment. Semiconductor module 1 includes a resin package body 80 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). Package body 80 may be made of a thermosetting resin (e.g., epoxy resin). Package body 80 has a first surface 81 on one side, a second surface 82 on the other side, and first to fourth side walls 83A to 83D connecting first surface 81 and second surface 82.

[0136] The first surface 81 and the second surface 82 are formed in a quadrangular shape in a plan view seen from their normal direction Z. The first side wall 83A and the second side wall 83B extend in the first direction X and face a second direction Y that is perpendicular to the first direction X. The third side wall 83C and the fourth side wall 83D extend in the second direction Y and face the first direction X.

[0137] The semiconductor module 1 includes a metallic support electrode 84 disposed within the package body 80. The support electrode 84 may be exposed from the second surface 82. The support electrode 84 includes a support portion 85 and a lead portion 86. The support portion 85 is disposed within the package body 80. The lead portion 86 is led from the support portion 85 toward the third side wall 83C, penetrates the third side wall 83C, and is located outside the package body 80. The lead portion 86 has a circular through-hole.

[0138] The semiconductor module 1 includes a plurality of (three in this embodiment) metal wiring electrodes 87 extending from the inside to the outside of the package body 80. The plurality of wiring electrodes 87 are arranged on the fourth side wall 83D side with respect to the support electrode 84. The plurality of wiring electrodes 87 are each formed in a strip shape extending in a direction perpendicular to the fourth side wall 83D (i.e., the first direction X). The wiring electrodes 87 on both sides are arranged at a distance from the support electrode 84, and the central wiring electrode 87 is formed integrally with the support electrode 84. The wiring electrodes 87 connected to the support electrode 84 may be arranged at any location.

[0139] The multiple wiring electrodes 87 include an emitter wiring electrode 87e, a gate wiring electrode 87g, and a collector wiring electrode 87c. The emitter wiring electrode 87e may also be referred to as a "source terminal" or an "emitter-source terminal." The collector wiring electrode 87c may also be referred to as a "drain terminal" or a "collector-drain terminal." In this embodiment, the emitter wiring electrode 87e is disposed on the second sidewall 83B side, the gate wiring electrode 87g is disposed on the first sidewall 83A side, and the collector wiring electrode 87c is disposed between the emitter wiring electrode 87e and the gate wiring electrode 87g.

[0140] The semiconductor module 1 includes the above-described IGBT device 2 disposed on a support electrode 84 (support portion 85) within the package body 80. In this embodiment, the IGBT device 2 is disposed in a region on the first sidewall 83A side with respect to the center of the support electrode 84. In other words, the IGBT device 2 is disposed in a position close to the gate wiring electrode 87g.

[0141] The IGBT device 2 is disposed on the support electrode 84 with the collector electrode 35 facing the support electrode 84. The IGBT device 2 is also disposed on the support electrode 84 with the first gate electrode 32 facing the fourth sidewall 83D in a plan view. The collector electrode 35 is electrically connected to the support electrode 84.

[0142] The IGBT device 2 is disposed at a first distance from the gate wiring electrode 87 g and at a second distance, which is greater than the first distance, from the emitter wiring electrode 87 e. In this embodiment, the IGBT device 2 faces the gate wiring electrode 87 g in the first direction X, but does not face the emitter wiring electrode 87 e in the first direction X. The IGBT device 2 may face the collector wiring electrode 87 c in the first direction X.

[0143] The semiconductor module 1 includes the above-mentioned MISFET device 3 disposed on the support electrode 84 (support portion 85) within the package body 80 and spaced apart from the IGBT device 2. In this embodiment, the MISFET device 3 is disposed on the second sidewall 83B side of the IGBT device 2 and faces the IGBT device 2 in the second direction Y. In other words, the MISFET device 3 is disposed closer to the emitter wiring electrode 87e than the IGBT device 2.

[0144] The MISFET device 3 is disposed on the support electrode 84 with the drain electrode 75 facing the support electrode 84. The MISFET device 3 is also disposed on the support electrode 84 with the second gate electrode 72 facing the fourth sidewall 83D in plan view. The drain electrode 75 is electrically connected to the collector electrode 35 of the IGBT device 2 via the support electrode 84, and is also electrically connected to the collector wiring electrode 87c via the support electrode 84.

[0145] The MISFET device 3 is disposed a third distance from the gate wiring electrode 87 g and a fourth distance, which is smaller than the third distance, from the emitter wiring electrode 87 e. In this embodiment, the MISFET device 3 faces the emitter wiring electrode 87 e in the first direction X, but does not face the gate wiring electrode 87 g in the first direction X. The MISFET device 3 may face the collector wiring electrode 87 c in the first direction X.

[0146] The semiconductor module 1 includes a first conductive adhesive 88 interposed between the support electrode 84 (support portion 85) and the collector electrode 35. The first conductive adhesive 88 may include solder or a metal paste. The solder may be lead-free solder. The metal paste may include at least one of Au, Ag, and Cu. The Ag paste may be an Ag sintering paste. The Ag sintering paste is a paste in which nano-sized or micro-sized Ag particles are added to an organic solvent.

[0147] The semiconductor module 1 includes a second conductive adhesive 89 interposed between the support electrode 84 (support portion 85) and the drain electrode 75. The second conductive adhesive 89 may include solder or a metal paste. The solder may be lead-free solder. The metal paste may include at least one of Au, Ag, and Cu. The Ag paste may be an Ag sintering paste.

[0148] The semiconductor module 1 includes a plurality of first to fourth conductive connection members 90A to 90D disposed within a package body 80. In this embodiment, the plurality of first to fourth conductive connection members 90A to 90D are made of metal wires (i.e., bonding wires). The plurality of first to fourth conductive connection members 90A to 90D may include at least one of gold wire, copper wire, and aluminum wire. Of course, at least one or all of the plurality of first to fourth conductive connection members 90A to 90D may be made of a metal plate such as a metal clip instead of a metal wire.

[0149] The first conductive connecting member 90A is electrically and mechanically connected to the source electrode 74 and the emitter wiring electrode 87e of the MISFET device 3. The second conductive connecting member 90B is electrically and mechanically connected to the second gate electrode 72 and the gate wiring electrode 87g of the MISFET device 3.

[0150] The third conductive connection member 90C is electrically connected to the emitter electrode 34 and the emitter wiring electrode 87e of the IGBT device 2. Specifically, the third conductive connection member 90C includes a first connection portion 91 electrically and mechanically connected to the emitter electrode 34 of the IGBT device 2 and a second connection portion 92 electrically and mechanically connected to the source electrode 74 of the MISFET device 3, and is electrically connected to the emitter wiring electrode 87e via the first conductive connection member 90A.

[0151] More specifically, the second connection portion 92 of the third conductive connection member 90C is joined to the first conductive connection member 90A above the source electrode 74. In other words, the third conductive connection member 90C is electrically connected to the emitter wiring electrode 87e via the first conductive connection member 90A by the stitch wire method.

[0152] Of course, the third conductive connection member 90C may be electrically and mechanically directly connected to the emitter electrode 34 and the emitter wiring electrode 87e. The fourth conductive connection member 90D is electrically and mechanically connected to the first gate electrode 32 and the gate wiring electrode 87g of the IGBT device 2.

[0153] Fig. 14 is a plan view showing another example of the configuration of the semiconductor module 1. Fig. 14 shows a configuration in which the positions of the IGBT device 2 and the MISFET device 3 are interchanged in the semiconductor module 1 according to the first embodiment. That is, in this configuration, the IGBT device 2 is arranged in an area on the second sidewall 83B side with respect to the center of the support electrode 84. The IGBT device 2 is also arranged in a position close to the emitter wiring electrode 87e.

[0154] The IGBT device 2 is disposed at a first distance from the emitter wiring electrode 87 e and at a second distance, which is greater than the first distance, from the gate wiring electrode 87 g. In this embodiment, the IGBT device 2 faces the emitter wiring electrode 87 e in the first direction X, but does not face the gate wiring electrode 87 g in the first direction X. The IGBT device 2 may face the collector wiring electrode 87 c in the first direction X.

[0155] In this embodiment, the MISFET device 3 is disposed on the first sidewall 83A side of the IGBT device 2, and faces the IGBT device 2 in the second direction Y. In other words, the MISFET device 3 is disposed at a position closer to the gate wiring electrode 87g than the IGBT device 2.

[0156] The MISFET device 3 is disposed at a third distance from the emitter wiring electrode 87 e and at a fourth distance, which is smaller than the third distance, from the gate wiring electrode 87 g. In this embodiment, the MISFET device 3 faces the gate wiring electrode 87 g in the first direction X, but does not face the emitter wiring electrode 87 e in the first direction X. The MISFET device 3 may face the collector wiring electrode 87 c in the first direction X.

[0157] The first conductive connection member 90A is electrically and mechanically connected to the emitter electrode 34 and the emitter wiring electrode 87e of the IGBT device 2. The second conductive connection member 90B is electrically and mechanically connected to the first gate electrode 32 and the gate wiring electrode 87g of the IGBT device 2.

[0158] The third conductive connection member 90C is electrically connected to the source electrode 74 and the emitter wiring electrode 87e of the MISFET device 3. Specifically, the third conductive connection member 90C includes a first connection portion 93 electrically and mechanically connected to the source electrode 74 of the MISFET device 3 and a second connection portion 94 electrically and mechanically connected to the emitter electrode 34 of the IGBT device 2, and is electrically connected to the emitter wiring electrode 87e via the first conductive connection member 90A.

[0159] More specifically, the second connection portion 94 of the third conductive connection member 90C is joined to the first conductive connection member 90A above the emitter electrode 34. In other words, the third conductive connection member 90C is electrically connected to the emitter wiring electrode 87e via the first conductive connection member 90A by the stitch wire method.

[0160] Of course, the third conductive connecting member 90C may be electrically and mechanically connected directly to the source electrode 74 and the emitter wiring electrode 87e. The fourth conductive connecting member 90D is electrically and mechanically connected to the second gate electrode 72 and the gate wiring electrode 87g of the MISFET device 3.

[0161] 14, depending on the locations of the IGBT devices 2 and the MISFET devices 3, the bending angle of the extension direction of the third conductive connection members 90C relative to the extension direction of the first conductive connection members 90A may be smaller (steeper) than in the case of the semiconductor module 1 of Fig. 13. Therefore, when taking into consideration the bending angle of the second conductive connection members 90B relative to the first conductive connection members 90A, the locations of the IGBT devices 2 and the MISFET devices 3 in the semiconductor module 1 of Fig. 13 are preferable.

[0162] 15 is a plan view showing yet another example configuration of the semiconductor module 1. The semiconductor module 1 includes a first semiconductor module 1A and a second semiconductor module 1B. The first semiconductor module 1A includes a package body 80, a support electrode 84, a plurality of wiring electrodes 87, an IGBT device 2, a first conductive adhesive 88, a first conductive connecting member 90A, and a second conductive connecting member 90B. The first conductive connecting member 90A is electrically and mechanically connected to the emitter electrode 34 and the emitter wiring electrode 87e. The second conductive connecting member 90B is electrically and mechanically connected to the first gate electrode 32 and the gate wiring electrode 87g.

[0163] The second semiconductor module 1B includes a package body 80, a support electrode 84, a plurality of wiring electrodes 87, a MISFET device 3, a second conductive adhesive 89, a third conductive connection member 90C, and a fourth conductive connection member 90D. The third conductive connection member 90C is electrically and mechanically connected to the source electrode 74 and the emitter wiring electrode 87e. The fourth conductive connection member 90D is electrically and mechanically connected to the second gate electrode 72 and the gate wiring electrode 87g.

[0164] The emitter wiring electrode 87e of the second semiconductor module 1B is electrically connected to the emitter wiring electrode 87e of the first semiconductor module 1A. The gate wiring electrode 87g of the second semiconductor module 1B is electrically connected to the gate wiring electrode 87g of the first semiconductor module 1A. The collector wiring electrode 87c of the second semiconductor module 1B is electrically connected to the collector wiring electrode 87c of the first semiconductor module 1A.

[0165] The "package body 80," "support electrode 84," and "plurality of wiring electrodes 87 (emitter wiring electrode 87e, gate wiring electrode 87g, and collector wiring electrode 87c)" of the first semiconductor module 1A may also be referred to as a "first package body," "first electrode," and "plurality of first terminals (first emitter terminal, first gate terminal, and first collector terminal)."

[0166] The "package body 80," "support electrode 84," and "plurality of wiring electrodes 87 (emitter wiring electrode 87e, gate wiring electrode 87g, and collector wiring electrode 87c)" of the second semiconductor module 1B may also be referred to as a "second package body," a "second electrode plate," and "plurality of second terminals (second emitter terminal, second gate terminal, and second collector terminal)."

[0167] 16 is a cross-sectional view showing another example of the configuration of the IGBT device 2. In this embodiment, the IGBT device 2 is an RC-IGBT (Reverse Conducting-IGBT) device that integrally includes an IGBT and a freewheeling diode (pn junction diode).

[0168] The IGBT device 2 includes one or more (preferably multiple) IGBT structures 18 provided in the first active region 17, and one or more (preferably multiple) diode structures 100 provided in the first active region 17. For example, when a polygonal region is set that includes all of the IGBT structures 18 and all of the diode structures 100 in a plan view, the first active area SA1 of the first active region 17 is defined by the planar area of ​​the polygonal region.

[0169] The plurality of IGBT structures 18 may each be formed in a quadrangular shape in a plan view. The plurality of diode structures 100 may each be formed in a quadrangular shape in a plan view. The plurality of IGBT structures 18 may be arranged in a matrix or staggered pattern with gaps in the first direction X and the second direction Y in a plan view. The plurality of diode structures 100 may be arranged with gaps in the first direction X and the second direction Y so as to be adjacent to at least one IGBT structure 18. The plurality of diode structures 100 may be arranged alternately with the plurality of IGBT structures 18 in the first direction X.

[0170] Each IGBT structure 18 includes a base region 19, a plurality of first trench structures 20, a plurality of emitter regions 24, a plurality of contact holes 25, and a plurality of first contact regions 26. The specific configurations of these structures have been described above and will not be described here.

[0171] Each diode structure 100 includes an n-type cathode region 101 formed in a surface layer portion of the second main surface 12. The cathode region 101 has an n-type impurity concentration higher than the p-type impurity concentration of the collector region 16, and is a region in which the conductivity type of a portion of the collector region 16 is converted from p-type to n-type.

[0172] The cathode region 101 preferably has a higher n-type impurity concentration than the semiconductor region 14 (buffer region 15). The cathode region 101 is formed in a layer shape extending along the second main surface 12 and is exposed from the second main surface 12. The cathode region 101 penetrates the collector region 16 so as to be electrically connected to the semiconductor region 14 (buffer region 15).

[0173] Each diode structure 100 includes a p-type anode region 102 formed in a surface layer portion of the first main surface 11. The anode region 102 may have a p-type impurity concentration substantially equal to that of the base region 19. Of course, the p-type impurity concentration of the anode region 102 may be higher than or lower than the p-type impurity concentration of the base region 19.

[0174] The anode region 102 is formed in a layer shape extending along the first main surface 11 so as to face the cathode region 101 in the thickness direction of the first chip 10, and is exposed from the first main surface 11. The anode region 102 is shallower than the plurality of first trench structures 20. The anode region 102 may have a depth approximately equal to that of the base region 19.

[0175] Of course, the anode region 102 may be formed deeper than the base region 19. The anode region 102 forms a pn junction with the semiconductor region 14. This forms a pn junction diode with the anode region 102 as the anode and the cathode region 101 as the cathode.

[0176] Each diode structure 100 includes a plurality of fourth trench structures 110 formed in the first major surface 11. A potential (emitter potential Ve in this embodiment) different from that of the first trench structure 20 (gate potential Vg) is applied to the fourth trench structures 110. The fourth trench structures 110 may also be referred to as "emitter trench structures" or "anode trench structures."

[0177] The multiple fourth trench structures 110 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. The multiple fourth trench structures 110 are formed in the first main surface 11 so as to penetrate the anode region 102 and reach the semiconductor region 14. It is preferable that each of the fourth trench structures 110 has a depth approximately equal to the depth of each of the first trench structures 20.

[0178] The depth of each fourth trench structure 110 may be 0.5 μm or more and 10 μm or less. The depth of each fourth trench structure 110 may have a value belonging to any one of the ranges of 0.5 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, and 7.5 μm or more and 10 μm or less. The depth of each fourth trench structure 110 is preferably 4 μm or more and 8 μm or less.

[0179] Each fourth trench structure 110 includes a fourth trench 111, a fourth insulating film 112, and a fourth buried electrode 113. The fourth trench 111 is formed in the first main surface 11 and defines the wall surface of the fourth trench structure 110. The fourth insulating film 112 coats the wall surface of the fourth trench 111 in a film-like manner. The fourth insulating film 112 may include a silicon oxide film. The fourth buried electrode 113 is buried in the fourth trench 111 with the fourth insulating film 112 sandwiched therebetween. In this embodiment, the fourth buried electrode 113 includes conductive polysilicon.

[0180] The first interlayer insulating film 27 includes a diode opening 114 that exposes each diode structure 100. The diode opening 114 exposes the anode region 102 and the plurality of fourth trench structures 110 in each diode structure 100. It is preferable that the diode opening 114 exposes all of the fourth trench structures 110.

[0181] The emitter electrode 34 is electrically connected to the plurality of emitter regions 24 and the plurality of first contact regions 26 via the plurality of contact electrodes 31 on the first interlayer insulating film 27. The emitter electrode 34 extends from above the first interlayer insulating film 27 into the diode opening 114.

[0182] The emitter electrode 34 is electrically connected to the anode region 102 and the plurality of fourth trench structures 110 within the diode opening 114. The aforementioned collector electrode 35 forms ohmic contact with the collector region 16 and the cathode region 101 exposed from the second main surface 12.

[0183] 17 is a cross-sectional view showing another example of the configuration of the MISFET device 3. Referring to FIG. 17, the MISFET device 3 may have a third trench structure 60 having substantially the same depth as the second trench structure 50.

[0184] 18 is a cross-sectional view showing another example of the configuration of the MISFET device 3. Referring to Fig. 18, the MISFET device 3 does not necessarily include the third trench structure 60. In this case, a plurality of source regions 64 are formed in a region between two adjacent second trench structures 50 in the surface layer portion of the body region 49. The above-described well region 65 is not formed.

[0185] The plurality of second contact regions 66 are formed in a region between two adjacent second trench structures 50 in the surface layer portion of the body region 49. The source electrode 74 is electrically connected to the plurality of source regions 64 and the plurality of second contact regions 66 through the second interlayer insulating film 67.

[0186] 19 is a cross-sectional view showing another configuration example of the MISFET device 3. Referring to Fig. 19, the MISFET device 3 may include a second semiconductor region 45 having a thickness smaller than the thickness of the first semiconductor region 44 inside the second chip 40. In other words, the second chip 40 may include a semiconductor substrate having a thickness smaller than the thickness of the epitaxial layer.

[0187] 20 is a cross-sectional view showing another configuration example of the MISFET device 3. Referring to Fig. 20, the MISFET device 3 may not have the second semiconductor region 45 inside the second chip 40, and may include only the first semiconductor region 44. In this case, the first semiconductor region 44 is exposed from the first main surface 41, the second main surface 42, and the first to fourth side surfaces 43A to 43D of the second chip 40. That is, in this embodiment, the second chip 40 does not have a semiconductor substrate, but has a single-layer structure made of an epitaxial layer.

[0188] The above-described embodiment may be implemented in other forms. In the above-described embodiment, the first chip 10 is a Si chip. However, the first chip 10 may be a wide bandgap semiconductor chip made of a single crystal of a wide bandgap semiconductor chip. For example, the first chip 10 may be a SiC chip made of a SiC single crystal.

[0189] In the above embodiment, the second chip 40 is a wide bandgap semiconductor chip. However, the second chip 40 may be a Si chip made of single crystal Si.

[0190] In the above-described embodiment, the trench gate type IGBT device 2 is shown, which controls inversion and non-inversion of the channel inside the first chip 10. However, a planar gate type IGBT device 2 may be employed, which controls inversion and non-inversion of the channel from above the first main surface 11 of the first chip 10.

[0191] In the above-described embodiment, the trench-gate type MISFET device 3 is shown, which controls the inversion and non-inversion of the channel inside the second chip 40. However, a planar-gate type MISFET device 3 may be employed, which controls the inversion and non-inversion of the channel from above the first main surface 41 of the second chip 40.

[0192] In the above-described embodiment, the "first conductivity type" is "n-type" and the "second conductivity type" is "p-type". However, the above-described embodiment may also adopt a configuration in which the "first conductivity type" is "p-type" and the "second conductivity type" is "n-type". A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and the accompanying drawings.

[0193] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments.

[0194] [A1] A semiconductor module (1) including an IGBT device (2) and a MISFET device (3) that forms a parallel circuit with the IGBT device (2), generating a drain current (Ids) of the MISFET device (3) in a voltage range less than a built-in voltage (Vbi) of the IGBT device (2), and generating a collector current (Ice) of the IGBT device (2) and a drain current (Ids) of the MISFET device (3) in a voltage range equal to or greater than the built-in voltage (Vbi).

[0195] [A2] The semiconductor module (1) described in A1, wherein the IGBT device (2) has a first breakdown voltage (VB1), and the MISFET device (3) has a second breakdown voltage (VB2) equal to or greater than the first breakdown voltage (VB1).

[0196] [A3] The semiconductor module (1) according to A2, wherein the first breakdown voltage (VB1) is 500V or more and 1500V or less, and the second breakdown voltage (VB2) is 500V or more and 3000V or less.

[0197] [A4] A semiconductor module (1) according to any one of A1 to A3, wherein the IGBT device (2) includes a first chip (10) made of Si, and the MISFET device (3) includes a second chip (40) made of a wide bandgap semiconductor.

[0198] [A5] The semiconductor module (1) according to A4, wherein the wide band gap semiconductor is SiC.

[0199] [A6] A semiconductor module (1) described in A4 or A5, wherein the first chip (10) has a first chip area (S1), and the second chip (40) has a second chip area (S2) smaller than the first chip area (S1).

[0200] [A7] The semiconductor module (1) according to A6, wherein the second chip area (S2) is 0.1 times or more and 0.6 times or less the first chip area (S1).

[0201] [A8] The semiconductor module (1) according to any one of A4 to A7, wherein the second chip (40) is thinner than the first chip (10).

[0202] [A9] The semiconductor module (1) according to any one of A4 to A7, wherein the second chip (40) is thicker than the first chip (10).

[0203] [A10] The semiconductor module (1) according to any one of A1 to A9, wherein, with respect to a first characteristic (C1) indicating an individual collector current (Ice) of the IGBT device (2) alone and a second characteristic (C2) indicating an individual drain current (Ids) of the MISFET device (3) alone, when the individual drain current (Ids) at an intersection (P) of the first characteristic (C1) and the second characteristic (C2) is set to a first current value A and the individual drain current (Ids) when the built-in voltage (Vbi) is applied is set to a second current value B (B < A), a current ratio A / B of the first current value A to the second current value B is greater than 1 and not greater than 3 (1 < A / B ≦ 3).

[0204] [A11] The semiconductor module (1) according to A10, wherein the slope of the line connecting the first current value A and the second current value B is greater than 1 and not greater than 30.

[0205] [A12] The semiconductor module (1) according to A10 or A11, wherein the difference value (A-B) between the first current value A and the second current value B is 0.5 or more and 30 or less.

[0206] [A13] The semiconductor module (1) according to any one of A1 to A12, wherein the MISFET device (3) is of a trench gate type, and the IGBT device (2) is of a trench gate type.

[0207] [A14] The semiconductor module (1) according to any one of A1 to A13, wherein the IGBT device (2) is an RC-IGBT device integrally including an IGBT and a free wheel diode.

[0208] [A15] The semiconductor module (1) according to any one of A1 to A14, further comprising a support electrode (84), the IGBT device (2) being disposed on the support electrode (84), and the MISFET device (3) being disposed on the support electrode (84) and electrically connected to the IGBT device (2) via the support electrode (84).

[0209] [A16] A semiconductor module (1) according to A15, comprising: a wiring electrode (87) spaced apart from the support electrode (84); a first conductive connection member (90A) electrically connected to the MISFET device (3) and the wiring electrode (87); and a second conductive connection member (90C) electrically connected to the IGBT device (2) and the wiring electrode (87).

[0210] [A17] A semiconductor module (1) described in A16, wherein the first conductive connection member (90A) is mechanically and electrically connected to the MISFET device (3) and the wiring electrode (87), and the second conductive connection member (90C) is mechanically and electrically connected to the MISFET device (3) and the IGBT device (2) and is electrically connected to the wiring electrode (87) via the first conductive connection member (90A).

[0211] Although the embodiments have been described in detail above, these are merely specific examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiments.

[0212] REFERENCE SIGNS LIST 1 Semiconductor module 2 IGBT device 3 MISFET device 10 First chip 40 Second chip 80 Package body 84 Support electrode 87 Wiring electrode 90A First conductive connection member 90B Second conductive connection member 90C Third conductive connection member 90D Fourth conductive connection member A First current value B Second current value C1 First characteristic C2 Second characteristic Ice Collector current Ids Drain current P Intersection S1 First chip area S2 Second chip area VB1 First breakdown voltage VB2 Second breakdown voltage Vbi Built-in voltage

Claims

1. an IGBT device; a MISFET device forming a parallel circuit with the IGBT device, a semiconductor module that generates a drain current of the MISFET device in a voltage range less than a built-in voltage of the IGBT device, and generates a collector current of the IGBT device and a drain current of the MISFET device in a voltage range equal to or greater than the built-in voltage.

2. the IGBT device has a first breakdown voltage; 2. The semiconductor module of claim 1, wherein said MISFET device has a second breakdown voltage greater than or equal to said first breakdown voltage.

3. the first breakdown voltage is greater than or equal to 500 V and less than or equal to 1500 V; The semiconductor module according to claim 2 , wherein the second breakdown voltage is not less than 500 V and not more than 3000 V.

4. The IGBT device includes a first chip made of Si; 2. The semiconductor module of claim 1, wherein the MISFET device includes a second chip made of a wide bandgap semiconductor.

5. The semiconductor module according to claim 4 , wherein the wide band gap semiconductor is SiC.

6. the first chip has a first chip area; 5. The semiconductor module according to claim 4, wherein the second chip has a second chip area smaller than the first chip area.

7. The semiconductor module according to claim 6 , wherein the second chip area is 0.1 to 0.6 times the area of ​​the first chip.

8. The semiconductor module according to claim 4 , wherein the second chip is thinner than the first chip.

9. The semiconductor module according to claim 4 , wherein the second chip is thicker than the first chip.

10. The MISFET device according to claim 1, wherein the MISFET device is of a trench gate type.

2. The semiconductor module according to claim 1, wherein the IGBT device is of a trench gate type.

11. The semiconductor module of claim 1, wherein the IGBT device comprises an RC-IGBT device integrally including an IGBT and a free wheel diode.

12. With respect to a first characteristic indicating an individual collector current of the IGBT device alone and a second characteristic indicating an individual drain current of the MISFET device alone, when the individual drain current at an intersection of the first characteristic and the second characteristic is set to a first current value A and the individual drain current when the built-in voltage is applied is set to a second current value B (B<A), 2. The semiconductor module according to claim 1, wherein a current ratio A / B of said first current value A to said second current value B is greater than 1 and equal to or less than 3 (1<A / B≦3).

13. 13 . The semiconductor module according to claim 12 , wherein a slope of a straight line connecting the first current value A and the second current value B is greater than 1 and equal to or less than 30.

14. 13. The semiconductor module according to claim 12, wherein a difference value (A-B) between the first current value A and the second current value B is equal to or greater than 0.5 and equal to or less than 30.

15. Further comprising a supporting electrode; the IGBT device is disposed on the support electrode; 15. The semiconductor module according to claim 1, wherein the MISFET device is disposed on the support electrode and is electrically connected to the IGBT device via the support electrode.

16. a wiring electrode provided at a distance from the support electrode; a first conductive connection member electrically connected to the MISFET device and the wiring electrode; 16. The semiconductor module according to claim 15, further comprising: a second conductive connection member electrically connected to the IGBT device and the wiring electrode.

17. the first conductive connection member is mechanically and electrically connected to the MISFET device and the wiring electrode; 17. The semiconductor module according to claim 16, wherein the second conductive connection member is mechanically and electrically connected to the MISFET device and the IGBT device, and is electrically connected to the wiring electrode via the first conductive connection member.