Group iii-v compound semiconductor single crystal substrate and manufacturing method therefor

Abstract

This group III-V compound semiconductor single crystal substrate has a circular main surface, is an indium phosphide single crystal substrate, and has a ripple pattern visible on the main surface by being subjected to the following process. The ripple pattern is a pattern corresponding to a part of ripples concentrically spread from a wave source, and the wave source is not positioned on the main surface.　Process: The main surface is horizontally disposed at a position 10 mm downward in the depth direction from a liquid level of a 25ºC mixed solution composed of 10 g of chromium(VI) oxide, 10 mL of a hydrofluoric acid solution having a concentration of 50 mass%, and 400 mL of pure water, and light of a reflection-type incandescent bulb of 500 W is radiated toward the main surface for 1-2 hours from a position that is spaced 20 cm upward from the liquid level.

Description

III-V group compound semiconductor single crystal substrate and manufacturing method thereof

[0001] The present disclosure relates to a III-V compound semiconductor single crystal substrate and a method for manufacturing the same.

[0002] Japanese Patent Laid-Open Publication No. 2012-236770 (Patent Document 1) and International Publication No. WO 2004 / 106597 (Patent Document 2) disclose III-V group compound semiconductor single crystal substrates such as indium phosphide single crystal substrates. Japanese Patent Laid-Open Publication No. 2019-043788 (Patent Document 3) discloses a method for growing a compound semiconductor single crystal, which serves as a raw material for compound semiconductor single crystal substrates, using a so-called VB method such as the vertical Bridgeman method. Generally, the above-mentioned III-V group compound semiconductor single crystal substrates are manufactured by cutting a III-V group compound semiconductor single crystal, such as an indium phosphide single crystal or a gallium arsenide single crystal, into a disk shape (hereinafter, the above-mentioned cutting is also referred to as "slicing").

[0003] JP 2012-236770 A International Publication No. 2004 / 106597 JP 2019-043788 A

[0004] A III-V compound semiconductor single crystal substrate according to the present disclosure is a III-V compound semiconductor single crystal substrate having a circular main surface, the III-V compound semiconductor single crystal substrate being an indium phosphide single crystal substrate, and the indium phosphide single crystal substrate having a ripple-like pattern visible on the main surface by undergoing the following treatment, the ripple-like pattern corresponding to part of ripples spreading concentrically from a wave source, the wave source not being located on the main surface: Treatment: The main surface was placed horizontally at a position 10 mm below the surface in a depth direction of a mixture of 10 g of chromium (VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water at 25°C, and light from a 500 W reflector incandescent lamp was irradiated toward the main surface from a position 20 cm above the liquid surface for at least one hour and at most two hours.

[0005] A III-V compound semiconductor single crystal substrate according to the present disclosure is a III-V compound semiconductor single crystal substrate having a circular main surface, the III-V compound semiconductor single crystal substrate being a gallium arsenide single crystal substrate, the gallium arsenide single crystal substrate having a ripple-like pattern visible on the main surface by undergoing the following treatment, the ripple-like pattern corresponding to a portion of ripples spreading concentrically from a wave source, the wave source not being located on the main surface: Treatment: The main surface was placed horizontally at a position 10 mm below the surface level of a 25°C mixture consisting of 10 g of chromium (VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water, and light from a 500 W reflector incandescent lamp was irradiated toward the main surface from a position 20 cm above the liquid surface for 5 to 20 minutes.

[0006] A method for manufacturing a III-V compound semiconductor single crystal substrate according to the present disclosure is a method for manufacturing a III-V compound semiconductor single crystal substrate using a crystal growth apparatus, and includes the steps of: bringing a seed crystal into contact with a source melt and growing a crystalline solid on the source melt side of the seed crystal to obtain a III-V compound semiconductor single crystal; and cutting out the III-V compound semiconductor single crystal to obtain a III-V compound semiconductor single crystal substrate having a circular main surface, wherein the crystal growth apparatus includes at least a cylindrical crucible and a heating element for heating the crucible, the seed crystal being accommodated in a bottom portion of the crucible and the source melt being accommodated in the crucible above the seed crystal, and the interface between the crystalline solid and the source melt forms an intersecting angle of less than 90° with respect to an axis of the crucible.

[0007] Fig. 1 is an explanatory diagram illustrating a ripple-like pattern visible on a main surface of a III-V compound semiconductor single crystal substrate according to this embodiment when the substrate is subjected to a light-based etching treatment, and the wave source position of the ripple-like pattern. Fig. 2 is an explanatory diagram illustrating a ripple-like pattern visible on a main surface of a conventional III-V compound semiconductor single crystal substrate when the substrate is subjected to a light-based etching treatment, and the wave source position of the ripple-like pattern. Fig. 3 is an explanatory diagram illustrating the residual strain, which is the absolute value of the difference between expansion and contraction strain in the radial direction and the tangential direction of the main surface, for the III-V compound semiconductor single crystal substrate according to this embodiment, in polar coordinates, with the center of the main surface as the origin and an imaginary line segment extending from the center of the main surface toward the wave source to a point 15 mm away from the outer periphery of the III-V compound semiconductor single crystal substrate as the starting line. Fig. 4 is an explanatory diagram showing the residual strain, which is the absolute value of the difference between the expansion and contraction strain in the radial direction and the tangential direction of the main surface, in polar coordinates with the center of the main surface as the origin and an imaginary line segment extending from the center of the main surface toward the wave source to a point 15 mm away from the outer periphery of the III-V compound semiconductor single crystal substrate for a conventional III-V compound semiconductor single crystal substrate. Fig. 5 is an explanatory diagram showing 69 measurement points set on the main surface for the purpose of determining the dislocation density of the main surface for a III-V compound semiconductor single crystal substrate according to this embodiment. Fig. 6 is an explanatory diagram showing a method for determining the degree of dislocation asymmetry present on the main surface by utilizing the ripple pattern shown in Fig. 1 and the 69 measurement points shown in Fig. 5 for a III-V compound semiconductor single crystal substrate according to this embodiment. Fig. 7 is a schematic diagram showing a crystal growth apparatus for growing a III-V compound semiconductor single crystal, which is the raw material for the III-V compound semiconductor single crystal substrate according to this embodiment. FIG. 8 is a flowchart showing an example of a method for manufacturing a III-V compound semiconductor single crystal substrate according to this embodiment.

[0008] [Problem to be Solved by the Present Disclosure] In the process of obtaining a compound semiconductor single crystal substrate by slicing as disclosed in Patent Documents 1 and 2, there have been cases where stricter yield standards have been required. Specifically, when slicing a compound semiconductor single crystal, the substrate may crack or chip, resulting in so-called crack defects. There has been a demand for reducing the probability of such crack defects (hereinafter also referred to as the "crack defect rate"). In such cases, there has been room for improvement in the III-V compound semiconductor single crystal substrates disclosed in Patent Documents 1 and 2 from the perspective of reducing the crack defect rate.

[0009] In view of the above circumstances, an object of the present disclosure is to provide a III-V compound semiconductor single crystal substrate with a reduced crack defect rate, and a method for manufacturing the same.

[0010] Effect of the Present Disclosure According to the present disclosure, it is possible to provide a III-V compound semiconductor single crystal substrate with a reduced crack defect rate, and a method for manufacturing the same.

[0011] [Summary of the Embodiments] First, an overview of the embodiments of the present disclosure will be described. The present inventors have completed the present disclosure after extensive research to solve the above-mentioned problems. Specifically, the inventors employed the following method as a method for growing a III-V compound semiconductor single crystal, which serves as a raw material for a III-V compound semiconductor single crystal substrate, in the crucible of a crystal growth apparatus using a so-called VB method, such as a vertical boat method. That is, the interface between the crystalline solid grown on the seed crystal's side toward the raw material melt and the raw material melt is not horizontal as in the conventional method, but is made to have an intersecting angle of less than 90° with respect to the axis of the crucible. The inventors have found that using such a method reduces the rate of crack defects when slicing the III-V compound semiconductor single crystal substrate. Furthermore, the inventors have found that, unlike conventional methods, the wave source of the ripple-like pattern obtained by performing a predetermined etching process on the main surface of a III-V compound semiconductor single crystal substrate obtained using the above method is not located on the main surface, which is different from conventional methods. This finding led to the present disclosure.

[0012] Next, embodiments of the present disclosure will be described below. [1] A III-V compound semiconductor single crystal substrate according to one aspect of the present disclosure is a III-V compound semiconductor single crystal substrate having a circular main surface, the III-V compound semiconductor single crystal substrate being an indium phosphide single crystal substrate, and the indium phosphide single crystal substrate having a ripple-like pattern visible on the main surface by performing the following treatment, the ripple-like pattern corresponding to part of ripples spreading concentrically from a wave source, the wave source not being located on the main surface: Treatment: The main surface was placed horizontally at a position 10 mm below the surface of a 25°C mixture consisting of 10 g of chromium (VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water, and light from a 500 W reflector incandescent lamp was irradiated toward the main surface from a position 20 cm above the liquid surface for at least one hour and at most two hours.

[0013] The indium phosphide single crystal substrate, which is a III-V group compound semiconductor single crystal substrate having such characteristics, can reduce the rate of crack defects during slicing.

[0014] [2] The diameter of the indium phosphide single crystal substrate is preferably 50 mm or more and 155 mm or less. This makes it possible to reduce the rate of crack defects during slicing for indium phosphide single crystal substrates having a diameter of 50 mm or more and 155 mm or less.

[0015] [3] The dislocation density of the main surface is 0 cm -2 More than 2000cm -2 This makes it possible to provide an indium phosphide single crystal substrate with a reduced dislocation density over the entire main surface.

[0016] [4] The asymmetry of dislocations present on the main surface is 1.8 or more, and the asymmetry is determined by dividing the main surface into a first region and a second region by an imaginary first line that intersects perpendicularly with an imaginary line extending in a direction from the wave source toward the center of the main surface and passes through the center of the main surface, and in each of the first region and the second region, two or more 1 mm interval dislocations are located at a pitch of 5 mm or more in a direction away from the center of the main surface on an imaginary second line that passes through the center of the main surface and intersects perpendicularly with the first line. 2 A square measurement point having an area of ​​1 cm is set, the number of dislocations is measured at the measurement point, and the number of dislocations is calculated based on the measurement result. 2 It is preferable to convert the average of the converted values ​​obtained from all the measurement points in the first region into a converted value per area of ​​1 / 2 mm, subtract the average of the converted values ​​obtained from all the measurement points in the second region from the average of the converted values ​​obtained from all the measurement points in the first region, and divide the absolute value of the obtained value by the average of the converted values ​​obtained from all the measurement points in the first region and the second region. This makes it possible to further reduce the crack defect rate during slicing.

[0017] [5] A III-V compound semiconductor single crystal substrate according to one embodiment of the present disclosure is a III-V compound semiconductor single crystal substrate having a circular main surface, the III-V compound semiconductor single crystal substrate being a gallium arsenide single crystal substrate, the gallium arsenide single crystal substrate having a ripple-like pattern visible on the main surface by performing the following treatment: the ripple-like pattern corresponds to a part of ripples spreading concentrically from a wave source, the wave source not being located on the main surface. Treatment: The main surface is placed horizontally at a position 10 mm below the surface of a 25°C mixture consisting of 10 g of chromium (VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water, and light from a 500 W reflector incandescent lamp is irradiated toward the main surface from a position 20 cm above the liquid surface for 5 to 20 minutes.

[0018] A gallium arsenide single crystal substrate, which is a III-V group compound semiconductor single crystal substrate having such characteristics, can reduce the rate of crack defects during slicing.

[0019] [6] The diameter of the gallium arsenide single crystal substrate is preferably 75 mm or more and 205 mm or less. This makes it possible to reduce the rate of cracking defects during slicing for gallium arsenide single crystal substrates having a diameter of 75 mm or more and 205 mm or less.

[0020] [7] The dislocation density of the main surface is 0 cm -2 More than 50cm -2 This makes it possible to provide a gallium arsenide single crystal substrate with a reduced dislocation density over the entire main surface.

[0021] [8] The asymmetry of dislocations present on the main surface is 2.0 or more, and the asymmetry is determined by dividing the main surface into a first region and a second region by an imaginary first line that intersects perpendicularly with an imaginary line extending in a direction from the wave source toward the center of the main surface and passes through the center of the main surface, and in each of the first region and the second region, two or more 1 mm interval dislocations are located at a pitch of 5 mm or more in a direction away from the center of the main surface on an imaginary second line that passes through the center of the main surface and intersects perpendicularly with the first line. 2 A square measurement point having an area of ​​1 cm is set, the number of dislocations is measured at the measurement point, and the number of dislocations is calculated based on the measurement result. 2 It is preferable to convert the average of the converted values ​​obtained from all the measurement points in the first region into a converted value per area of ​​1 / 2 mm, subtract the average of the converted values ​​obtained from all the measurement points in the second region from the average of the converted values ​​obtained from all the measurement points in the first region, and divide the absolute value of the obtained value by the average of the converted values ​​obtained from all the measurement points in the first region and the second region. This makes it possible to further reduce the crack defect rate during slicing.

[0022] [9] The main surface is preferably a plane having an off-angle of 0° or more and 15° or less from the {100} plane. This allows the main surface to have excellent electrical and optical properties. As a result, in a III-V compound semiconductor single crystal substrate having a main surface having excellent electrical and optical properties, the crack defect rate during slicing can be reduced.

[0023]

[10] The average value of the residual strain, which is the absolute value of the difference between the expansion and contraction strain in the direction along the diameter of the main surface and the expansion and contraction strain in the direction along the tangent, is 3.5 × 10 -5 This makes it possible to more sufficiently reduce the rate of cracking defects during slicing.

[0024]

[11] In polar coordinates in which the origin is the center of the main surface and an imaginary line segment extending from the center of the main surface toward the wave source to a point 15 mm away from the outer periphery of the III-V compound semiconductor single crystal substrate is taken as the starting line, the residual strain, which is the absolute value of the difference between the expansion and contraction strain in the direction along the diameter of the main surface and the expansion and contraction strain in the direction along the tangent, does not have a distribution with n-fold symmetry about the origin, where n is preferably an integer of 2 or greater. This makes it possible to more sufficiently reduce the rate of cracking during slicing.

[0025]

[12] The conductivity type of the III-V compound semiconductor single crystal substrate is preferably an electron-withdrawing type, which can reduce the rate of cracking defects during slicing in a III-V compound semiconductor single crystal substrate having an electron-withdrawing type (hereinafter also referred to as "n-type").

[0026]

[13] The III-V compound semiconductor single crystal substrate preferably contains tin or sulfur as an impurity atom when it is the indium phosphide single crystal substrate, and preferably contains silicon as an impurity atom when it is the gallium arsenide single crystal substrate. This makes it possible to reduce the crack defect rate during slicing in both the indium phosphide single crystal substrate containing tin or sulfur as an impurity atom and the gallium arsenide single crystal substrate containing silicon as an impurity atom.

[0027]

[14] The atomic concentration of the impurity atoms is 1×10 16 cm -3 1x10 or more 19 cm -3 This makes it possible to provide a III-V compound semiconductor single crystal substrate containing impurity atoms of an appropriate concentration that give the substrate an n-type conductivity.

[0028]

[15] It is preferable that the impurity atoms exhibit a concentration distribution that changes uniformly in the direction from the wave source toward the center of the main surface in the III-V compound semiconductor single crystal substrate, thereby further reducing the crack defect rate during slicing in a III-V compound semiconductor single crystal substrate having n-type conductivity.

[0029]

[16] A method for manufacturing a III-V compound semiconductor single crystal substrate according to one aspect of the present disclosure is a method for manufacturing a III-V compound semiconductor single crystal substrate using a crystal growth apparatus, the method including the steps of: bringing a seed crystal into contact with a source melt and growing a crystalline solid on the source melt side of the seed crystal to obtain a III-V compound semiconductor single crystal; and cutting out the III-V compound semiconductor single crystal to obtain a III-V compound semiconductor single crystal substrate having a circular main surface, wherein the crystal growth apparatus includes at least a cylindrical crucible and a heating element for heating the crucible, the seed crystal being accommodated in a bottom portion of the crucible and the source melt being accommodated in the crucible above the seed crystal, and the interface between the crystalline solid and the source melt forming an intersecting angle of less than 90° with respect to an axis of the crucible. By using the method for manufacturing a III-V compound semiconductor single crystal substrate having such characteristics, it is possible to obtain a III-V compound semiconductor single crystal substrate with a reduced rate of cracking defects during slicing.

[0030] [Details of the embodiment] One embodiment according to the present disclosure (hereinafter also referred to as "the present embodiment") will be described in further detail below, but the present disclosure is not limited thereto. The following description may be made with reference to the drawings, and the same or corresponding elements in this specification and the drawings will be denoted by the same reference numerals, and the same description will not be repeated. Furthermore, the scale of the drawings has been adjusted appropriately to facilitate understanding of each component, and the scale of each component shown in the drawings does not necessarily coincide with the scale of the actual component.

[0031] In this specification, the expression "A to B" means the upper and lower limits of a range (i.e., A or more and B or less), and when no unit is specified for A and only a unit is specified for B, the units of A and B are the same. Furthermore, when a compound or the like is expressed in this specification by a chemical formula, unless the atomic ratio is particularly limited, it is understood to include any conventionally known atomic ratio, and should not necessarily be limited to only those within a stoichiometric range.

[0032] In this specification, the "main surface" of a III-V compound semiconductor single crystal substrate refers to both of the two circular faces of the substrate. When at least one of the two faces of a III-V compound semiconductor single crystal substrate satisfies the scope of the claims of the present disclosure, the substrate falls within the scope of the present invention. Furthermore, when the diameter of a III-V compound semiconductor single crystal substrate is described as "50 mm," this means that the diameter is approximately 50 mm (approximately 50 to 50.8 mm), or 2 inches. When the diameter is described as "75 mm," this means that the diameter is approximately 75 mm (approximately 75 to 76.5 mm), or 3 inches. When the diameter is described as "100 mm," this means that the diameter is approximately 100 mm (approximately 95 to 105 mm), or 4 inches. When the diameter is described as "150 mm," this means that the diameter is approximately 150 mm (approximately 145 to 155 mm), or 6 inches. When the diameter is described as "200 mm," this means that the diameter is approximately 200 mm (approximately 195 to 205 mm), or 8 inches. The diameter can be measured using a conventionally known outer diameter measuring device such as a vernier caliper.

[0033] The III-V compound semiconductor single crystal substrate has a "circular" main surface, as described below. In this specification, the term "circular" used to describe the shape of the main surface includes not only a geometrically circular shape but also a shape in which the main surface does not form a geometrically circular shape due to the formation of at least one of a notch, an orientation flat (hereinafter also referred to as "OF"), and an index flat (hereinafter also referred to as "IF"). In other words, a "shape in which the main surface does not form a geometrically circular shape" refers to a shape in which, among line segments extending from any point on the periphery of the main surface to the center of the main surface, the length of a line segment extending from any point on the notch, OF, or IF to the center of the main surface is shorter. In other words, in this specification, the shape of the main surface is considered to be "circular" based on the shape before the notch, OF, and IF are formed. Therefore, the position and size (length) of the center of the main surface and the diameter of the substrate are determined based on the circular shape before the notch, OF, IF, etc. are formed. The "shape in which the main surface does not form a geometrically circular shape" also includes a shape in which the lengths of all line segments extending from any point on the periphery of the main surface to the center of the main surface are not necessarily the same due to the shape of the III-V compound semiconductor single crystal before it is cut out as a III-V compound semiconductor single crystal substrate. In this case, the center of the main surface refers to the position of the center of gravity, and the diameter of the substrate refers to the length of the longest line segment among the line segments extending from any point on the periphery of the substrate to the center of the main surface.

[0034] In the crystallographic descriptions in this specification, individual orientations are represented by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. A negative index in crystallographic terms is usually represented by placing a "- (bar)" before the number, but when this is expressed in this specification, a negative sign is placed before the number.

[0035] [III-V Compound Semiconductor Single Crystal Substrate] <First Embodiment: Indium Phosphide Single Crystal Substrate (InP Substrate)> A III-V compound semiconductor single crystal substrate according to this embodiment, for example, the first embodiment, has a circular main surface. In particular, the III-V compound semiconductor single crystal substrate is an indium phosphide single crystal substrate (hereinafter also referred to as an "InP substrate"). The InP substrate has a ripple-like pattern visible on the main surface by undergoing the following treatment. The ripple-like pattern is a pattern corresponding to a part of ripples spreading concentrically from a wave source. Furthermore, the wave source is not located on the main surface. Treatment: The main surface was placed horizontally at a position 10 mm below the liquid surface in a 25°C mixed liquid consisting of 10 g of chromium (VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water, and light from a 500 W reflector-type incandescent lamp was irradiated toward the main surface from a position 20 cm above the liquid surface for 1 hour to 2 hours.

[0036] In the case of an InP substrate, which is a III-V compound semiconductor single crystal substrate having such characteristics, the wave source of the ripple-like pattern is not located on the main surface, and therefore the crack defect rate during slicing can be reduced.

[0037] The diameter of the InP substrate is preferably 50 mm or more and 155 mm or less. This makes it possible to reduce the crack defect rate during slicing for InP substrates having a diameter of 50 mm or more and 155 mm or less. Specifically, an InP substrate having a diameter of 50 mm or more and 155 mm or less preferably refers to an InP substrate having a diameter of 50 mm, 75 mm, 100 mm, or 150 mm, or in other words, an InP substrate having a diameter of 2 inches, 3 inches, 4 inches, or 6 inches. As mentioned above, the diameter of the InP substrate can be measured using a conventionally known diameter measuring device such as a vernier caliper.

[0038] <Second Embodiment: Gallium Arsenide Single Crystal Substrate (GaAs Substrate)> A III-V group compound semiconductor single crystal substrate according to this embodiment, for example, the second embodiment, has a circular main surface. In particular, the III-V group compound semiconductor single crystal substrate is a gallium arsenide single crystal substrate (hereinafter also referred to as a "GaAs substrate"). The GaAs substrate has a ripple-like pattern visible on the main surface by undergoing the following treatment. The ripple-like pattern is a pattern corresponding to a part of ripples spreading concentrically from a wave source. Furthermore, the wave source is not located on the main surface. Treatment: The main surface was placed horizontally at a position 10 mm below the liquid surface in a 25°C mixed liquid consisting of 10 g of chromium (VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water, and light from a 500 W reflector-type incandescent lamp was irradiated toward the main surface from a position 20 cm above the liquid surface for 5 minutes to 20 minutes.

[0039] A GaAs substrate, which is a III-V compound semiconductor single crystal substrate having such characteristics, can reduce the rate of crack defects during slicing because the wave source of the ripple-like pattern is not located on the main surface.

[0040] The diameter of the GaAs substrate is preferably 75 mm or more and 205 mm or less. This reduces the crack defect rate during slicing for GaAs substrates having a diameter of 75 mm or more and 205 mm or less. A GaAs substrate having a diameter of 75 mm or more and 205 mm or less preferably specifically refers to a GaAs substrate having a diameter of 75 mm, 100 mm, 150 mm, or 200 mm, or in other words, a GaAs substrate having a diameter of 3 inches, 4 inches, 6 inches, or 8 inches. As mentioned above, the diameter of the GaAs substrate can be measured using a conventionally known outer diameter measuring device such as a vernier caliper.

[0041] <Main Surface> The III-V compound semiconductor single crystal substrate according to this embodiment has a circular main surface as described above. Furthermore, the III-V compound semiconductor single crystal substrate (InP substrate or GaAs substrate) has a visible ripple pattern on the main surface by undergoing the following treatment. Specifically, the ripple pattern is visualized on the main surface by a process (hereinafter also referred to as "light-assisted etching process") in which the main surface is placed horizontally at a position 10 mm below the surface depth of a 25°C mixture of 10 g of chromium (VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water, and light from a 500 W reflector-type incandescent lamp is directed toward the main surface from a position 20 cm above the liquid surface for at least one hour and at most two hours if the III-V compound semiconductor single crystal substrate is an indium phosphide single crystal substrate, or for at least ten minutes and at most 20 minutes if the III-V compound semiconductor single crystal substrate is a gallium arsenide single crystal substrate. In other words, the ripple pattern appears on the main surface only after the main surface is subjected to a light-assisted etching process.

[0042] (Ripple Pattern and Wave Source Location of the Ripple Pattern) The III-V compound semiconductor single crystal substrate has a ripple pattern as described above. The ripple pattern is visible on the main surface by performing a light-based etching treatment on the main surface as described above. FIG. 1 is an explanatory diagram illustrating a ripple pattern that is visible on the main surface of a III-V compound semiconductor single crystal substrate according to this embodiment by performing a light-based etching treatment on the main surface, and the wave source location of the ripple pattern. In this specification, the term "ripple pattern" refers to a pattern that can be likened to the wave pattern (so-called ripples) that appears when an object is dropped on the surface of water, for example, and spreads in a circular pattern. Furthermore, the "wave source" of the ripple pattern refers to the origin or source from which the waves of the ripple pattern are generated. 1, the ripple-like pattern P appearing on the main surface S of the III-V compound semiconductor single crystal substrate 100 according to this embodiment is a pattern corresponding to a part of the ripples spreading concentrically from a wave source O, i.e., a pattern consisting of multiple arcs curved in the same direction. Furthermore, as shown in FIG. 1, the wave source O of the ripple-like pattern P is not located on the main surface S.

[0043] The reason why the crack defect rate during slicing is reduced in the III-V compound semiconductor single crystal substrate 100 having such a ripple-like pattern P is reduced in detail, but is presumed to be due to the following factors. First, the ripple-like pattern P visible on the main surface by the above-described light-based etching process is thought to be a pattern corresponding to the concentration of impurity atoms added as dopants or the like to the III-V compound semiconductor single crystal substrate 100. In other words, the ripple-like pattern P can be thought of as a visualized image of the impurity atoms contained in the III-V compound semiconductor single crystal substrate 100.

[0044] 2 is an explanatory diagram illustrating a ripple-like pattern visible on a main surface of a conventional III-V compound semiconductor single crystal substrate by performing an optical etching process on the main surface, and the wave source position of the ripple-like pattern. As shown in FIG. 2 , in a conventional III-V compound semiconductor single crystal substrate 101, the ripple-like pattern P visible on the main surface S by performing an optical etching process typically has a wave source O located at or near the center of the main surface S, and corresponds to ripples spreading concentrically from the wave source O. Such a III-V compound semiconductor single crystal substrate 101 is achieved by ensuring that the interface between the crystalline solid to be grown on the seed crystal's side of the raw material melt and the raw material melt is horizontal (or nearly horizontal) during the process of growing the raw material III-V compound semiconductor single crystal in a crucible provided in a crystal growth apparatus. In this case, the impurity atoms contained in the III-V compound semiconductor single crystal substrate 101 correspond to the ripple-like pattern P described above and are distributed concentrically from or near the center of the main surface S. At this time, the strain (hereinafter also referred to as "residual strain") generated in the III-V compound semiconductor single crystal substrate 101 due to the impurity atoms is represented in polar coordinates with the wave source O as the origin, and exhibits a distribution that is point-symmetric (specifically, four-fold symmetric) about the wave source (see FIG. 4). This indicates that in the conventional III-V compound semiconductor single crystal substrate 101, the stress of the residual strain is difficult to release on the substrate. Therefore, the stress of the residual strain is likely to be released during, for example, a slicing process to obtain the III-V compound semiconductor single crystal substrate 101 from the III-V compound semiconductor single crystal, which is thought to result in cracks occurring in the substrate to a certain extent.

[0045] 1 , the ripple-like pattern P in the III-V compound semiconductor single crystal substrate 100 according to this embodiment has a wave source O outside the main surface S. In other words, the wave source O is not located on the main surface S. Therefore, the ripple-like pattern P in the III-V compound semiconductor single crystal substrate according to this embodiment is a pattern equivalent to a portion of ripples spreading concentrically from the wave source O, i.e., a pattern consisting of multiple arcs curved in the same direction. Such a III-V compound semiconductor single crystal substrate 100 can be achieved in the process of growing the III-V compound semiconductor single crystal, which serves as the raw material, in a crucible provided in a crystal growth apparatus, by ensuring that the interface between the crystalline solid grown on the seed crystal's side toward the raw material melt and the raw material melt is not horizontal but forms an intersecting angle of less than 90° with the axis of the crucible, as exemplified in the section "Method for Manufacturing III-V Compound Semiconductor Single Crystal Substrate" described later. In this case, the impurity atoms contained in the III-V compound semiconductor single crystal substrate 100 are distributed on the main surface S in the form of multiple arcs curved in the same direction, corresponding to the ripple-like pattern P described above. When the residual strain generated in the III-V compound semiconductor single crystal substrate 100 due to the impurity atoms is expressed in polar coordinates with the center of the main surface S as the origin, the residual strain does not exhibit an n-fold symmetry (where n is an integer of 2 or greater) distribution about the origin, but rather exhibits a simple one-fold symmetry distribution, particularly a distribution with approximate mirror symmetry (see FIG. 3 ). This demonstrates that the III-V compound semiconductor single crystal substrate 100 according to this embodiment is prone to release stress due to the residual strain on the substrate (for example, stress is likely to be released at the intersections of the outer periphery of the main surface with the left and right ends of the arcs). Therefore, the stress of the residual strain does not need to be released during a slicing process or the like to obtain the III-V compound semiconductor single crystal substrate 100 from the III-V compound semiconductor single crystal, which is thought to reduce the rate of cracking defects in the substrate.

[0046] Here, the details of the light-based etching process are described. First, a III-V compound semiconductor single crystal substrate is prepared by polishing at least one of the two main surfaces to an arithmetic mean roughness Ra of 0.1 nm to 0.5 nm. The substrate is then placed horizontally, with the polished surface facing upward, at a depth of 10 mm below the surface of a 25°C mixture consisting of 10 g of chromium (VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water. Next, if the substrate is, for example, an indium phosphide single crystal substrate, the polished surface is etched by irradiating it with light from a 500 W reflector-type incandescent lamp (e.g., product name: "Eye Lamp (registered trademark)" by Iwasaki Electric Co., Ltd.) for 1 to 2 hours from a position 20 cm above the liquid surface. This allows a pattern to be formed on the polished surface. On the other hand, if the substrate is, for example, a gallium arsenide single crystal substrate, the polished surface is etched by irradiating the polished surface with the light from a position 20 cm above the liquid surface for 5 to 20 minutes. This allows a pattern to be formed on the polished surface. Finally, by visually inspecting the pattern formed on the polished surface, it is possible to determine whether the pattern is a ripple-like pattern, and if the pattern is a ripple-like pattern, it is possible to identify whether the wave source is located on the main surface.

[0047] The time for irradiating the main surface with light from a reflector-type incandescent lamp (hereinafter also referred to as "etching time") differs depending on whether the III-V group compound semiconductor single crystal substrate is an indium phosphide single crystal substrate or a gallium arsenide single crystal substrate, and the reason for the range of the etching time is to enhance the sharpness of the pattern (ripple-like pattern) formed on the polished surface. Therefore, in the present disclosure, regardless of whether the III-V group compound semiconductor single crystal substrate is an indium phosphide single crystal substrate or a gallium arsenide single crystal substrate, the etching time can be extended or shortened within the aforementioned range in order to enhance the sharpness of the pattern formed on the polished surface. Furthermore, fine adjustments, such as increasing or decreasing the light intensity, can also be made. The temperature of the mixed liquid (25°C) refers to the temperature at the start of the light-based etching process. Therefore, the temperature of the mixed liquid may fluctuate during the etching process due to factors such as the thermal energy of the light from the reflector-type incandescent lamp. Furthermore, during the etching process, it is preferable to oscillate the substrate in the mixed liquid at predetermined intervals (e.g., every minute) to enhance the sharpness of the pattern formed on the polished surface.

[0048] (Residual Strain) In the III-V compound semiconductor single crystal substrate according to this embodiment, the average value of residual strain, which is the absolute value of the difference between the expansion and contraction strain in the direction along the diameter of the main surface and the expansion and contraction strain in the direction along the tangent, is 3.5×10 -5 It is preferable that the average value of the residual strain is 3.5×10 or less. -5 By keeping the residual strain at or below 1.0×10, the stress does not need to be released during slicing or other processes to obtain the III-V compound semiconductor single crystal substrate, and therefore the crack defect rate of the substrate can be reduced. -6 In this specification, the expansion strain in the direction along the diameter of the main surface may be represented by "Sr", and the expansion strain in the direction along the tangent to the main surface may be represented by "St".

[0049] In particular, the average value of the residual strain can have a more preferable value depending on whether the III-V compound semiconductor single crystal substrate is an InP substrate or a GaAs substrate, the type of impurity atoms contained in the substrate, the diameter of the substrate, etc. For example, in the case of an InP substrate with a diameter of 50 mm containing tin as an impurity atom, the average value of the residual strain is 5.9 × 10 -6 In the case of an InP substrate having a diameter of 50 mm containing sulfur as an impurity atom, the average value of the residual strain is 5.4×10 -6 More preferably, it is:

[0050] In the case of an InP substrate having a diameter of 75 mm containing tin as an impurity atom, the average value of the residual strain is 1.1×10 -5 In the case of an InP substrate having a diameter of 75 mm containing sulfur as an impurity atom, the average value of the residual strain is 9.5×10 -6 In the case of an InP substrate having a diameter of 100 mm containing tin as an impurity atom, the average value of the residual strain is 2.2×10 -5 In the case of an InP substrate having a diameter of 100 mm containing sulfur as an impurity atom, the average value of the residual strain is more preferably 2.0×10 -5 In the case of an InP substrate having a diameter of 150 mm containing tin as an impurity atom, the average value of the residual strain is 3.9×10 -5 In the case of an InP substrate having a diameter of 150 mm containing sulfur as an impurity atom, the average value of the residual strain is 3.4×10 -6 More preferably, it is:

[0051] In the case of a GaAs substrate having a diameter of 75 mm and containing silicon as an impurity atom, the average value of the residual strain is 8.2×10 -6 In the case of a GaAs substrate having a diameter of 100 mm containing silicon as an impurity atom, the average value of the residual strain is preferably 1.0×10 -5In the case of a GaAs substrate having a diameter of 150 mm containing silicon as an impurity atom, the average value of the residual strain is more preferably 2.0×10 -5 In the case of a GaAs substrate having a diameter of 200 mm containing silicon as an impurity atom, the average value of the residual strain is preferably 3.5×10 -5 More preferably, it is:

[0052] Regarding the residual strain, which is the absolute value of the difference between the expansion and contraction strain in the radial direction and the tangent direction of the main surface, expressing the residual strain in polar coordinates with the center of the main surface as the origin and an imaginary line segment extending from the center of the main surface toward the wave source to a point 15 mm away from the outer periphery of the III-V compound semiconductor single crystal substrate as the starting line is convenient for identifying the amount and distribution of the residual strain contained in the III-V compound semiconductor single crystal substrate. The polar coordinates allow the distribution of the residual strain in the III-V compound semiconductor single crystal substrate to be visually understood, thereby making it easy to grasp the likelihood of the residual strain being released during slicing to obtain the substrate, i.e., the likelihood of cracking (the cracking defect rate), etc. In this case, it is preferable that the residual strain in the III-V compound semiconductor single crystal substrate according to this embodiment does not have an n-fold symmetric distribution about the origin in the polar coordinates, and that n is an integer of 2 or greater. Specifically, the residual strain preferably exhibits a distribution with one-fold symmetry around the origin in the polar coordinate system. In particular, from the viewpoint of further reducing the crack defect rate of the substrate, the residual strain preferably exhibits a distribution with symmetry close to mirror symmetry (hereinafter also referred to as "approximate mirror symmetry") with a virtual line extending from the center of the main surface toward the wave source as the central axis. In this specification, "n-fold symmetry" around the origin refers to symmetry characterized as rotational symmetry around the origin, specifically, symmetry that overlaps with itself when rotated (360 / n) degrees around the origin. The n is an integer of 2 or greater. For example, "three-fold symmetry" refers to symmetry that overlaps with itself when rotated 120 degrees when n = 3.

[0053] The residual strain (hereinafter also referred to as "|Sr-St|"), which is the absolute value of the difference between the expansion and contraction strain in the radial direction and the tangential direction of the main surface, can be measured based on the photoelastic method described in Appl. Phys. Lett. 47 (1985) pp. 365-367. First, similar to the procedure for performing the light-based etching process described above, a III-V compound semiconductor single crystal substrate is prepared by polishing at least one of the two main surfaces to an arithmetic mean roughness Ra of 0.1 nm to 0.5 nm to form a polished surface. Next, the photoelastic method is applied to the polished surface to measure the residual strain present across the entire surface. In particular, in the photoelastic method, the residual strain can be determined as the absolute value |Sr-St|. In the photoelastic method, the residual strain (|Sr-St|) is defined as follows:

[0054]

[0055] In the above formula (1), λ represents the wavelength of the light used for measurement, d represents the thickness of the III-V group compound semiconductor single crystal substrate used for measurement, n0 represents the refractive index, δ represents the phase difference caused by the birefringence of the sample to be measured, φ represents the principal vibration azimuth angle, and p 11 , p 12 , p 44 denotes the photoelastic constant.

[0056] According to the photoelastic method, the residual strain (|Sr-St|) on the entire main surface of the substrate can be obtained by measuring only the phase difference δ and the principal vibration azimuth angle φ caused by the birefringence of the sample to be measured.

[0057] Furthermore, based on the residual strain (|Sr−St|) across the entire main surface of the substrate, as shown in FIGS. 3 and 4, for example, the residual strain can be expressed in polar coordinates with the center of the main surface as the origin and an imaginary line segment as the starting line, which extends from the center of the main surface toward the wave source to a point 15 mm away from the outer periphery of the III-V compound semiconductor single crystal substrate.

[0058] 3 is an explanatory diagram showing the residual strain, which is the absolute value of the difference between the expansion and contraction strain in the radial direction and the tangent direction of the main surface, for the III-V compound semiconductor single crystal substrate according to this embodiment, in polar coordinates with the center of the main surface as the origin and an imaginary line segment as the starting line extending from the center of the main surface along the direction from the center of the main surface toward the wave source to a point 15 mm away from the outer periphery of the III-V compound semiconductor single crystal substrate. 4 is an explanatory diagram showing the residual strain, which is the absolute value of the difference between the expansion and contraction strain in the radial direction and the tangent direction of the main surface, for a conventional III-V compound semiconductor single crystal substrate, in polar coordinates with the center of the main surface as the origin and an imaginary line segment as the starting line extending from the center of the main surface along the direction from the center of the main surface toward the wave source to a point 15 mm away from the outer periphery of the III-V compound semiconductor single crystal substrate.

[0059] As can be seen from a comparison of Figures 3 and 4, the residual strain in the main surface of the III-V compound semiconductor single crystal substrate according to this embodiment does not have a distribution with n-fold symmetry (where n is an integer of 2 or greater) in the polar coordinates, but rather exhibits a distribution with one-fold symmetry about the origin. In particular, Figure 3 shows that the residual strain in the III-V compound semiconductor single crystal substrate according to this embodiment exhibits a distribution with approximate mirror symmetry about an imaginary line extending from the center of the main surface toward the wave source. This distribution with one-fold symmetry, particularly approximate mirror symmetry, about the origin in the polar coordinates indicates that the III-V compound semiconductor single crystal substrate according to this embodiment has a site on the substrate that is easy to release the stress of the residual strain. On the other hand, a conventional III-V compound semiconductor single crystal substrate exhibits a distribution with four-fold symmetry about the origin in the polar coordinates, and therefore does not have a site on the substrate that is easy to release the stress of the residual strain.

[0060] In the III-V compound semiconductor single crystal substrate according to this embodiment, when the residual strain is measured, this may be performed before or after determining the dislocation density in the main surface, as described below. When the residual strain is measured after determining the dislocation density in the main surface, corrosion pits corresponding to dislocations (etch pits) are formed on the main surface, and therefore both sides of the main surface can be polished in order to remove the corrosion pits and to turn the main surface into the polished surface described above.

[0061] (Off Angle) The main surface is preferably a plane having an off angle of 0° or more and 15° or less from the {100} plane. When the main surface has an off angle of 0° or more and 15° or less from the {100} plane, the main surface of the III-V compound semiconductor single crystal substrate has an orientation that provides excellent electrical and optical properties. This embodiment can thereby reduce the crack defect rate in a III-V compound semiconductor single crystal substrate having as its main surface a plane that provides excellent electrical and optical properties.

[0062] Such a III-V compound semiconductor single crystal substrate can be obtained by slicing a III-V compound semiconductor single crystal, which is the raw material for the III-V compound semiconductor single crystal substrate, so that the main surface is a plane just off-axis (i.e., a {100} plane) with no off-axis angle. Alternatively, the III-V compound semiconductor single crystal can be obtained by performing a conventionally known inclined slicing method so that the main surface is a plane having an off-axis angle of more than 0° and not more than 15° from the {100} plane. When obtaining such a raw material (III-V compound semiconductor single crystal), the growth direction of the III-V compound semiconductor single crystal is preferably the <100> direction. Here, in the present disclosure, the "off-axis angle" is defined to have an accuracy error of ±0.5°. For example, if the main surface is a {100} just plane, the main surface may have an off-axis angle of −0.5 to 0.5° from the {100} plane. Furthermore, for example, when the main surface is a plane having an off angle of 15° from the {100} plane, the main surface may have an off angle of 14.5 to 15.5° from the {100} plane.

[0063] The off-angle from the {100} plane on the main surface of the III-V compound semiconductor single crystal can be measured using a conventionally known crystal orientation measuring device (for example, product name (product number): "2991G2" manufactured by Rigaku Corporation).

[0064] (Dislocation Density) When the III-V group compound semiconductor single crystal substrate is an InP substrate, the dislocation density of the main surface is 0 cm -2 More than 2000cm -2 The dislocation density of the main surface is preferably 0 cm -2 More than 1500cm -2 On the other hand, when the III-V group compound semiconductor single crystal substrate is a GaAs substrate, the dislocation density of the main surface is preferably 0 cm -2 More than 50cm -2 The dislocation density of the main surface is preferably 0 cm -2 30cm or more -2 It is more preferable that the dislocation density be less than or equal to 100 Å. This makes it possible to provide a III-V compound semiconductor single crystal substrate (InP substrate or GaAs substrate) having a reduced dislocation density across the entire main surface. Therefore, this embodiment can reduce the crack defect rate for a III-V compound semiconductor single crystal substrate having a reduced dislocation density across the entire main surface.

[0065] In particular, the dislocation density of the main surface can have a more preferable value depending on whether the III-V compound semiconductor single crystal substrate is an InP substrate or a GaAs substrate, the type of impurity atoms contained in the substrate, the diameter of the substrate, etc. For example, in the case of an InP substrate with a diameter of 50 mm containing tin as an impurity atom, the dislocation density of the main surface can be 1000 cm -2 It is more preferable that the thickness is 200 cm or less. -2 It is more preferable that:

[0066] In the case of an InP substrate having a diameter of 75 mm containing tin as an impurity atom, the dislocation density on the main surface is 2000 cm -2In the case of an InP substrate having a diameter of 75 mm containing sulfur as an impurity atom, the dislocation density of the main surface is more preferably 350 cm -2 In the case of an InP substrate having a diameter of 100 mm containing tin as an impurity atom, the dislocation density on the main surface is preferably 2000 cm -2 In the case of an InP substrate having a diameter of 100 mm containing sulfur as an impurity atom, the dislocation density of the main surface is more preferably 600 cm -2 In the case of an InP substrate having a diameter of 150 mm containing tin as an impurity atom, the dislocation density on the main surface is preferably 2000 cm -2 In the case of an InP substrate having a diameter of 150 mm containing sulfur as an impurity atom, the dislocation density of the main surface is more preferably 700 cm -2 More preferably, it is:

[0067] In the case of a GaAs substrate having a diameter of 75 mm and containing silicon as an impurity atom, the dislocation density on the main surface is 25 cm -2 In the case of a GaAs substrate having a diameter of 100 mm containing silicon as an impurity atom, the dislocation density on the main surface is more preferably 35 cm -2 In the case of a GaAs substrate having a diameter of 150 mm containing silicon as an impurity atom, the dislocation density on the main surface is more preferably 35 cm -2 In the case of a GaAs substrate having a diameter of 200 mm containing silicon as an impurity atom, the dislocation density on the main surface is more preferably 90 cm -2 More preferably, it is:

[0068] In this specification, "dislocations" and "dislocation density" on a main surface refer to "etch pits" and "etch pit density (hereinafter also referred to as "EPD")," respectively. "Etch pits" refer to corrosion pits formed on a surface of a III-V compound semiconductor single crystal substrate by treating the surface with a chemical. Specifically, when the III-V compound semiconductor single crystal substrate is an indium phosphide single crystal substrate, "etch pits" refer to corrosion pits formed on the main surface when the substrate is immersed for 1 to 5 minutes in a chemical solution at 25°C that contains hydrogen bromide and phosphoric acid in a hydrogen bromide:phosphoric acid ratio of 1:2 by mass. Furthermore, when the III-V compound semiconductor single crystal substrate is a gallium arsenide single crystal substrate, "etch pits" refer to corrosion pits formed on the main surface when the substrate is immersed for 45 minutes in molten potassium hydroxide at 600°C. In addition, when the main surface of a III-V compound semiconductor single crystal substrate is a polished surface, the polished surface of an indium phosphide single crystal substrate can be pretreated using reverse aqua regia before immersing the substrate in a chemical solution, for example. The polished surface of a gallium arsenide single crystal substrate can be pretreated using sulfuric acid and hydrogen peroxide, for example. This makes it possible to more clearly identify corrosion pits on the main surface. The corrosion pits appear as white dots when the main surface of a III-V compound semiconductor single crystal substrate is observed using an optical microscope or the like. Although etch pits are not academically synonymous with dislocations, they can be considered equivalent to dislocations in this technical field.

[0069] Hereinafter, a method for measuring etch pits formed on a main surface of a III-V compound semiconductor single crystal substrate and a method for calculating EPD will be described with reference to Fig. 5, taking as an example a case where the III-V compound semiconductor single crystal substrate is a GaAs substrate having a diameter of 150 mm. Fig. 5 is an explanatory diagram illustrating 69 measurement points set on the main surface of a III-V compound semiconductor single crystal substrate according to this embodiment for the purpose of determining the dislocation density of the main surface.

[0070] First, the main surface of a III-V compound semiconductor single crystal substrate (GaAs substrate) 100 is immersed in molten potassium hydroxide at 600°C for 45 minutes. A conventionally known method can be used for the immersion method. Then, the III-V compound semiconductor single crystal substrate 100 is taken out of the molten potassium hydroxide. Next, as shown in FIG. 5, 69 measurement points M (one measurement point M is 1 mm 2 A square having an area of ​​1 mm × 1 mm (i.e., a size of 1 mm × 1 mm) is set. The number of etch pits is measured at these 69 measurement points M at 100x magnification using a known optical microscope (for example, trade name: "ECLIPSE (registered trademark) LV150N" manufactured by Nikon Corporation). Finally, the number of etch pits measured at the 69 measurement points M is counted at 100x magnification. 2 This converts the value per area of ​​the etch pit to 1 cm 2 Since 69 values ​​per area are obtained, the average value of these 69 values ​​can be calculated as the EPD.

[0071] According to the above-described method, it is possible to measure the number of etch pits by associating one measurement point per field of view (1 mm × 1 mm in size). When III-V compound semiconductor single crystal substrate 100 is an InP substrate, the method of measuring etch pits formed on its main surface S and the method of calculating EPD can be the same as the method of measuring etch pits and the method of calculating EPD for a GaAs substrate described above, except that the main surface is immersed in the chemical solution of hydrogen bromide:phosphoric acid in a mass ratio of 1:2 at 25°C for 1 to 5 minutes.

[0072] 5, the 69 measurement points M are arranged in the following order from right to left in a direction perpendicular to an orientation flat OF provided on the upper portion. These measurement points M are spaced apart by an interval I of 15 mm. In other words, if the diameter of the III-V compound semiconductor single crystal substrate is 150 mm, it is possible to set 69 measurement points M within the plane of the main surface S by setting the interval I between one measurement point M and the other measurement point M most adjacent to that measurement point M to 15 mm.

[0073] When the diameter of the III-V compound semiconductor single crystal substrate is 50 mm, 69 measurement points M can be set within the plane of the main surface S by setting the interval I between one measurement point M and the other measurement point M nearest to that measurement point M to 5 mm. Similarly, when the diameter of the III-V compound semiconductor single crystal substrate is 75 mm, 69 measurement points M can be set within the plane of the main surface S by setting the interval I between one measurement point M and the other measurement point M nearest to that measurement point M to 7.5 mm. When the diameter of the III-V compound semiconductor single crystal substrate is 100 mm, 69 measurement points M can be set within the plane of the main surface S by setting the interval I between one measurement point M and the other measurement point M nearest to that measurement point M to 10 mm. When the diameter of the III-V compound semiconductor single crystal substrate is 200 mm, the measurement points M can be set at 69 locations within the plane of the main surface S by setting the interval I between one measurement point M and the other measurement point M most adjacent to that measurement point M to 20 mm.

[0074] (Dislocation Asymmetry) When the III-V compound semiconductor single crystal substrate is an InP substrate, the dislocation asymmetry in the main surface is preferably 1.8 or more, more preferably 2.0 or more. Furthermore, when the III-V compound semiconductor single crystal substrate is a GaAs substrate, the dislocation asymmetry is preferably 2.0 or more, more preferably 2.3 or more. The asymmetry is determined by dividing the main surface into a first region and a second region by an imaginary first line that intersects perpendicularly with an imaginary line extending in a direction from the wave source toward the center of the main surface and passes through the center of the main surface, and in each of the first region and the second region, two or more 1 mm apart dislocations are located at a pitch of 5 mm or more in a direction away from the center of the main surface on an imaginary second line that passes through the center of the main surface and intersects perpendicularly with the first line. 2 A square measurement point having an area of ​​1 cm is set, the number of dislocations is measured at the measurement point, and the number of dislocations is calculated from the measurement result. 2 The absolute value of the numerical value obtained by subtracting the average value of the converted values ​​obtained from all the measurement points in the second region from the average value of the converted values ​​obtained from all the measurement points in the first region is divided by the average value of the converted values ​​obtained from all the measurement points in the first region and the second region.

[0075] As used herein, "dislocation asymmetry" refers to an index that indicates the degree of difference between the number of dislocations present in a first region and a second region when the main surface is divided into the first region and the second region by a virtual first line that intersects perpendicularly with a virtual line extending from the wave source toward the center of the main surface and passes through the center of the main surface. The larger the "dislocation asymmetry," the more likely it is that the crack defect rate during slicing will be reduced, although the detailed reason is unknown. The "dislocation asymmetry" of the III-V compound semiconductor single crystal substrate according to this embodiment can exhibit a larger value than that of conventional III-V compound semiconductor single crystal substrates for the following reasons.

[0076] This is because, as described above, when the main surface of the III-V compound semiconductor single crystal substrate according to this embodiment is subjected to an optical etching treatment, a ripple-like pattern in which the wave source is not located on the main surface is visible on the main surface. On the other hand, when the main surface of a conventional III-V compound semiconductor single crystal substrate is subjected to an optical etching treatment, a ripple-like pattern in which the wave source is located at or near the center of the main surface is visible on the main surface. In this case, the ripple-like pattern in the conventional III-V compound semiconductor single crystal substrate corresponds to ripples spreading concentrically from a wave source located at or near the center of the main surface, as described above, and therefore the numbers of dislocations present in the first region and the second region are the same or similar, which is thought to result in a small "dislocation asymmetry." On the other hand, since the ripple pattern in the III-V compound semiconductor single crystal substrate according to this embodiment is a pattern of multiple consecutive arcs curved in the same direction as described above, the number of dislocations present in the first region and the second region is different, and therefore it is believed that the "degree of dislocation asymmetry" also becomes larger. Note that the larger the numerical value of the "degree of dislocation asymmetry," the more likely an orientation with low strain appears in the III-V compound semiconductor single crystal, and therefore it is believed that if the substrate is obtained by slicing the single crystal along that orientation, the crack defect rate can be further reduced.

[0077] In the III-V compound semiconductor single crystal substrate according to this embodiment, if the substrate is an InP substrate, the asymmetry of the dislocations can be 1.8 or more. In contrast, in conventional InP substrates, the asymmetry is usually less than 1.8. In the III-V compound semiconductor single crystal substrate according to this embodiment, if the substrate is a GaAs substrate, the asymmetry of the dislocations can be 2.0 or more. In contrast, in conventional GaAs substrates, the asymmetry is usually less than 2.0.

[0078] A method for calculating the "degree of asymmetry of dislocations" present on the main surface will now be described in detail with reference to Fig. 6. Fig. 6 is an explanatory diagram for explaining a method for determining the degree of asymmetry of dislocations present on the main surface of a III-V compound semiconductor single crystal substrate according to this embodiment by utilizing the ripple pattern shown in Fig. 1 and the 69 measurement points shown in Fig. 5.

[0079] First, the main surface S of the III-V compound semiconductor single crystal substrate 100 is subjected to the above-described light-based etching process, thereby forming a ripple-like pattern P on the main surface S. After identifying the position of a wave source from the ripple-like pattern P, an imaginary line extending from the wave source toward the center of the main surface S is set on the main surface S. Next, the position on the main surface S of an imaginary first line L1 that intersects the imaginary line perpendicularly to the imaginary line and passes through the center of the main surface is identified. Furthermore, the position of the imaginary first line L1 is recorded on the main surface S by, for example, removing a portion of the periphery of the III-V compound semiconductor single crystal substrate 100 or marking the main surface S. Thereafter, the main surface S is polished to remove the ripple-like pattern from the main surface S.

[0080] Next, 69 measurement points M are set on the main surface S in the same manner as in the dislocation density measurement method described above. Furthermore, the main surface S is divided into a first region R1 and a second region R2 based on an imaginary first straight line L1 recorded on the main surface S. Next, an imaginary second straight line L2 is set that passes through the center of the main surface S and intersects the first straight line L1 perpendicularly, and measurement points M that overlap with this second straight line L2 are selected in each of the first region R1 and the second region R2.

[0081] Next, the number of dislocations (etch pits) is measured at measurement points M selected in each of the first region R1 and the second region R2, and the number of dislocations is calculated per cm from the measurement results. 2The average value of the converted values ​​obtained from all of the measurement points M selected in the second region R2 is then subtracted from the average value of the converted values ​​obtained from all of the measurement points M selected in the first region R1. Finally, the absolute value of the numerical value obtained by the subtraction is divided by the average value of the converted values ​​obtained from all of the measurement points M selected in the first region R1 and the second region R2. The "degree of dislocation asymmetry" can be determined by the above method.

[0082] Here, if the imaginary second line L2 and measurement point M do not overlap at two or more locations in each of the first region R1 and the second region R2, it may be impossible to calculate the average value of the converted values ​​used to determine the "degree of dislocation asymmetry." In such cases, the measurement point M closest to the imaginary second line L2 and the measurement point M next closest to the imaginary second line L2 in each of the first region R1 and the second region R2 are regarded as measurement points M overlapping with the second line L2, and the number of dislocations at these measurement points M is measured, thereby making it possible to calculate the average value of the converted values, etc. Furthermore, if the diameter of the III-V compound semiconductor single crystal substrate 100 is 50 mm, the interval I between one measurement point M and the other measurement point M closest to that measurement point M is 5 mm. Therefore, if the diameter of the III-V compound semiconductor single crystal substrate 100 for which the "degree of dislocation asymmetry" is to be determined is 50 mm or greater, the interval I (pitch) between the measurement points M overlapping with the imaginary second line L2 will always be 5 mm or greater.

[0083] <Conductivity Type> The III-V compound semiconductor single crystal substrate according to this embodiment can be imparted with electron-withdrawing (n-type) conductivity by adding impurity atoms to the seed crystal that serves as the raw material. That is, the conductivity type of the III-V compound semiconductor single crystal substrate is preferably n-type. In particular, the III-V compound semiconductor single crystal substrate preferably contains tin or sulfur as an impurity atom when it is an indium phosphide single crystal substrate, and silicon when it is a gallium arsenide single crystal substrate. This makes it possible to reduce the crack defect rate during slicing in a III-V compound semiconductor single crystal substrate with n-type conductivity.

[0084] For example, an InP substrate may contain both or either of S (sulfur) atoms and Sn (tin) atoms to impart n-type conductivity. A conductive InP substrate containing both or either of S (sulfur) atoms and Sn (tin) atoms can have a resistivity of 1 Ω cm or less. A GaAs substrate may contain Si (silicon) atoms to impart n-type conductivity.

[0085] The atomic concentration of the impurity atoms (S, Sn or Si) is 1×10 16 cm -3 1x10 or more 19 cm -3 The atomic concentration of the impurity atoms is preferably 1×10 or less. 18 cm -3 1x10 or more 19 cm -3 It is more preferable that the atomic concentration of the impurity atoms is not more than 10 ...

[0086] The impurity atoms preferably exhibit a concentration distribution that changes uniformly in the direction from the wave source toward the center of the main surface in the III-V compound semiconductor single crystal substrate. Specifically, in a III-V compound semiconductor single crystal substrate 100 having a wave source O outside the main surface S and a pattern of multiple arcs curved in the same direction (ripple-like pattern P) as shown in Figure 1, the impurity atoms can exhibit a concentration distribution that changes uniformly in the direction from the wave source O toward the center of the main surface S. It is more preferable that the impurity atoms exhibit a concentration distribution that increases uniformly in the direction from the wave source O toward the center of the main surface S in the III-V compound semiconductor single crystal substrate 100. In this case, when the strain (residual strain) caused by the impurity atoms generated in the III-V compound semiconductor single crystal substrate 100 is expressed in polar coordinates with the center of the main surface S as the origin, the residual strain does not exhibit a distribution with n-fold symmetry (where n is an integer of 2 or more) about the origin, but simply exhibits a distribution with one-fold symmetry (see FIG. 3), and therefore the stress of the residual strain is easily released on the substrate. As a result, the stress of the residual strain does not need to be released during slicing or the like, and the cracking defect rate of the substrate can be reduced.

[0087] Specifically, the concentration distribution of the impurity atoms can be determined by the following method. First, a III-V compound semiconductor single crystal substrate is cleaved along the (100) plane at positions on the main surface where an imaginary line passing through the center of the main surface and extending in a direction from the wave source toward the center of the main surface overlaps with the periphery closer to the wave source than the center of the main surface, the center of the main surface, and the periphery opposite the wave source than the center of the main surface. This typically prepares a measurement sample having a square surface with sides measuring 10 mm and a thickness of 300 to 1000 μm, and the GDMS described above is performed using the measurement sample. This makes it possible to determine the concentration distribution of the impurity atoms in the III-V compound semiconductor single crystal substrate in a direction from the wave source toward the center of the main surface.

[0088] [Method for Manufacturing a Group III-V Compound Semiconductor Single Crystal Substrate] The method for manufacturing a Group III-V compound semiconductor single crystal substrate according to this embodiment is preferably, for example, the following manufacturing method. That is, the manufacturing method is a method for manufacturing a Group III-V compound semiconductor single crystal substrate using a crystal growth apparatus, and includes a first step of contacting a seed crystal with a source melt and growing a crystalline solid on the source melt side of the seed crystal to obtain a Group III-V compound semiconductor single crystal, and a second step of slicing the Group III-V compound semiconductor single crystal to obtain a Group III-V compound semiconductor single crystal substrate having a circular main surface. The crystal growth apparatus includes at least a cylindrical crucible and a heating element for heating the crucible. The seed crystal is accommodated in the bottom of the crucible, and the source melt is accommodated in the crucible above the seed crystal. The interface between the crystalline solid and the source melt forms an intersecting angle of less than 90° with respect to the axis of the crucible.

[0089] The present inventors have discovered that when growing a III-V compound semiconductor single crystal, which is a raw material for a III-V compound semiconductor single crystal substrate, in the crucible of a crystal growth apparatus using the VB method, the interface between the crystalline solid grown on the seed crystal's side toward the raw material melt and the raw material melt has an intersecting angle of less than 90° with the axis of the crucible, rather than being horizontal as in the conventional case, by devising the structure of a heating element, for example, as described below. In this case, the present inventors have discovered that the rate of crack defects when slicing the grown III-V compound semiconductor single crystal to obtain III-V compound semiconductor single crystal substrates is reduced compared to the conventional case.

[0090] As used herein, the term "failure rate due to cracking" refers to the rate at which III-V compound semiconductor single crystal substrates break during a series of steps in the manufacture of III-V compound semiconductor single crystal substrates. Specifically, the term refers to the rate at which cracks, chips, and other crack defects occur during a series of steps in which a III-V compound semiconductor single crystal is grown, its periphery is ground, an OF or notch is formed, and the substrate is sliced ​​to the desired thickness to obtain a III-V compound semiconductor single crystal substrate precursor, and the periphery of the III-V compound semiconductor single crystal substrate precursor is ground, the back surface is etched, the front surface is polished, and the substrate is washed and dried to obtain a III-V compound semiconductor single crystal substrate. Meanwhile, as used herein, the term "slicing yield" refers to the rate at which good III-V compound semiconductor single crystal substrates are obtained without the aforementioned crack defects.

[0091] Hereinafter, with reference to FIG. 7 , an example of a method for producing a III-V compound semiconductor single crystal substrate according to this embodiment, which employs a so-called VB method using a crucible, such as the vertical Bridgman method or the vertical temperature gradient freezing method, which are included in the vertical boat method, will be described. The method for producing a III-V compound semiconductor single crystal substrate according to this embodiment includes a seed crystal loading step, a raw material loading step, a sealant placement step, a crystal growth step as a first step, and a cutting and periphery grinding step as a second step, in this order. When carrying out this manufacturing method, for example, a crystal growth apparatus equipped with a crucible 1 and a heating element 2 shown in FIG. 7 can be used. FIG. 7 is a schematic diagram illustrating a crystal growth apparatus for growing a III-V compound semiconductor single crystal, which is the raw material for the III-V compound semiconductor single crystal substrate according to this embodiment.

[0092] In the crystal growth apparatus, the crucible 1 is cylindrical and includes a seed crystal holding portion and a crystal growth portion connected to the seed crystal holding portion. The crystal growth portion further includes a conical portion and a barrel portion. The seed crystal holding portion is a cylindrical region having a cylindrical cavity that opens on the side connected to the crystal growth portion and has a bottom wall formed on the opposite side. The seed crystal holding portion can hold a seed crystal 31 in the cavity. The conical portion of the crystal growth portion has a conical shape and is connected to the seed crystal holding portion on its small diameter side. The barrel portion has a hollow cylindrical shape and is connected to the large diameter side of the conical portion. The crystal growth portion of the crucible 1 has the function of holding a solid III-V compound semiconductor raw material therein. Furthermore, the crystal growth portion of the crucible 1 has the function of solidifying a raw material melt 33, which is a raw material that has been heated to a molten state, to grow a III-V compound semiconductor single crystal as a crystalline solid 32. Various materials that can withstand the temperature at which the III-V compound semiconductor raw material melts can be used for the crucible 1. For example, pyrolytic boron nitride (pBN) is conveniently used as the material for the crucible 1. The crystal growth apparatus can further include a crucible holder 4 that holds the crucible 1. For example, silicon carbide can be used as the material for the crucible holder 4.

[0093] In the crystal growth apparatus, two heating elements 2 are arranged to surround the outer periphery of a cylindrical crucible 1. Furthermore, each heating element 2 is divided into multiple sections perpendicular to the axis of the crucible, resulting in a multi-stage configuration. This allows the output of each heating element 2 to be controlled independently for each element and for each section. For example, the output of the heating element 2 can be easily gradually decreased upward along the axis of the crucible 1. Furthermore, by gradually decreasing the output of the heating element 2 upward along the axis of the crucible 1, the interface between the crystalline solid to be grown on the source melt side of the seed crystal and the source melt can be made to have an intersection angle of less than 90° with respect to the axis of the crucible 1. Hereinafter, with reference to FIG. 8 , the steps of the above-described manufacturing method will be described in detail, with reference to FIG. 8 , for manufacturing an InP substrate and a GaAs substrate as a III-V compound semiconductor single crystal substrate. FIG. 8 is a flowchart illustrating an example of a method for manufacturing a III-V compound semiconductor single crystal substrate according to this embodiment.

[0094] <InP Substrate Manufacturing Method> (Seed Crystal Loading Step S10) In the InP substrate manufacturing method, the seed crystal loading step S10 is first performed. In the seed crystal loading step S10, a seed crystal 31 (InP seed crystal) is loaded into the hollow portion of the seed crystal holding portion of the crucible 1. A conventionally known method can be used as the method for loading the seed crystal 31 into the seed crystal holding portion. Here, the cross-sectional area of ​​the seed crystal 31 is preferably 15% or more, more preferably 50% or more, of the cross-sectional area of ​​the straight body portion of the crucible 1. The average dislocation density of the seed crystal 31 is 5000 cm -2 Preferably, it is 2000 cm -2 It is also preferable to add a small amount of impurity atoms (S, Sn) to the seed crystal 31. Furthermore, the inclination angle of the conical portion of the crucible 1 to the cylindrical portion is preferably 40° or less, and more preferably 20° or less.

[0095] (Raw Material Charging Step S20) Next, the raw material charging step S20 is carried out. In the raw material charging step S20, a plurality of lumps made of polycrystalline III-V compound semiconductor raw material (InP polycrystalline) are charged into the crystal growth section (conical section and cylindrical section) in the crucible 1 and stacked. Furthermore, in this step, a predetermined amount of impurity atoms (S, Sn) can be added.

[0096] (Sealant Arranging Step S30) Next, the sealant arranging step S30 is performed. In the sealant arranging step S30, a sealant conventionally known in the VB method (for example, a solid sealant made of B2O3 (boron oxide)) is arranged on the above-mentioned mass.

[0097] (Crystal Growth Step S40: First Step) Next, the first step, the crystal growth step S40, is performed. That is, in the first step, a seed crystal 31 is brought into contact with a raw material melt 33 to grow a crystalline solid 32 on the raw material melt 33 side of the seed crystal 31 for the purpose of obtaining a III-V compound semiconductor single crystal (InP single crystal). Specifically, a crucible 1 containing the seed crystal 31, a lump of raw material for the III-V compound semiconductor single crystal, and a solid sealant is loaded into a crucible holder 4 of a crystal growth apparatus. Thereafter, an electric current is supplied to the heating element 2 to heat the crucible 1. As a result, the solid sealant melts to form a liquid sealant 5, and the lump of raw material melts to form a raw material melt 33. Next, a portion of the seed crystal 31 also melts and comes into contact with the raw material melt 33 at the interface. Furthermore, by gradually lowering the crucible 1 downward (toward the seed crystal holder) along its axis relative to the heating element 2, a temperature gradient is formed in the crucible 1 such that the temperature on the seed crystal 31 side is lower and the temperature on the raw material melt 33 side is higher, causing the raw material melt 33 in contact with the seed crystal 31 to solidify and growing a crystalline solid 32 on the raw material melt 33 side of the seed crystal 31. The speed at which the crucible 1 is lowered along its axis is preferably 10 mm / hour or less, and more preferably 5 mm / hour or less. Furthermore, when the crucible 1 is lowered along its axis, it is preferable to rotate the crucible 1 around its axis at about 5 rpm.

[0098] Here, as described above, two heating elements 2 (one set) are arranged on each half circumference of the crucible 1 so as to cover the outer periphery of the crucible 1. Furthermore, the output of the heating elements 2 is controlled so as to gradually decrease upward along the axis of the crucible 1. As a result, in the first step, when the crystalline solid 32 is grown on the raw material melt 33 side of the seed crystal 31, the interface 3a between the crystalline solid 32 and the raw material melt 33 is not horizontal, but has an intersection angle of less than 90° with the axis of the crucible 1. For example, the interface 3a preferably has an intersection angle of 10 to 70° with the axis of the crucible 1.

[0099] In the first step, the crucible 1 is subsequently pulled downward along its axis relative to the heating element 2, and the non-horizontal interface 3a between the crystalline solid 32 and the raw material melt 33 is raised toward the liquid sealant 5, thereby solidifying the raw material melt 33 and allowing the crystalline solid 32 to grow upward along the axis of the crucible 1. The growth of the crystalline solid 32 continues until the solidification of the raw material melt 33 remaining in the crystal growth portion of the crucible 1 is completed. In this way, a III-V compound semiconductor single crystal (InP single crystal) made of the crystalline solid 32 can be obtained.

[0100] (Cutting Step and Periphery Grinding Step S50: Second Step) The cutting step is a step of obtaining a III-V compound semiconductor substrate precursor by cutting out the III-V compound semiconductor crystal (InP single crystal) removed from the crucible 1. Furthermore, the periphery grinding step is a step of obtaining a III-V compound semiconductor substrate (InP substrate) having a circular main surface by grinding the periphery of the III-V compound semiconductor substrate precursor. That is, the cutting step and periphery grinding step S50 (second step) is a step of slicing the InP single crystal. The cutting step and periphery grinding step S50 can be performed by using a conventionally known cutting method and periphery grinding method, respectively, in a method for manufacturing an InP substrate using the VB method.

[0101] <Method for Manufacturing GaAs Substrate> (Seed Crystal Loading Step S10) In the method for manufacturing a GaAs substrate, first, a seed crystal loading step S10 is performed. In the seed crystal loading step S10, a seed crystal 31 (GaAs seed crystal) is loaded into a cavity of a seed crystal holding portion of the crucible 1. The seed crystal 31 can be loaded into the seed crystal holding portion by a conventionally known method.

[0102] (Raw Material Charging Step S20) Next, the raw material charging step S20 is carried out. In the raw material charging step S20, a plurality of lumps made of polycrystalline III-V compound semiconductor raw material (GaAs polycrystalline) are charged into the crystal growth section (conical section and cylindrical section) in the crucible 1 and stacked. Furthermore, in this step, a predetermined amount of impurity atoms (Si) can be added.

[0103] (Sealant Arranging Step S30) Next, the sealant arranging step S30 is performed. In the sealant arranging step S30, a sealant conventionally known in the VB method (for example, a solid sealant made of B2O3 (boron oxide)) is arranged on the above-mentioned mass.

[0104] (Crystal Growth Step S40: First Step) Next, the first step, the crystal growth step S40, is performed. That is, in the first step, a seed crystal 31 is brought into contact with a raw material melt 33 to grow a crystalline solid 32 on the raw material melt 33 side of the seed crystal 31 for the purpose of obtaining a III-V compound semiconductor single crystal (GaAs single crystal). Specifically, a crucible 1 containing the seed crystal 31, a lump of raw material for the III-V compound semiconductor single crystal, and a solid sealant is loaded into a crucible holder 4 of a crystal growth apparatus. Thereafter, an electric current is supplied to the heating element 2 to heat the crucible 1. As a result, the solid sealant melts to form a liquid sealant 5, and the lump of raw material melts to form a raw material melt 33. Next, a portion of the seed crystal 31 also melts and comes into contact with the raw material melt 33 at the interface. Furthermore, by gradually lowering the crucible 1 downward (toward the seed crystal holder) along its axis relative to the heating element 2, a temperature gradient is formed in the crucible 1 such that the temperature on the seed crystal 31 side is lower and the temperature on the raw material melt 33 side is higher, causing the raw material melt 33 in contact with the seed crystal 31 to solidify, and growing a crystalline solid 32 on the raw material melt 33 side of the seed crystal 31. The speed at which the crucible 1 is lowered along its axis is not particularly limited, but can be, for example, 2 to 10 mm / hour.

[0105] As described above, two heating elements 2 (one set) are arranged at every half circumference so as to cover the outer periphery of the crucible 1. Furthermore, the output of the heating elements 2 is controlled so as to gradually decrease upward along the axis of the crucible 1. As a result, in the first step, when the crystalline solid 32 is grown on the raw material melt 33 side of the seed crystal 31, the interface 3a between the crystalline solid 32 and the raw material melt 33 is not horizontal, but has an intersection angle of less than 90° with the axis of the crucible 1. For example, the interface 3a preferably has an intersection angle of 10 to 70° with the axis of the crucible 1.

[0106] In the first step, the crucible 1 is subsequently pulled downward along its axis relative to the heating element 2, and the non-horizontal interface 3a between the crystalline solid 32 and the raw material melt 33 is raised toward the liquid sealant 5, thereby solidifying the raw material melt 33 and allowing the crystalline solid 32 to grow upward along the axis of the crucible 1. The growth of the crystalline solid 32 continues until the solidification of the raw material melt 33 remaining in the crystal growth portion of the crucible 1 is completed. In this way, a III-V compound semiconductor single crystal (GaAs single crystal) made of the crystalline solid 32 can be obtained.

[0107] (Cutting Step and Outer Edge Grinding Step S50: Second Step) The cutting step is a step of obtaining a III-V compound semiconductor substrate precursor by cutting out the III-V compound semiconductor crystal (GaAs single crystal) removed from the crucible 1. Furthermore, the outer edge grinding step is a step of grinding the outer edge of the III-V compound semiconductor substrate precursor to obtain a III-V compound semiconductor substrate (GaAs substrate) having a circular main surface. That is, the cutting step and outer edge grinding step S50 (second step) is a step of slicing the GaAs single crystal. The cutting step and outer edge grinding step S50 can be performed by using a conventionally known cutting method and outer edge grinding method, respectively, in a method for manufacturing a GaAs substrate using the VB method.

[0108] <Effects> By performing the above steps, a III-V compound semiconductor single crystal substrate having a circular main surface can be manufactured. In the method for manufacturing a III-V compound semiconductor single crystal substrate according to this embodiment, particularly in the first step, the crystalline solid 32 is grown on the source melt 33 side of the seed crystal 31 so that the interface 3 a between the crystalline solid 32 and the source melt 33 forms an intersecting angle of less than 90° with respect to the axis of the crucible 1. This reduces the crack defect rate of the III-V compound semiconductor single crystal substrate during slicing in the second step. Therefore, the above manufacturing method can provide a III-V compound semiconductor single crystal substrate with a reduced crack defect rate.

[0109] In the above manufacturing method, the growth direction of the III-V compound semiconductor single crystal (crystalline solid 32) is preferably the <100> direction. Furthermore, the III-V compound semiconductor single crystal substrate according to this embodiment is preferably obtained by slicing a III-V compound semiconductor single crystal so that the {100} just plane is the main surface. Furthermore, the above-mentioned III-V compound semiconductor single crystal substrate, whose main surface has an off-angle of more than 0° and not more than 15° from the {100} plane, can be obtained by performing tilt slicing using a conventionally known method from a III-V compound semiconductor single crystal whose growth direction is the <100> direction.

[0110] The present disclosure will be described in more detail below with reference to examples, but the present disclosure is not limited thereto. In the examples described below, a crystal growth apparatus shown in FIG. 7 was used to grow III-V compound semiconductor single crystals using the VB method with the <100> direction as the growth direction, resulting in InP substrates (Examples 1 to 8) whose main surfaces were oriented in the (100) just plane and GaAs substrates (Examples 11 to 17) whose main surfaces were oriented at an off-angle of 0 to 15° from the (100) plane. In the comparative examples described below, on the other hand, a conventional crystal growth apparatus equipped with a heating element arranged to cover the entire periphery of the crucible was used to grow III-V compound semiconductor crystals (InP substrates and GaAs substrates). In each example and comparative example, 1,000 InP substrates or GaAs substrates were produced.

[0111] <<First Test>> [Manufacturing of III-V Compound Semiconductor Single Crystal Substrate] <Example 1: InP Substrate> (Seed Crystal Loading Step S10) A seed crystal 31 made of InP manufactured by a conventionally known method was loaded into a cavity in a seed crystal holding portion of a crucible 1 provided in a crystal growth apparatus by using a conventionally known method. A trace amount of tin (Sn) was added to the seed crystal 31 as an impurity element. The cross-sectional area of ​​the seed crystal 31 was set to 50% of the cross-sectional area of ​​the straight body portion of the crucible 1. Furthermore, the inclination angle of the conical portion of the crucible 1 leading to the straight body portion was set to 20°.

[0112] (Raw material loading step S20 and sealant placement step S30) Multiple blocks of polycrystalline InP were loaded into the crystal growth section of the crucible 1 and stacked. A predetermined amount of tin (Sn) was also added. Furthermore, a solid sealant made of BO was placed on top of the raw material blocks. The inner diameter of the crystal growth section of the crucible 1 used in this example was 60 mm.

[0113] (Crystal growth step S40: first step) An electric current was supplied to the heating element 2 to heat the crucible 1, thereby converting the solid sealant into a liquid sealant 5 and converting the mass in the crucible 1 into a raw material melt 33. Furthermore, a part of the seed crystal 31 and the mass located at the interface with the seed crystal 31 also became the raw material melt 33, and these were brought into contact with each other. Next, the crucible 1 was pulled downward (toward the seed crystal holder) along its axis relative to the heating element 2, thereby growing a crystalline solid 32 on the raw material melt 33 side of the seed crystal 31.

[0114] As described above, two heating elements 2 were arranged to surround the outer periphery of the cylindrical crucible 1. Furthermore, each heating element 2 was divided into a plurality of sections perpendicular to the axis of the crucible 1, resulting in a multi-stage configuration. With this configuration, the output of the heating element 2 was gradually reduced upward along the axis of the crucible 1. As a result, in the first step, the interface 3a between the crystalline solid 32 and the raw material melt 33 had an intersection angle of 30° with the axis of the crucible 1.

[0115] Subsequently, the heating element 2 was pulled downward along the axis of the crucible 1, and the interface 3a between the crystalline solid 32 and the raw material melt 33 was raised upward along the axis of the crucible 1, causing the crystalline solid 32 to grow upward along the axis of the crucible 1. This was continued until solidification of the raw material melt 33 remaining in the crystal growth portion of the crucible 1 was completed. In this way, an InP single crystal was produced in the crucible 1. Thereafter, the InP single crystal was removed from the crucible 1 using a conventionally known method.

[0116] (Cutting step and outer periphery grinding step S50: second step) Using a conventionally known cutting method and outer periphery grinding method, an InP substrate precursor was obtained by cutting the InP single crystal removed from the crucible 1, and the outer periphery of the InP substrate precursor was further ground to produce an InP substrate having a circular main surface. As a result, an InP substrate having a diameter of 50 mm and a thickness of 350 μm was obtained as Example 1.

[0117] Example 2 InP Substrate An InP substrate having a diameter of 50 mm and a thickness of 350 μm was obtained by using the same method as in Example 1, except that a seed crystal 31 to which a trace amount of sulfur (S) was added was prepared in the seed crystal loading step. In the crystal growth step (first step) of Example 2, the interface 3 a between the crystalline solid 32 grown in the crucible 1 and the raw material melt 33 had an intersecting angle of 30° with respect to the axis of the crucible 1.

[0118] Example 3 InP Substrate An InP substrate having a diameter of 75 mm and a thickness of 600 μm was obtained by using the same method as in Example 1, except that the inner diameter of the crystal growth portion of the crucible 1 in the crystal growth apparatus was set to 85 mm. In the crystal growth step (first step) of Example 3, the interface 3 a between the crystalline solid 32 grown in the crucible 1 and the raw material melt 33 had an intersecting angle of 30° with respect to the axis of the crucible 1.

[0119] Example 4 InP Substrate An InP substrate having a diameter of 75 mm and a thickness of 600 μm was obtained by using the same method as in Example 2, except that the inner diameter of the crystal growth portion of the crucible 1 in the crystal growth apparatus was set to 85 mm. In the crystal growth step (first step) of Example 4, the interface 3 a between the crystalline solid 32 grown in the crucible 1 and the raw material melt 33 had an intersecting angle of 30° with respect to the axis of the crucible 1.

[0120] Example 5 InP Substrate An InP substrate having a diameter of 100 mm and a thickness of 625 μm was obtained by using the same method as in Example 1, except that the inner diameter of the crystal growth portion of the crucible 1 in the crystal growth apparatus was set to 110 mm. In the crystal growth step (first step) of Example 5, the interface 3 a between the crystalline solid 32 grown in the crucible 1 and the raw material melt 33 had an intersecting angle of 30° with respect to the axis of the crucible 1.

[0121] Example 6 InP Substrate An InP substrate having a diameter of 100 mm and a thickness of 625 μm was obtained by using the same method as in Example 2, except that the inner diameter of the crystal growth portion of the crucible 1 in the crystal growth apparatus was set to 110 mm. In the crystal growth step (first step) of Example 6, the interface 3 a between the crystalline solid 32 grown in the crucible 1 and the raw material melt 33 had an intersecting angle of 30° with respect to the axis of the crucible 1.

[0122] Example 7 InP Substrate An InP substrate having a diameter of 150 mm and a thickness of 675 μm was obtained by using the same method as in Example 1, except that the inner diameter of the crystal growth portion of the crucible 1 in the crystal growth apparatus was set to 160 mm. In the crystal growth step (first step) of Example 7, the interface 3 a between the crystalline solid 32 grown in the crucible 1 and the raw material melt 33 had an intersecting angle of 30° with respect to the axis of the crucible 1.

[0123] Example 8 InP Substrate An InP substrate having a diameter of 150 mm and a thickness of 675 μm was obtained by using the same method as in Example 2, except that the inner diameter of the crystal growth portion of the crucible 1 in the crystal growth apparatus was set to 160 mm. In the crystal growth step (first step) of Example 8, the interface 3 a between the crystalline solid 32 grown in the crucible 1 and the raw material melt 33 had an intersecting angle of 30° with respect to the axis of the crucible 1.

[0124] Comparative Example 1: InP Substrate Using a conventional crystal growth apparatus, an InP substrate having a diameter of 50 mm and a thickness of 350 μm was obtained by the same method as in Example 1, except that in the crystal growth step (first step), interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 was set to have an intersecting angle of 90° with the axis of crucible 1 (i.e., horizontal).

[0125] Comparative Example 2: InP Substrate Using a conventional crystal growth apparatus, an InP substrate having a diameter of 50 mm and a thickness of 350 μm was obtained by the same method as in Example 2, except that in the crystal growth step (first step), interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 was set to have an intersecting angle of 90° with the axis of crucible 1 (i.e., horizontal).

[0126] Comparative Example 3: InP Substrate An InP substrate having a diameter of 75 mm and a thickness of 600 μm was obtained using the same method as in Comparative Example 1, except that the inner diameter of the crystal growth portion of the crucible 1 of the crystal growth apparatus was set to 85 mm.

[0127] Comparative Example 4: InP Substrate An InP substrate having a diameter of 75 mm and a thickness of 600 μm was obtained by the same method as in Comparative Example 2, except that the inner diameter of the crystal growth portion of the crucible 1 of the crystal growth apparatus was set to 85 mm.

[0128] Comparative Example 5: InP Substrate An InP substrate having a diameter of 100 mm and a thickness of 625 μm was obtained using the same method as in Comparative Example 1, except that the inner diameter of the crystal growth portion of the crucible 1 of the crystal growth apparatus was set to 110 mm.

[0129] Comparative Example 6: InP Substrate An InP substrate having a diameter of 100 mm and a thickness of 625 μm was obtained using the same method as in Comparative Example 2, except that the inner diameter of the crystal growth portion of the crucible 1 of the crystal growth apparatus was set to 110 mm.

[0130] Comparative Example 7: InP substrate An InP substrate having a diameter of 150 mm and a thickness of 675 μm was obtained by the same method as in Comparative Example 1, except that the inner diameter of the crystal growth portion of the crucible 1 of the crystal growth apparatus was set to 160 mm.

[0131] Comparative Example 8: InP Substrate An InP substrate having a diameter of 150 mm and a thickness of 675 μm was obtained using the same method as in Comparative Example 2, except that the inner diameter of the crystal growth portion of the crucible 1 of the crystal growth apparatus was set to 160 mm.

[0132] Example 11 GaAs Substrate (Seed Crystal Loading Step S10) A seed crystal 31 made of GaAs manufactured by a conventionally known method was loaded into a cavity in a seed crystal holding portion of a crucible 1 provided in a crystal growth apparatus by using a conventionally known method. A trace amount of silicon (Si) was added to the seed crystal 31 as an impurity element.

[0133] (Raw material loading step S20 and plugging material placement step S30) Multiple blocks of polycrystalline GaAs were loaded into the crystal growth section of the crucible 1 and stacked. A predetermined amount of Si was also added. Furthermore, a solid plug made of BO was placed on top of the raw material blocks. The inner diameter of the crystal growth section of the crucible 1 used in this example was 80 mm.

[0134] (Crystal growth step S40: first step) An electric current was supplied to the heating element 2 to heat the crucible 1, thereby converting the solid sealant into a liquid sealant 5 and converting the mass in the crucible 1 into a raw material melt 33. Furthermore, a part of the seed crystal 31 and the mass located at the interface with the seed crystal 31 also became the raw material melt 33, and these were brought into contact with each other. Next, the crucible 1 was pulled downward (toward the seed crystal holder) along its axis relative to the heating element 2, thereby growing a crystalline solid 32 on the raw material melt 33 side of the seed crystal 31.

[0135] As described above, two heating elements 2 were arranged to surround the outer periphery of the cylindrical crucible 1. Furthermore, each heating element 2 was divided into a plurality of sections perpendicular to the axis of the crucible 1, resulting in a multi-stage configuration. With this configuration, the output of the heating element 2 was gradually reduced upward along the axis of the crucible 1. As a result, in the first step, the interface 3a between the crystalline solid 32 and the raw material melt 33 had an intersection angle of 30° with the axis of the crucible 1.

[0136] Subsequently, the heating element 2 was pulled downward along the axis of the crucible 1, and the interface 3a between the crystalline solid 32 and the raw material melt 33 was raised upward along the axis of the crucible 1, causing the crystalline solid 32 to grow upward along the axis of the crucible 1. This was continued until solidification of the raw material melt 33 remaining in the crystal growth portion of the crucible 1 was completed. In this manner, a GaAs single crystal was produced in the crucible 1. The GaAs single crystal was then removed from the crucible 1 using a conventionally known method.

[0137] (Cutting step and outer periphery grinding step S50: second step) Using a conventionally known cutting method and outer periphery grinding method, the GaAs anticrystal removed from the crucible 1 was sliced ​​using a known slicing method so that the main surfaces had the (100) just plane, thereby obtaining a GaAs substrate precursor. Further, the outer periphery of the GaAs substrate precursor was ground to produce a GaAs substrate having a circular main surface. As a result, a GaAs substrate having a diameter of 75 mm and a thickness of 600 μm was obtained as Example 11.

[0138] Example 12 GaAs Substrate A GaAs substrate having a diameter of 75 mm and a thickness of 600 μm was obtained by the same method as in Example 11, except that in the cutting step and outer periphery grinding step (second step), the GaAs single crystal removed from the crucible 1 was cut so that the main surface had a 10° off-angle from the (100) plane to obtain a GaAs substrate precursor. In the crystal growth step (first step) of Example 12, the interface 3 a between the crystalline solid 32 grown in the crucible 1 and the raw material melt 33 had an intersecting angle of 30° with respect to the axis of the crucible 1.

[0139] Example 13 GaAs Substrate A GaAs substrate having a diameter of 100 mm and a thickness of 625 μm was obtained by using the same method as in Example 11, except that the inner diameter of the crystal growth section of the crucible 1 in the crystal growth apparatus was set to 110 mm. In the crystal growth step (first step) of Example 13, the interface 3 a between the crystalline solid 32 grown in the crucible 1 and the raw material melt 33 had an intersecting angle of 30° with respect to the axis of the crucible 1.

[0140] Example 14 GaAs Substrate A GaAs substrate having a diameter of 150 mm and a thickness of 760 μm was obtained using the same method as in Example 11, except that the inner diameter of the crystal growth section of crucible 1 in the crystal growth apparatus was set to 160 mm, and that in the cutting step and outer periphery grinding step S50, the GaAs single crystal removed from crucible 1 was cut so that its main surface had an off-angle of 2° from the (100) plane. In the crystal growth step (first step) of Example 14, interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 had an intersecting angle of 30° with respect to the axis of crucible 1.

[0141] Example 15 GaAs Substrate A GaAs substrate having a diameter of 150 mm and a thickness of 760 μm was obtained using the same method as in Example 11, except that the inner diameter of the crystal growth section of crucible 1 in the crystal growth apparatus was set to 160 mm, and that in the cutting step and outer periphery grinding step S50, the GaAs single crystal removed from crucible 1 was cut so that its main surface had an off-angle of 6° from the (100) plane. In the crystal growth step (first step) of Example 15, interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 had an intersecting angle of 30° with respect to the axis of crucible 1.

[0142] Example 16 GaAs Substrate A GaAs substrate having a diameter of 150 mm and a thickness of 760 μm was obtained by the same method as in Example 11, except that the inner diameter of the crystal growth section of crucible 1 in the crystal growth apparatus was set to 160 mm, and that in the cutting step and outer periphery grinding step S50, the GaAs single crystal removed from crucible 1 was cut so that its main surface had an off-angle of 15° from the (100) plane. In the crystal growth step (first step) of Example 16, interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 had an intersecting angle of 30° with respect to the axis of crucible 1.

[0143] Example 17 GaAs Substrate A GaAs substrate having a diameter of 200 mm and a thickness of 675 μm was obtained using the same method as in Example 11, except that the inner diameter of the crystal growth section of crucible 1 in the crystal growth apparatus was set to 210 mm, and that in the cutting step and outer periphery grinding step S50, the GaAs single crystal removed from crucible 1 was cut so that its main surface had an off-angle of 6° from the (100) plane. In the crystal growth step (first step) of Example 17, interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 had an intersecting angle of 30° with respect to the axis of crucible 1.

[0144] Comparative Example 11 GaAs Substrate A GaAs substrate having a diameter of 75 mm and a thickness of 600 μm was obtained by using a conventional crystal growth apparatus and by using the same method as in Example 11, except that in the crystal growth step (first step), interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 was set to have an intersecting angle of 90° with the axis of crucible 1 (i.e., horizontal).

[0145] Comparative Example 12 GaAs Substrate A GaAs substrate having a diameter of 75 mm and a thickness of 600 μm was obtained by using a conventional crystal growth apparatus and by using the same method as in Example 12, except that in the crystal growth step (first step), interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 was set to have an intersecting angle of 90° with the axis of crucible 1 (i.e., horizontal).

[0146] Comparative Example 13 GaAs Substrate A GaAs substrate having a diameter of 100 mm and a thickness of 625 μm was obtained by using a conventional crystal growth apparatus and by using the same method as in Example 13, except that in the crystal growth step (first step), interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 was set to have an intersecting angle of 90° with the axis of crucible 1 (i.e., horizontal).

[0147] Comparative Example 14 GaAs Substrate A GaAs substrate having a diameter of 150 mm and a thickness of 760 μm was obtained by using a conventional crystal growth apparatus and by using the same method as in Example 14, except that in the crystal growth step (first step), interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 was set to have an intersecting angle of 90° with the axis of crucible 1 (i.e., horizontal).

[0148] Comparative Example 15 GaAs Substrate A GaAs substrate having a diameter of 150 mm and a thickness of 760 μm was obtained by using a conventional crystal growth apparatus and by using the same method as in Example 15, except that in the crystal growth step (first step), interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 was set to have an intersecting angle of 90° with the axis of crucible 1 (i.e., horizontal).

[0149] Comparative Example 16 GaAs Substrate A GaAs substrate having a diameter of 150 mm and a thickness of 760 μm was obtained by using a conventional crystal growth apparatus and by using the same method as in Example 16, except that in the crystal growth step (first step), interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 was set to have an intersecting angle of 90° with the axis of crucible 1 (i.e., horizontal).

[0150] Comparative Example 17 GaAs Substrate A GaAs substrate having a diameter of 200 mm and a thickness of 675 μm was obtained by using a conventional crystal growth apparatus and by using the same method as in Example 17, except that in the crystal growth step (first step), interface 3 a between crystalline solid 32 grown in crucible 1 and raw material melt 33 was set to have an intersecting angle of 90° with the axis of crucible 1 (i.e., horizontal).

[0151] [Evaluation of III-V Compound Semiconductor Single Crystals] For the III-V compound semiconductor single crystal substrates of Examples 1 to 8, Examples 11 to 17, Comparative Examples 1 to 8, and Comparative Examples 11 to 17, the average impurity atom concentration of the substrate, the dislocation density of the main surface, and the asymmetry of dislocations present on the main surface were determined using the methods described above. Furthermore, the average value of residual strain and the shape of the distribution of residual strain in polar coordinates (whether or not it is n-fold symmetric, and whether or not it is mirror symmetric (including cases where it is approximately mirror symmetric)) were determined using the methods described above, and it was also determined whether or not the wave source of the ripple-like pattern visible on the main surface was located on the main surface. The results are shown in Tables 1 to 4.

[0152] Furthermore, when 1,000 III-V group compound semiconductor single crystal substrates of each of Examples 1 to 8, Examples 11 to 17, Comparative Examples 1 to 8, and Comparative Examples 11 to 17 were manufactured, the percentage of good III-V group compound semiconductor single crystal substrates obtained without cracking, chipping, etc. was calculated as the "slicing yield." The results are also shown in Tables 1 to 4. In Tables 1 to 4, the "slicing yield" was evaluated as good when it was 90% or higher, and as not good when it was less than 90%.

[0153]

[0154]

[0155]

[0156]

[0157] [Discussion] According to Tables 1 to 4, in the III-V group compound semiconductor single crystal substrates of Examples 1 to 8 and Examples 11 to 17, the wave source of the ripple-like pattern formed on the main surface was not located on the main surface, and in this case the "slicing yield" was 90% or more and could be evaluated as good. On the other hand, in the III-V group compound semiconductor single crystal substrates of Comparative Examples 1 to 8 and Comparative Examples 11 to 17, the wave source of the ripple-like pattern formed on the main surface was located on the main surface, and in this case the "slicing yield" was less than 90%, which could not be evaluated as good.

[0158] <<Second Test>> The concentration distribution of impurity atoms (S) on the main surface of the III-V compound semiconductor single crystal substrates (InP substrates) of Examples 4 and 6, and Comparative Examples 4 and 6 was measured using the method described above. The results are shown in Table 5. In Table 5, the impurity atom (S) concentration shown in the section titled "Wave Source Side" refers to the concentration measured in a measurement sample obtained from a position on the main surface where an imaginary line passing through the center of the main surface and extending in a direction from the wave source toward the center of the main surface overlaps with the outer periphery of the main surface on the wave source side relative to the center of the main surface. The impurity atom (S) concentration shown in the section titled "Center" refers to the concentration measured in a measurement sample obtained from the center of the main surface, and the impurity atom (S) concentration shown in the section titled "Ripple Spread Side" refers to the concentration measured in a measurement sample obtained from a position on the main surface where an imaginary line passing through the center of the main surface and extending in a direction from the wave source toward the center of the main surface overlaps with the outer periphery of the main surface on the opposite side from the wave source relative to the center of the main surface.

[0159]

[0160] [Discussion] According to Table 5, the impurity atoms present in the InP substrates of Examples 4 and 6 increased uniformly in the direction from the wave source toward the center of the main surface, i.e., from the "wave source side" to the "ripple spreading side," and thus exhibited a higher concentration distribution on the "ripple spreading side" than on the "wave source side." On the other hand, the impurity atoms present in the InP substrates of Comparative Examples 4 and 6 exhibited distributions with equivalent concentrations on the "wave source side" and the "ripple spreading side."

[0161] <<Third Test>> The concentration distribution of impurity atoms (Si) on the main surface of the III-V compound semiconductor single crystal substrates (GaAs substrates) of Examples 13 and 15, and Comparative Examples 13 and 15 was measured using the method described above. The results are shown in Table 6. In Table 6, the impurity atom (Si) concentration shown in the "Wave Source Side" column refers to the concentration measured in a measurement sample obtained from a position on the main surface where an imaginary line passing through the center of the main surface and extending in a direction from the wave source toward the center of the main surface overlaps with the outer periphery of the main surface on the wave source side relative to the center of the main surface. The impurity atom (Si) concentration shown in the "Center" column refers to the concentration measured in a measurement sample obtained from the center of the main surface, and the impurity atom (Si) concentration shown in the "Ripple Spread Side" column refers to the concentration measured in a measurement sample obtained from a position on the main surface where an imaginary line passing through the center of the main surface and extending in a direction from the wave source toward the center of the main surface overlaps with the outer periphery of the main surface on the opposite side from the wave source relative to the center of the main surface.

[0162]

[0163] [Discussion] According to Table 6, the impurity atoms present in the GaAs substrates of Examples 13 and 15 increased uniformly in the direction from the wave source toward the center of the main surface, i.e., from the "wave source side" to the "ripple spreading side," and thus exhibited a higher concentration distribution on the "ripple spreading side" than on the "wave source side." On the other hand, the impurity atoms present in the GaAs substrates of Comparative Examples 13 and 15 exhibited distributions with equivalent concentrations on the "wave source side" and the "ripple spreading side."

[0164] Although the embodiments and examples of the present disclosure have been described above, it is also planned from the beginning that the configurations of the above-described embodiments and examples may be appropriately combined.

[0165] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the embodiments and examples described above, and is intended to include meanings equivalent to the claims and all modifications within the scope of the claims.

[0166] O: wave source; P: ripple-like pattern; S: main surface; 100: III-V group compound semiconductor single crystal substrate; 101: III-V group compound semiconductor single crystal substrate (conventional); I: spacing; M: measurement point; L1: imaginary first line; L2: imaginary second line; R1: first region; R2: second region; OF: orientation flat; 1: crucible; 2: heating element; 3a: interface; 31: seed crystal; 32: crystalline solid; 33: raw material melt; 3a: interface; 4: crucible holder; 5: liquid sealant; S10: seed crystal loading step; S20: raw material loading step; S30: sealant placement step; S40: crystal growth step; S50: cutting step and outer periphery grinding step.

Claims

1. A III-V compound semiconductor single crystal substrate having a circular main surface, the III-V group compound semiconductor single crystal substrate is an indium phosphide single crystal substrate; The indium phosphide single crystal substrate has a ripple-like pattern visible on the main surface by carrying out the following treatment: The ripple-like pattern is a pattern corresponding to a part of ripples spreading concentrically from a wave source, The wave source is not located on the main surface of the III-V compound semiconductor single crystal substrate. Treatment: The main surface was placed horizontally at a position 10 mm below the liquid surface of a mixture of 10 g of chromium (VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water at 25° C., and light from a 500 W reflector-type incandescent lamp was irradiated toward the main surface from a position 20 cm above the liquid surface for 1 hour to 2 hours.

2. 2. The III-V compound semiconductor single crystal substrate according to claim 1, wherein the diameter of said indium phosphide single crystal substrate is not less than 50 mm and not more than 155 mm.

3. The dislocation density of the main surface is 0 cm -2 More than 2000cm -2 3. The III-V compound semiconductor single crystal substrate according to claim 1, wherein:

4. the asymmetry degree of dislocations present on the main surface is 1.8 or more; The asymmetry degree is dividing the main surface into a first region and a second region by an imaginary first straight line that intersects perpendicularly with an imaginary straight line extending in a direction from the wave source toward a center of the main surface and passes through the center of the main surface; In each of the first region and the second region, two or more 1 mm sized lines are provided on a virtual second line that passes through the center of the main surface and perpendicularly intersects with the first line, and the lines are spaced apart from each other at a pitch of 5 mm or more in a direction away from the center of the main surface. 2 A square measurement point having an area of ​​1 cm was set, the number of dislocations was measured at the measurement point, and the number of dislocations was calculated based on the measurement result. 2 Convert it to an equivalent value per area, 3. The III-V compound semiconductor single crystal substrate according to claim 1, wherein the absolute value of a numerical value obtained by subtracting an average value of the converted values ​​obtained at all of the measurement points in the second region from an average value of the converted values ​​obtained at all of the measurement points in the first region is divided by the average value of the converted values ​​obtained at all of the measurement points in the first region and the second region.

5. A III-V compound semiconductor single crystal substrate having a circular main surface, the III-V group compound semiconductor single crystal substrate is a gallium arsenide single crystal substrate; The gallium arsenide single crystal substrate has a visible ripple-like pattern on the main surface by performing the following process: The ripple-like pattern is a pattern corresponding to a part of ripples spreading concentrically from a wave source, The wave source is not located on the main surface of the III-V compound semiconductor single crystal substrate. Treatment: The main surface was placed horizontally at a position 10 mm below the liquid surface of a 25° C. mixture of 10 g of chromium (VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water, and the main surface was irradiated with light from a 500 W reflector-type incandescent lamp from a position 20 cm above the liquid surface for 5 to 20 minutes.

6. 6. The III-V compound semiconductor single crystal substrate according to claim 5, wherein the diameter of said gallium arsenide single crystal substrate is not less than 75 mm and not more than 205 mm.

7. The dislocation density of the main surface is 0 cm -2 More than 50cm -2 7. The III-V compound semiconductor single crystal substrate according to claim 5, wherein:

8. the asymmetry degree of dislocations present on the main surface is 2.0 or more; The asymmetry degree is dividing the main surface into a first region and a second region by an imaginary first straight line that intersects perpendicularly with an imaginary straight line extending in a direction from the wave source toward a center of the main surface and passes through the center of the main surface; In each of the first region and the second region, two or more 1 mm sized lines are provided on a virtual second line that passes through the center of the main surface and perpendicularly intersects with the first line, and the lines are spaced apart from each other at a pitch of 5 mm or more in a direction away from the center of the main surface. 2 A square measurement point having an area of ​​1 cm was set, the number of dislocations was measured at the measurement point, and the number of dislocations was calculated based on the measurement result. 2 Convert it to an equivalent value per area, 7. The III-V compound semiconductor single crystal substrate according to claim 5, wherein the absolute value of a numerical value obtained by subtracting an average value of the converted values ​​obtained at all of the measurement points in the second region from an average value of the converted values ​​obtained at all of the measurement points in the first region is divided by the average value of the converted values ​​obtained at all of the measurement points in the first region and the second region.

9. 6. The III-V compound semiconductor single crystal substrate according to claim 1, wherein the main surface is a plane having an off angle of 0° or more and 15° or less from a {100} plane.

10. The average residual strain, which is the absolute value of the difference between the expansion and contraction strain in the direction along the diameter of the main surface and the expansion and contraction strain in the direction along the tangent, is 3.5×10 -5 6. The III-V compound semiconductor single crystal substrate according to claim 1, wherein:

11. 6. The III-V compound semiconductor single crystal substrate according to claim 1, wherein a residual strain, which is an absolute value of a difference between an expansion and contraction strain in a direction along a diameter of the main surface and an expansion and contraction strain in a direction along a tangent to the main surface, does not have a distribution with n-fold symmetry about the origin in polar coordinates having a center of the main surface as the origin and an imaginary line segment extending from the center of the main surface along a direction toward the wave source to a point 15 mm away from an outer periphery of the III-V compound semiconductor single crystal substrate, wherein the n is an integer of 2 or more.

12. 6. The III-V compound semiconductor single crystal substrate according to claim 1, wherein the conductivity type of said III-V compound semiconductor single crystal substrate is an electron-withdrawing type.

13. 6. The III-V compound semiconductor single crystal substrate according to claim 1, wherein the III-V compound semiconductor single crystal substrate contains tin or sulfur as impurity atoms when the III-V compound semiconductor single crystal substrate is an indium phosphide single crystal substrate, and contains silicon as impurity atoms when the III-V compound semiconductor single crystal substrate is a gallium arsenide single crystal substrate.

14. The atomic concentration of the impurity atoms is 1×10 16 cm -3 Above 1 x 10 19 cm -3 14. The III-V compound semiconductor single crystal substrate according to claim 13, wherein:

15. 14. The III-V compound semiconductor single crystal substrate according to claim 13, wherein the impurity atoms exhibit a concentration distribution that changes uniformly in the direction from the wave source toward the center of the main surface in the III-V compound semiconductor single crystal substrate.

16. A method for producing a III-V compound semiconductor single crystal substrate using a crystal growth apparatus, comprising the steps of: a step of contacting a seed crystal with a raw material melt and growing a crystalline solid on the raw material melt side of the seed crystal to obtain a III-V compound semiconductor single crystal; and obtaining a III-V compound semiconductor single crystal substrate having a circular main surface by cutting the III-V compound semiconductor single crystal. The crystal growth apparatus includes at least a cylindrical crucible and a heating element for heating the crucible, the seed crystal is accommodated in the bottom of the crucible, and the raw material melt is accommodated in the crucible above the seed crystal; the interface between the crystalline solid and the raw material melt has an intersecting angle of less than 90° with respect to an axis of the crucible.