Nitride semiconductor device

Abstract

A nitride semiconductor device (10) comprises: a nitride semiconductor layer (12); a gate layer (14) formed on the nitride semiconductor layer (12) and including a plurality of main gate parts (18) which, in a plan view, extend in a first direction and are arranged in a second direction perpendicular to the first direction; a first dummy part (24) and a second dummy part (26) formed on the nitride semiconductor layer (12) and extending in the first direction in a plan view; and a passivation layer having a plurality of source openings (34A) and a plurality of drain openings (34B). The gate layer (14), the first dummy part (24), and the second dummy part (26) are each composed of a nitride semiconductor containing acceptor-type impurities. The gate layer (14), the plurality of source openings (34A), and the plurality of drain openings (34B) are disposed between the first dummy part (24) and the second dummy part (26) which are spaced apart from each other in the second direction in a plan view.

Description

nitride semiconductor devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] Currently, high electron mobility transistors (HEMTs) using nitride semiconductors are being commercialized. When applying HEMTs to power devices, a fail-safe requirement is that they must operate normally, blocking the current path (channel) between the source and drain at zero bias.

[0003] In the nitride semiconductor device described in Patent Document 1, a heterojunction is formed by forming a second nitride semiconductor layer (electron supply layer) having a different band gap (Al composition) on a first nitride semiconductor layer (electron transit layer). This generates a two-dimensional electron gas in the first nitride semiconductor layer near the interface between the first and second nitride semiconductor layers. Below the gate electrode, the energy levels of the first and second nitride semiconductor layers are raised by ionized acceptors contained in a gallium nitride (GaN) layer doped with acceptor-type impurities. As a result, the energy level of the conduction band at the heterojunction interface is higher than the Fermi level. As a result, when no bias is applied to the gate electrode, the channel formed by the two-dimensional electron gas is blocked directly below the gate electrode, thereby realizing a normally-off HEMT.

[0004] Japanese Patent Application Laid-Open No. 2017-73506

[0005] The shape of the GaN layer doped with acceptor-type impurities (p-type GaN layer) significantly affects the operating characteristics of the HEMT (e.g., on-resistance, gate threshold voltage, maximum rated voltage of the gate-source voltage, etc.). Therefore, if the shape of the p-type GaN layer is non-uniform within the chip, gate reliability may be reduced.

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes: a nitride semiconductor layer; a gate layer formed on the nitride semiconductor layer, the gate layer including a plurality of main gate portions extending in a first direction in a plan view and arranged in a second direction perpendicular to the first direction; a gate electrode formed on the gate layer; first and second dummy portions formed on the nitride semiconductor layer and extending in the first direction in a plan view; a passivation layer covering the gate layer, the gate electrode, the first dummy portions, and the second dummy portions, the passivation layer having a plurality of source openings and a plurality of drain openings; a source electrode in contact with the nitride semiconductor layer through the plurality of source openings; and a drain electrode in contact with the nitride semiconductor layer through the plurality of drain openings. The gate layer, the first dummy portions, and the second dummy portions are made of a nitride semiconductor containing acceptor-type impurities. The gate layer, the plurality of source openings, and the plurality of drain openings are arranged between the first dummy portion and the second dummy portion, which are spaced apart in the second direction in a plan view.

[0007] According to the nitride semiconductor device of the present disclosure, the uniformity of the shape of the main gate portion can be improved.

[0008] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to an embodiment. FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device taken along line F2-F2 in FIG. 1. FIG. 3 is a schematic cross-sectional view showing an exemplary manufacturing process of a nitride semiconductor device in an active region. FIG. 4 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 3. FIG. 5 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 4. FIG. 6 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 5. FIG. 7 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 6. FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 7. FIG. 9 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 8. FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 9. FIG. 11 is a schematic plan view of an exemplary nitride semiconductor device according to a first modified example. FIG. 12 is a schematic plan view of an exemplary nitride semiconductor device according to a second modified example. FIG. 13 is a schematic plan view of an exemplary nitride semiconductor device according to a third modified example. FIG. 14 is a schematic cross-sectional view of the nitride semiconductor device taken along line F14-F14 in FIG. 13. FIG. 15 is a schematic plan view of an exemplary nitride semiconductor device according to a fourth modification. FIG. 16 is a schematic plan view of an exemplary nitride semiconductor device according to a fifth modification. FIG. 17 is a schematic cross-sectional view of the nitride semiconductor device taken along line F17-F17 in FIG. 16. FIG. 18 is a schematic plan view of an exemplary nitride semiconductor device according to a sixth modification. FIG. 19 is a schematic plan view of an exemplary nitride semiconductor device according to a seventh modification. FIG. 20 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to an eighth modification. FIG. 21 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a ninth modification.

[0009] Hereinafter, several embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] (Exemplary Layout of Nitride Semiconductor Device) FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to one embodiment. The nitride semiconductor device 10 includes a nitride semiconductor layer 12, a gate layer 14 formed on the nitride semiconductor layer 12, and a gate electrode 16 formed on the gate layer 14. The Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1 is a direction perpendicular to the plane of the nitride semiconductor layer 12 on which a device is formed. The term "plan view" used in this specification refers to viewing the nitride semiconductor device 10 from above along the Z-axis direction, unless explicitly stated otherwise.

[0012] The top surface of the nitride semiconductor layer 12 may include two sides 12X1 and 12X2 extending along the X-axis direction and two sides 12Y1 and 12Y2 extending along the Y-axis direction. An area defined by the four sides 12X1, 12X2, 12Y1, and 12Y2 of the nitride semiconductor layer 12 may correspond to one chip (die). Further details of the nitride semiconductor layer 12 will be described later with reference to FIG. 2 .

[0013] The gate layer 14 is made of a nitride semiconductor containing acceptor-type impurities. In this embodiment, the gate layer 14 may be a gallium nitride layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), and carbon (C). In one example, the maximum concentration of the acceptor-type impurities in the gate layer 14 is 7×10 １８ cm －３ 1x10 or more ２０ cm －３ It may be the following:

[0014] The gate layer 14 includes a plurality of main gate portions 18 that extend in the Y-axis direction (first direction) and are arranged in the X-axis direction (second direction) in a plan view. In this specification, the Y-axis direction is also referred to as the first direction, and the X-axis direction is also referred to as the second direction. In the example of FIG. 1 , the gate layer 14 includes four main gate portions 18. The number of main gate portions 18 can be determined arbitrarily depending on the desired layout of the nitride semiconductor device 10, the area (chip area) of the nitride semiconductor layer 12, etc.

[0015] The gate layer 14 may further include a plurality of gate coupling portions 20 that interconnect the plurality of main gate portions 18. In the example of FIG. 1 , two main gate portions 18 are coupled by three gate coupling portions 20. The number of gate coupling portions 20 can be determined arbitrarily depending on the desired layout of the nitride semiconductor device 10, the area (chip area) of the nitride semiconductor layer 12, etc. The gate coupling portion 20 can be configured to couple two main gate portions 18 spaced apart in the X-axis direction.

[0016] The gate electrode 16 may be composed of one or more metal layers. In one example, the gate electrode 16 may be composed of a titanium nitride (TiN) layer. In another example, the gate electrode 16 may be composed of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The gate electrode 16 can form a Schottky junction with the gate layer 14. The gate electrode 16 may be formed in an area smaller than that of the gate layer 14 in a plan view.

[0017] The nitride semiconductor device 10 may further include a dummy pattern 22 formed on the nitride semiconductor layer 12. In the example of Fig. 1, the dummy pattern 22 is formed in a closed ring shape surrounding the gate layer 14 in a plan view. The dummy pattern 22 may extend substantially along the four sides 12X1, 12X2, 12Y1, and 12Y2 of the nitride semiconductor layer 12 in a plan view.

[0018] The dummy pattern 22 is formed on the nitride semiconductor layer 12 and includes a first dummy portion 24 and a second dummy portion 26 extending in the Y-axis direction in a planar view. The first dummy portion 24 and the second dummy portion 26 are made of a nitride semiconductor containing acceptor-type impurities, similar to the gate layer 14. In this embodiment, the dummy pattern 22 is formed on the nitride semiconductor layer 12 and may further include a third dummy portion 28 and a fourth dummy portion 30 extending in the X-axis direction in a planar view. The third dummy portion 28 and the fourth dummy portion 30 are made of a nitride semiconductor containing acceptor-type impurities, similar to the gate layer 14. As shown in FIG. 1 , the first dummy portion 24, the second dummy portion 26, the third dummy portion 28, and the fourth dummy portion 30 constitute at least a part of the ring-shaped dummy pattern 22 in a planar view.

[0019] The nitride semiconductor device 10 may further include a dummy electrode 32 formed on the dummy pattern 22. The dummy electrode 32 may be made of the same metal layer as the gate electrode 16. The dummy electrode 32 may be formed in an area smaller than the dummy pattern 22 in plan view. The dummy electrode 32 may be electrically floating.

[0020] The nitride semiconductor device 10 further includes a passivation layer 34 (see FIG. 2) having a plurality of source openings 34A and a plurality of drain openings 34B. In FIG. 1, the passivation layer 34 is shown as being transparent so that layers below the passivation layer 34 can be seen, but the plurality of source openings 34A and the plurality of drain openings 34B are depicted by dashed lines. The passivation layer 34 may cover the gate layer 14, the gate electrode 16, the dummy pattern 22 (the first dummy portion 24, the second dummy portion 26, the third dummy portion 28, and the fourth dummy portion 30), and the dummy electrode 32.

[0021] In the example shown in FIG. 1 , six source openings 34A and four drain openings 34B are formed in the passivation layer 34. Two source openings 34A spaced apart from each other are aligned in a line in the Y-axis direction. Two drain openings 34B spaced apart from each other are aligned in a line in the Y-axis direction. The source openings 34A and the drain openings 34B are alternately aligned in the X-axis direction. The number of source openings 34A and the number of drain openings 34B can be determined arbitrarily depending on the desired layout of the nitride semiconductor device 10, the area (chip area) of the nitride semiconductor layer 12, and the like. The number of source openings 34A and the number of drain openings 34B can be determined depending on, for example, the number of main gate portions 18.

[0022] Each main gate portion 18 is disposed between one of the plurality of source openings 34A and one of the plurality of drain openings 34B. Each gate connection portion 20 is spaced apart in the Y-axis direction from at least one of the plurality of drain openings 34B. Some of the plurality of gate connection portions 20 are disposed between two drain openings 34B aligned in the Y-axis direction.

[0023] The gate layer 14, the plurality of source openings 34A, and the plurality of drain openings 34B are disposed between the first dummy portion 24 and the second dummy portion 26, which are spaced apart in the X-axis direction in a plan view. Similarly, the gate layer 14, the plurality of source openings 34A, and the plurality of drain openings 34B are disposed between the third dummy portion 28 and the fourth dummy portion 30, which are spaced apart in the Y-axis direction in a plan view.

[0024] The nitride semiconductor device 10 further includes a source electrode 36 in contact with the nitride semiconductor layer 12 through a plurality of source openings 34A, and a drain electrode 38 in contact with the nitride semiconductor layer 12 through a plurality of drain openings 34B. In Figure 1, the source electrode 36 is depicted by a two-dot chain line and is shown as being transparent so that layers below the source electrode 36 can be seen.

[0025] The source electrode 36 and the drain electrode 38 may be formed of one or more metal layers (for example, a combination of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, an AlCu layer, etc.).

[0026] The source electrode 36 and the drain electrode 38 are disposed between the first dummy section 24 and the second dummy section 26, which are spaced apart in the X-axis direction in a plan view. Similarly, the source electrode 36 and the drain electrode 38 are disposed between the third dummy section 28 and the fourth dummy section 30, which are spaced apart in the Y-axis direction in a plan view.

[0027] The source electrode 36 can be disposed so as to partially cover the gate layer 14 and the gate electrode 16. Details of the source electrode 36 will be described later with reference to FIG. 2. The drain electrode 38 can be disposed so as to cover the drain opening 34B. The drain electrode 38 is disposed so as not to overlap with the gate layer 14 and the gate electrode 16 in a plan view.

[0028] The nitride semiconductor device 10 may further include a guard ring 40 formed on the nitride semiconductor layer 12. The guard ring 40 is formed so as to surround the dummy pattern 22 in a plan view. The guard ring 40 may include a guard ring layer 42 formed on the nitride semiconductor layer 12 and a guard ring electrode 44 formed on the guard ring layer 42.

[0029] The guard ring layer 42 may be made of a nitride semiconductor containing acceptor-type impurities. The guard ring electrode 44 may be made of the same metal layer as the source electrode 36 and the drain electrode 38. The guard ring electrode 44 may be electrically connected to the source electrode 36.

[0030] Fig. 2 is a schematic cross-sectional view of the nitride semiconductor device 10 taken along line F2-F2 in Fig. 1. The nitride semiconductor device 10 may include a semiconductor substrate 50, a buffer layer 52 formed on the semiconductor substrate 50, and the aforementioned nitride semiconductor layer 12. The nitride semiconductor layer 12 may include an electron transit layer 54 formed on the buffer layer 52, and an electron supply layer 56 formed on the electron transit layer 54.

[0031] The semiconductor substrate 50 may be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 50 may be a Si substrate. The thickness of the semiconductor substrate 50 may be, for example, 200 μm or more and 1500 μm or less.

[0032] The buffer layer 52 may be located between the semiconductor substrate 50 and the electron transport layer 54. In one example, the buffer layer 52 may be composed of any material that can facilitate epitaxial growth of the electron transport layer 54. The buffer layer 52 may include one or more nitride semiconductor layers. In one example, the buffer layer 52 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having a different aluminum (Al) composition. For example, the buffer layer 52 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0033] In one example, the buffer layer 52 may include a first buffer layer that is an AlN layer formed on the semiconductor substrate 50, and a second buffer layer that is an AlGaN layer formed on the AlN layer. The first buffer layer may be an AlN layer having a thickness of, for example, 200 nm, while the second buffer layer may be formed by stacking multiple graded AlGaN layers having a thickness of, for example, 300 nm. Note that, in order to suppress leakage current in the buffer layer 52, impurities may be introduced into a portion of the buffer layer 52 to make the buffer layer 52 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 １６ cm －３ It can be more than that.

[0034] The electron transit layer 54 is made of a nitride semiconductor. The electron transit layer 54 may be, for example, a GaN layer. The thickness of the electron transit layer 54 may be, for example, 0.5 μm or more and 2 μm or less. In order to suppress leakage current in the electron transit layer 54, impurities may be introduced into a portion of the electron transit layer 54 to make the electron transit layer 54 semi-insulating except for the surface region. In this case, the impurity may be, for example, C. The impurity concentration in the electron transit layer 54 may be, for example, 4×10 １６ cm －３ or more. That is, the electron transit layer 54 may include a plurality of GaN layers with different impurity concentrations, for example, a C-doped GaN layer and a non-doped GaN layer. In this case, the C-doped GaN layer may be formed on the buffer layer 52. The C-doped GaN layer may have a thickness of 0.3 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer may be 5×10 １７ cm －３ 9 x 10 or more １９ cm －３ The non-doped GaN layer is formed on the C-doped GaN layer and may have a thickness of 0.05 μm or more and 0.4 μm or less. The non-doped GaN layer is in contact with the electron supply layer 56. In one example, the electron transit layer 54 may include a C-doped GaN layer having a thickness of 0.4 μm and a non-doped GaN layer having a thickness of 0.4 μm. The C concentration in the C-doped GaN layer is about 2×10 １９ cm －３ It may be.

[0035] The electron supply layer 56 is made of a nitride semiconductor having a larger band gap than the electron transit layer 54. The electron supply layer 56 may be, for example, an AlGaN layer. Since the band gap increases as the Al composition increases, the electron supply layer 56, which is an AlGaN layer, has a larger band gap than the electron transit layer 54, which is a GaN layer. In one example, the electron supply layer 56 is made of Al ｘ Ga １－ｘThe electron supply layer 56 is composed of N, where x is 0.1<x<0.4, and more preferably 0.1<x<0.3. The electron supply layer 56 may have a thickness of 5 nm or more and 20 nm or less. In one example, the electron supply layer 56 may have a thickness of 8 nm or more.

[0036] The electron transit layer 54 and the electron supply layer 56 are composed of nitride semiconductors with different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transit layer 54 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 56 form a lattice-mismatched heterojunction. Due to spontaneous polarization in the electron transit layer 54 and the electron supply layer 56 and piezoelectric polarization caused by crystal strain near the heterojunction interface, the energy level of the conduction band of the electron transit layer 54 near the heterojunction interface is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) spreads within the electron transit layer 54 near the heterojunction interface between the electron transit layer 54 and the electron supply layer 56 (e.g., within a range of several nanometers from the interface). Note that increasing at least one of the Al composition and thickness of the electron supply layer 56 can increase the sheet carrier density of the 2DEG generated in the electron transit layer 54.

[0037] (Active Region of Nitride Semiconductor Device) As shown in FIG. 2 , the gate layer 14 is formed on the electron supply layer 56. The gate layer 14 may be, for example, a GaN layer having a smaller bandgap than the electron supply layer 56, which is an AlGaN layer. FIG. 2 shows a cross section of the main gate portion 18 of the gate layer 14. In this embodiment, the main gate portion 18 is located between the source opening 34A and the drain opening 34B. More specifically, the main gate portion 18 may be located between the source opening 34A and the drain opening 34B and closer to the source opening 34A than the drain opening 34B. The source electrode 36 contacts the electron supply layer 56 through the source opening 34A. The drain electrode 38 contacts the electron supply layer 56 through the drain opening 34B.

[0038] The main gate portion 18 includes a bottom surface 18A in contact with the nitride semiconductor layer 12 (electron supply layer 56) and an upper surface 18B on which the gate electrode 16 is formed. In the example shown in FIG. 2 , the main gate portion 18 may include a gate ridge portion 58 including the upper surface 18B, and a source-side extension portion 60 and a drain-side extension portion 62 having a thickness smaller than that of the gate ridge portion 58. The source-side extension portion 60 and the drain-side extension portion 62 extend outward from the gate ridge portion 58 in a plan view. Note that in the plan view shown in FIG. 1 , only the gate ridge portion 58 is depicted as the main gate portion 18, and the source-side extension portion 60 and the drain-side extension portion 62 are omitted.

[0039] The source-side extension 60 extends from the gate ridge 58 toward the source opening 34A in plan view. Note that the source opening 34A here refers to the source opening 34A that is closest to the gate ridge 58 among the multiple source openings 34A. The source-side extension 60 does not reach the source opening 34A. The source-side extension 60 is separated from the source electrode 36 by the passivation layer 34.

[0040] The drain-side extension 62 extends from the gate ridge 58 toward the drain opening 34B in plan view. Note that the drain opening 34B here refers to the drain opening 34B that is closest to the gate ridge 58 among the multiple drain openings 34B. The drain-side extension 62 does not reach the drain opening 34B. The drain-side extension 62 is separated from the drain electrode 38 by the passivation layer 34.

[0041] The gate ridge portion 58 is located between the source side extension portion 60 and the drain side extension portion 62 and is formed integrally with the source side extension portion 60 and the drain side extension portion 62. Due to the presence of the source side extension portion 60 and the drain side extension portion 62, the bottom surface 18A of the main gate portion 18 has a larger area than the top surface 18B. In the example shown in FIG. 2 , the drain side extension portion 62 extends further outward from the gate ridge portion 58 in a planar view than the source side extension portion 60. That is, the drain side extension portion 62 has a larger dimension in the X-axis direction than the source side extension portion 60. In another example, the source side extension portion 60 and the drain side extension portion 62 may have the same dimension in the X-axis direction. The source side extension portion 60 may have a dimension in the X-axis direction of, for example, 0.2 μm to 0.3 μm. On the other hand, the drain side extension portion 62 may have a dimension in the X-axis direction of, for example, 0.2 μm to 0.6 μm.

[0042] The gate ridge portion 58 corresponds to a relatively thick portion of the main gate portion 18. The gate ridge portion 58 may have a thickness of, for example, 80 nm or more and 150 nm or less. The thickness of the main gate portion 18, particularly the gate ridge portion 58, can be determined taking into account parameters including the gate threshold voltage. In one example, the main gate portion 18 (gate ridge portion 58) may have a thickness greater than 110 nm.

[0043] Each of the source side extension 60 and the drain side extension 62 has a thickness that is less than the thickness of the gate ridge 58. In one example, each of the source side extension 60 and the drain side extension 62 may have a thickness that is half or less of the thickness of the gate ridge 58.

[0044] Each of the source side extension 60 and the drain side extension 62 may include a flat portion having a substantially constant thickness. Each of the source side extension 60 and the drain side extension 62 may further include a sloped portion having a thickness that gradually decreases with increasing distance from the gate ridge 58, as shown in FIG. 2 . The sloped portion is formed between the gate ridge 58 and the flat portion. The flat portion of the source side extension 60 and the drain side extension 62 may have a thickness of 5 nm or more and 25 nm or less, for example. In this specification, the term "substantially constant thickness" refers to a thickness that is within a manufacturing variation range (e.g., 20%).

[0045] The gate electrode 16 is formed on the gate layer 14. As shown in Fig. 2, the gate electrode 16 is formed on the gate ridge portion 58 including the upper surface 18B of the main gate portion 18. The thickness of the gate electrode 16 may be, for example, not less than 50 nm and not more than 200 nm.

[0046] The source electrode 36 may include a source contact plug portion 36A filled in the source opening 34A and a source field plate portion 36B covering the passivation layer 34. The source field plate portion 36B may be continuous with the source contact plug portion 36A. In this case, the source field plate portion 36B is formed integrally with the source contact plug portion 36A. The source field plate portion 36B includes an end portion 36C located between the drain opening 34B and the main gate portion 18 in a plan view. The source field plate portion 36B extends along the surface of the passivation layer 34 from the source contact plug portion 36A to the end portion 36C toward the drain electrode 38 but is spaced apart from the drain electrode 38. The source field plate portion 36B extends along the uneven surface of the passivation layer 34 and therefore similarly has an uneven surface. The source field plate portion 36B plays a role in alleviating electric field concentration near the end of the gate electrode 16 when a drain voltage is applied to the drain electrode 38 in a zero bias state where no gate voltage is applied to the gate electrode 16.

[0047] At least a portion of the source electrode 36 is filled in the source opening 34A, and therefore can make ohmic contact with the 2DEG immediately below the electron supply layer 56 through the source opening 34A. Similarly, at least a portion of the drain electrode 38 is filled in the drain opening 34B, and therefore can make ohmic contact with the 2DEG immediately below the electron supply layer 56 through the drain opening 34B.

[0048] The nitride semiconductor device 10 may include an active region 64 that contributes to transistor operation and a non-active region 66 that does not contribute to transistor operation. In the region shown in FIG. 2 , the region extending in the X-axis direction from the source opening 34A (source contact plug portion 36A) to the drain opening 34B (drain electrode 38) generally corresponds to the active region 64. In this embodiment, the main gate portion 18 is made of a nitride semiconductor (e.g., p-type GaN) containing acceptor-type impurities, and therefore the active region 64 including the main gate portion 18 can function as a HEMT capable of normally-off operation.

[0049] As described above with reference to FIG. 1 , the nitride semiconductor device 10 includes a plurality of source openings 34A and a plurality of drain openings 34B arranged alternately in the X-axis direction, and each main gate portion 18 is disposed between one of the plurality of source openings 34A and one of the plurality of drain openings 34B. Therefore, the active region 64 shown in FIG. 2 may be repeated with every other active region 64 inverted in the X-axis direction. In the example of FIG. 1 , the region extending in the X-axis direction from the source opening 34A closest to the first dummy portion 24 to the source opening 34A closest to the second dummy portion 26 may correspond to the active region 64. Furthermore, the active region 64 may extend over the same range in the Y-axis direction as the source openings 34A or the drain openings 34B.

[0050] (Inactive Region of Nitride Semiconductor Device) As shown in FIG. 2 , a first dummy portion 24, which is part of the dummy pattern 22, and a guard ring 40 are formed on the electron supply layer 56. The first dummy portion 24 is located between the guard ring 40 and the source opening 34A in the X-axis direction. The second dummy portion 26 (see FIG. 1 ) can have a cross-sectional structure similar to that of the first dummy portion 24 shown in FIG. 2 . It should be noted that the description of the first dummy portion 24 is equally applicable to the second dummy portion 26.

[0051] Like the gate layer 14, the first dummy portion 24 is made of a nitride semiconductor containing acceptor-type impurities. The first dummy portion 24 includes a bottom surface 24A in contact with the nitride semiconductor layer 12 (electron supply layer 56) and an upper surface 24B opposite the bottom surface 24A. In the example shown in FIG. 2 , the first dummy portion 24 may include a dummy ridge portion 68 including the upper surface 24B, and outer extension portions 70 and inner extension portions 72 having a thickness smaller than that of the dummy ridge portion 68. Note that in the plan view shown in FIG. 1 , the dummy ridge portion 68 is depicted as the first dummy portion 24, and the outer extension portions 70 and inner extension portions 72 are omitted. In the example shown in FIG. 2 , a dummy electrode 32 is formed on the upper surface 24B of the first dummy portion 24. The first dummy portion 24 and the dummy electrode 32 formed on the first dummy portion 24 are covered with a passivation layer 34.

[0052] The outer extension portion 70 extends from the dummy ridge portion 68 toward the guard ring 40 in a plan view. In the example of FIG. 1, the dummy pattern 22 is formed in a ring shape in a plan view, and therefore the dummy pattern 22 separates an inner region surrounded by the dummy pattern 22 from an outer region of the dummy pattern 22. The outer extension portion 70 exists in the outer region of the dummy pattern 22. In the example of FIG. 2, the outer extension portion 70 does not reach the guard ring 40. The outer extension portion 70 is separated from the guard ring 40 by the passivation layer 34.

[0053] The inner extension 72 extends from the dummy ridge 68 toward the gate layer 14 (main gate 18) in plan view. The inner extension 72 exists in an inner region surrounded by the dummy pattern 22. The inner extension 72 does not reach the source opening 34A. The inner extension 72 is separated from the source electrode 36 by the passivation layer 34.

[0054] The dummy ridge portion 68 of the first dummy portion 24 is located between the outer extension portion 70 and the inner extension portion 72 and is formed integrally with the outer extension portion 70 and the inner extension portion 72. Due to the presence of the outer extension portion 70 and the inner extension portion 72, the bottom surface 24A of the first dummy portion 24 has a larger area than the top surface 24B. As shown in FIG. 2 , the outer extension portion 70 and the inner extension portion 72 may have the same dimension in the X-axis direction. The outer extension portion 70 and the inner extension portion 72 may have a dimension in the X-axis direction of, for example, 0.2 μm or more and 0.3 μm or less.

[0055] The dummy ridge portion 68 corresponds to a relatively thick portion of the first dummy portion 24. The dummy ridge portion 68 may have a thickness of 80 nm or more and 150 nm or less. The outer extension portion 70 and the inner extension portion 72 each have a thickness smaller than the thickness of the dummy ridge portion 68. In one example, the outer extension portion 70 and the inner extension portion 72 each may have a thickness equal to or less than half the thickness of the dummy ridge portion 68.

[0056] Each of the outer extension portion 70 and the inner extension portion 72 may include a flat portion having a substantially constant thickness. Each of the outer extension portion 70 and the inner extension portion 72 may further include a sloped portion having a thickness that gradually decreases with increasing distance from the dummy ridge portion 68, as shown in FIG. 2 . The sloped portion is formed between the dummy ridge portion 68 and the flat portion. The flat portion of the outer extension portion 70 and the inner extension portion 72 may have a thickness of 5 nm or more and 25 nm or less, for example.

[0057] The first dummy portion 24 is formed by the same manufacturing process as the main gate portion 18 (described later with reference to FIGS. 3 to 10 ). Therefore, the first dummy portion 24 can have a thickness approximately the same as that of the main gate portion 18 within the range of manufacturing variation. The X-axis dimension (design dimension) of the dummy ridge portion 68 may be equal to the X-axis dimension (design dimension) of the gate ridge portion 58. The X-axis dimension (design dimension) of the outer extension portion 70 and the inner extension portion 72 of the first dummy portion 24 may be equal to or different from the X-axis dimension (design dimension) of the source-side extension portion 60 and the drain-side extension portion 62, respectively. For example, the X-axis dimension of the outer extension portion 70 and the inner extension portion 72 of the first dummy portion 24 may be the same as each other. In this case, the X-axis dimension of the outer extension portion 70 and the inner extension portion 72 may be equal to the X-axis dimension of the drain-side extension portion 62, for example.

[0058] The source opening 34A located between the gate layer 14 and the first dummy portion 24 may be disposed equidistant from both the gate layer 14 (main gate portion 18) and the first dummy portion 24 in a plan view.

[0059] Like the gate layer 14, the guard ring layer 42 is composed of a nitride semiconductor containing acceptor-type impurities. The guard ring layer 42 includes a bottom surface 42A in contact with the nitride semiconductor layer 12 (electron supply layer 56) and a top surface 24B on which a guard ring electrode 44 is formed. In the example shown in FIG. 2 , the guard ring layer 42 may include a guard ring ridge portion 74 including the top surface 42B, and outer extension portions 76 and inner extension portions 78 having a thickness smaller than that of the guard ring ridge portion 74. Note that in the plan view shown in FIG. 1 , only the guard ring ridge portion 74 is depicted as the guard ring layer 42, and the outer extension portions 76 and inner extension portions 78 are omitted. The guard ring electrode 44 is formed on the top surface 42B of the guard ring layer 42. The guard ring layer 42 and the guard ring electrode 44 formed on the guard ring layer 42 are covered by a passivation layer 34.

[0060] The outer extension 76 extends from the guard ring ridge 74 toward the outside of the guard ring 40 in plan view. As shown in FIG. 1 , the guard ring 40 is formed in a ring shape in plan view, and therefore the guard ring 40 separates an inner region surrounded by the guard ring 40 from an outer region of the guard ring 40. The outer extension 76 exists in the outer region of the guard ring 40.

[0061] The inner extension portion 78 extends from the guard ring ridge portion 74 toward the inside of the guard ring 40 in plan view. The inner extension portion 78 exists in an inner region surrounded by the guard ring 40. In the example of FIG. 2 , the inner extension portion 78 does not reach the first dummy portion 24. The inner extension portion 78 is separated from the first dummy portion 24 by the passivation layer 34.

[0062] The guard ring ridge portion 74 of the guard ring layer 42 is located between the outer extension portion 76 and the inner extension portion 78 and is formed integrally with the outer extension portion 76 and the inner extension portion 78. Due to the presence of the outer extension portion 76 and the inner extension portion 78, the bottom surface 42A of the guard ring layer 42 has a larger area than the top surface 42B. As shown in FIG. 2 , the outer extension portion 76 and the inner extension portion 78 may have the same length in the X-axis direction. The outer extension portion 76 and the inner extension portion 78 may have a length in the X-axis direction of, for example, 0.2 μm or more and 0.3 μm or less.

[0063] The guard ring ridge 74 corresponds to a relatively thick portion of the guard ring layer 42 and can have a thickness of 80 nm to 150 nm. The outer extensions 76 and inner extensions 78 each have a thickness that is less than the thickness of the guard ring ridge 74. In one example, the outer extensions 76 and inner extensions 78 may each have a thickness that is half or less of the thickness of the guard ring ridge 74.

[0064] Each of the outer extension 76 and the inner extension 78 may include a flat portion having a substantially constant thickness. Each of the outer extension 76 and the inner extension 78 may further include a sloped portion having a thickness that gradually decreases with increasing distance from the guard ring ridge 74, as shown in FIG. 2 . The sloped portion is formed between the guard ring ridge 74 and the flat portion. In one example, the flat portion of the outer extension 76 and the inner extension 78 may have a thickness of 5 nm or more and 25 nm or less.

[0065] The guard ring layer 42 is formed by the same manufacturing process (described below with reference to FIGS. 3 to 10 ) as the main gate portion 18. Therefore, the guard ring layer 42 can have a thickness similar to that of the main gate portion 18 within the range of manufacturing variations. The width of the guard ring ridge portion 74 (the dimension in the X-axis direction in FIG. 2 ) is larger than the dimensions in the X-axis direction of any of the source opening 34A, the drain opening 34B, and the gate ridge portion 58. The dimensions in the X-axis direction of the outer extension portion 76 and the inner extension portion 78 of the guard ring layer 42 may be the same as or different from each other.

[0066] The first dummy portion 24 and the guard ring layer 42 described above do not directly contribute to the transistor operation of the nitride semiconductor device 10. The region where the dummy pattern 22 including the first dummy portion 24 and the guard ring 40 including the guard ring layer 42 are formed is included in the inactive region 66.

[0067] (Method of Manufacturing a Nitride Semiconductor Device) Next, an example of a method of manufacturing the nitride semiconductor device 10 of the active region 64 shown in Fig. 2 will be described. Figs. 3 to 10 are schematic cross-sectional views showing exemplary manufacturing steps of the nitride semiconductor device 10. For ease of understanding, in Figs. 3 to 10, components similar to those in Fig. 2 may be assigned the same reference numerals.

[0068] 3 , the method for manufacturing the nitride semiconductor device 10 includes sequentially forming a buffer layer 52, an electron transit layer 54, an electron supply layer 56, a gallium nitride (GaN) layer 80, and a metal layer 82 on a semiconductor substrate 50, such as a Si substrate. The buffer layer 52, the electron transit layer 54, the electron supply layer 56, and the GaN layer 80 can be epitaxially grown using a metal organic chemical vapor deposition (MOCVD) method. The metal layer 82 can be formed, for example, using a sputtering method.

[0069] Although detailed illustration is omitted, in one example, the buffer layer 52 may be a multi-layer buffer layer. The multi-layer buffer layer may include an AlN layer (first buffer layer) formed on the semiconductor substrate 50 and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The graded AlGaN layer may be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25%, in that order from the side closest to the AlN layer.

[0070] The electron transit layer 54 formed on the buffer layer 52 may be a GaN layer. The electron supply layer 56 formed on the electron transit layer 54 may be an AlGaN layer. Therefore, the electron supply layer 56 is made of a nitride semiconductor having a larger band gap than the electron transit layer 54.

[0071] The GaN layer 80 formed on the electron supply layer 56 may contain magnesium as an acceptor-type impurity. By doping the GaN layer 80 with magnesium during growth of the GaN layer 80 on the electron supply layer 56, the GaN layer 80 containing the acceptor-type impurity can be formed. The amount of magnesium doped into the GaN layer 80 can be controlled by, for example, the amount of doping gas (e.g., biscyclopentadienyl magnesium (Cp ２ The thickness can be adjusted by controlling the flow rate of Mg), the growth temperature, etc. In one example, the GaN layer 80 is 1×10 １８ cm －３ 1x10 or more ２０ cm －３It may contain magnesium as an impurity at a concentration of less than 10 ...

[0072] The metal layer 82 can be formed on the GaN layer 80 by, for example, a sputtering method. The metal layer 82 may be a TiN layer, for example. FIG. 4 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 3 . As shown in FIG. 4 , the manufacturing method for the nitride semiconductor device 10 further includes selectively removing the metal layer 82 by lithography and etching to form the gate electrode 16. In this step, a mask 84 is formed on a portion of the metal layer 82 that is to become the gate electrode 16. The mask 84 can be formed, for example, by exposing a photoresist provided on the metal layer 82. In another example, the mask 84 may be a hard mask. Next, the metal layer 82 is etched using this mask 84, thereby removing the metal layer 82 in areas not covered by the mask 84. As a result, the metal layer 82 in areas covered by the mask 84 remains, thereby forming the gate electrode 16. The mask 84 is removed after etching.

[0073] 5 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 5 . As shown in FIG. 5 , the manufacturing method for the nitride semiconductor device 10 further includes selectively removing the GaN layer 80 by lithography and etching to form the gate ridge portion 58. In this step, a mask 86 covering the top and side surfaces of the gate electrode 16 is formed, and the GaN layer 80 is patterned using the mask 86. As a result, the GaN layer 80 located under the mask 86 remains after etching, forming the gate ridge portion 58 of the main gate portion 18 shown in FIG. 2 . The thickness of the GaN layer 80 not covered by the mask 86 is reduced by etching. At this time, the GaN layer 80 may be etched so that its thickness gradually decreases with increasing distance from the gate ridge portion 58 in a region adjacent to the gate ridge portion 58, but is substantially constant in a region away from the gate ridge portion 58 by more than a predetermined distance.

[0074] 5 may include multiple etching steps to achieve the desired shape, as described above, or may include a single etching step with conditions selected to slow the etching rate near the structures covered by the mask 86. The mask 86 may be a resist mask or a hard mask. For example, the mask 86 may be a hard mask formed from a conformally depositable SiN film. The mask 86 is removed after etching.

[0075] 6 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. As shown in FIG. 6 , the manufacturing method for the nitride semiconductor device 10 further includes selectively removing the GaN layer 80 by lithography and etching to form the source-side extension 60 and the drain-side extension 62. In this step, a mask 88 is formed to cover the gate electrode 16, the gate ridge 58, and portions of the GaN layer 80 corresponding to the source-side extension 60 and the drain-side extension 62, and then the GaN layer 80 is patterned using the mask 88. As a result, the main gate 18 including the gate ridge 58, the source-side extension 60, and the drain-side extension 62 is formed on the electron supply layer 56. The mask 88 is removed after etching.

[0076] Fig. 7 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 6. As shown in Fig. 7, the method for manufacturing the nitride semiconductor device 10 further includes forming a passivation layer 34 so as to cover the entire exposed surfaces of the electron supply layer 56, the main gate portion 18, and the gate electrode 16. In one example, the passivation layer 34 may be a SiN layer formed by low-pressure chemical vapor deposition (LPCVD).

[0077] 8 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 8 . As shown in FIG. 8 , the manufacturing method for the nitride semiconductor device 10 further includes selectively removing the passivation layer 34 by lithography and etching to form a source opening 34A and a drain opening 34B. In this step, a mask 90 is formed to cover the passivation layer 34 except for the regions where the source opening 34A and the drain opening 34B are to be formed, and then the passivation layer 34 is patterned using the mask 90. ​​As a result, the source opening 34A and the drain opening 34B that expose the electron supply layer 56 are formed. The source opening 34A and the drain opening 34B are formed so that the main gate portion 18 is located between the source opening 34A and the drain opening 34B. The main gate portion 18 may be located closer to the source opening 34A than the drain opening 34B. The mask 90 is removed after etching.

[0078] 9 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 8 . As shown in Fig. 9 , the manufacturing method for the nitride semiconductor device 10 further includes forming a metal layer 92 covering the passivation layer 34. The metal layer 92 is formed to fill the source opening 34A and the drain opening 34B and to be in contact with the electron supply layer 56 through the source opening 34A and the drain opening 34B. In one example, the metal layer 92 may include at least one of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer.

[0079] FIG. 10 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. As shown in FIG. 10 , the manufacturing method for the nitride semiconductor device 10 further includes selectively removing the metal layer 92 by lithography and etching to form the source electrode 36 and the drain electrode 38. In this step, a mask 94 is formed on the portions of the metal layer 92 that will become the source electrode 36 and the drain electrode 38, and then the metal layer 92 is patterned using the mask 94. As a result, the source electrode 36 and the drain electrode 38 are formed. The drain electrode 38 covers an area relatively close to the drain opening 34B, while the source electrode 36 extends to cover not only the source opening 34A but also the main gate portion 18. An end portion 36C of the source electrode 36 (source field plate portion 36B) is located between the drain opening 34B and the main gate portion 18 in a plan view. This allows the nitride semiconductor device 10 having the active region 64 shown in FIG. 2 to be obtained.

[0080] 1 and 2 (first dummy portion 24, second dummy portion 26, third dummy portion 28, and fourth dummy portion 30) and guard ring layer 42 can be formed simultaneously by a process similar to the manufacturing process for main gate portion 18 described above. For example, as shown in FIG. 5 , a mask 86 formed on a portion of GaN layer 80 that will become gate ridge portion 58 is also simultaneously formed on portions of GaN layer 80 that will become dummy ridge portion 68 and guard ring ridge portion 74. Therefore, gate ridge portion 58, dummy ridge portion 68, and guard ring ridge portion 74 can be formed simultaneously by etching GaN layer 80 using mask 86.

[0081] (Functions of Nitride Semiconductor Device) The functions of the nitride semiconductor device 10 of this embodiment will now be described. When a voltage exceeding the threshold voltage is applied to the gate electrode 16 of the nitride semiconductor device 10, a channel due to 2DEG is formed in the electron transit layer 54, resulting in conduction between the source and the drain. On the other hand, at zero bias, 2DEG is not formed in at least a part of the region of the electron transit layer 54 located below the main gate portion 18. This is because the main gate portion 18 contains acceptor-type impurities, which raises the energy levels of the electron transit layer 54 and the electron supply layer 56, resulting in depletion of the 2DEG. This allows the nitride semiconductor device 10 to operate normally off.

[0082] Here, the shape of the main gate portion 18 has a significant effect on the operating characteristics (e.g., on-resistance, gate threshold voltage, maximum rated voltage of the gate-source voltage, etc.) of the nitride semiconductor device 10. Therefore, if the shape of the main gate portion 18 is non-uniform within the chip, gate reliability may be reduced.

[0083] In addition, in an example where the main gate portion 18 includes the source-side extension 60 and the drain-side extension 62, localized electric field concentration in the main gate portion 18 can be suppressed, thereby reducing the electric field strength applied to the Schottky diode formed between the gate electrode 16 and the main gate portion 18. Therefore, the source-side extension 60 and the drain-side extension 62 can improve the gate breakdown voltage by suppressing the generation of gate leakage current. In this case, if the source-side extension 60 and the drain-side extension 62 are too thin, the effect of improving the gate breakdown voltage provided by the source-side extension 60 and the drain-side extension 62 may be reduced. Therefore, it is important to obtain source-side extensions 60 and drain-side extensions 62 with uniform shapes across the entire chip.

[0084] The difference in pattern density between the active region 64 and the non-active region 66 within the chip can result in non-uniform shapes of the main gate portions 18. This is because some of the multiple main gate portions 18 in the active region 64 are located relatively close to the non-active region 66. For example, in the example shown in FIG. 1 , if the dummy pattern 22 is not present, the pattern density will be different between the region including the main gate portions 18 located at the ends in the X-axis direction and the region including the main gate portions 18 located at the center. Also, in the example shown in FIG. 1 , if the dummy pattern 22 is not present and the guard ring 40 is located close to the main gate portions 18, the width of the guard ring ridge portion 74 (the dimension in the X-axis direction in FIG. 2 ) is larger than the dimension in the X-axis direction of the gate ridge portion 58, so the pattern density will be different between the region including the main gate portions 18 located at the ends in the X-axis direction and the region including the main gate portions 18 located at the center.

[0085] Differences in pattern density lead to differences in mask aperture ratios in lithography (e.g., see mask 86 shown in FIG. 5 ), which can affect the etching rate. Therefore, even if the design dimensions of the multiple main gate portions 18 are the same, it can be difficult to form multiple main gate portions 18 with different pattern densities in the same shape.

[0086] In this regard, according to the nitride semiconductor device 10 of this embodiment, the gate layer 14 including the multiple main gate portions 18, the multiple source openings 34A, and the multiple drain openings 34B are arranged between the first dummy portion 24 and the second dummy portion 26, which are spaced apart in the X-axis direction in a plan view. Therefore, it is possible to reduce the difference in pattern density between the region including the main gate portions 18 arranged at the ends in the X-axis direction and the region including the main gate portions 18 arranged at the center in the X-axis direction. Reducing the difference in pattern density reduces the influence of processes (e.g., etching) that depend on pattern density, and improves the uniformity of the shapes of the multiple main gate portions 18. As a result, it is possible to improve the gate reliability of the nitride semiconductor device 10.

[0087] The nitride semiconductor device 10 of this embodiment has the following advantages: (1) The gate layer 14 including the multiple main gate portions 18, the multiple source openings 34A, and the multiple drain openings 34B are arranged between the first dummy portion 24 and the second dummy portion 26 that are spaced apart in the X-axis direction in a plan view. Therefore, it is possible to reduce the difference in pattern density between the region including the main gate portions 18 arranged at the ends in the X-axis direction and the region including the main gate portions 18 arranged in the center in the X-axis direction. As a result, it is possible to improve the uniformity of the shapes of the multiple main gate portions 18.

[0088] (2) The nitride semiconductor device 10 may further include a guard ring 40 formed on the nitride semiconductor layer 12 so as to surround the first dummy portion 24 and the second dummy portion 26 in a plan view, and the guard ring 40 may include a guard ring electrode 44 electrically connected to the source electrode 36. This can improve the breakdown voltage of the nitride semiconductor device 10.

[0089] (3) The nitride semiconductor device 10 may further include third dummy portions 28 and fourth dummy portions 30 formed on the nitride semiconductor layer 12 and extending in the X-axis direction in a plan view. The third dummy portions 28 and fourth dummy portions 30 are made of a nitride semiconductor containing acceptor-type impurities. The gate layer 14, the multiple source openings 34A, and the multiple drain openings 34B are arranged between the third dummy portion 28 and the fourth dummy portion 30, which are spaced apart in the Y-axis direction in a plan view. As a result, the difference in pattern density between the end and center portions of the gate layer 14 in the Y-axis direction can be reduced.

[0090] (4) One of the plurality of source openings 34A may be disposed equidistant from both the gate layer 14 and the first dummy portion 24 in a plan view. This can improve the uniformity of the pattern density.

[0091] (5) Each of the multiple main gate portions 18 may include a gate ridge portion 58 including an upper surface 18B, a source-side extension portion 60 that extends from the gate ridge portion 58 toward the source opening 34A in a plan view and has a thickness smaller than that of the gate ridge portion 58, and a drain-side extension portion 62 that extends from the gate ridge portion 58 toward the drain opening 34B in a plan view and has a thickness smaller than that of the gate ridge portion 58. By including the source-side extension portion 60 and the drain-side extension portion 62 in the main gate portion 18, local electric field concentration within the main gate portion 18 can be suppressed. As a result, the occurrence of gate leakage current is suppressed, and the gate breakdown voltage can be improved.

[0092] (6) The guard ring layer 42 may include a guard ring ridge portion 74 including the upper surface 42B, an outer extension portion 76 that extends from the guard ring ridge portion 74 toward the outside of the guard ring 40 in plan view and has a thickness smaller than that of the guard ring ridge portion 74, and an inner extension portion 78 that extends from the guard ring ridge portion 74 toward the inside of the guard ring 40 in plan view and has a thickness smaller than that of the guard ring ridge portion 74. This can improve the reliability of the guard ring 40.

[0093] (7) Each of the first dummy portion 24 and the second dummy portion 26 may include a dummy ridge portion 68, an outer extension portion 70 that extends from the dummy ridge portion 68 toward the guard ring 40 in a plan view and has a thickness smaller than that of the dummy ridge portion 68, and an inner extension portion 72 that extends from the dummy ridge portion 68 toward the gate layer 14 (main gate portion 18) in a plan view and has a thickness smaller than that of the dummy ridge portion 68. This reduces the difference in pattern density between a region including the main gate portion 18 located at the end in the X-axis direction and a region including the main gate portion 18 located at the center in the X-axis direction when forming the source-side extension portion 60 and the drain-side extension portion 62 of the main gate portion 18. As a result, the uniformity of the shapes of the source-side extension portion 60 and the drain-side extension portion 62 included in each of the multiple main gate portions 18 can be improved.

[0094] (8) The main gate portion 18 is disposed closer to the source opening 34A than to the drain opening 34B. This allows the distance between the gate electrode 16 and the drain electrode 38 to be relatively large, thereby suppressing dielectric breakdown between the gate and drain, which is prone to the application of a relatively large voltage.

[0095] [Modifications] Each of the above-described embodiments and modifications can be modified as follows: The layout of the gate layer 14 and the dummy patterns 22 may be modified as in the first to seventh modifications described below.

[0096] 11 is a schematic plan view of an exemplary nitride semiconductor device 100 according to a first modification. In Fig. 11, the same components as those in the nitride semiconductor device 10 shown in Fig. 1 are denoted by the same reference numerals. Detailed description of the same components as those in the nitride semiconductor device 10 will be omitted.

[0097] The nitride semiconductor device 100 differs from the nitride semiconductor device 10 in that the dummy pattern 22 does not include the third dummy portion 28 and the fourth dummy portion 30 shown in FIG. 1 . In the nitride semiconductor device 100 according to the first modification, the dummy pattern 22 is not formed between the side 12X1 of the nitride semiconductor layer 12 and the gate layer 14, and between the side 12X2 and the gate layer 14, in a plan view. Therefore, the nitride semiconductor device 100 can reduce the chip area compared to the nitride semiconductor device 10. In addition, the nitride semiconductor device 100 has advantages similar to the advantages (1), (2), and (4) to (8) described above for the nitride semiconductor device 10.

[0098] 12 is a schematic plan view of an exemplary nitride semiconductor device 200 according to a second modification. In Fig. 12, the same components as those in the nitride semiconductor device 10 shown in Fig. 1 are denoted by the same reference numerals. Detailed description of the same components as those in the nitride semiconductor device 10 will be omitted.

[0099] The nitride semiconductor device 200 differs from the nitride semiconductor device 10 in that the dummy pattern 22 is not formed in a closed ring shape in plan view. As shown in Fig. 12, the first dummy portion 24, the second dummy portion 26, the third dummy portion 28, and the fourth dummy portion 30 may be spaced apart from one another. The nitride semiconductor device 200 has the same advantages (1) to (8) as those of the nitride semiconductor device 10 described above.

[0100] 13 is a schematic plan view of an exemplary nitride semiconductor device 300 according to a third modification. In Fig. 13, the same components as those in the nitride semiconductor device 10 shown in Fig. 1 are denoted by the same reference numerals. Detailed description of the same components as those in the nitride semiconductor device 10 will be omitted.

[0101] The nitride semiconductor device 300 differs from the nitride semiconductor device 10 in that it further includes one or more fifth dummy portions 302 and one or more sixth dummy portions 304. The one or more fifth dummy portions 302 and the one or more sixth dummy portions 304 are formed on the nitride semiconductor layer 12 and extend in the Y-axis direction in a planar view. The one or more fifth dummy portions 302 may be disposed between the first dummy portion 24 and the gate layer 14 in a planar view. The one or more sixth dummy portions 304 may be disposed between the second dummy portion 26 and the gate layer 14 in a planar view. In the example shown in FIG. 13 , the nitride semiconductor device 300 includes one fifth dummy portion 302 and one sixth dummy portion 304. In another example, the nitride semiconductor device 300 may include a plurality of fifth dummy portions 302 and a plurality of sixth dummy portions 304. In this case, the plurality of fifth dummy sections 302 may be spaced apart from one another in the X-axis direction, and the plurality of sixth dummy sections 304 may be spaced apart from one another in the X-axis direction.

[0102] The one or more fifth dummy portions 302 and the one or more sixth dummy portions 304 are made of a nitride semiconductor containing acceptor-type impurities. The dummy electrode 32 may also be formed on the one or more fifth dummy portions 302 and the one or more sixth dummy portions 304.

[0103] 14 is a schematic cross-sectional view of the nitride semiconductor device 300 taken along line F14-F14 in FIG. 13. As shown in FIG. 14, a fifth dummy portion 302 is formed on the electron supply layer 56. The fifth dummy portion 302 is located between the first dummy portion 24 and the source opening 34A. The sixth dummy portion 304 (see FIG. 13) can have a cross-sectional structure similar to that of the fifth dummy portion 302 shown in FIG. 14. It should be noted that the description of the fifth dummy portion 302 is equally applicable to the sixth dummy portion 304.

[0104] Like the gate layer 14, the fifth dummy portion 302 is made of a nitride semiconductor containing acceptor-type impurities. The fifth dummy portion 302 includes a bottom surface 302A in contact with the nitride semiconductor layer 12 (electron supply layer 56) and an upper surface 302B opposite the bottom surface 302A. In the example shown in FIG. 14 , the fifth dummy portion 302 may include a dummy ridge portion 306 including the upper surface 302B, and outer extension portions 308 and inner extension portions 310 having a thickness smaller than that of the dummy ridge portion 306. Note that in the plan view shown in FIG. 13 , the dummy ridge portion 306 is depicted as the fifth dummy portion 302, and the outer extension portions 308 and inner extension portions 310 are omitted. In the example shown in FIG. 14 , a dummy electrode 32 is formed on the upper surface 302B of the fifth dummy portion 302. The fifth dummy section 302 and the dummy electrode 32 formed on the fifth dummy section 302 are covered with a passivation layer 34 .

[0105] The outer extending portion 308 of the fifth dummy portion 302 extends from the dummy ridge portion 306 toward the first dummy portion 24 in a plan view. In the example shown in Fig. 14, the outer extending portion 308 of the fifth dummy portion 302 may be coupled to the inner extending portion 72 of the first dummy portion 24. In another example, the outer extending portion 308 of the fifth dummy portion 302 may be separated from the inner extending portion 72 of the first dummy portion 24 by the passivation layer 34.

[0106] The inner extension portion 310 of the fifth dummy portion 302 extends from the dummy ridge portion 306 toward the gate layer 14 (main gate portion 18) in a plan view. The inner extension portion 310 does not reach the source opening 34A. The inner extension portion 310 is separated from the source electrode 36 by the passivation layer 34.

[0107] The dummy ridge portion 306 of the fifth dummy portion 302 is located between the outer extension portion 308 and the inner extension portion 310, and is formed integrally with the outer extension portion 308 and the inner extension portion 310. The dummy ridge portion 306 corresponds to a relatively thick portion of the fifth dummy portion 302. The dummy ridge portion 306 may have a thickness of 80 nm or more and 150 nm or less. Each of the outer extension portion 308 and the inner extension portion 310 has a thickness smaller than that of the dummy ridge portion 306. In one example, each of the outer extension portion 308 and the inner extension portion 310 may have a thickness equal to or less than half the thickness of the dummy ridge portion 306.

[0108] Each of the outer extension portion 308 and the inner extension portion 310 may include a flat portion having a substantially constant thickness. Each of the outer extension portion 308 and the inner extension portion 310 may further include a sloped portion having a thickness that gradually decreases with increasing distance from the dummy ridge portion 306, as shown in FIG. 14 . The sloped portion is formed between the dummy ridge portion 306 and the flat portion. The flat portion of the outer extension portion 308 and the inner extension portion 310 may have a thickness of 5 nm or more and 25 nm or less, for example.

[0109] The fifth dummy portion 302 is formed by the same manufacturing process (see FIGS. 3 to 10) as the main gate portion 18. Therefore, the fifth dummy portion 302 can have a thickness approximately the same as that of the main gate portion 18 within the range of manufacturing variations. The dimension (design dimension) of the dummy ridge portion 306 in the X-axis direction can be equal to the dimension (design dimension) of the gate ridge portion 58 in the X-axis direction.

[0110] The source opening 34A located between the gate layer 14 and the fifth dummy portion 302 may be disposed equidistant from both the gate layer 14 (main gate portion 18) and the fifth dummy portion 302 in plan view.

[0111] In the nitride semiconductor device 300 according to the third modification, one or more fifth dummy portions 302 are disposed between the first dummy portion 24 and the gate layer 14 in a plan view, thereby further increasing the distance between the guard ring 40 and the gate layer 14 (main gate portion 18). Similarly, one or more sixth dummy portions 304 are disposed between the second dummy portion 26 and the gate layer 14 in a plan view, thereby further increasing the distance between the guard ring 40 and the gate layer 14 (main gate portion 18). Therefore, in the nitride semiconductor device 300, the influence of the guard ring 40 can be further reduced, thereby improving the uniformity of the shapes of the multiple main gate portions 18. In addition, the nitride semiconductor device 300 has advantages similar to the advantages (1) to (8) described above for the nitride semiconductor device 10.

[0112] 15 is a schematic plan view of an exemplary nitride semiconductor device 400 according to a fourth modification. In Fig. 15, the same components as those in the nitride semiconductor device 10 shown in Fig. 1 are denoted by the same reference numerals. Detailed description of the same components as those in the nitride semiconductor device 10 will be omitted.

[0113] The nitride semiconductor device 400 differs from the nitride semiconductor device 10 in that it further includes a dummy pattern 402 that is ring-shaped in a plan view and formed on the nitride semiconductor layer 12. The dummy pattern 402 is surrounded by the guard ring 40 and surrounds the dummy pattern 22. Therefore, the dummy pattern 402 passes between the first dummy portion 24 and the guard ring 40 and between the second dummy portion 26 and the guard ring 40 in a plan view.

[0114] The dummy pattern 402 is made of a nitride semiconductor containing acceptor-type impurities. The dummy electrode 32 may also be formed on the dummy pattern 402. The dummy pattern 402 may have the same cross-sectional shape as the dummy pattern 22.

[0115] In the nitride semiconductor device 400 according to the fourth modification, the dummy pattern 402 passes between the first dummy portion 24 and the guard ring 40 and between the second dummy portion 26 and the guard ring 40 in plan view, thereby further increasing the distance between the guard ring 40 and the gate layer 14 (main gate portion 18). Therefore, in the nitride semiconductor device 400, the influence of the guard ring 40 can be further reduced, and the uniformity of the shapes of the plurality of main gate portions 18 can be improved. In addition, the nitride semiconductor device 400 has advantages similar to the advantages (1) to (8) described above for the nitride semiconductor device 10.

[0116] 16 is a schematic plan view of an exemplary nitride semiconductor device 500 according to a fifth modification. In Fig. 16, the same components as those in the nitride semiconductor device 10 shown in Fig. 1 are denoted by the same reference numerals. Detailed description of the same components as those in the nitride semiconductor device 10 will be omitted.

[0117] The nitride semiconductor device 500 differs from the nitride semiconductor device 10 in that none of the plurality of source openings 34A and the plurality of drain openings 34B are arranged between the gate layer 14 and the first dummy portion 24 or between the gate layer 14 and the second dummy portion 26 in a plan view. Each of the plurality of source openings 34A and the plurality of drain openings 34B is arranged between two of the plurality of main gate portions 18 in a plan view.

[0118] 17 is a schematic cross-sectional view of the nitride semiconductor device 500 taken along line F17-F17 in FIG. 17 shows two main gate portions 18 arranged near the first dummy portion 24. As shown in FIG. 17, a source opening 34A is arranged between the two main gate portions 18, but neither the source opening 34A nor the drain opening 34B is arranged between the first dummy portion 24 and the main gate portion 18 closest to the first dummy portion 24. Even with this layout, the nitride semiconductor device 500 has the same advantages as the advantages (1) to (8) described above for the nitride semiconductor device 10.

[0119] 18 is a schematic plan view of an exemplary nitride semiconductor device 600 according to a sixth modification. In Fig. 18, the same components as those in the nitride semiconductor device 500 shown in Fig. 16 are denoted by the same reference numerals. Detailed description of the same components as those in the nitride semiconductor device 500 will be omitted.

[0120] The nitride semiconductor device 600 differs from the nitride semiconductor device 500 in that it further includes one or more fifth dummy portions 602 and one or more sixth dummy portions 604. The one or more fifth dummy portions 602 and the one or more sixth dummy portions 604 are formed on the nitride semiconductor layer 12 and extend in the Y-axis direction in a planar view. The one or more fifth dummy portions 602 are arranged between the first dummy portion 24 and the gate layer 14 in a planar view. The one or more sixth dummy portions 604 are arranged between the second dummy portion 26 and the gate layer 14 in a planar view. The one or more fifth dummy portions 602 and the one or more sixth dummy portions 604 may be similar components to the one or more fifth dummy portions 302 and the one or more sixth dummy portions 304, respectively, described with reference to FIG. 13 .

[0121] In the nitride semiconductor device 600 according to the sixth modification, one or more fifth dummy portions 602 are disposed between the first dummy portion 24 and the gate layer 14 in a plan view, thereby further increasing the distance between the guard ring 40 and the main gate portion 18. Similarly, one or more sixth dummy portions 604 are disposed between the second dummy portion 26 and the gate layer 14 in a plan view, thereby further increasing the distance between the guard ring 40 and the main gate portion 18. Therefore, in the nitride semiconductor device 600, the influence of the guard ring 40 can be further reduced, thereby improving the uniformity of the shapes of the multiple main gate portions 18. In addition, the nitride semiconductor device 600 has advantages similar to the advantages (1) to (8) described above for the nitride semiconductor device 10.

[0122] 19 is a schematic plan view of an exemplary nitride semiconductor device 700 according to a seventh modification. In Fig. 19, the same components as those in the nitride semiconductor device 500 shown in Fig. 16 are denoted by the same reference numerals. Detailed description of the same components as those in the nitride semiconductor device 500 will be omitted.

[0123] The nitride semiconductor device 700 has a layout obtained by separating the two main gate portions 18 at both ends from the gate layer 14 in the layout of the nitride semiconductor device 500 shown in FIG. 16 . The two portions separated from the gate layer 14 can function as a first dummy portion 702 and a second dummy portion 704. By providing the first dummy portion 702 and the second dummy portion 704 in this manner, an increase in chip area can be suppressed. The nitride semiconductor device 700 has advantages similar to the advantages (1) to (8) described above for the nitride semiconductor device 10.

[0124] The guard ring 40 may be modified as in eighth and ninth modified examples described below. (Eighth Modification) Fig. 20 is a schematic cross-sectional view of an exemplary nitride semiconductor device 800 according to an eighth modification. In Fig. 20, the same components as those in the nitride semiconductor device 10 shown in Fig. 2 are denoted by the same reference numerals. Further, detailed description of the same components as those in the nitride semiconductor device 10 will be omitted.

[0125] The nitride semiconductor device 800 differs from the nitride semiconductor device 10 in that the inner extending portions 78 of the guard ring layer 42 are connected to the outer extending portions 70 of the first dummy portions 24. Although not shown, the inner extending portions 78 of the guard ring layer 42 are also connected to the outer extending portions 70 of the second dummy portions 26. Therefore, in the example of FIG. 20 , the guard ring layer 42, the first dummy portions 24, and the second dummy portions 26 are integrally formed.

[0126] As a result, the first dummy portion 24 and the second dummy portion 26 can be fixed to the same potential as the guard ring layer 42, thereby stabilizing the characteristics of the nitride semiconductor device 800. The nitride semiconductor device 800 has the same advantages as the advantages (1) to (8) described above for the nitride semiconductor device 10.

[0127] 21 is a schematic cross-sectional view of an illustrative nitride semiconductor device 900 according to a ninth modification. In Fig. 21, the same components as those in the nitride semiconductor device 10 shown in Fig. 2 are denoted by the same reference numerals. Detailed description of the same components as those in the nitride semiconductor device 10 will be omitted.

[0128] The nitride semiconductor device 900 differs from the nitride semiconductor device 10 in that the guard ring 40 includes a guard ring electrode 44 but does not include a guard ring layer 42. In the nitride semiconductor device 900, the passivation layer 34 has a guard ring opening 34C. The guard ring electrode 44 is in contact with the nitride semiconductor layer 12 (electron supply layer 56) through the guard ring opening 34C. In the example shown in FIG. 21 , the guard ring electrode 44 may be formed from the same metal layer as the source electrode 36 and the drain electrode 38.

[0129] The nitride semiconductor device 900 has advantages similar to the advantages (1) to (5) and (7) to (8) described above for the nitride semiconductor device 10. (Other Modifications) The main gate portion 18 includes the gate ridge portion 58, but may not include the source-side extension portion 60 and the drain-side extension portion 62. In that case, the first dummy portion 24 also includes the dummy ridge portion 68, but may not include the outer extension portion 70 and the inner extension portion 72.

[0130] The guard ring layer 42 includes the guard ring ridge portion 74, but may not include the outer extension portion 76 or the inner extension portion 78. For example, if the main gate portion 18 does not include the source side extension portion 60 or the drain side extension portion 62, the guard ring layer 42 may also not include the outer extension portion 76 or the inner extension portion 78.

[0131] The dummy electrode 32 may be electrically connected to the source electrode 36. The dummy electrode 32 may be made of a metal layer different from that of the gate electrode 16. For example, the dummy electrode 32 may be made of the same metal layer as the source electrode 36 and the drain electrode 38.

[0132] The dummy electrode 32 does not have to be formed on the dummy pattern 22. In this case, the dummy pattern 22 may be directly covered with the passivation layer 34. One or more of the various examples described in this specification may be combined to the extent that they are not technically inconsistent.

[0133] As used herein, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

[0134] As used herein, the term "on" includes the meanings "on" and "above" unless the context clearly indicates otherwise. Therefore, the phrase "a first layer is formed on a second layer" means that in some embodiments, the first layer may be in contact with the second layer and disposed directly on the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which another layer is formed between the first and second layers. For example, a structure in which the electron supply layer 56 is formed on the electron transit layer 54 may include a structure in which an intermediate layer is located between the electron supply layer 56 and the electron transit layer 54 to stably form a 2DEG.

[0135] As used herein, directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," "rear," etc., depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0136] For example, the Z-axis direction used herein does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to the present disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0137] [Notes] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each note should not be limited to the components indicated by the reference symbols.

[0138] (Supplementary Note 1) A nitride semiconductor layer (12); a gate layer (14) formed on the nitride semiconductor layer (12), the gate layer (14) including a plurality of main gate portions (18) extending in a first direction in a plan view and arranged in a second direction perpendicular to the first direction; a gate electrode (16) formed on the gate layer (14); first and second dummy portions (24, 26) formed on the nitride semiconductor layer (12) and extending in the first direction in a plan view; a passivation layer (34) covering the gate layer (14), the gate electrode (16), the first dummy portions (24), and the second dummy portions (26), the passivation layer (34) having a plurality of source openings (34A) and a plurality of drain openings (34B); and a source electrode (36) in contact with the nitride semiconductor layer (12) via the plurality of source openings (34A). a drain electrode (38) in contact with the nitride semiconductor layer (12) via the plurality of drain openings (34B), wherein the gate layer (14), the first dummy portion (24), and the second dummy portion (26) are made of a nitride semiconductor containing an acceptor-type impurity, and the gate layer (14), the plurality of source openings (34A), and the plurality of drain openings (34B) are arranged between the first dummy portion (24) and the second dummy portion (26) that are spaced apart in the second direction in a plan view.

[0139] (Supplementary Note 2) The nitride semiconductor device according to Supplementary Note 1, further comprising a guard ring (40) formed in a ring shape on the nitride semiconductor layer (12) so as to surround the first and second dummy portions (24, 26) in a planar view, the guard ring (40) including a guard ring electrode (44) electrically connected to the source electrode (36).

[0140] (Supplementary Note 3) The nitride semiconductor device according to Supplementary Note 2, wherein the guard ring (40) further includes a guard ring layer (42) formed on the nitride semiconductor layer (12), the guard ring layer (42) being made of a nitride semiconductor containing acceptor-type impurities, and the guard ring electrode (44) being formed on the guard ring layer (42).

[0141] (Supplementary Note 4) The nitride semiconductor device according to Supplementary Note 2, wherein the passivation layer (34) has a guard ring opening (34C), and the guard ring electrode (44) is in contact with the nitride semiconductor layer (12) via the guard ring opening (34C).

[0142] (Supplementary Note 5) The nitride semiconductor device according to any one of Supplementary Notes 2 to 4, wherein the width of the guard ring (40) is larger than the dimensions in the second direction of the source opening (34A), the drain opening (34B), and the main gate portion (18).

[0143] (Supplementary Note 6) The nitride semiconductor device according to any one of Supplementary Notes 1 to 5, further comprising third and fourth dummy portions (28, 30) formed on the nitride semiconductor layer (12) and extending in the second direction in a planar view, the third and fourth dummy portions (28, 30) being made of a nitride semiconductor containing acceptor-type impurities, and the gate layer (14), the plurality of source openings (34A), and the plurality of drain openings (34B) being arranged between the third dummy portion (28) and the fourth dummy portion (30) spaced apart in the first direction in a planar view.

[0144] (Supplementary Note 7) The nitride semiconductor device according to Supplementary Note 6, wherein the first, second, third, and fourth dummy portions (24, 26, 28, 30) form at least a part of a dummy pattern (22) that is ring-shaped in plan view.

[0145] (Supplementary Note 8) The nitride semiconductor device according to any one of Supplementary Notes 1 to 7, further comprising one or more fifth dummy portions (302) and one or more sixth dummy portions (304) formed on the nitride semiconductor layer (12) and extending in the first direction in a planar view, wherein the one or more fifth dummy portions (302) are arranged between the first dummy portion (24) and the gate layer (14) in a planar view, and the one or more sixth dummy portions (304) are arranged between the second dummy portion (26) and the gate layer (14) in a planar view.

[0146] (Supplementary Note 9) The nitride semiconductor device according to any one of Supplementary Notes 1 to 8, wherein one of the plurality of source openings (34A) is arranged between the gate layer (14) and the first dummy portion (24) in a planar view.

[0147] (Supplementary Note 10) The nitride semiconductor device according to any one of Supplementary Notes 1 to 9, wherein one of the plurality of source openings (34A) is arranged equidistant from both the gate layer (14) and the first dummy portion (24) in a planar view.

[0148] (Supplementary Note 11) The nitride semiconductor device according to any one of Supplementary Notes 1 to 10, wherein one of the plurality of source openings (34A) is arranged between the gate layer (14) and the second dummy portion (26) in a planar view.

[0149] (Supplementary Note 12) The nitride semiconductor device according to any one of Supplementary Notes 1 to 11, wherein one of the plurality of source openings (34A) is arranged equidistant from both the gate layer (14) and the second dummy portion (26) in a planar view.

[0150] (Appendix 13) The nitride semiconductor device according to any one of Appendices 1 to 8, wherein each of the plurality of source openings (34A) and the plurality of drain openings (34B) is arranged between two of the plurality of main gate portions (18) in a planar view, and none of the plurality of source openings (34A) and the plurality of drain openings (34B) is arranged between the gate layer (14) and the first dummy portion (24) or between the gate layer (14) and the second dummy portion (26) in a planar view.

[0151] (Supplementary Note 14) The nitride semiconductor device according to any one of Supplementary Notes 1 to 13, wherein each of the plurality of main gate portions (18) includes a bottom surface (18A) in contact with the nitride semiconductor layer (12) and an upper surface (18B) on which the gate electrode (16) is formed, and each of the plurality of main gate portions (18) includes: a gate ridge portion (58) including the upper surface (18B); a source-side extension portion (60) extending from the gate ridge portion (58) toward the source opening (34A) in a planar view and having a thickness smaller than that of the gate ridge portion (58); and a drain-side extension portion (62) extending from the gate ridge portion (58) toward the drain opening (34B) in a planar view and having a thickness smaller than that of the gate ridge portion (58).

[0152] (Appendix 15) The nitride semiconductor device according to Appendix 3, wherein the guard ring layer (42) includes a bottom surface (42A) in contact with the nitride semiconductor layer (12) and a top surface (42B) on which the guard ring electrode (44) is formed, and the guard ring layer (42) includes: a guard ring ridge portion (74) including the top surface (42B); an outer extension portion (76) extending from the guard ring ridge portion (74) toward the outside of the guard ring (40) in a planar view and having a thickness smaller than that of the guard ring ridge portion (74); and an inner extension portion (78) extending from the guard ring ridge portion (74) toward the inside of the guard ring (40) in a planar view and having a thickness smaller than that of the guard ring ridge portion (74).

[0153] (Appendix 16) The nitride semiconductor device according to appendix 15, wherein each of the first dummy portion (24) and the second dummy portion (26) includes a bottom surface (24A) in contact with the nitride semiconductor layer (12) and an upper surface (24B) opposite the bottom surface (24A), and each of the first dummy portion (24) and the second dummy portion (26) includes: a dummy ridge portion (68) including the upper surface (24B); an outer extension portion (70) extending from the dummy ridge portion (68) toward the guard ring (40) in a planar view and having a thickness smaller than that of the dummy ridge portion (68); and an inner extension portion (72) extending from the dummy ridge portion (68) toward the gate layer (14) in a planar view and having a thickness smaller than that of the dummy ridge portion (68).

[0154] (Supplementary Note 17) The nitride semiconductor device according to Supplementary Note 16, wherein the inner extension portion (78) of the guard ring layer (42) is connected to the outer extension portion (70) of the first dummy portion (24) and the outer extension portion (70) of the second dummy portion (26).

[0155] (Supplementary Note 18) The nitride semiconductor device according to any one of Supplementary Notes 1 to 12, wherein each of the plurality of main gate portions (18) is disposed between one of the plurality of source openings (34A) and one of the plurality of drain openings (34B).

[0156] (Supplementary Note 19) The nitride semiconductor device according to any one of Supplementary Notes 1 to 18, wherein the nitride semiconductor layer (12) includes: an electron transit layer (54) made of a nitride semiconductor; and an electron supply layer (56) formed on the electron transit layer (54) and made of a nitride semiconductor having a larger band gap than the electron transit layer (54).

[0157] (Supplementary Note 20) The nitride semiconductor device according to any one of Supplementary Notes 1 to 19, further comprising a dummy electrode (32) formed on the first dummy portion (24).

[0158] (Supplementary Note 21) The nitride semiconductor device according to Supplementary Note 14, wherein the drain side extension (62) has a dimension in the second direction larger than that of the source side extension (60).

[0159] (Supplementary Note 22) The nitride semiconductor device according to Supplementary Note 16, wherein the outer extension portion (70) and the inner extension portion (72) of the first dummy portion (24) have the same size in the second direction.

[0160] (Supplementary Note 23) The nitride semiconductor device according to Supplementary Note 16, wherein the outer extension portion (70) and the inner extension portion (72) of the second dummy portion (26) have the same size in the second direction.

[0161] (Supplementary Note 24) The nitride semiconductor device according to Supplementary Note 20, wherein the dummy electrode (32) is electrically floating.

[0162] (Supplementary Note 25) The nitride semiconductor device according to Supplementary Note 20, wherein the dummy electrode (32) is electrically connected to the source electrode (36).

[0163] (Appendix 26) The nitride semiconductor device according to Appendix 2, further comprising a dummy pattern (402) having a ring shape in a planar view formed on the nitride semiconductor layer (12), the dummy pattern (402) passing between the first dummy portion (24) and the guard ring (40) and between the second dummy portion (26) and the guard ring (40) in a planar view.

[0164] (Supplementary Note 27) The nitride semiconductor device according to Supplementary Note 16, wherein each of the plurality of main gate portions (18) includes a bottom surface (18A) in contact with the nitride semiconductor layer (12) and an upper surface (18B) on which the gate electrode (16) is formed, and each of the plurality of main gate portions (18) includes: a gate ridge portion (58) including the upper surface (18B); a source side extension portion (60) extending from the gate ridge portion (58) toward the source opening (34A) in a planar view and having a thickness smaller than that of the gate ridge portion (58); and a drain side extension portion (62) extending from the gate ridge portion (58) toward the drain opening (34B) in a planar view and having a thickness smaller than that of the gate ridge portion (58).

[0165] (Supplementary Note 28) The nitride semiconductor device according to Supplementary Note 27, wherein a design dimension of the dummy ridge portion (68) in the second direction is equal to a design dimension of the gate ridge portion (58) in the second direction.

[0166] (Supplementary Note 29) The nitride semiconductor device according to any one of Supplementary Notes 1 to 28, further comprising a plurality of gate coupling portions (20) that couple the plurality of main gate portions (18) to one another.

[0167] (Supplementary Note 30) The nitride semiconductor device according to any one of Supplementary Notes 1 to 29, wherein the main gate portion (18) is arranged closer to the source opening (34A) than to the drain opening (34B).

[0168] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0169] REFERENCE SIGNS LIST 10, 100, 200, 300... nitride semiconductor device 12... nitride semiconductor layer 14... gate layer 16... gate electrode 18... main gate portion 18A... bottom surface 18B... upper surface 20... gate coupling portion 22, 402... dummy pattern 24, 702... first dummy portion 24A... bottom surface 24B... upper surface 26, 704... second dummy portion 28... third dummy portion 30... fourth dummy portion 32... dummy electrode 34... passivation layer 34A... source opening 34B... drain opening 34C... guard ring opening 36... source electrode 36A... source contact plug portion 36B... source field plate portion 36C... end portion 38... drain electrode 40... guard ring 42... guard ring layer 42A... bottom surface 42B... upper surface 44... guard ring electrode 50...Semiconductor substrate 52...Buffer layer 54...Electron transit layer 56...Electron supply layer 58...Gate ridge portion 60...Source side extension portion 62...Drain side extension portion 64...Active region 66...Inactive region 68, 306...Dummy ridge portion 70, 308...Outer extension portion 72, 310...Inner extension portion 74...Guard ring ridge portion 76...Outer extension portion 78...Inner extension portion 80...Gallium nitride (GaN) layer 82, 92...Metal layer 84, 86, 88, 90, 94...Mask 302, 602...Fifth dummy portion 304, 604...Sixth dummy portion

Claims

1. A nitride semiconductor layer; a gate layer formed on the nitride semiconductor layer, the gate layer including a plurality of main gate portions extending in a first direction in a plan view and arranged in a second direction perpendicular to the first direction; a gate electrode formed on the gate layer; first and second dummy portions formed on the nitride semiconductor layer and extending in the first direction in a plan view; a passivation layer covering the gate layer, the gate electrode, the first dummy portion, and the second dummy portion, the passivation layer having a plurality of source openings and a plurality of drain openings; a source electrode in contact with the nitride semiconductor layer through the plurality of source openings; a drain electrode in contact with the nitride semiconductor layer via the drain openings; Equipped with the gate layer, the first dummy portion, and the second dummy portion are made of a nitride semiconductor containing an acceptor-type impurity, a nitride semiconductor device, wherein the gate layer, the plurality of source openings, and the plurality of drain openings are disposed between the first dummy portion and the second dummy portion spaced apart in the second direction in a plan view.

2. a guard ring formed in a ring shape on the nitride semiconductor layer so as to surround the first and second dummy portions in a plan view; The nitride semiconductor device according to claim 1 , wherein said guard ring includes a guard ring electrode electrically connected to said source electrode.

3. 3. The nitride semiconductor device according to claim 2, wherein the guard ring further includes a guard ring layer formed on the nitride semiconductor layer, the guard ring layer being composed of a nitride semiconductor containing an acceptor-type impurity, and the guard ring electrode being formed on the guard ring layer.

4. the passivation layer having a guard ring opening; The nitride semiconductor device according to claim 2 , wherein said guard ring electrode is in contact with said nitride semiconductor layer through said guard ring opening.

5. 5. The nitride semiconductor device according to claim 2, wherein a width of said guard ring is larger than a dimension in said second direction of each of said source opening, said drain opening and said main gate portion.

6. 5. The nitride semiconductor device according to claim 1, further comprising third and fourth dummy portions formed on the nitride semiconductor layer and extending in the second direction in a planar view, the third and fourth dummy portions being composed of a nitride semiconductor containing an acceptor-type impurity, and the gate layer, the plurality of source openings, and the plurality of drain openings being arranged between the third dummy portion and the fourth dummy portion which are spaced apart in the first direction in a planar view.

7. The nitride semiconductor device according to claim 6 , wherein said first, second, third and fourth dummy portions form at least a part of a dummy pattern having a ring shape in a plan view.

8. one or more fifth dummy portions and one or more sixth dummy portions are formed on the nitride semiconductor layer and extend in the first direction in a plan view, The nitride semiconductor device according to any one of claims 1 to 4, wherein the one or more fifth dummy portions are arranged between the first dummy portion and the gate layer in a planar view, and the one or more sixth dummy portions are arranged between the second dummy portion and the gate layer in a planar view.

9. 5. The nitride semiconductor device according to claim 1, wherein one of said plurality of source openings is disposed between said gate layer and said first dummy portion in a plan view.

10. 5. The nitride semiconductor device according to claim 1, wherein one of the plurality of source openings is arranged equidistantly from both the gate layer and the first dummy portion in a plan view.

11. 5. The nitride semiconductor device according to claim 1, wherein each of the plurality of source openings and the plurality of drain openings is arranged between two of the plurality of main gate portions in a planar view, and none of the plurality of source openings and the plurality of drain openings is arranged between the gate layer and the first dummy portion or between the gate layer and the second dummy portion in a planar view.

12. Each of the plurality of main gate portions includes a bottom surface in contact with the nitride semiconductor layer and an upper surface on which the gate electrode is formed, Each of the plurality of main gate portions is a gate ridge portion including the upper surface; a source-side extension portion that extends from the gate ridge portion toward the source opening in a plan view and has a thickness smaller than that of the gate ridge portion; a drain side extension portion that extends from the gate ridge portion toward the drain opening in a plan view and has a thickness smaller than that of the gate ridge portion; 5. The nitride semiconductor device according to claim 1, comprising:

13. the guard ring layer includes a bottom surface in contact with the nitride semiconductor layer and an upper surface on which the guard ring electrode is formed, The guard ring layer is a guard ring ridge portion including the upper surface; an outer extension portion that extends from the guard ring ridge portion toward the outside of the guard ring in a plan view and has a thickness smaller than that of the guard ring ridge portion; an inner extension portion that extends from the guard ring ridge portion toward the inside of the guard ring in a plan view and has a thickness smaller than that of the guard ring ridge portion; The nitride semiconductor device according to claim 3 , comprising:

14. each of the first dummy portion and the second dummy portion includes a bottom surface in contact with the nitride semiconductor layer and an upper surface opposite to the bottom surface; Each of the first dummy section and the second dummy section is a dummy ridge portion including the upper surface; an outer extension portion that extends from the dummy ridge portion toward the guard ring in a plan view and has a thickness smaller than that of the dummy ridge portion; an inner extension portion that extends from the dummy ridge portion toward the gate layer in a plan view and has a thickness smaller than that of the dummy ridge portion; The nitride semiconductor device according to claim 13 , comprising:

15. The nitride semiconductor device according to claim 14 , wherein the inner extension portion of the guard ring layer is coupled to the outer extension portion of the first dummy portion and the outer extension portion of the second dummy portion.

16. 5. The nitride semiconductor device according to claim 1, wherein each of the plurality of main gate portions is disposed between one of the plurality of source openings and one of the plurality of drain openings.

17. The nitride semiconductor layer is an electron transit layer made of a nitride semiconductor; an electron supply layer formed on the electron transit layer and made of a nitride semiconductor having a band gap larger than that of the electron transit layer; 5. The nitride semiconductor device according to claim 1, comprising:

18. The nitride semiconductor device according to claim 1, further comprising a dummy electrode formed on said first dummy portion.

19. The nitride semiconductor device according to claim 12 , wherein said drain-side extension portion has a dimension in said second direction larger than said source-side extension portion.

20. The nitride semiconductor device according to claim 14 , wherein the outer extension portion and the inner extension portion of the first dummy portion have the same size in the second direction.