Chip placement device, processing system, and processing method

Abstract

This treatment method is for chips and uses an electrostatic carrier which includes a body part having an electric conductivity and having a plurality of through-holes in the thickness direction, and an insulating layer formed on a surface of the body part. The method includes: arranging a plurality of the chips on a holding surface of the electrostatic carrier; supplying electricity to the body part and electrifying the body part; and bringing the chips into contact with a ground wire and generating electrostatic force between the chips and the body part.

Description

Electrostatic carrier, processing system and processing method

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to electrostatic carriers, processing systems and processing methods.

[0002] Patent Document 1 discloses a chip-on-wafer (CoW) bonding method for mounting chips on a wafer. In this chip-on-wafer bonding method, before a plurality of chips are permanently bonded to corresponding bonding portions of a substrate, the bonding surfaces of the chips are subjected to a surface activation treatment and a hydrophilization treatment, and then the plurality of chips are temporarily bonded to the substrate.

[0003] Patent Document 2 discloses a reinforcing material for a thin plate material such as a silicon wafer. This reinforcing material has a reinforcing material main body equipped with a thin plate-shaped electrostatic holding portion having an electrode portion embedded in an electrically insulating layer (polyimide layer). A high voltage is applied to the electrode portion, and an electric charge of the opposite polarity to the voltage applied to the electrode portion is supplied to the object to be reinforced. This causes the electrostatic holding portion to exert an adhesive force and attract the object to be reinforced, allowing the reinforcing material main body to function as a reinforcing material.

[0004] Japanese Patent No. 6337400 Japanese Patent Publication No. 2009-099674

[0005] The technology disclosed herein provides an electrostatic carrier that can properly transfer chips to a wafer after dicing in a chip-on-wafer manufacturing process.

[0006] One aspect of the present disclosure is an electrostatic carrier used in a chip-on-wafer manufacturing process, comprising: a conductive main body portion having a plurality of through holes in the thickness direction; and an insulating layer formed on the surface of the main body portion.

[0007] According to the present disclosure, an electrostatic carrier can be provided that can appropriately transfer chips to a wafer after dicing in a chip-on-wafer manufacturing process.

[0008] 1 is an explanatory diagram showing an outline of the configuration of a chip attached to a dicing sheet; FIG. 1 is a cross-sectional diagram showing an outline of the configuration of an electrostatic carrier according to the present embodiment; FIG. 2 is a plan view showing an outline of the configuration of an electrostatic carrier according to the present embodiment; FIG. 3 is a cross-sectional diagram showing an outline of another configuration of an electrostatic carrier; FIG. 4 is a plan view showing an outline of another configuration of an electrostatic carrier; FIG. 5 is a cross-sectional diagram showing an outline of the configuration of a wafer to which chips are bonded; FIG. 6 is a plan view showing an outline of the configuration of a processing system according to the present embodiment; FIG. 7 is a cross-sectional diagram showing an outline of the configuration of a chip placement device; FIG. 8 is an explanatory diagram showing another configuration example of a charge removal unit; FIG. 9 is an explanatory diagram showing another configuration example of a charge removal unit; FIG. 10 is a cross-sectional diagram showing an outline of the configuration of a bonding device; FIG. 11 is a flow diagram showing main steps of a chip-on-wafer manufacturing process according to the present embodiment; FIG. 12 is an explanatory side view showing main steps of a chip-on-wafer manufacturing process according to the present embodiment; FIG. 13 is an explanatory side view showing how chips are electrostatically attracted to an electrostatic carrier in the chip placement device; FIG. 14 is an explanatory diagram showing how chips are detached from an electrostatic carrier in the bonding device; FIG. 15 is an explanatory diagram showing how chips are detached from an electrostatic carrier in the bonding device; FIG. 16 is a cross-sectional diagram showing another configuration example of a bonding device; FIG. 17 is a cross-sectional diagram showing another configuration example of a bonding device.

[0009] In recent years, in the manufacturing process of semiconductor devices, in response to demands for even higher performance and higher density of devices, a chip-on-wafer (CoW) manufacturing process has been studied as one method of three-dimensional packaging technology. Chip-on-wafer manufacturing is carried out, for example, by the method described in Patent Document 1.

[0010] In this chip-on-wafer manufacturing process, as described in Patent Document 1, prior to mounting a semiconductor chip (hereinafter simply referred to as a "chip") on a semiconductor substrate (hereinafter referred to as a "wafer"), a series of processes is required on the bonding surface of the chip, including surface activation, hydrophilization, removal of a protective film, etc. These series of processes on the chip are performed, for example, while the chip is placed on a dicing tape fixed to a dicing frame, but if the series of processes are performed in this state, the dicing tape on which the chip is placed may be damaged, causing a problem that the dicing tape cannot be reused.

[0011] Therefore, the present inventors conducted extensive research and found that the use of an electrostatic holding mechanism may be able to reduce wear on the dicing tape during the chip-on-wafer manufacturing process. Specifically, instead of performing the above-described series of processes on chips on a dicing tape during the chip-on-wafer manufacturing process, the above-described series of processes are performed while the chips are held on a carrier substrate (hereinafter referred to as an "electrostatic carrier wafer (ESW)") that has an electrostatic (Coulomb) force-based attraction and holding function. Patent Document 2 discloses an electrostatic reinforcing device for holding and reinforcing a thin plate material such as a silicon wafer, but does not describe holding multiple chips on a carrier wafer by electrostatic attraction, performing the above-described series of processes, and then finally mounting the chips on a target wafer.

[0012] Furthermore, as disclosed in Patent Document 2, electrostatic carriers used to transport thin plate materials such as silicon wafers require an insulating layer (e.g., a polyimide layer) that covers the periphery of the electrode for insulation. However, if the insulating layer covering the electrode is hard (has a high elastic modulus), electric charge may leak through the conductive liquid used in the above series of processes, resulting in a loss of electrostatic attraction of the thin plate material to the electrostatic carrier. However, Patent Document 2 does not mention a decrease in electrostatic attraction due to such electric charge leakage through the conductive liquid.

[0013] The technology disclosed herein provides an electrostatic carrier that can properly transfer chips to a wafer after dicing in a chip-on-wafer manufacturing process. Hereinafter, a processing system and a processing method according to the present embodiment will be described with reference to the drawings. Note that in this specification and the drawings, elements having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0014] In a processing system 10 according to this embodiment, which will be described later, a plurality of chips C that are aligned and attached to the adhesive surface of a dicing tape T, which will be described later, are placed on an electrostatic carrier Cw, which will be described later, and the plurality of chips C on the electrostatic carrier Cw are then bonded to a wafer W to be mounted (chip-on-wafer manufacturing process). Hereinafter, the surface of the plurality of chips C on which a device layer D, which will be described later, is formed is referred to as the front surface Ca (or "device surface"), and the surface that is attached to the dicing tape T, opposite the front surface Ca (device surface), is referred to as the back surface Cb.

[0015] 1, on the chip C, a silicon layer Si, a device layer D including a plurality of devices, and a protective film P that protects the device layer D are sequentially formed from the back surface Cb side to the front surface Ca side. The silicon layer Si on the back surface Cb side of the chip C is attached to a dicing tape T. Note that the dicing tape T is fixed to a dicing frame F as shown in FIG. 1 when being transported in a processing system 10 described below.

[0016] The electrostatic carrier Cw has an adsorption surface on its upper surface for holding multiple chips C by electrostatic and vacuum adsorption. As shown in Fig. 2, the electrostatic carrier Cw has a configuration in which an insulating layer 2 is formed on the surface of a main body 1. Therefore, in the electrostatic carrier Cw according to the technology of the present disclosure, no electrode portion (electrode wiring pattern) for electrostatically adsorbing the chips C is formed on the main body 1. The electrostatic carrier Cw adsorbs and holds the silicon layer Si on the back surface Cb side of the chip C as shown in Fig. 2.

[0017] The main body 1 has approximately the same diameter and thickness as the wafer W (described later) on which the chips C are to be mounted, and is made of any conductive material, such as silicon, aluminum, an aluminum alloy, stainless steel, or titanium. In other words, a silicon substrate serving as a conductive substrate may be used as the main body 1. Alternatively, the main body 1 may have approximately the same diameter as the wafer W (described later) on which the chips C are to be mounted, but may have a thickness different from that of the wafer W (e.g., 500 μm to 1000 μm). Furthermore, as shown in FIGS. 2 and 3 , the main body 1 has a plurality of through-holes 1a formed therethrough in the thickness direction thereof, so as to correspond to the holding positions of the chips C within the attraction surface of the electrostatic carrier Cw. In one example, the holding positions of the chips C within the attraction surface of the electrostatic carrier Cw are arranged to correspond to the bonding positions of the chips C (mounting positions of the chips C) on the mounting surface of the wafer W.

[0018] The through holes 1a can be formed at any position on the attraction surface of the electrostatic carrier Cw. In one example, as shown in FIGS. 2 and 3, the through holes 1a may be formed one for each of the chips C held by the electrostatic carrier Cw, in other words, the same number as the number of chips C held by the electrostatic carrier Cw. Alternatively, as shown in FIGS. 4 and 5, the through holes 1a may be formed in a number corresponding to each of the chips C held by the electrostatic carrier Cw, in other words, a number greater than the number of chips C held by the electrostatic carrier Cw. In this case, the number, size, spacing, and arrangement of the through holes 1a are not particularly limited, but it is desirable to determine the number, size, and spacing so as to ensure the strength (rigidity) of the electrostatic carrier Cw to prevent deformation such as bending. In one example, the size of the through holes 1a is 0.5 mm to 1.0 mm, and the spacing (the grid width of the metal portion remaining between the through holes 1a) is 0.5 mm to 1.0 mm.

[0019] The insulating layer 2 is a layer formed on the surface of the main body 1 and is made of a flexible and insulating material, such as polyimide or EVA (ethylene-vinyl acetate copolymer). As shown in FIG. 2 , the insulating layer 2 forms the attraction surface of the electrostatic carrier Cw for the chips C. The insulating layer 2 has a thickness of, for example, 10 μm, sufficient to hold the chips on the electrostatic carrier Cw by electrostatic attraction. In one example, as shown in FIGS. 2 and 3 , the insulating layer 2 has multiple through holes 2 a (second through holes) formed at positions corresponding to the positions where the chips C are held within the attraction surface of the electrostatic carrier Cw, i.e., the positions where the multiple through holes 1 a are formed in the main body 1. The multiple through holes 2 a preferably have a smaller diameter than the multiple through holes 1 a formed in the main body 1. In the technology disclosed herein, "the insulating layer 2 is flexible" means that the elastic modulus of the insulating layer 2 on the main body 1 is 2 GPa or less, preferably 0.5 GPa or less. In the technology of the present disclosure, "the insulating layer 2 has insulating properties" means that the dielectric breakdown voltage of the insulating layer 2 on the main body 1 is 30 kV or more, preferably 40 kV or more.

[0020] Depending on the purpose of processing the chips C on the electrostatic carrier Cw, the insulating layer 2 may not necessarily have the plurality of through holes 2a formed therein (see also FIGS. 4 and 5 described above), or the plurality of through holes 2a may be formed with the same diameter as the plurality of through holes 1a formed in the main body 1. In other words, in the electrostatic carrier Cw according to the technology of the present disclosure, it is sufficient that the insulating layer 2 having insulating properties is at least formed on the surface of the main body 1 having conductivity and having the plurality of through holes 1a formed therein.

[0021] The insulating layer 2 is formed on the main body 1 by any method. For example, the insulating layer 2 may be a film formed by applying polyimide by spin coating to the surface of the main body 1. Alternatively, for example, the insulating layer 2 may be an insulating film formed by attaching an insulating film (for example, a polyimide film or a backgrind (BG) tape) to the surface of the main body 1.

[0022] The through holes 1a, 2a in the main body 1 and the insulating layer 2 may be formed by any method and at any timing. For example, when both the through hole 1a in the main body 1 and the through hole 2a in the insulating layer 2 are formed, the through hole 1a and the through hole 2a may be formed simultaneously by laser irradiation or the like after the insulating layer 2 is formed on the surface of a silicon substrate corresponding to the main body 1. Alternatively, the through hole 1a in the main body 1 and the through hole 2a in the insulating layer 2 may be formed independently, and then the insulating layer 2 may be attached to the main body 1 while aligning the through holes 1a and 2a. Furthermore, when the through hole 1a is formed only in the main body 1 and the through hole 2a is not formed in the insulating layer 2, the through hole 1a may be formed in the main body 1 by laser irradiation, punching, or the like, and then an insulating film may be attached to the main body 1.

[0023] The electrostatic carrier Cw according to the technique of the present disclosure is configured as described above, and attracts and holds the chips C on the attracting surface by generating an electrostatic (Coulomb) force between the electrostatic carrier Cw and the chips C. Details of the method for holding the chips C by the electrostatic carrier Cw will be described later.

[0024] The wafer W on which the chips C are mounted is a semiconductor wafer such as a silicon substrate or a glass substrate used in the semiconductor device manufacturing process. As shown in FIG. 6 , a device layer Dw including multiple devices is formed on the front surface Wa, which is the mounting surface for the chips C. In one example, the thickness of the wafer W is the same as or slightly larger than the electrostatic carrier Cw, e.g., 800 μm. The device layer Dw is diced into pieces approximately the same size as the chips C to be mounted, as shown in FIG. 6 . In other words, each of the diced device layers Dw on the mounting surface of the wafer W becomes the bonding position of the chips C on the wafer W (the mounting position of the chips C). In addition, a protective film Pw is formed on the front surface Wa of the wafer W, and the thickness of the protective film Pw is approximately the same as the thickness of the device layer Dw. In other words, the front surface Wa of the wafer W has exposed portions where each of the diced device layers Dw is exposed, and exposed portions of the protective film Pw between the device layers Dw.

[0025] The size of the device layer Dw does not necessarily have to be approximately the same as that of the chip C to be mounted, and may be larger or smaller than the chip C.

[0026] The wafer W is bonded to the chip C as described below, but prior to bonding to the chip C, various pretreatments for bonding are performed on the front surface Wa side of the wafer W. More specifically, a series of pretreatments including surface activation and hydrophilization are performed in advance on the front surface Wa side of the wafer W in one or more pretreatment devices (described below) arranged in the processing system 10.

[0027] 7, the processing system 10 has a configuration in which a carry-in / out station 11 and a processing station 12 are integrally connected. In the carry-in / out station 11, for example, FOUPs Ff, Fc, and Fw, each capable of accommodating a plurality of dicing frames F, a plurality of electrostatic carriers Cw, and a plurality of wafers W, are carried in and out between the station 11 and the outside. The processing station 12 is equipped with various processing devices for implementing a series of chip-on-wafer manufacturing processes, which will be described later.

[0028] The loading / unloading station 11 is provided with a FOUP mounting table 20. In the illustrated example, a plurality of FOUPs, for example, three FOUPs Ff, Fc, and Fw, are placed on the FOUP mounting table 20, aligned in a line in the Y-axis direction. Note that the number and arrangement of FOUPs Ff, Fc, and Fw placed on the FOUP mounting table 20 are not limited to those in this embodiment and can be determined arbitrarily.

[0029] A transfer device 30 is provided adjacent to the FOUP mounting table 20 on the positive side of the X-axis. The transfer device 30 is configured to be movable on a transfer path 31 extending in the Y-axis direction. The transfer device 30 also has, for example, two transfer arms 32, 32 that hold and transfer a dicing frame F, an electrostatic carrier Cw, and a wafer W (hereinafter, these may be collectively referred to as the "dicing frame F, etc."). Each transfer arm 32 is configured to be movable horizontally, vertically, around a horizontal axis, and around a vertical axis. Note that the configuration of the transfer arm 32 is not limited to this embodiment and may have any configuration. The transfer device 30 is configured to be able to transfer the dicing frame F, etc. to the FOUPs Ff, Fc, and Fw on the FOUP mounting table 20 and to a transition device 40, which will be described later.

[0030] In the loading / unloading station 11, a transition device 40 for transferring dicing frames F and the like to and from the processing station 12 is provided adjacent to the transfer device 30 on the positive side of the X axis of the transfer device 30.

[0031] The processing station 12 is provided with a transport device 50, a chip placement device 60, a protective film removal device 70, a surface modification device 80, a surface hydrophilization device 90, a pretreatment device 100, and a bonding device 110. The number and arrangement of these various processing devices are not limited to those in this embodiment, and can be determined as desired.

[0032] The transfer device 50 is provided on the positive side of the transition device 40 in the X-axis direction. The transfer device 50 is configured to be movable on a transfer path 51 extending in the X-axis direction. The transfer device 50 also has, for example, two transfer arms 52, 52 that hold and transfer a dicing frame F or the like. Each transfer arm 52 is configured to be movable horizontally, vertically, around a horizontal axis, and around a vertical axis, and is configured to be able to transfer a dicing frame F or the like to the transition device 40 in the carry-in / out station 11 and various processing devices in the processing station 12.

[0033] In the chip placement device 60, a plurality of chips C with their back surfaces Cb attached to the dicing tape T are arranged in a line with the protective film P on the front surface Ca facing upward on the attraction surface of the electrostatic carrier Cw, which serves as a relay member when mounting the chips C on the wafer W. That is, in the chip placement device 60, the chips C are transferred from the dicing tape T to the electrostatic carrier Cw without turning over the front and back surfaces of the chips C.

[0034] 8, a pickup area 60a and an arrangement area 60b are formed inside the chip placement device 60. In the pickup area 60a, the chips C are picked up from the dicing frame F. In the arrangement area 60b, the chips C are arranged on the electrostatic carriers Cw.

[0035] The pickup area 60 a is provided with a frame holding portion 61 , a push-up portion 62 , and a collet 63 .

[0036] The frame holding unit 61 has a holding surface for the dicing frame F on its upper surface and holds the dicing frame F transported by the transport device 50 with the plurality of chips C attached to the dicing tape T facing upward. The push-up unit 62 is disposed below the frame holding unit 61 and configured to be movable horizontally relative to the frame holding unit 61. As long as the frame holding unit 61 and the push-up unit 62 can move horizontally relative to each other, it is sufficient that at least one of the frame holding unit 61 and the push-up unit 62 is configured to be movable. As a result, the push-up unit 62 selectively pushes up one chip C from below among the plurality of chips C on the dicing tape T and lifts it up. The collet 63 is disposed above the frame holding unit 61 and holds one chip C pushed up by the push-up unit 62 from above, and transports the held chip C between the pickup area 60a and the arrangement area 60b.

[0037] The arrangement area 60b is provided with a carrier holding unit 64, a power supply unit 65, a charge removal unit 66, and an alignment mechanism 67.

[0038] The carrier holding section 64 has a holding surface for the electrostatic carriers Cw on its upper surface, and holds the electrostatic carriers Cw transported by the transport device 50 with the insulating layer 2, which is the attracting surface of the chips C, facing upward.

[0039] In one example, the power supply unit 65 is disposed below the carrier holding unit 64, and includes a power supply pin 65a that contacts the back side of the electrostatic carriers Cw on the carrier holding unit 64, i.e., the main body 1, to apply a voltage, a power supply source 65b that supplies power to the power supply pin 65a, and a ground wire 65c. In the chip placement device 60, the chips C are attracted and held on the attracting surface of the electrostatic carriers Cw by Coulomb force generated by supplying power from the power supply pin 65a to the main body 1. The principle of attraction of the chips C by the electrostatic carriers Cw will be described in detail later. The location of the power supply unit 65 is not limited to this, and it may be disposed outside the carrier holding unit 64, for example, to the side or above, as long as it can apply an appropriate voltage to the electrostatic carriers Cw.

[0040] In this embodiment, the power supply unit 65 has one power feed pin 65a. However, the power supply unit 65 may have a plurality of power feed pins 65a.

[0041] In one example, the charge removal unit 66 is disposed above the carrier holding unit 64, facing the holding surface of the electrostatic carrier Cw, and has an earth wire 66b for removing electricity (earthing) from the chips C on the electrostatic carrier Cw held by the carrier holding unit 64. In one example, the charge removal unit 66 is configured to be movable above the carrier holding unit 64, and can come into contact with and earth the chips C placed at any position on the electrostatic carrier Cw.

[0042] The arrangement and configuration of the charge removal unit 66 are not limited to this, and it can be located anywhere as long as it can properly remove charge from the chips C. For example, as shown in FIG. 9, the charge removal unit 66 may be configured by embedding a ground wire 66b inside the collet 63. In other words, the collet 63 that holds and transports the chips C and the charge removal unit 66 that grounds the chips C may be integrally configured. For example, as shown in FIG. 10, the charge removal unit 66 may be configured to cover the entire surface of the electrostatic carrier Cw on the carrier holding unit 64, so that it can simultaneously remove charge (ground) from multiple chips C on the electrostatic carrier Cw. Furthermore, for example, the pad portion of the collet 63 that holds and transports the chips C may be made of a conductor, and the ground wire 66b may be connected to the collet 63, thereby forming the charge removal unit 66 with the collet 63. In this case, it is desirable that the pad member of the collet 63 be made of a material having a resistance value (e.g., 10e6 Ω to 10e9 Ω) that allows proper charge removal from the chips C. If this resistance value is too low (less than 10e6 Ω), it may not be possible to properly neutralize the charge on the chip C. On the other hand, if the resistance value is too high (more than 10e9 Ω), abnormal discharge may occur when holding (neutralizing) the chip C, which may damage the held chip C or the collet 63.

[0043] The alignment mechanism 67 aligns the electrostatic carrier Cw held by the carrier holder 64 with the chip C held by the collet 63. More specifically, it aligns one chip C held by the collet 63 with the attracting and holding position of the chip C on the attracting surface of the electrostatic carrier Cw. The attracting and holding position of the chip C on the attracting surface of the electrostatic carrier Cw may be determined, for example, by the through-hole 2a formed in the insulating layer 2, or may be determined based on a previously acquired recipe, etc. The alignment mechanism 67 can also detect whether the chip C is appropriately positioned on the attracting surface of the electrostatic carrier Cw. More specifically, it can align the position of the chip C actually placed on the attracting surface of the electrostatic carrier Cw with the set attracting and holding position of the chip C within the attracting surface of the electrostatic carrier Cw. The alignment mechanism 67 includes, for example, a camera, a sensor, etc.

[0044] 8, the example has been described with reference to a configuration in which chips C on the dicing tape T are transferred one by one onto the electrostatic carrier Cw, but the chip placement device 60 may be configured to transfer multiple chips C onto the electrostatic carrier Cw simultaneously. In this case, multiple collets 63 may be placed above the frame holding unit 61, or a chip transport mechanism capable of picking up multiple chips C simultaneously may be provided.

[0045] The protective film removal device 70 removes the protective film P formed on the front surface side of the chip C. The configuration of the protective film removal device 70 is arbitrary, but in one example, the protective film removal device 70 can remove the protective film P formed on the chip C by supplying an etching chemical solution to the protective film P (wet etching process) or by irradiating the protective film P with laser light (ablation process).

[0046] In the surface modification device 80, for example, under a reduced pressure, oxygen gas or nitrogen gas serving as a processing gas is excited to form plasma and then ionized. The oxygen ions or nitrogen ions are irradiated onto the surface (device surface) of the device layer D exposed by removing the protective film P, and the device surface is subjected to plasma processing and modified.

[0047] In the surface hydrophilization device 90, pure water is supplied onto the electrostatic carriers Cw, more specifically onto the device surface that has been subjected to surface modification, while rotating the electrostatic carriers Cw held by, for example, a spin chuck. The supplied pure water then diffuses over the device surface, making the device surface hydrophilic.

[0048] In the pretreatment device 100, pretreatment, such as surface activation or hydrophilization, is performed on the surface of the wafer W (the surface of the device layer Dw) before bonding to the chip C. The pretreatment method for the surface of the wafer W is the same as the pretreatment method performed on the chip C in, for example, the surface modification device 80 or the surface hydrophilization device 90.

[0049] In the processing system 10 according to the present embodiment, the pretreatment for the chips C and the pretreatment for the wafer W are performed in different apparatuses. However, the pretreatment for the chips C and the pretreatment for the wafer W may be performed in the same processing apparatus. That is, for example, the pretreatment for the wafer W may be performed in the surface modification apparatus 80 and the surface hydrophilization apparatus 90. Also, in the processing system 10 according to the present embodiment, only one pretreatment apparatus 100 for performing the pretreatment for the wafer W is provided, and the surface activation treatment and the hydrophilization treatment are performed in the pretreatment apparatus 100. However, the surface activation treatment and the hydrophilization treatment may be performed in different apparatuses. That is, the processing system 10 may be provided with a surface modification apparatus (not shown) and a surface hydrophilization apparatus (not shown) for performing the pretreatment for the wafer W, instead of the pretreatment apparatus 100. Similarly, the surface modification apparatus 80 and the surface hydrophilization apparatus 90 for performing the pretreatment for the chips C may be integrated into one unit.

[0050] In the bonding device 110, a plurality of chips C attracted and held by electrostatic carriers Cw are bonded to the mounting surface of a wafer W on which the chips C are to be mounted.

[0051] As shown in FIG. 11, the bonding device 110 is provided with a carrier holder 111 , an air supply unit 112 , a wafer holder 113 , and an alignment mechanism 114 .

[0052] The carrier holding unit 111, which serves as the second carrier holding unit, has a holding surface for the electrostatic carrier Cw on its upper surface, and holds the electrostatic carrier Cw, which adsorbs and holds the chip C, which has been transported by the transport device 50 and has had the protective film P removed, surface modification treatment, and surface hydrophilization treatment performed, with the chip C facing upward.

[0053] The air supply unit 112 has a supply port 112a formed on the holding surface of the carrier holding unit 111 and an air supply source 112b connected to the end opposite the supply port 112a. The air supply unit 112 supplies air from the lower side of the carrier holding unit 111 toward the back surface Cb of the chip C held by the electrostatic carrier Cw through the through holes 1a and 2a. In the bonding device 110, by supplying air to the back surface Cb of the chip C in this manner, the chip C is lifted up from the attraction surface of the electrostatic carrier Cw, thereby detaching the chip C from the attraction surface of the electrostatic carrier Cw. The method of detaching the chip C will be described in detail below.

[0054] The wafer holding unit 113 as a substrate holding unit has a holding surface for a wafer W on which chips C are to be mounted on the lower surface, and holds the wafer W transported by the transport device 50 with the mounting surface for chips C facing downward. In one example, the wafer holding unit 113 is configured to be movable in the horizontal direction, the vertical direction, and around a horizontal axis, and can invert the top and bottom surfaces of the held wafer W and move the held wafer W relative to the electrostatic carrier Cw.

[0055] The alignment mechanism 114 aligns the electrostatic carriers Cw held by the carrier holder 111 with the wafer W held by the wafer holder 113. More specifically, it aligns the multiple chips C attracted and held by the electrostatic carriers Cw with the bonding positions of the chips C on the mounting surface of the wafer W, i.e., positions corresponding to the diced device layers Dw on the surface Wa of the wafer W. The alignment mechanism 114 includes, for example, a camera, a sensor, etc.

[0056] In the illustrated example, the carrier holding unit 111 is fixed to the bottom surface of the bonding apparatus 110 and the wafer holding unit 113 is disposed above it, but the carrier holding unit 111 may be fixed to the top surface of the bonding apparatus 110 and the wafer holding unit 113 may be disposed below it. In other words, in the bonding apparatus 110, the carrier holding unit 111 may hold the plurality of chips C attracted and held on the attraction surface of the electrostatic carrier Cw in a state facing downward, and further the wafer holding unit 113 may hold the wafer W in a state where the mounting surface of the chip C faces upward.

[0057] The processing system 10 described above is provided with a control device 120. The control device 120 is, for example, a computer equipped with a CPU, a memory, etc., and has a program storage unit (not shown). The program storage unit stores a program for controlling the chip-on-wafer manufacturing process in the processing system 10. Note that the program may be recorded on a computer-readable storage medium H and installed into the control device 120 from the storage medium H. Furthermore, the storage medium H may be temporary or non-temporary.

[0058] Although the processing system 10 according to one embodiment is configured as described above, other processing devices may be further provided in the processing system 10 depending on the purpose, or some processing devices may be provided outside the processing system 10 depending on the purpose. Specifically, for example, the processing system 10 may further be provided with various devices for thinning the silicon layer Si formed on the back surface Cb side of the chip C. Also, for example, the pre-processing device 100 for performing pre-processing on the wafer W may be omitted from the processing system 10, and the wafer W that has been pre-processed (surface activation processing and hydrophilization processing) outside the processing system 10 may be carried into the processing system 10 by the FOUP Fw.

[0059] Next, a chip-on-wafer manufacturing process performed in the processing system 10 configured as described above will be described. Fig. 12 is a flow diagram showing the main steps of the chip-on-wafer manufacturing process. Fig. 13 is a side view explanatory diagram schematically showing some steps of the chip-on-wafer manufacturing process.

[0060] First, the FOUPs Ff, Fc, and Fw, each housing a plurality of dicing frames F, electrostatic carriers Cw, and wafers W, are placed on the FOUP mounting table 20 of the carry-in / out station 11. As shown in Fig. 13(a), a dicing tape T, to which a plurality of chips C are affixed, is fixed to the dicing frame F housed in the FOUP Ff. The silicon layer Si on the back surface Cb side of the plurality of chips C is affixed to the dicing tape T.

[0061] Next, the transport device 30 removes the dicing frame F from the FOUP Ff and transports it to the transition device 40. The dicing frame F transported to the transition device 40 is then transported to the chip placement device 60 by the transport device 50. Simultaneously with this, or subsequently, the electrostatic carriers Cw from the FOUP Fc are transported to the chip placement device 60.

[0062] In the chip placement device 60, the chip C, with its back surface Cb attached to the adhesive surface of the dicing tape T, is placed at a position corresponding to the holding position in the attraction surface of the electrostatic carrier Cw so that the back surface Cb faces downward, as shown in Fig. 13(b), and is then attracted and held (step St1 in Fig. 12). An example of the operation of placing the chip C on the electrostatic carrier Cw in the chip placement device 60 will be described below (see also Fig. 8).

[0063] First, the frame holding unit 61 and the push-up unit 62 are moved horizontally relative to each other, and the push-up unit 62 is moved below one of the chips C attached to the dicing tape T. Then, the push-up unit 62 is used to selectively push up and lift one of the chips C from below (the back surface Cb side). Next, the front surface Ca of the pushed-up chip C is held from above by the collet 63. At this time, because a protective film P is formed on the front surface Ca side of the chip C, the holding, e.g., suction, of the collet 63 does not damage the device layer D. Next, the collet 63 holding the chip C is moved to a position corresponding to one suction holding position of the electrostatic carrier Cw on the carrier holding unit 64, and the chip C is placed (placed) on the suction surface of the electrostatic carrier Cw. The holding, e.g., suction, of the chip C by the collet 63 is then released. Next, the alignment mechanism 67 is used to detect whether the chip C has been properly placed at one suction holding position. If the detection result indicates that the chip C is properly positioned, the operation of placing the next chip C on the dicing tape T is started. On the other hand, if it indicates that the chip C is not properly positioned, the collet 63 is used to hold the placed chip C again, and the chip C is repositioned at one of the suction holding positions. Finally, the power supply pin 65a of the power supply unit 65 is brought into contact with the main body 1 of the electrostatic carrier Cw, and a voltage is applied to the electrostatic carrier Cw via the power supply pin 65a, and the generated Coulomb force causes the chip C to be attracted and held on the attraction surface of the electrostatic carrier Cw.

[0064] The electrostatic attraction of the chips C by the electrostatic carriers Cw will be described in more detail. When all the chips C are placed in the attraction holding positions of the electrostatic carriers Cw by the collet 63, a voltage (positive (+) charge in the illustrated example) is applied to the electrostatic carriers Cw via the power supply pin 65a, as shown in FIG. 14(a), causing the main body 1 of the electrostatic carriers Cw to be positively charged. When the main body 1 is positively charged, as shown in FIG. 14(b), charges of the opposite polarity (i.e., negative (-)) to the charges accumulated on the main body 1 accumulate on the back surface Cb of the chip C across the insulating layer 2, and charges of the same polarity (i.e., positive (+)) as the charges accumulated on the main body 1 accumulate on the front surface Ca of the chip C. Next, the earth wire of the charge removal unit 66 is brought into contact with the front surface Ca of the chip C (the side opposite the back surface Cb, which is the holding surface). 14C, the positive charge on the surface Ca of the chip C is neutralized (grounded), leaving behind a negative charge that attracts the positive charge on the main body 1. After that, when the neutralization unit 66 is retracted, a potential difference is generated across the insulating layer 2 between the main body 1 of the electrostatic carrier Cw and the chip C, generating an electrostatic force that attracts them, and the chip C is attracted to the attraction surface of the electrostatic carrier Cw by the electrostatic force.

[0065] In this way, in the technology of the present disclosure, the main body 1 of the electrostatic carrier Cw acts as a pseudo-unipolar electrode, and the chip C can be attracted and held on the attraction surface via the insulating layer 2 without forming an electrode wiring pattern inside the main body 1. In other words, the insulating layer 2 serves to maintain the charge accumulated in the main body 1 by insulating the charge applied to the main body 1.

[0066] Furthermore, in the electrostatic carrier Cw according to the technology of the present disclosure, the insulating layer 2 is formed from a flexible material with a small elastic modulus. After the chips C are placed on the electrostatic carrier Cw, before the chips C are attracted and held by electrostatic force, a gap is formed between the silicon layer Si of the chips C and the insulating layer 2 of the electrostatic carrier Cw. Due to the flexibility of the insulating layer 2, when the chips C are attracted to the insulating layer 2 by electrostatic force, the force of attraction of the chips C to the insulating layer 2 causes air to escape between the silicon layer Si of the chips C and the insulating layer 2, which serves as the attracting surface, and a pseudo-vacuum state is formed between the chips C and the insulating layer 2. As a result, in addition to electrostatic attraction by electrostatic force, a vacuum attraction force formed by the pseudo-vacuum state is generated between the electrostatic carrier Cw and the chips C, and a strong holding state is formed using both the electrostatic attraction force and the vacuum attraction force.

[0067] The electrostatic attraction of the chips C by the electrostatic carriers Cw is performed as described above. The operation of placing the chips C on the electrostatic carriers Cw may be performed sequentially, one by one, for each of the multiple chips C attached to the dicing tape T, or multiple chips C on the dicing tape T may be placed on the electrostatic carriers Cw simultaneously.

[0068] Furthermore, the timing of applying a voltage to the main body 1 and grounding the chips C are not limited to the above examples. That is, for example, a voltage may be applied to the main body 1 in advance before placing the chips C on the attraction surface (when there are no chips C on the electrostatic carriers Cw), or a voltage may be applied after placing the chips C on the attraction surface (after all the chips C are placed on the electrostatic carriers Cw) as shown in FIG. 14 . Furthermore, when multiple chips C are simultaneously placed on the electrostatic carriers Cw, a voltage may be applied to the main body 1 simultaneously with placing the chips C on the attraction surface. Furthermore, the chips C on the electrostatic carriers Cw may be neutralized (grounded) simultaneously with the application of a voltage after the chips C are placed on the attraction surface, or after the placement of the chips C on the attraction surface is completed and the voltage is applied to attract and hold the chips C. However, if a voltage is applied to the main body 1 when there are no chips C placed on the attraction surface, particles may be attracted to and adhere to the attraction surface due to the generated electrostatic force. In view of this, it is preferable that the timing of applying a voltage to the main body 1 be after the placement of the chips C on the attraction surface or be simultaneous with the placement of the chips C on the attraction surface. More preferably, it is desirable to apply a voltage to the main body 1 after all the chips C have been placed on the electrostatic carriers Cw.

[0069] As described above, the chip placement device 60 may use the alignment mechanism 67 to check whether the chips C are properly placed and may reposition the chips C, but when bonding chips C to a wafer W one by one in a bonding device 110 described below, high alignment precision is not required in the chip placement device 60, and it is sufficient that the chips C do not interfere with each other. In other words, when bonding chips C one by one in the bonding device 110, it is sufficient that the chips C and their mounting positions on the wafer W are aligned and bonded with high precision in the bonding process described below in the bonding device 110, and alignment precision in the chip placement device 60 is not required.

[0070] After the chips C are placed on the electrostatic carriers Cw, the electrostatic carriers Cw that attract and hold the chips C are then transported by the transport device 50 to the protective film removal device 70. As shown in FIG. 13C, the protective film removal device 70 removes the protective film P formed on the device layer D of the chips C (step St2 in FIG. 12).

[0071] Here, if a conductive chemical solution (e.g., an etching solution in the protective film removal device 70) is used to remove the protective film P, as described above, the charge accumulated on the electrostatic carriers Cw or the chips C may leak through the conductive chemical solution, potentially resulting in a loss of the electrostatic attraction force of the chips C to the electrostatic carriers Cw. In this regard, the electrostatic carriers Cw according to the technology disclosed herein generate a vacuum attraction force in addition to the electrostatic attraction force between the electrostatic carriers Cw and the chips C, as described above, to attract and hold the chips. As a result, even if the electrostatic attraction force between the electrostatic carriers Cw and the chips C is lost, the electrostatic carriers Cw according to the technology disclosed herein can maintain the attraction and holding of the chips C by the vacuum attraction force. This effect also applies to the surface modification treatment and hydrophilization treatment described below.

[0072] Furthermore, when the protective film P is removed while the chips C are attached to the dicing tape T, as in the conventional method, the dicing tape T holds the chips C with the adhesive side facing up, which causes wear on the dicing tape T, making it impossible to maintain the chip C or to reuse the dicing tape T. In this regard, the chip-on-wafer manufacturing process according to the technology disclosed herein removes the protective film P from chips C held by an electrostatic carrier Cw instead of the dicing tape T. In this embodiment, the electrostatic carrier Cw is composed of a main body 1 made of a chemical-resistant material such as silicon or aluminum and an insulating layer 2 made of a chemical-resistant material such as a polyimide film or backgrind tape. Therefore, wear on the electrostatic carrier Cw during the removal of the protective film P is suppressed compared to wear on the dicing tape T. This allows the dicing tape T fixed to the dicing frame F to be reused, and the electrostatic carrier Cw can be reused repeatedly. This effect also applies to the surface modification treatment and hydrophilization treatment described below.

[0073] Next, the electrostatic carriers Cw holding the chips C from which the protective film P has been removed are transported by the transport device 50 to the surface modification device 80. In the surface modification device 80, as shown in Fig. 13(d), the device surfaces exposed on the surface Ca side of the chips C are modified by plasma treatment (step St3 in Fig. 12).

[0074] Next, the electrostatic carrier Cw holding the chip C whose device surface has been modified is transported by the transport device 50 to the surface hydrophilization device 90. In the surface hydrophilization device 90, as shown in FIG. 13( e), hydroxyl groups (silanol groups) are attached to the device surface of the chip C modified in the surface modification device 80, thereby hydrophilizing the device surface. The electrostatic carrier Cw and the chip C are also washed with the pure water (step St4 in FIG. 12 ).

[0075] Following, simultaneously with, or prior to the surface modification treatment of the chips C in the surface modification apparatus 80 in step St3 and the hydrophilization treatment of the chips C in the surface hydrophilization apparatus 90 in step St4, the wafers W in the FOUP Fw are transferred to the pretreatment apparatus 100. In the pretreatment apparatus 100, the device layer Dw on the front surface Wa of the wafer W is subjected to the surface modification treatment and hydrophilization treatment, similar to the surface modification treatment and hydrophilization treatment on the chips C (steps St3-2 and St4-2 in FIG. 12 ).

[0076] Next, the electrostatic carrier Cw holding the chip C whose device surface has been hydrophilized is transported to the bonding device 110 by the transport device 50. Simultaneously or subsequently, the wafer W whose front surface Wa side (device layer Dw) has been hydrophilized is transported to the bonding device 110.

[0077] 13(f), the bonding apparatus 110 overlaps the plurality of chips C on the electrostatic carrier Cw with the mounting surface (pretreated surface Wa) of the wafer W on which the chips C are to be mounted, and then presses the chips C from above and below to bond the chips C to the wafer W (so-called fusion bonding) (step St5 in FIG. 12). An example of the bonding operation of the chips C to the wafer W in the bonding apparatus 110 will be described below (see also FIG. 11).

[0078] First, an electrostatic carrier Cw that attracts and holds a plurality of chips C is placed on the carrier holder 111 with its attracting surface facing up, i.e., with the plurality of chips C facing upward. Next, a wafer holder 113 that holds a wafer W is placed above the electrostatic carrier Cw. The wafer W is held by the wafer holder 113 with its front surface Wa, which is the mounting surface of the pre-processed chips C, facing downward. At this time, the wafer W held by the wafer holder 113 is aligned by an alignment mechanism 114 so that each of the diced device layers Dw on the mounting surface of the wafer W corresponds to the positions of the plurality of chips C on the electrostatic carrier Cw. The chip placement device 60 performs high-precision alignment and repositioning of the chips C relative to the electrostatic carrier Cw in order to align the device layer Dw on the wafer W with the chips C on the electrostatic carrier Cw.

[0079] Next, the chips C on the electrostatic carrier Cw held by the carrier holder 111 and the device layer Dw on the wafer W held by the wafer holder 113 are pressed from above and below to bond the chips C and the device layer Dw. At this time, because the device surfaces of the device layer Dw of the wafer W and the chips C on the electrostatic carrier Cw have been modified, van der Waals forces (intermolecular forces) are first generated between the device layer Dw and the device surfaces of the chips C, bonding the device layer Dw of the wafer W and the chips C on the electrostatic carrier Cw. Furthermore, because the device surfaces of the device layer Dw and the chips C have been hydrophilized, the hydrophilic groups between the device layer Dw and the chips C form hydrogen bonds (intermolecular forces), firmly bonding the device layer Dw of the wafer W and the chips C on the electrostatic carrier Cw.

[0080] When the device layer Dw of the wafer W and the chips C on the electrostatic carrier Cw are bonded, air pressure is applied from the supply port 112a of the air supply unit 112 through the through holes 1a and 2a to the back surface Cb of the chips C on the electrostatic carrier Cw, thereby reducing the adhesion between the chips C on the attraction surface of the electrostatic carrier Cw and the insulating layer 2. More specifically, when air is supplied to the back surface Cb of the chips C, the through holes 2a formed in the insulating layer 2 are blocked by the chips C, and therefore, as shown in FIG. 15 , the insulating layer 2 expands with its apex at the center of the through hole 1a formed in the main body 1 directly below the chips C. As a result, the chips C maintain adhesion to the insulating layer 2 at the center of the chips C corresponding to the center of the through hole 1a, while the chips C float from the insulating layer 2 at the outer periphery of the chips C corresponding to the peripheral portion of the through hole 1a. This reduces the adhesion between the chips C and the insulating layer 2, more specifically, it becomes lower than the bonding strength between the chips C and the device layer Dw of the wafer W.

[0081] 16 , even if no through hole 2a is formed in the insulating layer 2, the adhesive force between the chip C and the insulating layer 2 can be reduced by supplying air to the back surface Cb of the chip C through the through hole 1a. Furthermore, according to the technology disclosed herein, both electrostatic and vacuum suction forces act between the chip C and the insulating layer 2 as described above. Therefore, even if the through hole 2a in the insulating layer 2 and the through hole 1a in the main body 1 have the same diameter as described above, the chip C is prevented from scattering due to breakdown of the vacuum suction between the chip C and the insulating layer 2 (air being blown upward from the through hole 1a below the chip C) when the adhesive force between the chip C and the insulating layer 2 is reduced by supplying air.

[0082] Next, the wafer holder 113 holding the wafer W is raised. As a result, the adhesion between the chips C and the insulating layer 2 is reduced, and the chips C are completely detached from the insulating layer 2. Finally, the wafer holder 113 is rotated around a horizontal axis, thereby inverting the front and back surfaces of the wafer W. In other words, the mounting surface of the wafer W to which multiple chips C are bonded faces upward.

[0083] The bonding operation of the chip C to the wafer W according to the embodiment is performed as described above.

[0084] As described above, the electrostatic carrier Cw that attracts and holds the plurality of chips C may be held with its attracting surface facing downward, i.e., with the plurality of chips C facing downward, and the wafer W may be placed below the electrostatic carrier Cw. In other words, the vertical arrangement of the electrostatic carrier Cw and the wafer W is not limited to the example shown in the figure, and they may be held and transported upside down.

[0085] Once the plurality of chips C are bonded to the device layer Dw of the wafer W, the wafer W on which the chips C are mounted is then transferred by the transfer device 50 to the transition device 40, and then further transferred by the transfer device 30 to the FOUP Fw of the FOUP mounting table 20. Similarly, the electrostatic carriers Cw from which the chips C have been detached are transferred by the transfer device 50 to the transition device 40, and then further transferred by the transfer device 30 to the FOUP Fc of the FOUP mounting table 20. In this way, a series of chip-on-wafer manufacturing processes in the processing system 10 is completed.

[0086] The FOUPs into which the dicing frame F, electrostatic carrier Cw, and wafer W are recovered do not necessarily have to be the same FOUPs that housed the dicing frame F, etc. when they were carried in. That is, for example, the FOUPs that housed the dicing frame F, etc. may carry out different members, or new FOUPs, etc. for carrying out the dicing frame, etc. may be carried into the processing system 10.

[0087] According to the above embodiment, in a series of chip-on-wafer manufacturing processes, the electrostatic carrier Cw, which serves as a relay member for transferring the chips C from the dicing tape T to the wafer W, can be configured with a simple structure in which only the insulating layer 2 is formed on the surface of the conductive main body 1. This eliminates the need to configure an electrode wiring pattern inside the conductive main body as in conventional electrostatic carriers, and therefore the degree of freedom in forming the through holes used to release the chips C is greatly improved, and the effort and cost associated with configuring the electrostatic carrier Cw can be greatly reduced.

[0088] More specifically, in the structure of conventional electrostatic carriers (electrostatic holding mechanisms), through-holes required for releasing a held object had to be formed directly below the held object and positioned to avoid the wiring pattern of the embedded electrode part for attracting and holding the held object. Furthermore, this required changing the position of the through-holes or the wiring pattern depending on the number and position of the held objects, which required a great deal of effort and cost. In contrast, the electrostatic carrier Cw according to the technology disclosed herein does not require an electrode wiring pattern to be formed inside the conductive main body, so the number and position of the through-holes can be determined arbitrarily.

[0089] Furthermore, with the electrostatic carrier Cw according to the technology of the present disclosure, the insulating layer 2 formed on the surface of the main body 1 is made of a flexible material with a low elastic modulus, which allows air to be expelled from between the insulating layer 2 and the chip C, generating a pseudo-vacuum suction force in addition to the electrostatic suction force generated by applying a voltage to the main body 1, thereby enabling the chip C to be more appropriately attracted and held.

[0090] Furthermore, since it is possible to generate a vacuum suction force in addition to an electrostatic suction force, even if a conductive liquid is supplied onto the electrostatic carrier Cw, for example, when removing the protective film P, and the electrostatic suction force between the electrostatic carrier Cw and the chip C is lost, the holding force for the chip C can be maintained appropriately.

[0091] Furthermore, according to the electrostatic carrier Cw of this embodiment, as described above, the insulating layer 2 formed on the surface of the main body 1 is made of a flexible material with a low elastic modulus, so that the insulating layer 2 can be easily expanded by supplying air when the chip C is detached, and the adhesive force between the chip C and the insulating layer 2 can be appropriately reduced.

[0092] As described above, the electrostatic carriers Cw according to this embodiment are configured to have approximately the same diameter as the wafer W on which the chips C are mounted. This allows the electrostatic carriers Cw to be transported and processed using the same transport device and processing device as the wafer W, and there is no need to provide a new device for transporting and processing the electrostatic carriers Cw.

[0093] In the bonding apparatus 110 according to the above embodiment, the electrostatic carrier Cw on the carrier holding portion 111 and the wafer W on the wafer holding portion 113 are placed opposite each other and brought into contact with each other, thereby simultaneously mounting multiple chips C on the wafer W, but the mounting of chips C on the wafer W may also be performed one by one.

[0094] 17, a bonding apparatus 200 according to another embodiment for mounting chips C one by one on a wafer W is formed with a desorption area 200a, a bonding area 200b, and a delivery area 200c. In the desorption area 200a, the chips C are picked up from the electrostatic carriers Cw. In the bonding area 200b, the chips C are bonded to the wafer W. In the delivery area 200c, the chips C are delivered between the desorption area 200a and the bonding area 200b.

[0095] In the separation area 200a, a carrier holding section 201 as a second carrier holding section, an air supply section 202, and a first collet 203 are provided.

[0096] The carrier holding unit 201 and the air supply unit 202 have substantially the same configuration as the carrier holding unit 111 and the air supply unit 112 of the bonding apparatus 110 according to the above embodiment. The air supply unit 202 has a supply port 202a and an air supply source 202b, and supplies air through the through holes 1a and 2a toward the back surface Cb side of the chip C held by the electrostatic carrier Cw.

[0097] In the bonding device 200 according to another embodiment, air can be supplied from the air supply source 202b independently to each of the chips C attracted and held on the electrostatic carriers Cw, in other words, independently to each of the plurality of through-holes 1a formed in the main body 1. In this case, it is desirable that each of the air supply units 202 is provided with a control valve (not shown) for independently supplying air to each of the chips C.

[0098] Note that the bonding apparatus 200 according to another embodiment may be configured so that air can be supplied from the air supply source 202b independently to each of the chips C attracted and held on the electrostatic carriers Cw. For example, as shown in Fig. 17, a common air supply source 202b may be connected to multiple supply ports 202a, or as shown in Fig. 18, one air supply source 202b may be connected to each of the multiple supply ports 202a. In other words, the bonding apparatus 200 may be provided with any number of air supply sources 202b, one or more.

[0099] The first collet 203 is disposed above the carrier holding part 201, and holds the chip C whose outer periphery has been lifted due to the decrease in adhesion between the first collet 203 and the insulating layer 2 caused by the supply of air from the air supply part 202, and releases the chip C from the electrostatic carrier Cw, and transports the held chip C between the release area 200 a and the delivery area 200 c. In one example, the first collet 203 is configured to be rotatable about a horizontal axis, and as shown in the figure, the top and bottom surfaces of the held chip C can be inverted.

[0100] In the bonding apparatus 200, the upper surface of the chip C held by the first collet 203 is the device surface where the device layer D is exposed by removing the protective film P as described above. Therefore, the first collet 203 must hold the chip C without damaging this exposed device surface. Specifically, the first collet 203 is preferably a non-contact chuck that can hold the chip C from above without contact, for example, by utilizing the Bernoulli effect or ultrasonic squeeze effect. Alternatively, instead of holding the upper surface (device surface) of the chip C, the first collet 203 may be configured to clamp and hold the side surface of the chip C, which has been lifted by supplying air, for example.

[0101] In the bonding area 200b, a wafer holder 204, a second collet 205, and an alignment mechanism 206 are provided.

[0102] The wafer holding part 204 as a substrate holding part has a holding surface for the wafer W on its upper surface, and holds the wafer W transported by the transport device 50 with the forming surface of the device layer Dw, which is the mounting surface of the chip C, facing upward.

[0103] The second collet 205 is disposed above the wafer holding part 204, holds the chip C held by the first collet 203 from above, and transports the held chip C between the bonding area 200b and the delivery area 200c. Note that in one example, the second collet 205 may be configured to be rotatable about a horizontal axis instead of the first collet 203. In this case, the second collet 205 holds the chip C held by the first collet 203 from below in the delivery area 200c, inverts the top and bottom surfaces of the chip C, and then bonds the chip C to the wafer W in the bonding area 200b.

[0104] In the bonding device 200, the back surface Cb side of the chip C held by the second collet 205 does not have an exposed device layer, unlike the front surface Ca side held by the first collet 203. Therefore, the second collet 205 does not necessarily have to be configured by a non-contact chuck or the like, unlike the first collet 203.

[0105] In one example, the alignment mechanism 206 has a configuration similar to that of the alignment mechanism 67 of the chip placement device 60. That is, the alignment mechanism 206 includes, for example, a camera, a sensor, etc., and aligns the wafer W held by the wafer holding part 204 with the chip C held by the second collet 205.

[0106] The bonding apparatus 200 according to the second embodiment is configured as described above. An example of a method for bonding a chip C to a wafer W using the bonding apparatus 200 will now be described.

[0107] When bonding chips C to a wafer W in the bonding apparatus 200, first, an electrostatic carrier Cw that attracts and holds a plurality of chips C is placed on the carrier holder 201 with the plurality of chips C facing upward. Next, a wafer W on which the chips C are to be mounted is placed on the wafer holder 204 with the surface on which the device layer Dw is formed facing upward.

[0108] Next, air is selectively supplied to the through-hole 1a corresponding to one chip C to be removed, expanding the insulating layer 2 and pushing up the chip C from below, causing it to float up. Next, the floated chip C is held and lifted by the first collet 203 so as not to damage the device surface. Note that the holding of the chip C by the first collet 203 may be performed before or simultaneously with the air lifting of the chip C. Next, the first collet 203 is rotated around a horizontal axis, thereby inverting the front and back surfaces of the chip C. In other words, the back surface Cb (the surface facing the device surface) of the chip C held by the first collet 203 is brought into a state where it faces upward. Next, the back surface Cb of the chip C held by the first collet 203 is held from above by the second collet 205, and then the first collet 203's hold of the front surface Ca of the chip C is released. In other words, the chip C is transferred from the first collet 203 to the second collet 205. Next, the second collet 205 holding the chip C is moved to a position corresponding to one device layer Dw on the mounting surface of the wafer W. The alignment mechanism 206 is used to appropriately align the second collet 205 with the device layer Dw. Finally, the device surface of the chip C held by the second collet 205 and one device layer Dw of the wafer W are pressed from above and below to bond the chip C and the device layer Dw.

[0109] The bonding operation of the chips C to the wafer W according to another embodiment is performed as described above. The bonding operation of the chips C is performed independently and continuously for each of the plurality of chips C attracted and held on the electrostatic carrier Cw.

[0110] In the above example, air is selectively supplied to the through hole 1a corresponding to one chip C to be removed, and only that chip C is pushed up from below and lifted up. However, if it is not possible to supply air independently to each of the through holes 1a (for example, if no control valve is provided), air may be supplied to all of the through holes 1a in advance, causing all of the chips C to be lifted up, and the chips C may then be picked up sequentially with the first collet 203.

[0111] Alternatively, for example, as in the carrier holding unit 301 shown in FIG. 19 , an air supply unit 310 may be arranged in which only one supply port 311 is arranged so as to be common to all of the multiple chips C. An air supply source 312 is connected to the supply port 311. In this case, it is desirable that the carrier holding unit 301 and the one supply port 311 are configured to be movable relatively in the horizontal direction. As long as the carrier holding unit 301 and the supply port 311 can be moved relatively in the horizontal direction, it is sufficient that at least one of the carrier holding unit 301 and the supply port 311 is configured to be movable.

[0112] In the carrier holding unit 301, air may be supplied from the supply port 311 to the entire lower surface of the electrostatic carrier Cw held in the carrier holding unit 301, and all of the multiple chips C held by the electrostatic carrier Cw may be detached from the electrostatic carrier Cw at once. Alternatively, the carrier holding unit 301 and the supply port 311 may be moved relatively in the horizontal direction, and the supply port 311 may be positioned below one of the multiple chips C, thereby selectively supplying air to that one chip C and selectively detaching that one chip C from the electrostatic carrier Cw.

[0113] In the bonding apparatus according to the above embodiment, the chips C held by the electrostatic carriers Cw are detached by supplying air from an air supply unit to the electrostatic carriers Cw on the carrier holding unit. However, the method of detaching the chips C held by the electrostatic carriers Cw is not limited to this. For example, instead of supplying air, a lift pin (not shown) may be inserted into the through hole 1a from below the electrostatic carrier Cw, with the tip of the lift pin being configured to be able to protrude and retract from the upper surface of the main body 1 of the electrostatic carrier Cw (the upper end of the through hole 1a). In this case, the lift pin abuts against the lower surface of the chips C held by the electrostatic carriers Cw through the through hole 1a, thereby lifting the chips C and detaching them from the electrostatic carriers Cw.

[0114] Furthermore, in the bonding apparatus according to the above embodiments, the chips C were detached by supplying air to the underside of the electrostatic carrier Cw from below or by contacting the lift pins with the underside of the chips C. However, the chips C may be detached from the electrostatic carrier Cw using only the upper collet (corresponding to the first collet in the above embodiments) without applying force from the underside of the chips C on the electrostatic carrier Cw. Specifically, possible stresses acting on the chips C on the electrostatic carrier Cw include, in addition to the stress caused by the collet, centrifugal force caused by the rotation of the spin chuck in the surface modification device 80 or the surface hydrophilization device 90, stress caused by the flow of the conductive liquid, and inertial force caused by the transport of the electrostatic carrier Cw. Of these, the stress caused by the collet's pickup acts on the chips C in the up-down direction (vertical direction), while the other centrifugal force, flow force, and inertial force are shear forces acting horizontally. From this perspective, for example, by making the holding force of the chip C by the electrostatic carrier Cw strong in the horizontal direction (against shear stress) and weak in the vertical direction (against tensile force), it may be possible to detach the chip C from the electrostatic carrier Cw simply by holding it with the collet, without supplying air or lifting it with a lift pin as described above.

[0115] The embodiments disclosed herein should be considered illustrative in all respects and not restrictive. The above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims. For example, the components of the above-described embodiments may be arbitrarily combined. Such an arbitrary combination naturally provides the functions and effects of each of the components involved in the combination, as well as other functions and effects that would be apparent to a person skilled in the art from the description herein. Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology disclosed herein may provide other effects that would be apparent to a person skilled in the art from the description herein, in addition to or in place of the above-described effects.

[0116] For example, in the above embodiment, the chip placement device 60 and the bonding device 110 are arranged in the same processing system 10, but the chip placement device 60 and the bonding device 110 may be arranged in different processing systems. In other words, a first processing system for placing the chips C on the dicing frame F on the electrostatic carrier Cw and a second processing system for bonding the chips C on the electrostatic carrier Cw to the wafer W may be configured independently.

[0117] 1 Main body portion 1a Through hole 2 Insulating layer Cw Electrostatic carrier

Claims

1. A chip placement device, comprising: a chip transfer carrier; and a chip transfer mechanism configured to pick up chips and arrange them side by side on the adsorption surface of the chip transfer carrier. The chip transfer carrier includes: a main body portion having a plurality of through holes in the thickness direction; and a film formed on the surface of the main body portion to cover the plurality of through holes. The chip transfer mechanism is configured to: when arranging the chips on the chip transfer carrier, discharge air from between the film of the chip transfer carrier and the chips, thereby generating a vacuum adsorption force between the chip transfer carrier and the chips. A chip placement device.

2. A chip placement device configured to pick up chips and arrange them side by side on the adsorption surface of a chip transfer carrier, comprising: the chip transfer carrier is an electrostatic carrier having: a main body portion having conductivity and a plurality of through holes in the thickness direction; and an insulating film formed on the surface of the main body portion to cover the plurality of through holes; a carrier holding portion having the holding surface of the electrostatic carrier on the upper surface; a power supply portion configured to supply power to the main body portion of the electrostatic carrier on the carrier holding portion; and a static elimination portion configured to contact the chips on the electrostatic carrier and ground them. The static elimination portion has a ground wire that contacts the chips and faces the holding surface of the electrostatic carrier in the carrier holding portion.

3. The chip placement device according to claim 2, further comprising a collet configured to pick up the chips and transfer them to the electrostatic carrier on the carrier holding portion, wherein the ground wire that contacts the chips in the static elimination portion is integrally formed with the collet.

4. The chip placement device according to claim 2, wherein the static elimination portion is constituted by a collet configured to pick up the chips and transfer them to the electrostatic carrier on the carrier holding portion, and the collet has a resistance value of 10e6Ω to 10e9Ω.

5. The chip placement device according to claim 2, further comprising a chip transfer mechanism configured to simultaneously hold a plurality of the chips and transfer them to the electrostatic carrier on the carrier holding portion.

6. The chip placement device according to claim 2, wherein the static elimination portion is arranged above the carrier holding portion to cover the entire surface of the electrostatic carrier, and simultaneously contacts a plurality of the chips on the electrostatic carrier to simultaneously ground the plurality of chips.

7. The chip placement device according to any one of claims 1 to 6, wherein the main body is a conductor substrate made of silicon.

8. The chip placement device according to any one of claims 1 to 6, wherein the film is made of a material having an elastic modulus of 2 GPa or less, preferably 0.5 GPa or less.

9. The chip placement device according to claim 8, wherein the film is a polyimide film formed on the surface of the main body by spin coating.

10. The chip placement device according to claim 8, wherein the film is an insulating film formed by attaching a polyimide film or a back grind tape to the surface of the main body.

11. A processing system having the chip placement device according to any one of claims 1 to 10 and a bonding device, wherein the bonding device is configured to bond the chip adsorbed and held by the chip transfer carrier to a substrate to which the chip is to be mounted.

12. The bonding device includes a carrier holding portion that holds the chip transfer carrier, a substrate holding portion that holds the substrate, and a gas supply portion that supplies gas toward the through hole formed in the main body portion of the chip transfer carrier on the carrier holding portion. The processing system according to claim 11.

13. The bonding device includes a carrier holding portion that holds the chip transfer carrier, a substrate holding portion that holds the substrate, and a lift pin that is inserted into the through hole formed in the main body portion of the chip transfer carrier on the carrier holding portion.

14. The processing system according to claim 12, wherein the chip transfer carrier and the gas supply portion are configured to be relatively movable.

15. The processing system according to claim 13, wherein the chip transfer carrier and the lift pin are configured to be relatively movable.

16. The processing system according to claim 11, further comprising a surface modification device that modifies the surface of the chip adsorbed and held by the chip transfer carrier.

17. The processing system according to claim 11, further comprising a surface hydrophilization device that hydrophilizes the surface of the chip adsorbed and held by the chip transfer carrier.

18. A processing method for processing a chip, comprising: applying power to the main body portion of the electrostatic chuck in the chip placement device according to any one of claims 2 to 5 to charge a plurality of the chips and charge the main body portion. A processing method including bringing a ground wire into contact with the chip to generate an electrostatic force between the chip and the main body portion.

19. Power supply to the main body portion is performed prior to the placement of the chip on the electrostatic carrier, The processing method according to claim 18, wherein contact of the ground wire with the chip is performed after the placement of the chip on the electrostatic carrier.

20. The processing method according to claim 18, wherein power supply to the main body portion and contact of the ground wire with the chip are performed after the placement of the chip on the electrostatic carrier.

21. The processing method according to claim 18, wherein contact of the ground wire with the chip is performed simultaneously for a plurality of the chips arranged on the electrostatic carrier.