Semiconductor device and production method for semiconductor device

Abstract

A semiconductor device (100) comprises a semiconductor substrate (10), an emitter electrode (52), and a polyimide protection film (150). The semiconductor substrate has: an active part (120) that has alternating transistor parts (70) and diode parts (80); and a plurality of trench parts (30, 40) that extend in the extension direction of the transistor parts and the diode parts. The emitter electrode is provided above a front surface of the semiconductor substrate, and the protection film is provided on a top surface of the emitter electrode. The diode parts have a lifetime control region (85) that includes a lifetime killer that has been irradiated from the front surface side of the semiconductor substrate. The active part has protected regions (151-1) at which the protection film is provided and unprotected regions (152-2) at which the protection film is not provided. The diode parts are in the unprotected regions, and the protected regions are at the transistor parts.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Conventionally, in a semiconductor device in which a transistor section such as an insulated gate bipolar transistor (IGBT) and a diode section are formed on the same substrate, a technique has been known in which a particle beam such as helium ions is irradiated at a predetermined depth position in the semiconductor substrate to provide a lifetime control region including a lifetime killer (see, for example, Patent Document 1). Also, a semiconductor device has been described in which a protective film made of polyimide resin formed in a cross pattern is provided on the surface of an element electrode made of an aluminum thin film (see, for example, Patent Document 2). [Prior Art Literature] [Patent Document] [Patent Document 1] JP 2017-135339 A [Patent Document 2] JP 2009-38140 A Problem to be solved

[0003] When light ions such as helium ions are irradiated from the front surface side of a semiconductor substrate, the range of the light ions in the semiconductor substrate varies depending on whether or not polyimide is present. General disclosure

[0004] A first aspect of the present invention provides a semiconductor device, comprising: a semiconductor substrate having an active section in which transistor sections and diode sections are alternately arranged, the semiconductor substrate having a plurality of trench sections extending in the direction of extension of the transistor sections and the diode sections, an emitter electrode provided above a front surface of the semiconductor substrate, and a polyimide protective film provided on an upper surface of the emitter electrode, the diode section having a lifetime control region including a lifetime killer irradiated from the front surface side of the semiconductor substrate, the active section having a protected region provided with the protective film and an unprotected region not provided with the protective film, the diode section being included in the unprotected region and the protected region being included in the transistor section.

[0005] The width of the transistor portion in the trench arrangement direction may be 300 μm or more and 2000 μm or less.

[0006] The width of the diode portion in the trench arrangement direction may be 200 μm or more and 2000 μm or less.

[0007] The width of the protection region in the trench arrangement direction may be 100 μm or more and 1800 μm or less.

[0008] In the trench arrangement direction, the distance between the protection region and the diode portion may be equal to or greater than the thickness of the semiconductor substrate.

[0009] The lifetime control region is provided so as to extend from the diode portion to at least a portion of the transistor portion in the trench arrangement direction, and the distance by which the lifetime control region extends in the transistor portion in the trench arrangement direction may be 80% or more and 250% or less of the thickness of the semiconductor substrate.

[0010] The thickness of the semiconductor substrate may be 50 μm or more and 150 μm or less.

[0011] The lifetime control region may be provided only in the non-protected region, and the distance between the protected region and the lifetime control region in the trench arrangement direction may be 20 μm or more and 1800 μm or less.

[0012] The emitter electrode may further include a first plating portion and a second plating portion provided on the upper surface of the emitter electrode and sandwiching the protective film therebetween, and the emitter electrode may extend below the protective film, the first plating portion, and the second plating portion.

[0013] The protective film may have a first protective film and a second protective film sandwiching the first plating portion therebetween, and the thicknesses of the first protective film and the second protective film may be greater than the thickness of the first plating portion.

[0014] The unprotected area may include a first unprotected area and a second unprotected area, and the protected area may be sandwiched between the first unprotected area and the second unprotected area.

[0015] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of: forming an active section in a semiconductor substrate, the active section including transistor sections and diode sections arranged alternately; forming a plurality of trenches in the semiconductor substrate, the trenches extending in a direction in which the transistor sections and the diode sections extend; forming an emitter electrode above a front surface of the semiconductor substrate; forming a polyimide protective film on an upper surface of the emitter electrode; and irradiating the diode section with a lifetime killer from the front surface side of the semiconductor substrate to form a lifetime control region, the active section having, in a top view, a protected region where the protective film is provided and an unprotected region where the protective film is not provided, the diode section being included in the unprotected region and the protected region being included in the transistor section.

[0016] The lifetime killer may be irradiated through a resist disposed above the protective film, and the width of the resist may be larger than the width of the protective film in the trench arrangement direction.

[0017] The resist may be disposed so as to cover at least the entire protective film when viewed from above.

[0018] In the trench arrangement direction, the distance between an end of the resist and an end of the protective film may be 0 μm or more and 1800 μm or less.

[0019] The resist may be disposed in the transistor portion at a distance from the diode portion, and the distance between the diode portion and the resist in the trench arrangement direction may be 80% or more and 250% or less of the thickness of the semiconductor substrate.

[0020] In the trench arrangement direction, the distance between the diode portion and the protection region may be equal to or greater than the thickness of the semiconductor substrate.

[0021] The thickness of the semiconductor substrate may be 50 μm or more and 150 μm or less.

[0022] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0023] 1 shows an example of the arrangement of each component on the front surface of the semiconductor device 100 according to the embodiment. 2 shows an example of the arrangement of the emitter electrode 52 provided on the front surface of the semiconductor device 100. 3 shows an example of the arrangement of the protective film 150 provided on the front surface of the semiconductor device 100. 4 shows an example of the a-a' cross section of FIG. 3. 5 shows an example of a top view of the semiconductor device 100. 6 shows a schematic diagram of the structure of the front surface of the semiconductor substrate 10 near the protective region 151-1. 7 shows an example of the bb' cross section of FIG. 8. 9 shows an example of the manufacturing method of the semiconductor device 100.

[0024] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0025] In this specification, one side of a semiconductor substrate in a direction parallel to the depth direction is referred to as the "front" or "top," and the other side is referred to as the "back" or "bottom." Of the two main surfaces of a substrate, layer, or other member, one is referred to as the top surface, and the other is referred to as the bottom surface. The directions of "front," "top," "back," and "bottom" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0026] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a particular direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis. In this specification, viewing from the +Z-axis direction may be referred to as a top view.

[0027] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0028] In this specification, the conductivity type of a doped region doped with impurities is described as P-type or N-type. However, the conductivity types of each doped region may be opposite polarities. Furthermore, in this specification, P+ type or N+ type means a doping concentration higher than P-type or N-type, and P- type or N- type means a doping concentration lower than P-type or N-type.

[0029] In this specification, the doping concentration refers to the concentration of an impurity activated as a donor or an acceptor. In this specification, the difference in concentration between a donor and an acceptor may be referred to as the concentration of the larger donor or acceptor. This concentration difference can be measured by a voltage-capacitance measurement method (CV method). Alternatively, the carrier concentration measured by a spreading resistance measurement method (SR) may be referred to as the donor or acceptor concentration. Furthermore, when the donor or acceptor concentration distribution has a peak, the peak value may be referred to as the donor or acceptor concentration in that region. In cases where the donor or acceptor concentration in a region where a donor or acceptor is present is approximately uniform, the average value of the donor or acceptor concentration in that region may be referred to as the donor or acceptor concentration.

[0030] 1 shows an example of the arrangement of components on the front surface of a semiconductor device 100 according to an embodiment. The semiconductor device 100 includes a semiconductor substrate 10, a gate pad 50, a current sense pad 172, a temperature sense unit 178, an anode pad 174 and a cathode pad 176 electrically connected to the temperature sense unit 178, a bidirectional diode unit 210, and an output comparison diode unit 220. The region in which the current sense pad 172, the anode pad 174, the cathode pad 176, the bidirectional diode unit 210, and the output comparison diode unit 220 are provided may be collectively referred to as a pad region.

[0031] The semiconductor substrate 10 has an edge 102. In this specification, the direction of one edge 102-1 of the semiconductor substrate 10 in the top view of FIG. 1 is defined as the X-axis, and the direction perpendicular to the X-axis is defined as the Y-axis. In this example, the X-axis is taken in the direction of the edge 102-1. Furthermore, the direction perpendicular to the X-axis direction and the Y-axis direction, which forms a right-handed system, is referred to as the Z-axis direction. In this example, the temperature sensing unit 178 is provided in the +Z-axis direction of the semiconductor substrate 10.

[0032] The semiconductor substrate 10 is made of a semiconductor material such as silicon or a compound semiconductor. The side of the semiconductor substrate 10 on which the temperature sensing unit 178 is provided is referred to as the front surface, and the opposite surface is referred to as the back surface. In this specification, the direction connecting the front surface and the back surface of the semiconductor substrate 10 is referred to as the depth direction. In this example, the semiconductor substrate 10 has a substantially rectangular shape on the front surface, but may have a different shape.

[0033] The semiconductor substrate 10 has an active portion 120. The active portion 120 is a region through which a main current flows in the depth direction between the front and back surfaces of the semiconductor substrate 10 when the semiconductor device 100 is turned on. A gate conductive portion 44 (described later) of the active portion 120 is electrically connected to a gate pad 50 by a gate wiring portion (described later).

[0034] The active portion 120 may be divided into active portion 120-1 and active portion 120-2 when viewed from above. In this example, the active portion 120-1 and active portion 120-2 are separated in the Y-axis direction by a separation portion 90 that extends in the Y-axis direction through a center Ac of the front surface of the semiconductor substrate 10. Here, the center Ac of the active portion 120 is the geometric center of gravity of the active portion 120 when viewed from above. The active portion 120-1 and active portion 120-2 may be provided with a pad region sandwiched between them.

[0035] The active section 120 is provided with a transistor section 70 including a transistor element such as an IGBT (insulated gate bipolar transistor) and a diode section 80 including a diode element such as an FWD (freewheel diode). The transistor section 70 and the diode section 80 form an RC-IGBT (reverse conducting IGBT).

[0036] 1 , in the active section 120, the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this example, the transistor sections 70 and the diode sections 80 are arranged alternately in the X-axis direction in each region of the active section 120. In the X-axis direction, the width of the transistor section 70 is 300 μm or more and 2000 μm or less, and the width of the diode section 80 is 200 μm or more and 2000 μm or less.

[0037] The semiconductor device 100 has an edge termination structure on the front surface between the outer periphery of the active section 120 and the edge 102. The edge termination structure has, for example, a guard ring provided in an annular shape surrounding the active section 120, a field plate, or a structure that combines these.

[0038] The temperature sensing unit 178 may be disposed in the isolation unit 90. The isolation unit 90 does not include the active unit 120. When the active unit 120 of the semiconductor substrate 10 is integrated, the center of the semiconductor substrate 10 is more likely to heat up due to heat generated by the switching elements formed in the active unit 120. By providing the temperature sensing unit 178 in the isolation unit 90 near the center, the temperature of the transistor unit 70 can be monitored. This makes it possible to prevent the transistor unit 70 from overheating beyond the junction temperature, which is within the normal operating temperature range.

[0039] The temperature sensing unit 178 may be implemented by a temperature sensing diode. As an example, the temperature sensing unit 178 is implemented by a Schottky diode. Alternatively, the temperature sensing unit 178 may be implemented by a PN junction diode made of polycrystalline silicon provided above the semiconductor substrate 10 via an insulating film.

[0040] The anode and cathode of the temperature sensing diode are connected to a metal anode wiring 180 and a metal cathode wiring 182, respectively. The anode wiring 180 and the cathode wiring 182 are wirings containing a metal such as aluminum. The anode wiring 180 and the cathode wiring 182 are examples of temperature sensing wiring. The anode wiring 180 and the cathode wiring 182 are provided by extending the separation portion 90.

[0041] The cathode pad 176 is connected to a temperature sensor 178 via a cathode wiring 182. The anode pad 174 is connected to the temperature sensor 178 via an anode wiring 180. The cathode pad 176 and the anode pad 174 are electrodes containing a metal such as aluminum.

[0042] The current sense pad 172 is electrically connected to the current sense unit 110. The current sense pad 172 is an example of a front surface electrode. The current sense unit 110 has a structure similar to that of the transistor unit 70 of the active unit 120, and simulates the operation of the transistor unit 70. A current proportional to the current flowing through the transistor unit 70 flows through the current sense unit 110. This makes it possible to monitor the current flowing through the transistor unit 70.

[0043] Unlike the transistor section 70, the current sense section 110 does not have an emitter region 12, which will be described later. In other words, the current sense section 110 does not function as a transistor. The current sense section 110 has a gate trench section. The gate trench section of the current sense section 110 is electrically connected to the gate wiring section.

[0044] The bidirectional diode section 210 is disposed on the front surface of the semiconductor device 100 between the anode pad 174 and the cathode pad 176. The bidirectional diode section 210 includes diodes electrically connected in series and in both directions between the anode pad 174 and the cathode pad 176. The bidirectional diode section 210 prevents the temperature sensing section 178 from being damaged by electrostatic discharge (ESD).

[0045] The output comparison diode section 220 is provided between the anode pad 174 and the cathode pad 176. The output comparison diode section 220 is electrically connected to the anode pad 174 and the cathode pad 176. The output comparison diode section 220 includes an output comparison diode having a PN junction direction connected in anti-parallel with the PN junction direction of the temperature sense diode of the temperature sense section 178.

[0046] The output comparison diode of the output comparison diode section 220 may have a design similar to that of the diode of the temperature sense section 178, except for the direction of the PN junction. When the semiconductor device 100 is in operation, no current flows through the output comparison diode section 220. An output comparison operation is performed at predetermined intervals. During the output comparison operation, a current flows through the output comparison diode section 220. The output comparison operation makes it possible to determine when the temperature sense diode of the temperature sense section 178 needs to be replaced.

[0047] A protection diode having the same forward direction as the output comparison diode section 220 may be provided in parallel with the output comparison diode section 220. The protection diode prevents the application of an overvoltage or the inflow of an overcurrent to the temperature sensing section 178 due to noise or the like when the temperature sensing section 178 is operating.

[0048] 2 shows an example of the arrangement of emitter electrodes 52 provided on the front surface of the semiconductor device 100. The emitter electrodes 52 are made of a metal conductor such as aluminum. In this example, the emitter electrodes 52 are set to an emitter potential, which is a predetermined reference potential. Alternatively, the emitter potential may be set to a ground potential.

[0049] The emitter electrode 52 is formed of a conductive material containing metal. For example, the emitter electrode 52 is formed of aluminum or an alloy containing aluminum as a main component (such as an alloy of aluminum-silicon or aluminum-silicon-copper). The emitter electrode 52, like the current sense pad 172, is an example of a front surface electrode. Each electrode may have a barrier metal formed of titanium or a titanium compound below the region formed of aluminum or the like.

[0050] 2, the emitter electrode 52 is disposed in the hatched region. The emitter electrode 52 is not provided above the separation portion 90 that separates the active portion 120-1 and the active portion 120-2 from each other in the Y-axis direction. Similarly, the emitter electrode 52 is not provided above the pad region.

[0051] 3 shows an example of the arrangement of a protective film 150 provided above the front surface of the semiconductor device 100. In this example, the protective film 150 is made of polyimide. In FIG. 3, the outline of the region where the protective film 150 is arranged is indicated by a dashed line and hatched with diagonal lines. The protective film 150 may contact the upper surface of the emitter electrode 52.

[0052] The protective film 150 in this example includes a protective film 150-1 that covers the region where the gate pad 50 is provided, and a protective film 150-2 that covers the pad region. The protective film 150-1 may have an opening that exposes a portion of the upper surface of the gate pad 50. Furthermore, the protective film 150-1 may have an opening 153 that exposes a portion of the upper surface of the current sense pad 172, and an opening 154 that exposes a portion of the upper surfaces of the anode pad 174 and the cathode pad 176. This allows wires and the like to be connected to the upper surface of the gate pad 50. Similarly, wires and the like can also be connected to the upper surfaces of the current sense pad 172, the anode pad 174, and the cathode pad 176.

[0053] The protective film 150 may further include a protective film 150-3 provided between the outer periphery of the active section 120 and the edge 102 (edges 102-1 to 102-4), and a protective film 150-4 covering the isolation section 90. In other words, the emitter electrode 52 is divided into two regions surrounded by the protective film 150-1, the protective film 150-2, the protective film 150-3, and the protective film 150-4.

[0054] The protective film 150 in this example further includes protective films 150-5 and 150-6 that extend in the Y-axis direction on the upper surface of the emitter electrode 52. In Figure 3, in the Y-axis direction, the protective film 150-5 is sandwiched between the protective film 150-2 and the protective film 150-3, and the protective film 150-6 is sandwiched between the protective film 150-1 and the protective film 150-3.

[0055] Unlike the other protective films 150 provided on the front surface of the semiconductor substrate 10, the protective films 150-5 and 150-6 are provided on the upper surface of the emitter electrode 52. That is, of the protective films 150, only the protective films 150-5 and 150-6 are provided within the active section 120. The active section 120 has a protective region 151 provided with a protective film and an unprotected region 152 not provided with a protective film. The active section 120 in this example has a protective region 151-1 and a protective region 151-2 provided with the protective films 150-5 and 150-6, and an unprotected region 152-1, an unprotected region 152-2, and an unprotected region 152-3 not provided with a protective film.

[0056] FIG. 4 shows an example of the a-a' cross section of FIG. 3. The a-a' cross section is an XZ plane passing through the active section 120-1. In this example, the active section 120-1 has an unprotected region 152-1 located near the center in a top view, and unprotected regions 152-2 and 152-3 located on either side of the unprotected region 152-1 in the X-axis direction. The active section 120-1 further has a protected region 151-1 sandwiched between the unprotected region 152-1 and the unprotected region 152-2, and a protected region 151-2 sandwiched between the unprotected region 152-1 and the unprotected region 152-3. Protective films 150-5 and 150-6 are provided on the protected region 151-1 and the protected region 151-2, respectively.

[0057] A plating portion 161 is provided on the upper surface of the emitter electrode 52. In one example, the plating portion 161 is Ni / Au, in which an Au layer is stacked on a Ni layer. The plating portion 161 is separated into plating portions 161-1, 161-2, and 161-3 by protective films 150-5 and 150-6. The plating portions 161-1, 161-2, and 161-3 are provided in unprotected regions 152-2 and 152-3, respectively, which are located on either side of the unprotected region 152-1.

[0058] 4, protective film 150-5 is sandwiched between plating portion 161-1 and plating portion 161-2, and protective film 150-6 is sandwiched between plating portion 161-1 and plating portion 161-3. Emitter electrode 52 is provided extending below protective film 150-5 and protective film 150-6, as well as plating portion 161-1, plating portion 161-2, and plating portion 161-3.

[0059] In the X-axis direction, the width W1 of the protection region 151-1 and the width W2 of the protection region 151-2 may be the same. In this example, the width W1 of the protection region 151-1 and the width W2 of the protection region 151-2 are 100 μm or more and 1800 μm or less.

[0060] The thickness D1 of the protective film 150-5 and the thickness D2 of the protective film 150-6 may be the same. Here, the thickness refers to the distance in the +Z-axis direction with the top surface of the emitter electrode 52 as the reference. In this example, the thickness D1 of the protective film 150-5 and the thickness D2 of the protective film 150-6 are greater than the thickness d1 of the plating portion 161-1 sandwiched between the protective film 150-5 and the protective film 150-6. The thickness D1 of the protective film 150-5 and the thickness D2 of the protective film 150-6 are 5 μm or more and 15 μm or less. The thickness d1 of the plating portion 161-1 is 1 μm or more and 10 μm or less.

[0061] 2, the area of ​​the unprotected region 152-1 is larger than the areas of the unprotected regions 152-2 and 152-3 in a top view. Therefore, when the semiconductor device 100 is mounted, the emitter electrode 52 can be easily electrically connected to the outside by joining wiring such as a lead frame via a solder layer provided on the plated portion 161-1 of the unprotected region 152-1.

[0062] Furthermore, because the heights of protective films 150-5 and 150-6 are greater than the height of plating portion 161-1, it is possible to prevent the solder layer or the like on plating portion 161-1 of unprotected region 152-1 from flowing out into unprotected region 152-2 and unprotected region 152-3. Furthermore, by arranging unprotected region 152-2 and unprotected region 152-3 on opposite sides of unprotected region 152-1, it is possible to prevent the position of the solder layer or the like on the front surface of semiconductor substrate 10 from becoming uneven.

[0063] Although FIG. 4 shows the XZ plane passing through the active portion 120-1, the XZ plane passing through the active portion 120-2 has a similar configuration, and therefore a description thereof will be omitted here.

[0064] 5 shows an example of a top view of the semiconductor device 100. The semiconductor device 100 includes a semiconductor substrate 10 having a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD).

[0065] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 130, an emitter region 12, a base region 14, and a contact region 15, which are provided inside the front surface side of a semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0066] The semiconductor device 100 of this example also includes a gate metal layer 48 and an emitter electrode 52 provided above the front surface of the semiconductor substrate 10. The gate metal layer 48 and the emitter electrode 52 are also examples of front surface electrodes. The gate metal layer 48 and the emitter electrode 52 are provided separately from each other. The gate metal layer 48 and the emitter electrode 52 are electrically insulated from each other.

[0067] An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 48 and the front surface of the semiconductor substrate 10, but is not shown in Fig. 5. In this example, contact holes 49, 54, and 56 are provided through the interlayer insulating film. In Fig. 5, each contact hole is hatched with diagonal lines.

[0068] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 130, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is electrically connected to the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate 10 via a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 via a contact hole 56.

[0069] The gate metal layer 48 may be provided in a ring shape along the outer periphery of the active portion 120. In this example, the gate metal layer 48 is provided along the outer periphery of each of the active portions 120-1 and 120-2. The gate metal layer 48 is connected to the gate conductive portion in the gate trench portion 40 by a contact hole 49.

[0070] The front surface electrodes, such as the emitter electrode 52 or the gate metal layer 48, are made of a conductive material containing metal, such as aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal made of titanium, a titanium compound, or the like, beneath the region made of aluminum or the like.

[0071] Each electrode may have a plug formed of tungsten or the like in the contact hole. The plug may have a barrier metal on the side in contact with the semiconductor substrate 10, with tungsten buried so as to be in contact with the barrier metal, and may be formed of aluminum or the like on the tungsten.

[0072] The plug is provided in a contact hole in contact with the contact region 15 or the base region 14. A P++-type plug region having a higher doping concentration than the contact region 15 may be provided below the plug contact hole. This can improve the contact resistance between the barrier metal and the contact region 15. The depth of the plug region is approximately 0.1 μm or less, which is smaller than the depth of the contact region 15 by 10% or less.

[0073] The plug region improves the contact resistance, thereby improving the latch-up resistance in the operation of the transistor section 70. On the other hand, in the operation of the diode section 80, increases in conduction loss and switching loss can be suppressed.

[0074] A connection portion 25 may be further provided to electrically connect a front surface electrode such as the emitter electrode 52 or the gate metal layer 48 to the semiconductor substrate 10. In one example, the connection portion 25 is provided in a region between the gate metal layer 48 and the gate conductive portion, including the inside of the contact hole 49. The connection portion 25 may also be provided in a region between the emitter electrode 52 and the dummy conductive portion, including the inside of the contact hole 56.

[0075] The connection portion 25 is made of a conductive material such as a metal such as tungsten or polysilicon doped with impurities. The connection portion 25 may also have a barrier metal such as titanium nitride. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0076] The well region 130 is provided closer to the front surface of the semiconductor substrate 10 than the drift region 18, which will be described later. The well region 130 in this example is of P+ type. The well region 130 in this example is provided in the edge termination structure and the isolation region 90. The well region 130 is also provided in a predetermined range extending from the outer periphery to the interior of the active portion 120-1 and the active portion 120-2. The well region 130 is electrically connected to the emitter electrode 52. The well region 130 is provided from the front surface of the semiconductor substrate 10 to a position deeper than the lower end of the base region 14.

[0077] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction.

[0078] In this example, the arrangement direction of the trench portions is the X-axis direction, and the extension direction perpendicular to the arrangement direction is the Y-axis direction. The gate trench portion 40 in this example may have two extension portions 39 (parts of the trench that are linear along the extension direction) that extend along the extension direction, and a connection portion 41 that connects the two extension portions 39.

[0079] At least a part of the connection portion 41 may be curved in top view. The connection portion 41 connects the ends of the two extension portions 39 in the Y-axis direction to the gate metal layer 48, thereby functioning as a gate electrode for the gate trench portion 40. On the other hand, by making the connection portion 41 curved, electric field concentration at the ends can be alleviated more effectively than if the connection portion 41 were completed at the extension portion 39.

[0080] In the transistor section 70, the dummy trench section 30 is provided between the respective extension portions 39 of the gate trench section 40. In the example of Fig. 4, one dummy trench section 30 is provided between the respective extension portions 39, but two or more dummy trench sections 30 may be provided.

[0081] Furthermore, the dummy trench portion 30 may not be provided between the extension portions 39, and the gate trench portion 40 may be provided instead. With such a structure, the electron current from the emitter region 12 can be increased, thereby reducing the on-voltage.

[0082] The dummy trench portion 30 may have a linear shape extending in the extension direction, and may have an extension portion 29 and a connection portion 31, similar to the gate trench portion 40. In the semiconductor device 100 shown in FIG. 4 , only dummy trench portions 30 having connection portions 31 are arranged, but in other examples, the semiconductor device 100 may include linear dummy trench portions 30 that do not have connection portions 31.

[0083] The diffusion depth of the well region 130 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 130 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction (-Z-axis direction) is covered by the well region 130. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0084] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the depth position of the mesa portion is from the front surface of the semiconductor substrate to the bottom end of the trench portion.

[0085] The mesa portion in this example is sandwiched between adjacent trench portions in the X-axis direction, and is provided on the front surface of the semiconductor substrate 10 so as to extend in the extension direction (Y-axis direction) along the trenches.

[0086] Each mesa portion has a base region 14. In each mesa portion, at least one of an emitter region 12 and a contact region 15 may be provided in a region sandwiched between the base regions 14 in a top view. In this example, the base region 14 is P- type, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The base region 14 is provided in contact with the well region 130. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction. Examples of dopants for the emitter region 12 include arsenic (As), phosphorus (P), and antimony (Sb).

[0087] The mesa portion of the transistor section 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion in contact with the gate trench portion 40 has a contact region 15 exposed on the front surface of the semiconductor substrate 10.

[0088] The contact regions 15 and the emitter regions 12 in the mesa portion are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion are alternately arranged along the extension direction of the trench portions (the Y-axis direction).

[0089] In another example, the contact region 15 and the emitter region 12 of the mesa portion may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0090] The mesa portion of the diode portion 80 does not have an emitter region 12. A base region 14 may be provided on the upper surface of the mesa portion of the diode portion 80. The base region 14 may be disposed over the entire mesa portion of the diode portion 80. The base region 14 of the diode portion 80 operates as an anode.

[0091] A contact hole 54 is provided above each mesa portion. The contact holes 54 are arranged in a region sandwiched between the base regions 14 in the extension direction (Y-axis direction). In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 may be arranged in the center in the arrangement direction (X-axis direction) of the mesa portions.

[0092] In the diode section 80, an N+ type cathode region 82 is provided on the rear surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in the rear surface of the semiconductor substrate in an area where the cathode region 82 is not provided. In Figure 5, the boundary between the cathode region 82 and the collector region 22 is indicated by a dashed line.

[0093] 6 is a schematic diagram showing the structure of the front surface of the semiconductor substrate 10 in the vicinity of the protection region 151-1. The emitter electrode 52 and other elements provided above the front surface of the semiconductor substrate 10 are omitted from FIG. 6. While FIG. 6 illustrates the structure of the active portion 120-1 in the vicinity of the protection region 151-1, the active portion 120-2 also has a similar structure, and therefore its description will be omitted. In the diode portion 80, a cathode region 82 is provided on the rear surface of the semiconductor substrate 10.

[0094] As described above, the unprotected region 152-1 is provided near the center of the active section 120-1, and the unprotected region 152-2 is provided on the positive side of the pad region in the Y-axis direction, between the pad region, the protected region 151-1, and the gate metal layer 48. Transistor sections 70 and diode sections 80 are alternately provided in the unprotected region 152-1 and the unprotected region 152-2.

[0095] 6, for the sake of simplicity, one transistor section 70 and one diode section 80 are illustrated in each of the unprotected regions 152-1 and 152-2, but this is not limiting. A plurality of transistor sections 70 and a plurality of diode sections 80 may be provided alternately in each of the unprotected regions 152-1 and 152-2.

[0096] In the Y-axis direction, the length of the unprotected region 152-1 is greater than the length of the unprotected region 152-2. In other words, the unprotected region 152-2 is a region provided in a corner portion of the chip where the unprotected region 152-1 and the pad region are not provided, and by extending the active portion 120-1 to such a portion, the area on the chip can be used effectively.

[0097] The protected region 151-1 is sandwiched between the unprotected region 152-1 and the unprotected region 152-2. In this example, the protected region 151-1 is provided with only the transistor section 70, and is not provided with the diode section 80. The protected region 151-1 may be provided in the center of the transistor section 70.

[0098] Fig. 7 shows an example of the bb' cross section of Fig. 6. The bb' cross section is an XZ plane passing through the transistor section 70 and part of the diode section 80, and passes through the emitter region 12 in the transistor section 70.

[0099] In the bb' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a protective film 150-5, a plating portion 161-2, and a collector electrode 24. The interlayer insulating film 38 is formed above the front surface 21 of the semiconductor substrate 10, and the emitter electrode 52 is formed above the interlayer insulating film 38.

[0100] The drift region 18 is a region provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0101] The buffer region 20 is a region provided below the drift region 18. In this example, the buffer region 20 has the same conductivity type as the drift region 18, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0102] The collector region 22 is a region of a different conductivity type from the drift region 18, which is provided below the buffer region 20 in the transistor section 70. The cathode region 82 is a region of the same conductivity type as the drift region 18, which is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80.

[0103] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal.

[0104] The base region 14 is a region of a different conductivity type from the drift region 18, which is provided above the drift region 18 in the mesa portion. In this example, the base region 14 is, for example, a P-type. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may also be provided in contact with the dummy trench portion 30.

[0105] The emitter region 12 is provided between the base region 14 and the front surface 21 of the semiconductor substrate 10. In this example, the emitter region 12 is provided in the mesa portion of the transistor portion 70, but is not provided in the mesa portion of the diode portion 80. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0106] 6, the contact regions 15 are provided alternately with the emitter regions 12 in the mesa portion of the transistor section 70. The contact regions 15 may be provided to a position deeper in the semiconductor substrate 10 than the emitter regions 12.

[0107] The accumulation region 16 is a region that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. The accumulation region 16 in this example has the same conductivity type as the drift region 18, and is, for example, N+ type. The accumulation region 16 in this example is provided only in the transistor section 70, but may also be provided in the diode section 80. The accumulation region 16 may also be provided in multiple stages.

[0108] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0109] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided in the front surface 21 of the semiconductor substrate 10. Each trench portion is provided from the front surface 21 of the semiconductor substrate 10 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these regions to reach the drift region 18.

[0110] Note that the trench portion penetrating the doping region is not limited to a case where the trench portion is formed after the doping region is formed, but also includes a case where the trench portion is formed and then the doping region is formed between the trench portions.

[0111] The gate trench portion 40 has a gate trench formed in the front surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10.

[0112] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa side across the gate insulating film 42 in the depth direction (−Z-axis direction) of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0113] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side of the semiconductor substrate 10. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided more inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10.

[0114] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided so as to penetrate the interlayer insulating film 38.

[0115] A lifetime control region 85 including a lifetime killer is provided in the drift region 18, extending from the diode section 80 to at least a portion of the transistor section 70. The lifetime control region 85 is a crystal defect formed inside the semiconductor substrate 10 by implanting helium ions or the like at a predetermined depth. When the diode section 80 is turned off, the lifetime control region 85 promotes recombination between holes generated in the base region 14 of the diode section 80 and the transistor section 70 and electrons injected from the cathode region 82, thereby promoting carrier annihilation and suppressing peak current during reverse recovery.

[0116] 7, the peak position of the lifetime killer concentration distribution in the Z-axis direction is indicated by an "x" symbol. In the Z-axis direction, the peak position of the lifetime killer concentration distribution may be at the same depth as the bottom end of the well region 130, or may be deeper. The lifetime control region 85 may be formed so that the lifetime killer concentration distribution has multiple peaks in the Z-axis direction.

[0117] The lifetime control region 85 in this example is formed by irradiating protons or helium from the front surface 21 side of the semiconductor substrate 10. In one example, the lifetime control region 85 is formed by shielding the region where the lifetime control region 85 is not to be formed with a mask such as resist and irradiating with helium ions.

[0118] In this example, the lifetime control region 85 is provided only in the unprotected region 152, and is not provided in the protected region 151. The lifetime control region 85 is spaced apart from the protected region 151, and the distance L1 between the protected region 151-1 and the lifetime control region 85 in the X-axis direction is not less than 20 μm and not more than 1800 μm.

[0119] As described above, to form the lifetime control region 85, helium ions are irradiated from the front surface 21 side of the semiconductor substrate 10. However, because helium ions are light ions, their range changes in the protected region 151 where the protective film 150 is provided, and this causes variation in the depth direction position of the lifetime control region 85 between the protected region 151 and the unprotected region 152.

[0120] Therefore, in this example, helium ions are not irradiated onto the protected region 151, and helium ions are irradiated only onto the unprotected region 152, thereby making the depth direction position of the lifetime control region 85 uniform and promoting carrier annihilation when the diode section 80 is turned off, thereby suppressing the peak current during reverse recovery.

[0121] In the X-axis direction, the distance L2 by which the lifetime control region 85 extends in the transistor portion 70 is 80% or more and 250% or less of the thickness D0 of the semiconductor substrate 10. The thickness D0 of the semiconductor substrate 10 refers to the distance from the front surface 21 to the back surface 23 in the depth direction (-Z-axis direction) of the semiconductor substrate 10. The thickness D0 of the semiconductor substrate 10 in this example may be 50 μm or more and 150 μm or less, or may be 70 μm or more and 80 μm or less.

[0122] When the diode section 80 is in operation, carriers diffuse from the diode section 80 to the outside. In one example, the carriers move at an angle of approximately 45° from the front surface 21 of the semiconductor substrate 10 toward the back surface 23. In this example, the lifetime control region 85 is provided so as to extend into the transistor section 70 by a distance L2, thereby making it possible to capture the carriers that have diffused from the diode section 80.

[0123] Furthermore, the distance in the X-axis direction between the protection region 151-1 and the diode section 80 is equal to or greater than the thickness D0 of the semiconductor substrate 10. The protection film 150 is formed by over-etching polyimide, but there is a large variation in the finished position. Therefore, by providing a margin, it is possible to suppress the impact on performance even if variation occurs.

[0124] In this way, the protective region 151 of this example is provided inside the transistor portion 70, separated from the diode portion 80 and the lifetime control region 85. This allows the lifetime control region 85 to be provided without being affected by the protective film 150, and by promoting carrier annihilation when the diode portion 80 is turned off, it is possible to suppress the peak current during reverse recovery.

[0125] 8 shows an example of a manufacturing method of the semiconductor device 100. Here, the process of forming the lifetime control region 85 in the manufacturing method of the semiconductor device 100 will be mainly described using the bb' cross section of FIG. 6, which is the same as FIG. 7, as an example.

[0126] The manufacturing method of the semiconductor device 100 in this example includes the steps of forming an active portion 120 (plated active portion 120-1 in Figure 8) in which transistor portions 70 and diode portions 80 are alternately arranged in the semiconductor substrate 10, forming a plurality of trench portions (gate trench portions 40 and dummy trench portions 30 in Figure 8) in the semiconductor substrate 10, and forming an emitter electrode 52 above the front surface 21 of the semiconductor substrate 10.

[0127] The step of forming the active portion 120 includes a step of injecting dopants into the semiconductor substrate 10 to form impurity-implanted regions such as the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16. The step of forming the plurality of trench portions includes a step of etching the front surface 21 of the semiconductor substrate 10 to form trenches, oxidizing or nitriding the semiconductor on the inner walls of the trenches to form insulating films (gate insulating film 42 and dummy insulating film 32 in FIG. 8 ), and filling the inside of the insulating film with a conductive material such as polysilicon to form conductive portions (gate conductive portion 44 and dummy conductive portion 34 in FIG. 8 ). Either the step of forming the active portion 120 or the step of forming the plurality of trench portions may be performed first.

[0128] The step of forming the emitter electrode 52 includes the steps of forming an interlayer insulating film 38 of BPSG or the like above the front surface 21 of the semiconductor substrate 10, etching the interlayer insulating film 38 to form a contact hole, and then depositing a film of aluminum or an alloy containing aluminum as a main component (e.g., an aluminum-silicon alloy, an aluminum-silicon-copper alloy, etc.) on the front surface 21 of the semiconductor substrate 10 and the interlayer insulating film 38.

[0129] The manufacturing method of semiconductor device 100 further includes a step of forming a polyimide protective film 150 (protective film 150-5 in FIG. 8) on the upper surface of emitter electrode 52. After the polyimide applied to front surface 21 of semiconductor substrate 10 is spin-coated and cured, the polyimide in unprotected region 152 (unprotected region 152-2 in FIG. 8) is removed, thereby forming protective film 150 in protected region 151 (protected region 151-1 in FIG. 8).

[0130] In the unprotected region 152, a plating portion 161 (plating portion 161-2 in FIG. 8) may be formed on the upper surface of the emitter electrode 52. In this example, the plating portion 161 is a Ni / Au film formed by immersion growing an Au film for oxidation prevention on a Ni film formed by electroless plating.

[0131] In this example, the diode section 80 is included in the unprotected region 152, and the protected region 151 is included in the transistor section 70. In the X-axis direction, the distance between the diode section 80 and the protected region 151 is equal to or greater than the thickness D0 of the semiconductor substrate 10. The thickness of the semiconductor substrate 10 may be equal to or greater than 50 μm and equal to or less than 150 μm, or may be equal to or greater than 70 μm and equal to or less than 80 μm.

[0132] The method for manufacturing the semiconductor device 100 further includes a step of forming a lifetime control region 85 in the diode portion 80 by irradiating a lifetime killer from the front surface 21 side of the semiconductor substrate 10. In one example, the lifetime killer is helium or protons.

[0133] In this example, helium ions are irradiated through resist 190 arranged above protective film 150. In the X-axis direction, the width of resist 190 is larger than the width of protective film 150, and resist 190 is arranged to cover at least the entire protective film 150 in top view.

[0134] In the X-axis direction, the distance L1 between the end of the resist 190 and the end of the protective film 150 is 0 μm or more and 1800 μm or less. In a top view, the end of the resist 190 may coincide with the end of the lifetime control region 85.

[0135] The resist 190 is disposed in the transistor portion 70 at a distance from the diode portion 80. In the X-axis arrangement direction, the distance between the diode portion 80 and the resist 190 is 80% or more and 250% or less of the thickness D0 of the semiconductor substrate 10. After the lifetime control region 85 is formed, the resist 190 is removed with a developer.

[0136] As described above, according to the manufacturing method of the semiconductor device 100 of this example, the protective region 151 is formed inside the transistor portion 70, separate from the diode portion 80 and the lifetime control region 85. This allows the lifetime control region 85 to be formed without being affected by the protective film 150, and by promoting the annihilation of carriers when the diode portion 80 is turned off, it is possible to suppress the peak current during reverse recovery.

[0137] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0138] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0139] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 18...Drift region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 29...Extended portion, 30...Dummy trench portion, 31...Connection portion, 32...Dummy insulating film, 34...Dummy conductive portion, 38...Interlayer insulating film, 39...Extended portion, 40...Gate trench portion, 41...Connection portion, 42...Gate insulating film, 44...Gate conductive portion, 48...Gate metal layer, 49...Contact hole, 50...Gate pad, 52...Emitter electrode, 54...Contact hole, 55...Contact hole Contact hole, 56...contact hole, 70...transistor section, 80...diode section, 82...cathode region, 85...lifetime control region, 90...isolation section, 100...semiconductor device, 102...edge, 110...current sense section, 120...active section, 130...well region, 150...protective film, 151...protected region, 152...unprotected region, 153...opening, 154...opening, 161...plated section, 172...current sense pad, 174...anode pad, 176...cathode pad, 178...temperature sense section, 180...anode wiring, 182...cathode wiring, 190...resist, 210...bidirectional diode section, 220...output comparison diode section

Claims

1. a semiconductor substrate having an active portion in which transistor portions and diode portions are alternately provided, and having a plurality of trench portions provided therein, the trench portions extending in an extension direction of the transistor portions and the diode portions; an emitter electrode provided above a front surface of the semiconductor substrate; a polyimide protective film provided on an upper surface of the emitter electrode; Equipped with the diode portion has a lifetime control region including a lifetime killer irradiated from a front surface side of the semiconductor substrate, the active portion has a protected region in which the protective film is provided and a non-protected region in which the protective film is not provided, The diode portion is included in the unprotected region, and the protected region is included in the transistor portion. Semiconductor device.

2. In the trench arrangement direction, the width of the transistor portion is 300 μm or more and 2000 μm or less. The semiconductor device according to claim 1 .

3. In the trench arrangement direction, the width of the diode portion is 200 μm or more and 2000 μm or less. The semiconductor device according to claim 1 .

4. In the trench arrangement direction, the width of the protection region is 100 μm or more and 1800 μm or less. The semiconductor device according to claim 1 .

5. In a trench arrangement direction, the distance between the protection region and the diode portion is equal to or greater than the thickness of the semiconductor substrate. The semiconductor device according to claim 1 .

6. the lifetime control region is provided to extend from the diode portion to at least a part of the transistor portion in a trench arrangement direction, In the trench arrangement direction, the distance that the lifetime control region extends in the transistor portion is 80% or more and 250% or less of the thickness of the semiconductor substrate. The semiconductor device according to claim 1 .

7. The thickness of the semiconductor substrate is 50 μm or more and 150 μm or less.

7. The semiconductor device according to claim 5.

8. the lifetime control area is provided only in the unprotected area, In the trench arrangement direction, the distance between the protection region and the lifetime control region is 20 μm or more and 1800 μm or less. The semiconductor device according to claim 1 .

9. a first plating portion and a second plating portion provided on an upper surface of the emitter electrode and sandwiching the protective film therebetween; The emitter electrode is provided extending below the protective film, the first plating portion, and the second plating portion. The semiconductor device according to claim 1 .

10. the protective film includes a first protective film and a second protective film sandwiching the first plating portion therebetween, The thickness of the first protective film and the second protective film is greater than the thickness of the first plating portion. The semiconductor device according to claim 9.

11. The unprotected area includes a first unprotected area and a second unprotected area, and the protected area is sandwiched between the first unprotected area and the second unprotected area. The semiconductor device according to claim 1 .

12. forming an active portion in which transistor portions and diode portions are alternately provided on a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, the trenches extending in a direction in which the transistor portion and the diode portion extend; forming an emitter electrode above a front surface of the semiconductor substrate; forming a polyimide protective film on an upper surface of the emitter electrode; forming a lifetime control region in the diode portion by irradiating a lifetime killer from a front surface side of the semiconductor substrate; Equipped with the active portion has, in a top view, a protected region in which the protective film is provided and an unprotected region in which the protective film is not provided, The diode portion is included in the unprotected region, and the protected region is included in the transistor portion. A method for manufacturing a semiconductor device.

13. the lifetime killer is irradiated through a resist disposed above the protective film, In the trench arrangement direction, the width of the resist is larger than the width of the protective film. The method for manufacturing a semiconductor device according to claim 12 .

14. The resist is disposed so as to cover at least the entirety of the protective film when viewed from above. The method for manufacturing a semiconductor device according to claim 13.

15. In the trench arrangement direction, the distance between the end of the resist and the end of the protective film is 0 μm or more and 1800 μm or less. The method for manufacturing a semiconductor device according to claim 14.

16. the resist is disposed in the transistor portion and spaced apart from the diode portion; In a trench arrangement direction, the distance between the diode portion and the resist is 80% or more and 250% or less of the thickness of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 13.

17. In a trench arrangement direction, the distance between the diode portion and the protection region is equal to or greater than the thickness of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 13.

18. The thickness of the semiconductor substrate is 50 μm or more and 150 μm or less. The method for manufacturing a semiconductor device according to claim 16 or 17.

19. The protected region provided parallel to the extension direction is sandwiched between the non-protected regions and provided in the center of the transistor portion. The semiconductor device according to claim 1 .

20. The protected region provided parallel to the extension direction is sandwiched between the non-protected regions and provided in the center of the transistor portion. The method for manufacturing a semiconductor device according to claim 12 .

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