Printed wiring board

Abstract

A printed wiring board comprising: an insulating layer having a first main surface and a second main surface; a first copper layer disposed on the first main surface; a second copper layer disposed on the second main surface; and a third copper layer. The insulating layer and the first copper layer have a through-hole reaching the second copper layer. The third copper layer lies on the second copper layer inside the through-hole, on the inner-wall surface of the through-hole, and on the first copper layer surrounding the through-hole. A single copper layer has been disposed on the inner-wall surface of the through-hole, and the single copper layer is some of the third copper layer.

Description

printed wiring board

[0001] This application claims priority to Japanese Patent Application No. 2022-168266, filed on October 20, 2022, and incorporates by reference all of the contents of said Japanese application.

[0002] Japanese Patent Laid-Open Publication No. 2017-037990 (Patent Document 1) describes a printed wiring board including an inner resin layer, an inner circuit, an organic adhesive layer, an organic insulating resin layer, an outer copper layer, and an outer circuit.

[0003] The inner layer resin layer has a first main surface. The inner layer circuit is disposed on the first main surface. The organic adhesive layer is disposed on the first main surface so as to cover the inner layer circuit. The organic insulating resin layer has a second main surface and a third main surface. The third main surface is the surface opposite to the second main surface. The organic insulating resin layer is disposed on the organic adhesive layer so that the second main surface faces the organic adhesive layer. Through holes are formed in the organic adhesive layer and the organic insulating resin layer to expose the inner layer circuit.

[0004] The outer copper layer is a copper layer formed by electroless plating. The outer copper layer is disposed on the inner layer circuit exposed from the through hole, on the inner wall surface of the through hole, and on the third main surface around the through hole. The outer layer circuit is a copper layer formed by electrolytic plating. The outer layer circuit is disposed on the outer copper layer. In this way, in the printed wiring board described in Patent Document 1, the outer layer circuit and the inner layer circuit are electrically connected.

[0005] JP 2017-037990 A

[0006] The printed wiring board of the present disclosure comprises an insulating layer having a first main surface and a second main surface, a first copper layer disposed on the first main surface, a second copper layer disposed on the second main surface, and a third copper layer, wherein through holes are formed in the insulating layer and the first copper layer to reach the second copper layer, and the third copper layer is disposed on the second copper layer inside the through holes, on the inner wall surfaces of the through holes, and on the first copper layer around the through holes, and a single copper layer is disposed on the inner wall surfaces of the through holes, and the single copper layer is the third copper layer.

[0007] FIG. 1 is a cross-sectional view of a printed wiring board 100. FIG. 2 is a manufacturing process diagram for the printed wiring board 100. FIG. 3 is a cross-sectional view illustrating a preparation step S1. FIG. 4 is a cross-sectional view illustrating a first etching step S2. FIG. 5 is a cross-sectional view illustrating a hole drilling step S3. FIG. 6 is a cross-sectional view illustrating a resist pattern forming step S5. FIG. 7 is a cross-sectional view illustrating an electrolytic plating step S6. FIG. 8 is a cross-sectional view illustrating a resist pattern removing step S7. FIG. 9 is a cross-sectional view of a printed wiring board 100A. FIG. 10 is a cross-sectional view of a printed wiring board 200. FIG. 11 is a manufacturing process diagram for the printed wiring board 200. FIG. 12 is a cross-sectional view illustrating a preparation step S11. FIG. 13 is a cross-sectional view illustrating a first hole drilling step S12. FIG. 14 is a cross-sectional view illustrating a first resist pattern forming step S13. FIG. 15 is a cross-sectional view illustrating a first electrolytic plating step S14. FIG. 16 is a cross-sectional view illustrating a first resist pattern removing step S15. FIG. 17 is a cross-sectional view illustrating a first etching step S16. Fig. 18 is a cross-sectional view illustrating the insulating layer attaching step S17. Fig. 19 is a cross-sectional view illustrating the second hole drilling step S18. Fig. 20 is a cross-sectional view illustrating the second resist pattern forming step S19. Fig. 21 is a cross-sectional view illustrating the second electrolytic plating step S20. Fig. 22 is a cross-sectional view illustrating the second resist pattern removing step S21.

[0008] [Problem to be Solved by the Present Disclosure] In the printed wiring board described in Patent Document 1, palladium is used as a catalyst when forming an outer copper layer by electroless plating. Therefore, palladium may remain at the interface between the inner circuit and the outer copper layer. Palladium remaining between the inner circuit and the outer copper layer may cause the outer circuit together with the outer copper layer to peel off from the inner circuit due to, for example, thermal shock, leading to disconnection.

[0009] In the printed wiring board described in Patent Document 1, etching is sometimes performed to remove foreign matter and oxide films (hereinafter referred to as "foreign matter, etc.") on the surface of the inner layer circuit before forming the outer copper layer by electroless plating. This etching must be performed weakly to avoid excessive erosion of the inner layer circuit, and foreign matter, etc., remains on the surface of the inner layer circuit. If foreign matter, etc., remains on the surface of the inner layer circuit, the adhesion between the inner layer circuit and the outer copper layer decreases, which can cause the outer layer circuit and the outer copper layer to peel off from the inner layer circuit, resulting in a break.

[0010] The present disclosure has been made in consideration of the above-mentioned problems of the conventional technology. More specifically, the present disclosure provides a printed wiring board capable of suppressing the occurrence of disconnections in blind via holes. A blind via hole is a hole that electrically or physically connects the outermost circuit of a printed wiring board to one or more inner layer circuits by copper plating or the like. A blind via hole does not penetrate all the way to the outermost circuit on the opposite side.

[0011] Effect of the Present Disclosure The printed wiring board of the present disclosure can suppress the occurrence of disconnections in blind via holes.

[0012] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be described below. (1) A printed wiring board according to an embodiment includes an insulating layer having a first main surface and a second main surface, a first copper layer disposed on the first main surface, a second copper layer disposed on the second main surface, and a third copper layer, through holes are formed in the insulating layer and the first copper layer to reach the second copper layer, the third copper layer is disposed on the second copper layer inside the through holes, on the inner wall surfaces of the through holes, and on the first copper layer around the through holes, and a single copper layer is disposed on the inner wall surfaces of the through holes, the single copper layer being the third copper layer.

[0013] According to the printed wiring board of (1) above, it is possible to suppress the occurrence of disconnections in blind via holes.

[0014] (2) In the printed wiring board of (1) above, the thickness of the third copper layer on the first copper layer may be at least 0.4 times the thickness of the insulating layer and at most 0.6 times the minimum width of the through hole on the first main surface.

[0015] According to the printed wiring board of (2) above, it is possible to easily connect the third copper layer formed on the first copper layer around the through hole with the third copper layer formed on the second copper layer exposed from the through hole.

[0016] (3) In the printed wiring board of (1) above, the thickness of the third copper layer on the first copper layer may be 0.8 times or more the thickness of the insulating layer and 0.45 times or less the minimum width of the through hole on the first main surface.

[0017] According to the printed wiring board of (3) above, it is possible to further facilitate connection between the third copper layer formed on the first copper layer around the through hole and the third copper layer formed on the second copper layer exposed from the through hole.

[0018] (4) In the printed wiring boards of (1) to (3) above, the concentration of palladium in the region of the third copper layer extending from the interface between the insulating layer and the third copper layer to a depth of 10 nm and in the region of the third copper layer extending from the interface between the second copper layer and the third copper layer to a depth of 10 nm may be 0.5 mass percent or less.

[0019] (5) In the printed wiring boards of (1) to (4) above, the third copper layer may be an electrolytically plated copper layer.

[0020] (6) A printed wiring board according to an embodiment comprises: a first insulating layer having a first main surface; a first copper layer disposed on the first main surface; an adhesive layer disposed on the first main surface so as to cover the first copper layer; a second insulating layer having a second main surface and a third main surface and disposed on the adhesive layer so that the second main surface faces the adhesive layer; a second copper layer disposed on the third main surface; and a third copper layer, wherein a through hole leading to the first copper layer is formed in the second insulating layer, the second copper layer, and the adhesive layer, and the third copper layer is disposed on the first copper layer inside the through hole, on the inner wall surface of the through hole, and on the second copper layer around the through hole, and a single copper layer is disposed on the inner wall surface of the through hole, the single copper layer being the third copper layer.

[0021] According to the printed wiring board of (6) above, it is possible to suppress the occurrence of disconnections in blind via holes.

[0022] (7) In the printed wiring board of (6) above, the thickness of the third copper layer on the second copper layer may be 0.4 times or more the sum of the thickness of the second insulating layer and the thickness of the adhesive layer between the first copper layer and the second insulating layer, and may be 0.6 times or less the minimum width of the through hole on the third main surface.

[0023] According to the printed wiring board of (7) above, it is possible to easily connect the third copper layer formed on the second copper layer around the through hole with the third copper layer formed on the first copper layer exposed from the through hole.

[0024] (8) In the printed wiring board of (6) above, the thickness of the third copper layer on the second copper layer may be 0.8 times or more the sum of the thickness of the second insulating layer and the thickness of the adhesive layer between the first copper layer and the second insulating layer, and may be 0.45 times or less the minimum width of the through hole on the third main surface.

[0025] According to the printed wiring board of (8) above, it is possible to further facilitate connection between the third copper layer formed on the second copper layer around the through hole and the third copper layer formed on the first copper layer exposed from the through hole.

[0026] (9) In the printed wiring boards of (6) to (8) above, the concentration of palladium in a region of the third copper layer extending from the interface between the second insulating layer and the third copper layer to a depth of 10 nm and in a region of the third copper layer extending from the interface between the first copper layer and the third copper layer to a depth of 10 nm may be 0.5 mass percent or less.

[0027] (10) In the printed wiring boards of (6) to (9) above, the third copper layer may be an electrolytically plated copper layer.

[0028] [Details of the embodiment of the present disclosure] Details of the embodiment of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant description will not be repeated.

[0029] First Embodiment A printed wiring board according to a first embodiment will be described. The printed wiring board according to the first embodiment is designated as a printed wiring board 100.

[0030] <Configuration of Printed Wiring Board 100> The configuration of the printed wiring board 100 will be described below.

[0031] Fig. 1 is a cross-sectional view of a printed wiring board 100. As shown in Fig. 1, the printed wiring board 100 has an insulating layer 10, a first copper layer 11, a second copper layer 12, and a third copper layer 20.

[0032] The constituent material of the insulating layer 10 has electrical insulating properties and flexibility. The constituent material of the insulating layer 10 is, for example, polyimide. However, the constituent material of the insulating layer 10 is not limited to this. The insulating layer 10 has a first main surface 10a and a second main surface 10b. The first main surface 10a and the second main surface 10b are surfaces perpendicular to the thickness direction of the insulating layer 10 and constitute the front and back surfaces of the insulating layer 10. The second main surface 10b is the surface opposite to the first main surface 10a. The thickness of the insulating layer 10 is defined as thickness T1. Thickness T1 is, for example, 12.5 μm or more and 100 μm or less. Thickness T1 is the average value measured at any 10 points on a cross-sectional photograph.

[0033] The first copper layer 11 is made of copper or a copper alloy and is disposed on the first main surface 10a. The second copper layer 12 is made of copper or a copper alloy and is disposed on the second main surface 10b.

[0034] A through hole 13 is formed in the insulating layer 10 and the first copper layer 11. The through hole 13 penetrates the insulating layer 10 and the first copper layer 11 in the thickness direction. The shape of the through hole 13 in a plan view is, for example, circular. However, the planar shape of the through hole 13 is not limited to this. The opening diameter of the through hole 13, for example, becomes smaller as it approaches the second main surface 10b. The width of the through hole 13 on the first main surface 10a is defined as width W1. The second copper layer 12 is exposed from the through hole 13. The width W1 is, for example, 25 μm or more and 250 μm or less.

[0035] The third copper layer 20 is made of copper or a copper alloy. The third copper layer 20 may be a copper layer formed by electrolytic plating (electrolytically plated copper layer). A single copper layer is disposed on the inner wall surface of the through hole 13. The single copper layer referred to here is the third copper layer 20. "A single copper layer is disposed on the inner wall surface of the through hole 13" means that two or more copper layers are not continuously laminated on the inner wall surface of the through hole 13. In other words, a resin layer or an adhesive layer, for example, is formed on the surface of the third copper layer 20 opposite the inner wall surface of the through hole 13. Alternatively, a metal layer other than copper is laminated on the surface of the third copper layer 20 opposite the inner wall surface.

[0036] The third copper layer 20 is disposed on the second copper layer 12 exposed inside the through hole 13, on the inner wall surface of the through hole 13, and on the first copper layer 11 around the through hole 13. Here, "the third copper layer 20 is disposed on the first copper layer 11 around the through hole 13" means that the third copper layer 20 is disposed on the side surface of the first copper layer 11 that constitutes the through hole 13, and on at least a portion of the top surface of the first copper layer 11 (the surface opposite to the surface in contact with the first main surface 10a). By disposing the third copper layer 20 on at least a portion of the top surface of the first copper layer 11, an anchor effect can be achieved, thereby preventing the third copper layer 20 from peeling off from the insulating layer 10 (through hole 13). The third copper layer 20 is also disposed on the first copper layer 11 other than around the through hole 13. The third copper layer 20 constitutes the wiring of the printed wiring board 100. The wiring of the printed wiring board 100 is electrically connected to the second copper layer 12 exposed inside the through hole 13 .

[0037] The thickness of the third copper layer 20 on the first copper layer 11 is defined as thickness T2. Thickness T2 may be 0.4 times or more than thickness T1 and 0.6 times or less than width W1. Thickness T2 is an average value measured at any 10 points on a cross-sectional photograph. Thickness T2 may be 0.8 times or more than thickness T1 and 0.45 times or less than width W1. Thickness T2 is, for example, 10 μm or more and 45 μm or less. The width W1 here refers to the minimum width of the through hole 13 on the first main surface 10a. The "minimum width of the through hole 13 on the first main surface 10a" refers to the diameter of the inscribed circle of the shape of the through hole 13 in a plan view on the first main surface 10a.

[0038] Palladium is either absent at the interface between the insulating layer 10 and the third copper layer 20, which constitute the inner wall surface of the through hole 13, and at the interface between the second copper layer 12 and the third copper layer 20, or palladium unintentionally mixed into the plating bath is unavoidably attached. That is, the palladium concentration in the region of the third copper layer 20 extending from the interface between the insulating layer 10 (the inner wall surface of the through hole 13) and the third copper layer 20 to a depth of 10 nm is 0.5 mass percent or less. Furthermore, the palladium concentration in the region of the third copper layer 20 extending from the interface between the second copper layer 12 and the third copper layer 20 exposed inside the through hole 13 to a depth of 10 nm is 0.5 mass percent or less. Palladium is also absent at the interface between the first copper layer 11 and the third copper layer 20, and the palladium concentration in the region of the third copper layer 20 extending from the interface between the first copper layer 11 and the third copper layer 20 to a depth of 10 nm is 0.5 mass percent or less. The palladium concentration in the region of the third copper layer 20 is measured, for example, by energy dispersive X-ray spectroscopy of a cross section obtained by cutting the hole with a focused ion beam.

[0039] <Method for Manufacturing Printed Wiring Board 100> A method for manufacturing the printed wiring board 100 will be described below.

[0040] 2 is a manufacturing process diagram of the printed wiring board 100. As shown in FIG. 2, the manufacturing method of the printed wiring board 100 includes a preparation step S1, a first etching step S2, a hole drilling step S3, a desmearing step S4, a resist pattern forming step S5, an electrolytic plating step S6, a resist pattern removing step S7, and a second etching step S8.

[0041] 3 is a cross-sectional view illustrating the preparation step S1. As shown in FIG. 3, in the preparation step S1, an insulating layer 10 is prepared. The insulating layer 10 prepared in the preparation step S1 has a first copper layer 11 disposed over the entire first main surface 10a and a second copper layer 12 disposed over the entire second main surface 10b. The insulating layer 10 prepared in the preparation step S1 does not have through holes 13 formed therein.

[0042] The first etching step S2 is performed after the preparation step S1. FIG. 4 is a cross-sectional view illustrating the first etching step S2. As shown in FIG. 4, in the first etching step S2, etching is performed to form a portion of the through hole 13 in the first copper layer 11. The drilling step S3 is performed after the first etching step S2. FIG. 5 is a cross-sectional view illustrating the drilling step S3. As shown in FIG. 5, the portion of the through hole 13 in the insulating layer 10 is formed by, for example, irradiating with laser light.

[0043] The desmear step S4 is performed after the hole drilling step S3. In the desmear step S4, foreign matter and the like on the surface of the second copper layer 12 exposed inside the through hole 13 is removed by etching.

[0044] The resist pattern forming step S5 is performed after the desmearing step S4. The etching in the desmearing step S4 is performed weakly so as not to excessively erode the second copper layer 12 exposed inside the through hole 13. Therefore, at the stage after the desmearing step S4 and before the resist pattern forming step S5, foreign matter and the like may remain on the surface of the second copper layer 12 exposed inside the through hole 13.

[0045] 6 is a cross-sectional view illustrating the resist pattern forming step S5. As shown in FIG. 6, in the resist pattern forming step S5, a resist pattern 30 is formed. The resist pattern 30 is formed, for example, by applying a dry film resist to the first copper layer 11 and then exposing and developing the applied dry film resist. Because the dry film resist is developed using an alkaline solution, some of the foreign matter remaining on the surface of the second copper layer 12 exposed inside the through hole 13 is removed during this process.

[0046] The electrolytic plating step S6 is performed after the resist pattern forming step S5. Fig. 7 is a cross-sectional view illustrating the electrolytic plating step S6. As shown in Fig. 7, in the electrolytic plating step S6, electrolytic plating is performed to form a third copper layer 20 on the first copper layer 11 exposed from the openings of the resist pattern 30 and on the second copper layer 12 exposed inside the through hole 13.

[0047] As growth progresses, the third copper layer 20 on the first copper layer 11 around the through hole 13 extends along the inner wall surface of the through hole 13. As growth progresses, the third copper layer 20 on the second copper layer 12 exposed inside the through hole 13 also extends along the inner wall surface of the through hole 13. Therefore, the third copper layer 20 extending from the first copper layer 11 around the through hole 13 along the inner wall surface of the through hole 13 and the third copper layer 20 extending from the second copper layer 12 exposed inside the through hole 13 along the inner wall surface of the through hole 13 are integrated, and the third copper layer 20 is formed also on the inner wall surface of the through hole 13.

[0048] After the resist pattern forming step S5 and before the electrolytic plating step S6, a degreasing treatment is carried out, which further removes foreign matter remaining on the surface of the second copper layer 12 exposed inside the through hole 13.

[0049] The resist pattern removing step S7 is performed after the electrolytic plating step S6. FIG. 8 is a cross-sectional view illustrating the resist pattern removing step S7. As shown in FIG. 8, the resist pattern 30 is removed in the resist pattern removing step S7. The second etching step S8 is performed after the resist pattern removing step S7. In the second etching step S8, the first copper layer 11 that was under the resist pattern 30 is removed. This results in the formation of the printed wiring board 100 having the structure shown in FIG.

[0050] <Effects of Printed Wiring Board 100> The effects of printed wiring board 100 will be described below in comparison with a comparative example. The printed wiring board according to the comparative example is designated as printed wiring board 100A.

[0051] 9 is a cross-sectional view of printed wiring board 100A. As shown in FIG. 9, printed wiring board 100A further includes electrolessly plated copper layer 40. Electrolessly plated copper layer 40 is a copper layer formed by electroless plating. Electrolessly plated copper layer 40 is disposed on first copper layer 11, on the inner wall surface of through hole 13, and on second copper layer 12 exposed inside through hole 13. Except for these points, the configuration of printed wiring board 100A is the same as the configuration of printed wiring board 100.

[0052] The method for manufacturing printed wiring board 100A further includes electroless plating step S9. Electroless plating step S9 is performed after desmearing step S4 and before resist pattern forming step S5. In electroless plating step S9, a palladium catalyst is applied to first copper layer 11, the inner wall surfaces of through holes 13, and the second copper layer 12 exposed inside through holes 13, and then electroless plating is performed to form electrolessly plated copper layer 40.

[0053] In the method for manufacturing printed wiring board 100A, in resist pattern formation step S5, resist pattern 30 is formed on electrolessly plated copper layer 40 on first copper layer 11. In the method for manufacturing printed wiring board 100A, in electrolytic plating step S6, third copper layer 20 is formed on electrolessly plated copper layer 40. In the method for manufacturing printed wiring board 100A, in second etching step S8, electrolessly plated copper layer 40 and first copper layer 11 that were under resist pattern 30 are removed. Except for these points, the method for manufacturing printed wiring board 100A is the same as the method for manufacturing printed wiring board 100.

[0054] Since the manufacturing method of printed wiring board 100A includes electroless plating step S9, palladium remains at the interface between insulating layer 10 (the inner wall surface of through hole 13) and electrolessly plated copper layer 40, and at the interface between second copper layer 12 exposed inside through hole 13 and electrolessly plated copper layer 40.

[0055] Furthermore, after the desmearing step S4 has been performed, foreign matter and the like may remain on the surface of the second copper layer 12 exposed inside the through hole 13, and therefore, foreign matter and the like may remain between the second copper layer 12 exposed inside the through hole 13 and the electrolessly plated copper layer 40. In the method for manufacturing the printed wiring board 100A, the second copper layer 12 exposed inside the through hole 13 is covered with the electrolessly plated copper layer 40 when the resist pattern forming step S5 and the electrolytic plating step S6 are performed, and therefore, the foreign matter and the like are not removed by the development in the resist pattern forming step S5 and the degreasing treatment before the electrolytic plating step S6 are performed.

[0056] Palladium remaining at the interface between the insulating layer 10 (the inner wall surface of the through hole 13) and the electrolessly plated copper layer 40, and at the interface between the second copper layer 12 exposed inside the through hole 13 and the electrolessly plated copper layer 40, as well as foreign matter between the second copper layer 12 exposed inside the through hole 13 and the electrolessly plated copper layer 40, can cause the third copper layer 20 to peel off together with the electrolessly plated copper layer 40, resulting in a break in the wire.

[0057] In the manufacturing method of the printed wiring board 100, the electroless plating step S9 is not performed, and therefore palladium does not remain at the interface between the insulating layer 10 (the inner wall surface of the through hole 13) and the third copper layer 20, and at the interface between the second copper layer 12 exposed inside the through hole 13 and the third copper layer 20. Furthermore, in the manufacturing method of the printed wiring board 100, foreign matter and the like on the surface of the second copper layer 12 exposed inside the through hole 13 is also removed by the degreasing treatment before the development in the resist pattern formation step S5 and the electrolytic plating step S6. In this way, the printed wiring board 100 can prevent the third copper layer 20 from peeling off due to palladium or foreign matter, and thus prevent disconnections in the blind via holes.

[0058] If the thickness T2 is less than 0.4 times the thickness T1, the growth of the third copper layer 20 is insufficient, and it becomes difficult to connect the third copper layer 20 extending from the first copper layer 11 around the through hole 13 along the inner wall surface of the through hole 13 to the third copper layer 20 extending from the second copper layer 12 exposed inside the through hole 13 along the inner wall surface of the through hole 13. Furthermore, if the thickness T2 is more than 0.6 times the width W1, the third copper layer on the first copper layer 11 around the through hole 13 may block the upper end of the through hole 13, and the growth of the third copper layer 20 on the second copper layer 12 exposed inside the through hole 13 may become insufficient.

[0059] Therefore, by making the thickness T2 at least 0.4 times the thickness T1 and at most 0.6 times the width W1, it becomes easier to connect the third copper layer 20 extending from the first copper layer 11 around the through hole 13 along the inner wall surface of the through hole 13 to the third copper layer 20 extending from the second copper layer 12 exposed inside the through hole 13 along the inner wall surface of the through hole 13, and it becomes possible to properly form the third copper layer 20 on the inner wall surface of the through hole 13.

[0060] Example To evaluate the effect of thickness T2, Samples 1 to 8 were prepared. In Samples 1 to 8, the ratio of thickness T2 to thickness T1 and the ratio of thickness T2 to width W1 were changed. Details of Samples 1 to 8 are shown in Table 1. In Samples 1, 2, and 4 to 6, thickness T2 is 0.4 times or more than thickness T1 and 0.6 times or less than width W1. On the other hand, in Sample 3, thickness T2 is less than 0.4 times thickness T1 and more than 0.6 times width W1. In Sample 7, thickness T2 is less than 0.4 times thickness T1, and in Sample 8, thickness T2 is more than 0.6 times width W1.

[0061]

[0062] The presence or absence of breaks in the blind via holes was observed for Samples 1 to 8. The defect rates in Table 1 represent the proportion of improperly formed blind via holes in each sample. As shown in Table 1, the defect rates for Samples 1, 2, and 4 to 6 are lower than the defect rates for Samples 3, 7, and 8.

[0063] From this comparison, it became clear that by making the thickness T2 at least 0.4 times the thickness T1 and at most 0.6 times the width W1, the third copper layer 20 extending from the first copper layer 11 around the through hole 13 along the inner wall surface of the through hole 13 and the third copper layer 20 extending from the second copper layer 12 exposed inside the through hole 13 along the inner wall surface of the through hole 13 are connected, making it easier to properly form the third copper layer 20 on the inner wall surface of the through hole 13.

[0064] In sample 1, thickness T2 is 0.8 times or more the thickness T1, while in sample 6, thickness T2 is 0.4 times or more and less than 0.8 times the thickness T1. The defect rate in sample 1 is lower than the defect rate in sample 6. In sample 2, thickness T2 is 0.45 times or less the width W1, while in sample 5, thickness T2 is more than 0.45 times and less than 0.6 times the width W1. The defect rate in sample 2 is lower than the defect rate in sample 5.

[0065] From these comparisons, if the condition that thickness T2 is 0.8 times or more than thickness T1 or the condition that thickness T2 is 0.45 times or less than width W2 is also met, the third copper layer 20 extending from above the first copper layer 11 around the through hole 13 along the inner wall surface of the through hole 13 and the third copper layer 20 extending from above the second copper layer 12 exposed inside the through hole 13 along the inner wall surface of the through hole 13 become more easily connected, and it becomes possible to form the third copper layer 20 more appropriately on the inner wall surface of the through hole 13.

[0066] Second Embodiment A printed wiring board according to a second embodiment will be described. The printed wiring board according to the second embodiment is designated as a printed wiring board 200.

[0067] <Configuration of Printed Wiring Board 200> The configuration of the printed wiring board 200 will be described below.

[0068] Fig. 10 is a cross-sectional view of printed wiring board 200. As shown in Fig. 10, printed wiring board 200 has a first insulating layer 50, a first copper layer 51, an adhesive layer 60, a second insulating layer 70, a second copper layer 71, and a third copper layer 80.

[0069] The constituent material of the first insulating layer 50 has electrical insulating properties and flexibility. The constituent material of the first insulating layer 50 is, for example, polyimide. However, the constituent material of the first insulating layer 50 is not limited to this. The first insulating layer 50 has a first main surface 50a. The first main surface 50a is a surface perpendicular to the thickness direction of the first insulating layer 50 and constitutes either the front or back surface of the first insulating layer 50.

[0070] The first copper layer 51 is made of copper or a copper alloy. The first copper layer 51 is disposed on the first main surface 50a. A fourth copper layer 52 may be interposed between the first copper layer 51 and the first main surface 50a. In this case, the first copper layer 51 is an electroplated copper layer.

[0071] The adhesive layer 60 is disposed on the first main surface 50 a so as to cover the first copper layer 51 (and the fourth copper layer 52). The adhesive layer 60 is made of an adhesive, such as an epoxy adhesive.

[0072] The material of the second insulating layer 70 has electrical insulation properties and flexibility. The material of the second insulating layer 70 is, for example, polyimide. However, the material of the second insulating layer 70 is not limited to this. The second insulating layer 70 has a second main surface 70a and a third main surface 70b. The second main surface 70a and the third main surface 70b are surfaces perpendicular to the thickness direction of the second insulating layer 70 and constitute the front and back surfaces of the second insulating layer 70. The third main surface 70b is the surface opposite the second main surface 70a. The second insulating layer 70 is disposed on the adhesive layer 60 so that the second main surface 70a faces the adhesive layer 60.

[0073] The second copper layer 71 is made of copper or a copper alloy and is disposed on the third main surface 70b.

[0074] A through hole 72 is formed in the adhesive layer 60, the second insulating layer 70, and the second copper layer 71. The through hole 72 penetrates the adhesive layer 60, the second insulating layer 70, and the second copper layer 71 in the thickness direction. The first copper layer 51 is exposed through the through hole 72. The width of the through hole 72 on the third main surface 70b is defined as width W2. Here, width W2 is the minimum width of the through hole 72 on the third main surface 70b. The minimum width of the through hole 72 on the third main surface 70b refers to the diameter of the inscribed circle of the shape of the through hole 72 in a plan view on the third main surface 70b. Width W2 is, for example, 25 μm or more and 250 μm or less. The sum of the thickness of the second insulating layer 70 and the thickness of the adhesive layer 60 between the first copper layer 51 and the second insulating layer 70 is defined as thickness T3. Thickness T3 is, for example, 12.5 μm or more and 250 μm or less. The thickness T3 is an average value obtained by measuring 10 arbitrary points on the cross-sectional photograph. The shape of the through-hole 72 in plan view is, for example, circular. However, the planar shape of the through-hole 72 is not limited to this.

[0075] The third copper layer 80 is disposed on the first copper layer 51 exposed inside the through hole 72, on the inner wall surface of the through hole 72, and on the second copper layer 71 around the through hole 72. The third copper layer 80 is also disposed on the second copper layer 71 outside the periphery of the through hole 72. The constituent material of the third copper layer 80 is copper or a copper alloy. The third copper layer 80 may be an electrolytically plated copper layer.

[0076] The palladium concentration in the region of the third copper layer 80 extending from the interface between the first copper layer 51 and the third copper layer 80 exposed inside the through hole 72 to a depth of 10 nm is 0.5 mass percent or less. The palladium concentration in the region of the third copper layer 80 extending from the interface between the second insulating layer 70 (the inner wall surface of the through hole 72) and the third copper layer 80 to a depth of 10 nm is 0.5 mass percent or less. The palladium concentration in the region of the third copper layer 80 extending from the interface between the second copper layer 71 and the third copper layer 80 to a depth of 10 nm is 0.5 mass percent or less. The palladium concentration in the region of the third copper layer 80 is measured, for example, by energy dispersive X-ray spectroscopy of a cross section of the hole cut with a focused ion beam.

[0077] The thickness of the third copper layer 80 on the second copper layer 71 is defined as thickness T4. Thickness T4 is the average value of measurements taken at 10 arbitrary points on the cross-sectional photograph. Thickness T4 may be 0.4 times or more the thickness T3 and 0.6 times or less the width W2. Thickness T4 may be 0.8 times or more the thickness T3 and 0.45 times or less the width W2. Thickness T4 is, for example, 10 μm or more and 45 μm or less.

[0078] The printed wiring board 200 may further include a fifth copper layer 53, a sixth copper layer 54, an adhesive layer 61, a third insulating layer 73, a seventh copper layer 74, and an eighth copper layer 81. A through hole 55 may be formed in the first insulating layer 50, the fourth copper layer 52, and the fifth copper layer 53. The through hole 55 penetrates the first insulating layer 50, the fourth copper layer 52, and the fifth copper layer 53 in the thickness direction.

[0079] The fourth main surface 50b is a surface perpendicular to the thickness direction of the first insulating layer 50 and is the surface opposite to the first main surface 50a. A fifth copper layer 53 is disposed on the fourth main surface 50b. The fifth copper layer 53 is made of copper or a copper alloy. A sixth copper layer 54 is disposed on the fifth copper layer 53. The sixth copper layer 54 is made of copper or a copper alloy. The sixth copper layer 54 is an electroplated copper layer. The first copper layer 51 and the sixth copper layer 54 are connected to each other on the inner wall surface of the through hole 55.

[0080] The adhesive layer 61 is disposed on the fourth main surface 50b so as to cover the fifth copper layer 53 and the sixth copper layer 54. The adhesive layer 61 is made of an adhesive, such as an epoxy adhesive.

[0081] The third insulating layer 73 is made of a material that is electrically insulating and flexible. The material is, for example, polyimide. However, the material of the third insulating layer 73 is not limited to this. The third insulating layer 73 has a fifth main surface 73a and a sixth main surface 73b. The fifth main surface 73a and the sixth main surface 73b are surfaces perpendicular to the thickness direction of the third insulating layer 73 and form the front and back surfaces of the third insulating layer 73. The sixth main surface 73b is the surface opposite the fifth main surface 73a. The third insulating layer 73 is disposed on the adhesive layer 61 such that the fifth main surface 73a faces the adhesive layer 61.

[0082] The seventh copper layer 74 is made of copper or a copper alloy and is disposed on the sixth main surface 73b.

[0083] A through hole 75 is formed in the adhesive layer 61, the third insulating layer 73, and the seventh copper layer 74. The through hole 75 penetrates the adhesive layer 61, the third insulating layer 73, and the seventh copper layer 74 in the thickness direction. The sixth copper layer 54 is exposed through the through hole 75. The width of the through hole 75 on the sixth main surface 73b is defined as width W3. Here, width W3 is the minimum width of the through hole 75 on the sixth main surface 73b. The "minimum width of the through hole 75 on the sixth main surface 73b" refers to the diameter of the inscribed circle of the shape of the through hole 75 in a plan view on the sixth main surface 73b. The width W3 is, for example, 25 μm or more and 250 μm or less. The sum of the thickness of the third insulating layer 73 and the thickness of the adhesive layer 61 between the sixth copper layer 54 and the third insulating layer 73 is defined as thickness T5. The shape of the through hole 75 in a plan view is, for example, circular. However, the planar shape of the through-hole 75 is not limited to this. The thickness T5 is, for example, 12.5 μm or more and 250 μm or less. The thickness T5 is an average value obtained by measuring arbitrary 10 points on the cross-sectional photograph.

[0084] The eighth copper layer 81 is disposed on the sixth copper layer 54 exposed inside the through hole 75, on the inner wall surface of the through hole 75, and on the seventh copper layer 74 around the through hole 75. The eighth copper layer 81 is also disposed on the seventh copper layer 74 outside the periphery of the through hole 75. The constituent material of the eighth copper layer 81 is copper or a copper alloy. The eighth copper layer 81 may be an electrolytically plated copper layer.

[0085] The thickness of the eighth copper layer 81 on the seventh copper layer 74 is defined as thickness T6. Thickness T6 may be 0.4 times or more the thickness T5 and 0.6 times or less the width W3. Thickness T6 may be 0.8 times or more the thickness T5 and 0.45 times or less the width W3. Thickness T6 is, for example, 10 μm or more and 45 μm or less.

[0086] The palladium concentration in a region of the eighth copper layer 81 extending from the interface between the sixth copper layer 54 and the eighth copper layer 81 exposed inside the through hole 75 to a depth of 10 nm is 0.5 mass percent or less. The palladium concentration in a region of the eighth copper layer 81 extending from the interface between the third insulating layer 73 (the inner wall surface of the through hole 75) and the eighth copper layer 81 to a depth of 10 nm is 0.5 mass percent or less. The palladium concentration in a region of the eighth copper layer 81 extending from the interface between the seventh copper layer 74 and the eighth copper layer 81 to a depth of 10 nm is 0.5 mass percent or less. The palladium concentration in the region of the eighth copper layer 81 is measured, for example, by energy dispersive X-ray spectroscopy of a cross section of the hole cut with a focused ion beam.

[0087] 10 includes circuits formed on both sides of the first insulating layer 50 and two through holes (through hole 72 and through hole 75) connecting the two sides, but the printed wiring board of the present disclosure is not limited to this. A printed wiring board may also be formed by combining a plurality of single-sided boards, and the circuit may include two or more, three or more, or six or more layers.

[0088] <Method for Manufacturing Printed Wiring Board 200> A method for manufacturing printed wiring board 200 will be described below.

[0089] 11 is a manufacturing process diagram of the printed wiring board 200. As shown in FIG. 11, the manufacturing method of the printed wiring board 200 includes a preparation step S11, a first hole drilling step S12, a first resist pattern forming step S13, a first electrolytic plating step S14, a first resist pattern removing step S15, and a first etching step S16.

[0090] The method for manufacturing the printed wiring board 200 further includes an insulating layer attaching step S17, a second hole drilling step S18, a second resist pattern forming step S19, a second electrolytic plating step S20, a second resist pattern removing step S21, and a second etching step S22.

[0091] 12 is a cross-sectional view illustrating the preparation step S11. As shown in FIG. 12, in the preparation step S11, a first insulating layer 50 is prepared. The first insulating layer 50 prepared in the preparation step S11 has a fourth copper layer 52 disposed on a first main surface 50a and a fifth copper layer 53 disposed on a fourth main surface 50b. At this stage, no through holes 55 are formed in the first insulating layer 50, the fourth copper layer 52, and the fifth copper layer 53.

[0092] The first hole drilling step S12 is performed after the preparation step S11. Fig. 13 is a cross-sectional view illustrating the first hole drilling step S12. As shown in Fig. 13, in the first hole drilling step S12, a through hole 55 is formed. The through hole 55 is formed, for example, by irradiating with a laser beam.

[0093] The first resist pattern forming step S13 is performed after the first hole making step S12. Fig. 14 is a cross-sectional view illustrating the first resist pattern forming step S13. As shown in Fig. 14, in the first resist pattern forming step S13, a resist pattern 31 is formed on the fourth copper layer 52, and a resist pattern 32 is formed on the fifth copper layer 53. The resist patterns 31 and 32 are formed, for example, by applying a dry film resist and then exposing and developing the applied dry film resist.

[0094] The first electrolytic plating step S14 is performed after the first resist pattern forming step S13. Fig. 15 is a cross-sectional view illustrating the first electrolytic plating step S14. As shown in Fig. 15 , in the first electrolytic plating step S14, electrolytic plating is performed to form a first copper layer 51 on the fourth copper layer 52 exposed through the openings of the resist pattern 31, and a sixth copper layer 54 on the fifth copper layer 53 exposed through the openings of the resist pattern 32. Furthermore, as the first copper layer 51 and the sixth copper layer 54 grow, the first copper layer 51 and the sixth copper layer 54 are connected to each other and integrated at the through holes 55.

[0095] The first resist pattern removing step S15 is performed after the first electrolytic plating step S14. Fig. 16 is a cross-sectional view illustrating the first resist pattern removing step S15. As shown in Fig. 16, in the first resist pattern removing step S15, the resist pattern 31 and the resist pattern 32 are removed.

[0096] The first etching step S16 is performed after the first resist pattern removing step S15. Fig. 17 is a cross-sectional view illustrating the first etching step S16. As shown in Fig. 17, in the first etching step S16, the fourth copper layer 52 that was under the resist pattern 31 and the fifth copper layer 53 that was under the resist pattern 32 are removed by etching.

[0097] The insulating layer attaching step S17 is performed after the first etching step S16. FIG. 18 is a cross-sectional view illustrating the insulating layer attaching step S17. As shown in FIG. 18, in the insulating layer attaching step S17, the second insulating layer 70 and the third insulating layer 73 are attached. In the insulating layer attaching step S17, first, an uncured adhesive layer 60 is applied to the first main surface 50a so as to cover the first copper layer 51 and the fourth copper layer 52, and an uncured adhesive layer 61 is applied to the fourth main surface 50b so as to cover the fifth copper layer 53 and the sixth copper layer 54. Second, the second insulating layer 70 and the third insulating layer 73 are prepared. At this stage, the second copper layer 71 is disposed on the third main surface 70b, and the seventh copper layer 74 is disposed on the sixth main surface 73b.

[0098] Third, the second insulating layer 70 is disposed on the adhesive layer 60 so that the second main surface 70a faces the adhesive layer 60, and the third insulating layer 73 is disposed on the adhesive layer 61 so that the fifth main surface 73a faces the adhesive layer 61. Fourth, the adhesive layer 60 and the adhesive layer 61 are heated and cured, thereby attaching the second insulating layer 70 and the third insulating layer 73.

[0099] The second hole drilling step S18 is performed after the insulating layer attaching step S17. Fig. 19 is a cross-sectional view illustrating the second hole drilling step S18. As shown in Fig. 19, in the second hole drilling step S18, the through holes 72 and 75 are formed by, for example, irradiating with laser light.

[0100] The second resist pattern forming step S19 is performed after the second hole opening step S18. Fig. 20 is a cross-sectional view illustrating the second resist pattern forming step S19. As shown in Fig. 20, in the second resist pattern forming step S19, a resist pattern 33 is formed on the second copper layer 71, and a resist pattern 34 is formed on the seventh copper layer 74. The resist patterns 33 and 34 are formed, for example, by applying a dry film resist and then exposing and developing the applied dry film resist.

[0101] The second electrolytic plating step S20 is performed after the second resist pattern forming step S19. Fig. 21 is a cross-sectional view illustrating the second electrolytic plating step S20. As shown in Fig. 20, in the second electrolytic plating step S20, electrolytic plating is performed to form a third copper layer 80 on the second copper layer 71 exposed from the openings of the resist pattern 33, on the inner wall surfaces of the through holes 72, and on the first copper layer 51 exposed inside the through holes 72. In addition, in the second electrolytic plating step S20, an eighth copper layer 81 is formed on the seventh copper layer 74 exposed from the openings of the resist pattern 34, on the inner wall surfaces of the through holes 75, and on the sixth copper layer 54 exposed inside the through holes 75.

[0102] The second resist pattern removing step S21 is performed after the second electrolytic plating step S20. FIG. 22 is a cross-sectional view illustrating the second resist pattern removing step S21. As shown in FIG. 22, in the second resist pattern removing step S21, the resist patterns 33 and 34 are removed. The second etching step S22 is performed after the second resist pattern removing step S21. In the second etching step S22, the second copper layer 71 that was under the resist pattern 33 and the seventh copper layer 74 that was under the resist pattern 34 are removed by etching. In this way, the printed wiring board 200 having the structure shown in FIG. 10 is manufactured.

[0103] <Effects of Printed Wiring Board 200> The effects of the printed wiring board 200 will be described below.

[0104] In the manufacturing method of the printed wiring board 200, an electroless plating step is not performed, and therefore palladium does not remain at the interface between the second insulating layer 70 (the inner wall surface of the through hole 72) and the third copper layer 80, and at the interface between the first copper layer 51 exposed inside the through hole 72 and the third copper layer 80. Furthermore, in the manufacturing method of the printed wiring board 200, foreign matter and the like on the surface of the first copper layer 51 exposed inside the through hole 72 is removed by a degreasing treatment before development in the second resist pattern formation step S19 and the second electrolytic plating step S20 are performed.

[0105] In this way, printed wiring board 200 can prevent the occurrence of disconnections in blind via holes due to peeling of third copper layer 80 caused by palladium, foreign matter, etc. For the same reason, printed wiring board 200 can prevent the occurrence of disconnections in blind via holes due to peeling of eighth copper layer 81 caused by palladium, foreign matter, etc.

[0106] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include any modifications within the scope of the claims and meanings equivalent to the claims.

[0107] REFERENCE SIGNS LIST 10 insulating layer 10a first main surface 10b second main surface 11 first copper layer 12 second copper layer 13 through hole 20 third copper layer 30, 31, 32, 33, 34 resist pattern 40 electrolessly plated copper layer 50 first insulating layer 50a first main surface 50b fourth main surface 51 first copper layer 52 fourth copper layer 53 fifth copper layer 54 sixth copper layer 55 through hole 60, 61 adhesive layer 70 second insulating layer 70a second main surface 70b third main surface 71 second copper layer 72 through hole 73 third insulating layer 73a fifth main surface 73b sixth main surface 74 seventh copper layer 75 through hole 80 third copper layer 81 eighth copper layer 100, 100A, 200 printed wiring board S1 Preparation step S2 First etching step S3 Hole drilling step S4 Desmearing step S5 Resist pattern forming step S6 Electrolytic plating step S7 Resist pattern removing step S8 Second etching step S9 Electroless plating step S11 Preparation step S12 First hole drilling step S13 First resist pattern forming step S14 First electrolytic plating step S15 First resist pattern removing step S16 First etching step S17 Insulation layer attaching step S18 Second hole drilling step S19 Second resist pattern forming step S20 Second electrolytic plating step S21 Second resist pattern removing step S22 Second etching step T1, T2, T3, T4, T5, T6 Thickness W1, W2, W3 Width

Claims

1. an insulating layer having a first major surface and a second major surface; a first copper layer disposed on the first major surface; a second copper layer disposed on the second major surface; and and a third copper layer; a through hole is formed in the insulating layer and the first copper layer, the through hole reaching the second copper layer; the third copper layer is disposed on the second copper layer inside the through hole, on an inner wall surface of the through hole, and on the first copper layer around the through hole; A printed wiring board, wherein a single copper layer is disposed on the inner wall surface of the through hole, the single copper layer being the third copper layer.

2. 2. The printed wiring board according to claim 1, wherein a thickness of the third copper layer on the first copper layer is 0.4 times or more the thickness of the insulating layer and is 0.6 times or less the minimum width of the through hole on the first main surface.

3. 2. The printed wiring board according to claim 1, wherein a thickness of the third copper layer on the first copper layer is 0.8 times or more the thickness of the insulating layer and is 0.45 times or less the minimum width of the through hole on the first main surface.

4. 2. The printed wiring board according to claim 1, wherein a concentration of palladium in a region of the third copper layer from an interface between the insulating layer and the third copper layer to a depth of 10 nm and in a region of the third copper layer from an interface between the second copper layer and the third copper layer to a depth of 10 nm is 0.5 mass percent or less.

5. The printed wiring board according to claim 1 , wherein the third copper layer is an electrolytically plated copper layer.

6. a first insulating layer having a first major surface; a first copper layer disposed on the first major surface; an adhesion layer disposed on the first major surface so as to cover the first copper layer; a second insulating layer having a second main surface and a third main surface, the second insulating layer being disposed on the adhesive layer such that the second main surface faces the adhesive layer; a second copper layer disposed on the third major surface; and and a third copper layer; a through hole reaching the first copper layer is formed in the second insulating layer, the second copper layer and the adhesive layer; the third copper layer is disposed on the first copper layer inside the through hole, on an inner wall surface of the through hole, and on the second copper layer around the through hole; A printed wiring board, wherein a single copper layer is disposed on the inner wall surface of the through hole, the single copper layer being the third copper layer.

7. 7. The printed wiring board according to claim 6, wherein the thickness of the third copper layer on the second copper layer is 0.4 times or more the sum of the thickness of the second insulating layer and the thickness of the adhesive layer between the first copper layer and the second insulating layer, and is 0.6 times or less the minimum width of the through hole on the third main surface.

8. 7. The printed wiring board according to claim 6, wherein the thickness of the third copper layer on the second copper layer is 0.8 times or more the sum of the thickness of the second insulating layer and the thickness of the adhesive layer between the first copper layer and the second insulating layer, and is 0.45 times or less the minimum width of the through hole on the third main surface.

9. 7. The printed wiring board according to claim 6, wherein a concentration of palladium in a region of the third copper layer extending from an interface between the second insulating layer and the third copper layer to a depth of 10 nm and in a region of the third copper layer extending from an interface between the first copper layer and the third copper layer to a depth of 10 nm is 0.5 mass percent or less.

10. The printed wiring board according to claim 6 , wherein the third copper layer is an electrolytically plated copper layer.

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