Semiconductor device manufacturing method and bonded wafer

Abstract

The purpose of the present disclosure is to improve productivity and suppress cracking of wafers in manufacturing a semiconductor device in which wafers are re-used. A semiconductor device manufacturing method according to the present disclosure comprises: (a) a step for obtaining, from a plurality of SiC wafers (13, 17) by dividing the SiC wafers (13, 17) in the thickness direction, at least each one of divided wafers (20, 23) not including device structures (12, 16); (b) a step for obtaining a bonded wafer (24) by bonding the divided wafers (20, 23) obtained from the different SiC wafers (13, 17); and (c) a step for forming a device structure (26) on the surface of the bonded wafer (24).

Description

Semiconductor device manufacturing method and bonded wafer

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a bonded wafer.

[0002] Conventionally, in order to reduce the cost of semiconductor devices, techniques for effectively utilizing expensive single crystal wafers have been proposed. For example, Patent Document 1 proposes a method of slicing a wafer during the thinning step of a device process and reusing the divided wafers on which no devices are formed.

[0003] Japanese Patent Application Laid-Open No. 2019-50362

[0004] In the method disclosed in Patent Document 1, in order to reduce cracks in the divided wafers to be reused, it is necessary to form a thick epitaxial film on the divided wafers as a buffer layer that is not related to device operation, so that the divided wafers have the same thickness as the wafers from which they were divided. Forming a thick epitaxial film is disadvantageous from the viewpoint of productivity. On the other hand, forming a thin epitaxial film increases the risk of cracks when the divided wafers are reused.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to improve productivity and suppress cracking of wafers in the manufacture of semiconductor devices using reused wafers.

[0006] The method for manufacturing a semiconductor device according to the present disclosure includes: (a) obtaining at least one first divided wafer that does not include a device structure from each of a plurality of first wafers by dividing each of the plurality of first wafers in the thickness direction; (b) obtaining a first bonded wafer that is a bonded wafer by bonding the plurality of first divided wafers obtained from different first wafers; and (c) forming a device structure on a surface of the first bonded wafer.

[0007] According to the semiconductor device manufacturing method of the present disclosure, a device structure is formed on a bonded wafer formed by bonding split wafers together. Therefore, it is possible to form a bonded wafer with a sufficient thickness that takes cracks into consideration at a lower cost than forming an epitaxial film on split wafers, and to reuse the wafer. Objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0008] FIG. 1 is a diagram showing a basic process of a semiconductor device manufacturing method according to a first embodiment; FIG. 2 is a flowchart showing a semiconductor device manufacturing method according to a first embodiment; FIG. 3 is a diagram showing a semiconductor device manufacturing method according to a first embodiment when the thickness of the bonded wafer is 500 μm; FIG. 4 is a diagram showing a semiconductor device manufacturing method according to a first embodiment when the thickness of the bonded wafer is 500 μm; FIG. 5 is a diagram showing a semiconductor device manufacturing method according to a first embodiment when the thickness of the bonded wafer is 350 μm; FIG. 6 is a diagram showing a semiconductor device manufacturing method according to a first embodiment when the thickness of the bonded wafer is 350 μm; FIG. 7 is a diagram showing a depth of a bonding surface in a bonded wafer formed of two divided wafers; FIG. 8 is a diagram showing a depth of a bonding surface in a bonded wafer formed of three divided wafers; FIG. 9 is a diagram showing a pattern of wafer division timing in the semiconductor device manufacturing method according to the first embodiment; FIG. 10 is a diagram showing a basic process in the case where a SiC wafer is divided before formation of an epitaxial film in the semiconductor device manufacturing method according to the first embodiment; FIG. 11 is a diagram showing a basic process of a semiconductor device manufacturing method according to a modification of the second embodiment; FIG. 12 is a diagram showing a basic process of a semiconductor device manufacturing method according to a modification of the third embodiment;

[0009] <A. First Embodiment> <A-1. Basic Process> Fig. 1 is a schematic diagram showing the basic process of a method for manufacturing a semiconductor device in this embodiment. Fig. 2 is a flowchart of the method for manufacturing a semiconductor device in this embodiment. The method for manufacturing a semiconductor device in this embodiment will be described below with reference to Figs. 1 and 2.

[0010] First, in step S101, an epitaxial film 11 is formed on a single-crystal SiC wafer 10, and a device surface structure (hereinafter referred to as a device structure) 12 is formed on the epitaxial film 11. Formation of the device structure 12 includes ion implantation and formation of a surface electrode. The device structure 12 is, for example, a SiC power device structure. When a GaN wafer or a gallium oxide wafer is used instead of a SiC wafer, the device structure 12 is, for example, a GaN high-frequency device structure, a GaN power device structure, or a gallium oxide power device structure. A GaN high-frequency device structure, a GaN power device structure, or a gallium oxide power device structure may be formed on the SiC wafer. The SiC wafer 10 on which the epitaxial film 11 and the device structure 12 are formed is referred to as a SiC wafer 13.

[0011] In step S101, a SiC wafer 17 similar to the SiC wafer 13 is formed. That is, an epitaxial film 15 is formed on a single crystal SiC wafer 14, and a device structure 16 is formed on the epitaxial film 15. The SiC wafer 14 on which the epitaxial film 15 and the device structure 16 are formed is referred to as the SiC wafer 17. The SiC wafers 13 and 17 are also referred to as first wafers. Here, the SiC wafers 10 and 14 may be bonded wafers formed by bonding multiple SiC wafers. The SiC wafers 10 and 14 have N-type or P-type conductivity, or are semi-insulating.

[0012] Next, in step S102, the SiC wafer 13 is divided into a device-equipped wafer 19 including the device structure 12 and a divided wafer 20 not including the device structure 12. The device-equipped wafer 19 includes a SiC wafer 18 divided from the SiC wafer 10, an epitaxial film 11 on the SiC wafer 18, and a device structure 12 on the epitaxial film 11.

[0013] In step S102, the SiC wafer 17 is divided in the same manner as the SiC wafer 13. That is, the SiC wafer 17 is divided into a device-equipped wafer 22 including the device structure 16 and a divided wafer 23 not including the device structure 16. The device-equipped wafer 22 includes a SiC wafer 21 divided from the SiC wafer 14, an epitaxial film 15 on the SiC wafer 21, and a device structure 16 on the epitaxial film 15. The device-equipped wafers 19 and 22 are also referred to as first device-equipped wafers, and the divided wafers 20 and 23 are also referred to as first divided wafers. Note that laser slicing technology or the like is used to divide the SiC wafers 13 and 17 in this step.

[0014] Then, in step S103, the backside of the device-equipped wafers 19, 22, which is the side opposite to the device structures 12, 16, is processed. First, the damaged layer on the backside of the device-equipped wafers 19, 22 that has been damaged by laser slicing is removed by grinding or polishing, and the device-equipped wafers 19, 22 are adjusted to the desired thickness. Then, normal backside processes, such as the formation of backside electrodes (not shown), are performed on the backside of the device-equipped wafers 19, 22.

[0015] Next, in step S104, the front surfaces of the divided wafers 20 and 23 are processed. Because the divided wafers 20 and 23 also contain damaged layers caused by laser slicing, these damaged layers are removed by grinding or polishing, and the divided wafers 20 and 23 are then adjusted to the desired thickness. Taking into account the depth of the bonding surface in the bonded wafer (described below), the thickness of the divided wafers 20 and 23 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. When adjusting the thickness of the divided wafers 20 and 23, the back surfaces of the divided wafers 20 and 23 may also be processed, for example, by grinding or polishing, as needed. Processing the back surfaces not only adjusts the thickness but also removes scratches and other imperfections that may have occurred during the device process. As a result, a high-quality bonded wafer can be obtained in the subsequent step S105. Here, a high-quality bonded wafer refers to a wafer that has been subjected to damage suppression, warpage suppression, or improved flatness. It can be said that processing the rear surface side of the divided wafers 20 and 23 is a step that has a certain effect in producing a wafer with devices by dividing and bonding.

[0016] Then, in step S105, the divided wafers 20 and 23 are bonded together. The wafer formed by bonding the divided wafers 20 and 23 together is referred to as a bonded wafer 24. The bonded wafer 24 is also referred to as a first bonded wafer. At this time, the bonding surfaces of the divided wafers 20 and 23 may be subjected to surface processing such as grinding, polishing, or CMP. To reduce warpage in the bonded wafer 24, the warpage or surface condition of the divided wafers 20 and 23 may be inspected, and the combination of the divided wafers 20 and 23 to be bonded may be determined based on the inspection results. This results in a high-quality bonded wafer. Here, the two divided wafers 20 and 23 may be fabricated simultaneously or separately. That is, the two divided wafers 20 and 23 may be fabricated simultaneously or sequentially using different processing equipment, or may be fabricated sequentially using the same processing equipment. This enables flexible production and improves productivity of the divided wafers. Although the description here is of two divided wafers 20 and 23 being bonded together, any number of divided wafers, three or more, may be bonded together to form the bonded wafer 24 .

[0017] The split wafers 20, 23 are bonded together by, for example, room-temperature bonding. Room-temperature bonding results in a clean bonded interface, free from metal layers and the like. Furthermore, room-temperature bonding results in an amorphous layer at the bonded interface. After bonding the split wafers 20, 23, the bonded wafer 24 may be processed to a desired thickness by grinding, polishing, CMP, or the like. This process results in the bonded wafer 24 having a thickness similar to that of a commonly used SiC wafer. This allows the split wafers 20, 23 to be reused at lower cost and without the risk of cracking, compared to when a thick epitaxial film is formed on a thin SiC wafer to maintain overall strength.

[0018] Before bonding, the divided wafers 20, 23 may be beveled to remove sharp portions at the intersections of the outer circumferential surfaces and the cut surfaces, in other words, the corners of the divided wafers 20, 23. In this case, the edge of the bonded wafer 24 has a cross-sectional shape resembling the number "3" or a polygonal line shape with five to seven inflection points. If the edges of the divided wafers 20, 23 are curved, the edge of the bonded wafer 24 will have a cross-sectional shape resembling the number "3" after bonding. If the edges of the divided wafers 20, 23 are each triangular, one inflection point will overlap after bonding, resulting in the edge of the bonded wafer 24 having a polygonal line shape with five inflection points. If the edges of the divided wafers 20, 23 are each trapezoidal, one inflection point will overlap after bonding, resulting in the edge of the bonded wafer 24 having a polygonal line shape with seven inflection points. In this case, beveling after bonding is not required, and the amount of removal required is small, allowing for a larger area of ​​the bonded wafer 24.

[0019] Alternatively, beveling may be performed on bonded wafer 24 without performing beveling on divided wafers 20 and 23 before bonding. In this case, the bevel shape of the bonded wafer will be a curved shape like ")" or a trapezoidal shape in cross section, similar to that of a normal wafer that is not bonded. In this case, the effect of preventing chipping of bonded wafer 24 is enhanced compared to a shape like "3". Also, beveling may be performed on both divided wafers 20 and 23 before bonding and bonded wafer 24 after bonding. In this case, it is possible to obtain the effects of preventing chipping during processing and chipping of bonded wafer 24.

[0020] Next, in step S106, an epitaxial film 25 is formed on the bonded wafer 24, and a device structure 26 is further formed on the epitaxial film 25. The wafer thus formed is referred to as a bonded wafer 27.

[0021] Thereafter, in step S107, the bonded wafer 27 is divided in the thickness direction to obtain a device-equipped wafer 29 including the device structure 26 and a divided wafer 30 not including the device structure 26. The device-equipped wafer 29 is also referred to as a second device-equipped wafer, and the divided wafer 30 is also referred to as a second divided wafer. The device-equipped wafer 29 has a structure in which an epitaxial film 25 is formed on the SiC wafer 10, and the device structure 26 is formed on the epitaxial film 25. This step is similar to step S102.

[0022] Although the bonded wafer 27 includes the bonding surfaces of the two divided wafers 20 and 23, it is desirable that this bonding surface not be included in the device-equipped wafer 29. This prevents variations in device characteristics due to the bonding surface in the device-equipped wafer 29. Here, if the bonded wafer 27 is formed by room-temperature bonding, an amorphous layer will form at the bonding interface. Therefore, it can be said that it is desirable that the SiC wafer 28 of the device-equipped wafer 29 does not include an amorphous layer. However, even if the device-equipped wafer 29 includes the bonding surfaces of the two divided wafers 20 and 23, this may not be a problem, taking into account the type of device structure or the characteristics required for the device. In this case, it is not necessary to avoid including the bonding surface when obtaining the device-equipped wafer 29, and this allows for greater flexibility in process adjustments or thickness adjustments in the wafer separation process.

[0023] The device-equipped wafer 29 obtained in step S107 is again subjected to backside processing (not shown) in step S103. The divided wafer 30 obtained in step S107 may again be subjected to processing from step S104 onward. The divided wafer 30 can then be bonded with another divided wafer to be used to create a further wafer with devices. That is, the processing from step S105 to step S107 is repeated at least once, using the divided wafer 30, which is the second divided wafer, as a new first divided wafer.

[0024] In this way, three device-equipped wafers 19, 22, and 29 were obtained from the two SiC wafers 13 and 17. By repeating the above process, it is possible to obtain a greater number of device-equipped wafers than the original SiC wafers. Furthermore, it is possible to produce multiple device-equipped wafers based on a SiC wafer containing a small amount of various defects, a so-called high-quality wafer, and thus it is possible to efficiently produce a large number of high-quality devices.

[0025] A bonded wafer obtained by bonding multiple divided wafers may have different amounts of crystal defects, such as threading dislocations, across the bonded surface depending on the state of each divided wafer. In this case, the crystal defect density in the surface layer of the bonded wafer may differ between the device structure-forming side and the opposite side, or the crystal defect density near the bonded interface may differ. Furthermore, threading dislocations, which are continuous from the front to back surface in a normal wafer, become discontinuous at the bonded interface in a bonded wafer. However, even if the amount of various defects differs between multiple divided wafers, the impact of this on device processing or device characteristics is negligible. Here, by appropriately selecting the device structure or divided wafers, the impact of the above-mentioned defect discontinuities on device processing or device characteristics can be further reduced. Furthermore, by excluding the bonded surface from a wafer with devices, the impact of the above-mentioned defect discontinuities on device characteristics can be eliminated.

[0026] <A-2. Actual Operation> Figures 3 to 6 are diagrams showing the flow when the basic process shown in Figure 1 is applied to actual operation. Figures 3 and 4 show an example of the flow for SiC wafers with a thickness of 500 μm, and Figures 5 and 6 show an example of the flow for SiC wafers with a thickness of 350 μm.

[0027] 3 and 5 show the process starting from SiC wafers A3 and B3 until bonded wafer E1 is formed. FIGS. 4 and 6 show the process until bonded wafer G1 is formed from bonded wafer E1 and SiC wafer F3. In FIGS. 3 to 6, the numbers inside the wafers indicate the wafer thickness (μm). Furthermore, the numbers in parentheses above or below the wafers indicate the thickness (μm) of the removed wafer. Furthermore, the dashed lines inside the wafers indicate the bonding surfaces, and the numbers in square brackets next to the bonding surfaces indicate the depth (μm) of the bonding surfaces, i.e., the depth (μm) from the front surfaces of the bonded wafers to the bonding surfaces. However, the thicknesses and depths of each layer shown in these figures are merely examples and can be changed as appropriate.

[0028] As shown in FIG. 3 , SiC wafers A3 and B3 are prepared. The thickness of SiC wafers A3 and B3, including the epitaxial film, is 510 μm. SiC wafer A3 is a SiC wafer A1 with device structure A2 formed on the front surface thereof. SiC wafer B3 is a SiC wafer B1 with device structure B2 formed on the front surface thereof. In the descriptions of FIGS. 3 to 6 , the device structure is assumed to include the epitaxial film. For example, device structure A2 more specifically includes an epitaxial film formed on SiC wafer A1 and a device structure formed on the epitaxial film. This also applies to the other device structures appearing in the descriptions of FIGS. 3 to 6 .

[0029] The SiC wafer A3 is divided into a device-equipped wafer A4 having the device structure A2 and a divided wafer A12 without the device structure A2. The device-equipped wafer A4 is composed of the SiC wafer A11 and the device structure A2 thereon. 50 μm is removed from the back surface of the SiC wafer A11, leaving the SiC wafer A11 with a thickness of 100 μm. The divided wafer A12 has 50 μm removed from the front surface and 10 μm removed from the back surface, leaving a thickness of 300 μm.

[0030] The rear surface of the divided wafer A12 is further removed by 25 μm, resulting in a thickness of 275 μm.

[0031] The SiC wafer B3 is divided into a device-equipped wafer B4 having the device structure B2 and a divided wafer B12 without the device structure B2. The device-equipped wafer B4 is composed of the SiC wafer B11 and the device structure B2 thereon. The back surface of the SiC wafer B11 is removed by 50 μm, resulting in a thickness of 100 μm. The divided wafer B12 is removed by 50 μm on the front surface and 10 μm on the back surface, resulting in a thickness of 300 μm.

[0032] The front surface of the divided wafer B12 is further removed by 25 μm, resulting in a thickness of 275 μm.

[0033] Next, the divided wafers A12 and B12 are bonded together to obtain a bonded wafer C1 having a thickness of 550 μm. Here, the depth of the bonded surface of the bonded wafer C1 is 275 μm.

[0034] Thereafter, the front surface of the bonded wafer C1 is removed by a thickness of 50 μm, so that the thickness of the bonded wafer C1 is 500 μm. Here, the depth of the bonded surface of the bonded wafer C1 is 225 μm.

[0035] Next, a device structure C2 is formed on the bonded wafer C1. The wafer consisting of the bonded wafer C1 and the device structure C2 is referred to as a bonded wafer C3. The thickness of the bonded wafer C3 is 510 μm, and the depth of the bonded surface in the bonded wafer C3 is 235 μm.

[0036] The bonded wafer C3 is then divided into a device-equipped wafer C4 having the device structure C2 and a divided wafer C5 without the device structure C2. The device-equipped wafer C4 is composed of a SiC wafer A121, which is a part of the divided wafer A12, and the device structure C2 on the SiC wafer A121. The bonding surface of the bonded wafer C3 is not included in the device-equipped wafer C4. 50 μm of the back surface of the SiC wafer A121 is removed, resulting in a device-equipped wafer C4 with a thickness of 100 μm. The divided wafer C5 is composed of a SiC wafer A122, which is a part of the divided wafer A12, and a divided wafer B12. 50 μm of the front surface of the divided wafer C5 is removed, and 10 μm of the back surface is removed, resulting in a thickness of 300 μm. Here, the depth of the bonding surface in the divided wafer C5 is 35 μm.

[0037] The rear surface of the divided wafer C5 is further removed by 25 μm, resulting in a thickness of 275 μm.

[0038] An SiC wafer D3 is prepared. The SiC wafer D3 is an SiC wafer D1 having a device structure D2 formed on the front surface thereof.

[0039] The SiC wafer D3 is divided into a device-equipped wafer D4 having the device structure D2 and a divided wafer D12 without the device structure D2. The device-equipped wafer D4 is composed of the SiC wafer D11 and the device structure D2 thereon. 50 μm is removed from the back surface of the SiC wafer D11, resulting in a thickness of 100 μm. 50 μm is removed from the front surface of the divided wafer D12, and 10 μm is removed from the back surface, resulting in a thickness of 300 μm.

[0040] The front surface of the divided wafer D12 is further removed by 25 μm, resulting in a thickness of 275 μm.

[0041] Next, divided wafers C5 and D12 are bonded to obtain a bonded wafer E1 having a thickness of 550 μm. The bonded wafer E1 includes a first bonding surface between the SiC wafer A122 and divided wafer B12, and a second bonding surface between the divided wafer B12 and divided wafer D12. The depth of the first bonding surface is 35 μm, and the depth of the second bonding surface is 275 μm.

[0042] 4, the front surface of the bonded wafer E1 is removed by 50 μm. As a result, the SiC wafer A122 is removed from the bonded wafer E1, and the thickness of the bonded wafer E1 becomes 500 μm. Here, the depth of the bonded surface in the bonded wafer E1 is 225 μm.

[0043] Next, a device structure E2 is formed on the front surface of the bonded wafer E1. The SiC wafer consisting of the bonded wafer E1 and the device structure E2 thereon is referred to as a bonded wafer E3. The thickness of the bonded wafer E3 is 510 μm, and the depth of the bonded surface in the bonded wafer E3 is 235 μm.

[0044] The bonded wafer E3 is then divided into a device-equipped wafer E4 having the device structure E2 and a divided wafer E5 without the device structure E2. The device-equipped wafer E4 is composed of a SiC wafer B121, which is a part of the divided wafer B12, and the device structure E2 thereon. The divided wafer E5 is composed of a divided wafer D12 and a SiC wafer B122, which is a part of the divided wafer B12. The divided wafer E5 has 50 μm removed from its front surface and 10 μm removed from its back surface, resulting in a thickness of 300 μm.

[0045] The rear surface of the divided wafer D12 is further removed by 25 μm, resulting in a thickness of 275 μm.

[0046] An SiC wafer F3 is prepared. The SiC wafer F3 is the SiC wafer F1 having a device structure F2 formed on the front surface thereof.

[0047] The SiC wafer F3 is divided into a device-equipped wafer F4 having the device structure F2 and a divided wafer F12 without the device structure F2. The device-equipped wafer F4 is composed of the SiC wafer F11 and the device structure F2 thereon. 50 μm is removed from the backside of the SiC wafer F11, resulting in a thickness of 100 μm. 50 μm is removed from the front side of the divided wafer F12, and 10 μm is removed from the backside, resulting in a thickness of 300 μm.

[0048] The front surface of the divided wafer F12 is further removed by 25 μm, resulting in a thickness of 275 μm.

[0049] Next, divided wafers E5 and F12 are bonded to obtain a bonded wafer G1 having a thickness of 550 μm. At this time, bonded wafer G1 includes a first bonding surface, which is the bonding surface between SiC wafer B122 and divided wafer D12, and a second bonding surface, which is the bonding surface between divided wafer D12 and divided wafer F12. The depth of the first bonding surface is 35 μm, and the depth of the second bonding surface is 275 μm.

[0050] Thereafter, 50 μm of the front surface of the bonded wafer G1 is removed. As a result, the SiC wafer B122 is removed from the bonded wafer G1, and the thickness of the bonded wafer G1 becomes 500 μm. The depth of the bonded surface in the bonded wafer G1 is 225 μm.

[0051] 3 and 4 have been described up to the formation of the bonded wafer G1, but it is also possible to form a device structure on the bonded wafer G1 and then separate wafers from the bonded wafer G1. In this way, by repeating the process of bonding separate wafers together to form a bonded wafer, forming a device structure on the bonded wafer, and then separating the bonded wafer, it is possible to repeatedly create wafers with devices using separate wafers.

[0052] Three device-equipped wafers A4, B4, and C4 were obtained from two SiC wafers A3 and B3. Furthermore, five device-equipped wafers A4, B4, C4, D4, and E4 were obtained from three SiC wafers A3, B3, and D3. In other words, (2n-1) device-equipped wafers can be obtained from n SiC wafers 10. This allows the number of SiC wafers used to be reduced when producing device-equipped wafers, resulting in cost reduction effects.

[0053] In the examples of Figures 3 and 4, SiC wafers A3, B3, D3, and F3 are depicted as having a 10 μm thick epitaxial film formed on a 500 μm thick SiC wafer. However, the thickness of each layer constituting SiC wafers A3, B3, D3, and F3 is not limited to this and can be changed as appropriate depending on the desired device characteristics or wafer thickness. For example, Figures 5 and 6 show a case where the wafer thickness is 350 μm and the epitaxial film thickness is 10 μm.

[0054] 3 and 4, the thickness of the device-equipped wafers A4, C4, and E4 is 100 μm, but this is not limited thereto and can be appropriately selected depending on the device characteristics. Also, although 50 μm of the backside of the SiC wafers A11, A121, and B121 is removed, this is not limited thereto. To remove the damaged layer caused during separation and to obtain the device-equipped wafers A4, C4, and E4 with the desired thickness, the amount of removal of the backside of the SiC wafers A11, A121, and B121 can be appropriately selected, for example, between 10 μm and 100 μm.

[0055] 3 and 4, the thickness of the divided wafers A12, C5, and E5 is 275 μm, but this is not limited thereto. The thickness of the divided wafers A12, C5, and E5 may be 50 μm or more, preferably 80 μm or more, and most preferably 100 μm or more. This prevents cracking of the divided wafers and also enables operation of the device-equipped wafers C4 and E4 without bonding surfaces. By not including bonding surfaces in the device-equipped wafers, the influence of the bonding surfaces on device characteristics can be eliminated, and characteristics equivalent to those of devices using regular wafers without bonding can be obtained.

[0056] Although 50 μm is removed from the front surfaces of the divided wafers A12, C5, and E5, this is not a limitation. In order to remove layers damaged during division or to make the divided wafers A12, C5, and E5 have the desired thickness, the amount of removal from the front surfaces of the divided wafers A12, C5, and E5 may be appropriately selected, for example, between 10 μm and 100 μm.

[0057] 3 and 4, the backside processing of the divided wafers A12, C5, and E5 is performed in two separate steps, but this is not limited thereto, and the processing may be performed in one step or in two or more separate steps. If the processing is performed in one step, the number of steps can be reduced. If the processing is performed in multiple steps, improvement in quality after removal can be expected.

[0058] In the examples shown in Figures 3 and 4, the backsides of the divided wafers A12, C5, and E5 are removed by a total of 35 μm in two processes. However, the amount of removal of the backsides of the divided wafers A12, C5, and E5 is not limited to this and can be appropriately selected so that the divided wafers A12, C5, and E5 have the desired thickness. Furthermore, if the divided wafers A12, C5, and E5 can be adjusted to the desired thickness by processing the front side, backside processing is not necessary. By removing the backsides of the divided wafers A12, C5, and E5, the laser markings typically applied to wafers can be removed, thereby eliminating the effects of the laser markings during bonding, i.e., damage or unevenness on the bonding surface, and improving the quality of the bonded wafers. This effect is apparent when the total amount of removal of the backsides of the divided wafers is 1 μm or more, and is particularly pronounced when the total amount of removal is 30 μm or more.

[0059] In the examples of Figures 3 and 4, the total removal amounts of the front surfaces of the divided wafers A12, C5, and E5 and the total removal amounts of the divided wafers B12, D12, and F12 are different, but they may be the same. If they are the same, the processing processes for these divided wafers can be unified, which is advantageous from the perspective of productivity. Also, in the examples of Figures 3 and 4, the total removal amounts of the back surfaces of the divided wafers A12, C5, and E5 and the total removal amounts of the back surfaces of the divided wafers B12, D12, and F12 are different, but they may be the same. If they are the same, the processing processes for these divided wafers can be unified, which is advantageous from the perspective of productivity.

[0060] 3 and 4, two divided wafers each having a thickness of 275 μm are bonded to produce bonded wafers C1, E1, and G1 each having a thickness of 550 μm. However, the thickness of the divided wafers is not limited to this and can be changed as appropriate. Also, divided wafers of different thicknesses may be bonded together; for example, divided wafer A12 and divided wafer B12 may have different thicknesses.

[0061] In the examples shown in FIGS. 3 and 4 , 50 μm of the front surface of the bonded wafers C1, E1, and G1 is removed. However, the amount of removal from the front surface of the bonded wafers C1, E1, and G1 is not limited to this and can be changed as needed so that the bonded wafers C1, E1, and G1 have the desired thickness. Furthermore, if the desired thickness is achieved at the time of bonding, this removal is not necessary. The thickness of the bonded wafer does not need to be the same as that of the original wafers; it can be different. If the bonded wafer is thicker, cracks and warpage can be further reduced in the device manufacturing process. If the thickness is the same, the same process as for a normal wafer is possible. Even if the bonded wafer is thin, a thickness of 100 μm or more, more preferably 250 μm or more, and most preferably 300 μm or more, facilitates device processing.

[0062] After each film thickness removal step, finishing may be performed by grinding, polishing, CMP, or the like. In particular, precision processing may be required to minimize surface roughness when finishing the bonding surfaces of the split wafers, and mirror finishing by polishing or CMP is desirable. This allows for the production of high-quality bonded wafers.

[0063] The device structures A2, B2, C2, D2, E2, and F2 illustrated in FIGS. 3 and 4 may be the same or different. That is, the device structures on the normal wafer and the device structures on the bonded wafer may be different. For example, device structure A2 may be different from device structure C2. If the bonded wafer is thin and therefore more sensitive to warping or cracking than the normal wafer, warping or cracking can be avoided by fabricating devices with low process loads on the bonded wafer. Alternatively, the effects of warping or cracking on the bonded wafer can be reduced by fabricating devices requiring thick epitaxial films. The device structure referred to here may be a semiconductor element such as a diode, transistor, or thyristor, or a combination of these.

[0064] The device structure on the bonded wafer may also be determined based on the manufacturing yield of devices fabricated from normal wafers. That is, if the quality of normal wafers is low and the manufacturing yield of devices fabricated using them is low, a device structure that is insensitive to wafer quality may be formed on the bonded wafer obtained by dividing and bonding the wafer. Also, if the quality of normal wafers is high and the manufacturing yield of devices fabricated using them is high, a device structure that is sensitive to wafer quality may be formed on the bonded wafer obtained by dividing and bonding the wafer. Here, wafer quality may be determined by the amount or type of defects that affect device characteristics. Therefore, not only the device manufacturing yield but also at least one of the amount and type of defects may be measured before fabricating the device structure, and the device structure on the bonded wafer may be determined after obtaining information that determines whether the desired characteristics can be obtained. In this way, by changing the device structure formed between high-yield, high-quality wafers and low-yield, low-quality wafers, the manufacturing yield of the entire factory can be improved.

[0065] 3 and 4, (2n-1) wafers with devices can be obtained from n SiC wafers 10. In this way, the amount of SiC wafers used can be reduced, resulting in a cost reduction effect. In other words, the effects of the technology disclosed herein can be fully achieved.

[0066] 5 and 6 differ from FIGS. 3 and 4 only in the thickness of the wafer, and therefore the explanation of these figures will be omitted. As with FIGS. 3 and 4, the numerical values ​​exemplified in FIGS. 5 and 6 can be changed as appropriate.

[0067] <A-3. Wafer Thickness and Bonding Surface Depth> Using the example of FIG. 1 , if the device-mounted wafer 29 includes a bonding surface, the bonding surface may affect the device characteristics. In particular, if bonding failure occurs at the bonding surface, this may adversely affect the device characteristics. To avoid this risk, it is desirable to form the device-mounted wafer 29 away from the bonding surface of the bonded wafer. Therefore, it is desirable that the depth of the bonding surface in the bonded wafer 24 be greater than the thickness of the device-mounted wafer 29. Taking this into consideration, the depth of the bonding surface in the bonded wafer 24 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. As a result, even when a device structure is formed using a bonded wafer, the bonding surface does not affect the device characteristics, and characteristics equivalent to those obtained when using a normal wafer without bonding can be obtained.

[0068] The depth of the bonded surfaces of the bonded wafers C1, E1, and G1 before the formation of the device structures shown in Figures 3 and 4 is 225 µm. The depth of the bonded surfaces of the bonded wafers C1, E1, and G1 before the formation of the device structures shown in Figures 5 and 6 is 160 µm.

[0069] When the bonded wafer is formed by bonding two divided wafers together as shown in Fig. 7, the depth of the bonded surface is preferably 50 μm or more from the surface of the bonded wafer. When the bonded wafer is formed by bonding three divided wafers together as shown in Fig. 8, the depth of the shallowest bonded surface is preferably 50 μm or more from the surface of the bonded wafer.

[0070] The thickness of the bonded wafers C1, E1, and G1 in Figures 3 and 4 was 500 μm, and the thickness of the bonded wafers C1, E1, and G1 in Figures 5 and 6 was 350 μm. The thickness of these bonded wafers is determined taking into consideration the prevention of warpage when device structures are formed on the bonded wafers. In other words, the thickness of the bonded wafer is preferably 100 μm or more, more preferably 250 μm, and most preferably 300 μm or more.

[0071] <A-4. Wafer Dividing Timing> In FIGS. 1 to 6 , the divided wafers are divided from a SiC wafer having a device structure. That is, the division was performed after the device structure was formed on the SiC wafer. However, the timing at which the divided wafers constituting the bonded wafer are divided from the original SiC wafer is not limited to after the device structure was formed on the original SiC wafer. In FIG. 9 , the division timing of various wafers is indicated by a “+”. Both the divided wafer that will become the front side of the bonded wafer after later bonding and the divided wafer that will become the back side may be divided before an epitaxial film is formed on the original SiC wafer (pre-epi), after the epitaxial film is formed on the original SiC wafer and before the device structure is formed (post-epi), or after the device structure is formed on the original SiC wafer. Furthermore, the timing at which the divided wafer that will become the front side of the bonded wafer after later bonding and the divided wafer that will become the back side may be divided from the original SiC wafer may differ. In other words, the division process may be performed before the epitaxial film is formed, before the device is formed, or after the device is formed.

[0072] 10 shows a basic process for dividing a SiC wafer before forming an epitaxial film. The basic process will be described below with reference to FIG.

[0073] First, a high-quality SiC wafer 40 and a low-quality SiC wafer 43 are prepared. The difference in quality between the two SiC wafers 40, 43 is manifested, for example, in the number of defects or flatness. The high-quality SiC wafer 40 has a lower surface defect density or a lower dislocation density in the crystal than the low-quality SiC wafer 43. The quality of the SiC wafer can be determined, for example, by optical microscope observation, photoluminescence imaging observation, or X-ray diffraction analysis.

[0074] SiC wafer 40 is divided into two high-quality divided wafers 41 and 42, and similarly SiC wafer 43 is divided into two low-quality divided wafers 44 and 45. Damaged layers formed on the cut surfaces of divided wafers 41, 42, 44, and 45 are then removed by grinding, polishing, or the like.

[0075] Next, the high-quality divided wafer 41 and the low-quality divided wafer 44 are bonded together to form a bonded wafer 46. Furthermore, the high-quality divided wafer 42 and the low-quality divided wafer 45 are bonded together to form a bonded wafer 47.

[0076] Thereafter, an epitaxial film 48 and a device structure 49 are formed on the bonded wafer 46. A wafer consisting of the bonded wafer 46, the epitaxial film 48, and the device structure 49 is referred to as a bonded wafer 50. Similarly, an epitaxial film 51 and a device structure 52 are formed on the bonded wafer 47. A wafer consisting of the bonded wafer 47, the epitaxial film 51, and the device structure 52 is referred to as a bonded wafer 53.

[0077] Next, the bonded wafer 50 is divided into a device-equipped wafer 54 having a device structure 49 and divided wafers 44. The device-equipped wafer 54 is composed of a high-quality divided wafer 41, an epitaxial film 48, and a device structure 49. Similarly, the bonded wafer 53 is divided into a device-equipped wafer 55 having a device structure 52 and divided wafers 45. The device-equipped wafer 55 is composed of a high-quality divided wafer 42, an epitaxial film 51, and a device structure 52.

[0078] According to this method, a low-quality SiC wafer is used as the backside wafer of a bonded wafer, i.e., as a support substrate, and multiple wafers with devices are produced from a high-quality SiC wafer. Furthermore, by dividing multiple wafers from the initial SiC wafer before forming an epitaxial film, all of the divided wafers can be reused. Using a high-quality divided wafer as the front side of a bonded wafer and a low-quality wafer as the backside of a bonded wafer is also applicable to cases where wafers are divided after device formation, as described with reference to FIGS. 1 to 6 . By determining the quality of wafers and using a high-quality divided wafer as the front side of a bonded wafer, as in this method, the high-quality wafers can be used more efficiently, improving the overall device yield of a manufacturing plant and further improving productivity.

[0079] <A-5. Modifications> In the above description, the original wafers were assumed to be single-crystal SiC wafers. In this case, SiC is easy to process, which has the advantage of making it easy to bond the divided wafers together. However, the original wafers, such as the first wafer, the first divided wafer, or the first bonded wafer, are not limited to SiC, and may be made of other single-crystal materials such as diamond, gallium nitride (GaN), gallium oxide (Ga2O3), or aluminum nitride (AlN). Even in such cases, there is no difference in the thermal expansion coefficient between the divided wafers, allowing for stable bonding.

[0080] In the examples of Figures 3 to 6, the thickness of each divided wafer constituting the bonded wafer was the same. For example, in Figure 3, the thickness of divided wafers A12 and B12 constituting bonded wafer C1 was both 275 µm. Also, in Figure 5, the thickness of divided wafers A12 and B12 constituting bonded wafer C1 was both 190 µm. However, the thickness of each divided wafer constituting the bonded wafer does not have to be the same.

[0081] 3 to 6, one bonded wafer is divided into one wafer with devices and one divided wafer without a device structure. However, one bonded wafer may be divided into one wafer with devices and multiple divided wafers without a device structure.

[0082] 10, one SiC wafer 40 is divided into two divided wafers 41 and 42. However, one SiC wafer 40 may be divided into a plurality of divided wafers. The same applies to SiC wafer 43 in the example of FIG. 10.

[0083] 1 , the method for manufacturing a semiconductor device according to the first embodiment includes the steps of: (a) obtaining at least one divided wafer 20, 23 not including a device structure from each of the plurality of SiC wafers 13, 17 by dividing each of the plurality of SiC wafers 13, 17 in the thickness direction; (b) obtaining a bonded wafer 24 by bonding the plurality of divided wafers 20, 23 obtained from different SiC wafers 13, 17; and (c) forming a device structure 26 on the surface of the bonded wafer 24. In this way, by reusing the remaining divided wafers 20 from which device-equipped wafers 19 have been obtained from SiC wafer 13 together with other divided wafers 23, a further device-equipped wafer 29 can be obtained.

[0084] As a method for reusing wafers, the method described in Patent Document 1, in which a thick epitaxial layer is formed on divided wafers, is not economical and has the problem that the wafers are prone to warping and cracking. In contrast, the method of the present embodiment bonds divided wafers together, which makes it possible to reuse wafers at low cost while suppressing warping.

[0085] 1 , bonded wafer 24 is a bonded wafer formed by bonding together multiple divided wafers 20, 23 that do not include device structures and that are separated from different SiC wafers 13, 17. The bonded surfaces of the multiple divided wafers 20, 23 are located at a depth of 50 μm or more from the surface of bonded wafer 24. This allows bonded wafer 24 to be used to manufacture wafer 29 with devices that does not include the bonded surfaces. This prevents the bonded surfaces from affecting the device characteristics.

[0086] <B. Second Embodiment> In the first embodiment, a bonded wafer is formed by bonding a plurality of divided wafers together. In contrast, in the second embodiment, a bonded wafer is formed by bonding one divided wafer to a single crystal wafer that is not a divided wafer.

[0087] <B-1. Basic Process> Fig. 11 is a schematic diagram showing a basic process in the method for manufacturing a semiconductor device in embodiment 2. Hereinafter, the method for manufacturing a semiconductor device in embodiment 2 will be described with reference to Fig. 11.

[0088] First, a SiC wafer 63 and a single crystal SiC wafer 67 are prepared. The SiC wafer 63 is formed by forming an epitaxial film 61 on a SiC wafer 60, and further forming a device structure 62 on the epitaxial film 61.

[0089] Next, the SiC wafer 63 is divided into a device-equipped wafer 65 having the device structure 62 and a divided wafer 66 without the device structure 62. The device-equipped wafer 65 is composed of a SiC wafer 64 divided from the SiC wafer 60, an epitaxial film 61 on the SiC wafer 64, and a device structure 62 on the epitaxial film 61.

[0090] Damaged layers due to the division are generated on the back surface of the device-equipped wafer 65 and on the front surface of the divided wafer 66. These damaged layers are removed by grinding or polishing.

[0091] Next, the divided wafer 66 is bonded to the single crystal SiC wafer 67, thus forming a bonded wafer 68. The divided wafer 66 is the front side of the bonded wafer 68, and the single crystal SiC wafer 67 is the back side of the bonded wafer 68. In this way, the single crystal SiC wafer 67 is used as a support substrate for the divided wafer 66.

[0092] Thereafter, an epitaxial film 69 is formed on the bonded wafer 68, and a device structure 70 is further formed on the epitaxial film 69. A wafer consisting of the bonded wafer 68, the epitaxial film 69, and the device structure 70 is referred to as a bonded wafer 71.

[0093] Next, the bonded wafer 71 is divided into a device-equipped wafer 72 having the device structure 70 and a single-crystal SiC wafer 67. Here, it is preferable that the device-equipped wafer 72 does not include the bonding surface between the divided wafer 66 and the single-crystal SiC wafer 67. Therefore, taking into consideration the thickness of the device structure 70, the bonding surface between the divided wafer 66 and the single-crystal SiC wafer 67 in the bonded wafer 68 is preferably located at a depth of 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more, from the surface of the bonded wafer 68. In other words, the thickness of the divided wafer 66 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. This prevents the device-equipped wafer 72 from including the bonding surface, thereby eliminating any influence of the bonding surface on the devices.

[0094] In this way, the single crystal SiC wafer 67 is used as a support substrate when forming the device structure 70 on the divided wafer 66. After being divided from the bonded wafer 71, the single crystal SiC wafer 67 can be reused as a support substrate for another divided wafer. Here, the support substrate may not have a structure, such as warpage, surface roughness, or surface irregularities, suitable for bonding with the SiC wafer. Therefore, before bonding the SiC wafer and the support substrate, the surface of the SiC wafer to be bonded with the support substrate may be ground, polished, or processed by CMP, or the SiC wafer may be subjected to pressure or heat treatment, thereby forming a structure, such as warpage, surface roughness, or surface irregularities, suitable for bonding with the support substrate on the SiC wafer, the support substrate, or both. This allows for good bonding between the SiC wafer and the support substrate.

[0095] The thickness of the single crystal SiC wafers 67 separated from the bonded wafer 71 may be different from the thickness of the original single crystal SiC wafers 67. That is, when the single crystal SiC wafers 67 are separated from the bonded wafer 71, the separation does not need to be along the bonding surface between the separated wafers 66 and the single crystal SiC wafers 67. The bonding surface may be removed by removing a damaged layer of the separated single crystal SiC wafers 67. The bonding surface may remain in the separated single crystal SiC wafers 67.

[0096] 11, one SiC wafer 63 is divided into one wafer with devices 65 and one divided wafer without a device structure 66. However, one SiC wafer 63 may be divided into one wafer with devices 65 and multiple divided wafers without a device structure.

[0097] A single-crystal GaN wafer or a single-crystal gallium oxide wafer may be used instead of the single-crystal SiC wafer 67. Such an alternative wafer may be used from the viewpoint of heat management in the device manufacturing process, such as heat dissipation from the wafer or heat accumulation in the wafer.

[0098] Wafers made of other materials mentioned in the first embodiment may be used instead of the SiC wafer 63. In this case, if the wafer used as the support substrate and the divided wafers are made of the same material, it is easy to ensure the bonding strength.

[0099] Bonded wafers, which are formed by bonding split wafers and a support substrate, may have different amounts of crystal defects, such as threading dislocations, across the bonded surface depending on the state of each wafer. In this case, the density of crystal defects present in the surface layer on the device structure-forming side of the bonded wafer may differ from that on the opposite side, or the density of crystal defects present near the bonded interface may differ. Furthermore, threading dislocations, which are continuous from the front to back surface in a normal wafer, become discontinuous at the bonded interface in a bonded wafer. However, even if the amount of various defects differs between multiple wafers, the impact of this on device processing or device characteristics is negligible. Here, by appropriately selecting the device structure, split wafers, or support substrate, the impact of the above-mentioned defect discontinuities on device processing or device characteristics can be further reduced. Furthermore, by excluding the bonded surface from a wafer with devices, the impact of the above-mentioned defect discontinuities on device characteristics can be eliminated.

[0100] <B-2. Modification> Fig. 12 is a schematic diagram showing a basic process in a semiconductor device manufacturing method according to a modification of the second embodiment. In this modification, the SiC wafer is divided before the epitaxial film is formed. Hereinafter, the semiconductor device manufacturing method according to the modification of the second embodiment will be described with reference to Fig. 12.

[0101] First, a SiC wafer 80 and two single crystal SiC wafers 83 and 84 are prepared.

[0102] Next, the SiC wafer 80 is divided into two divided wafers 81 and 82 .

[0103] Damaged layers caused by the division are generated on the rear surface of divided wafer 81 and the front surface of divided wafer 82. These damaged layers are removed by grinding, polishing, or the like.

[0104] Thereafter, divided wafer 81 and single crystal SiC wafer 83 are bonded to form bonded wafer 85, and divided wafer 82 and single crystal SiC wafer 84 are bonded to form bonded wafer 86. In this manner, single crystal SiC wafers 83 and 84 are used as support substrates for divided wafers 81 and 82.

[0105] Next, an epitaxial film 87 is formed on the bonded wafer 85, and a device structure 88 is formed on the epitaxial film 87. A wafer consisting of the bonded wafer 85, the epitaxial film 87, and the device structure 88 is referred to as a bonded wafer 89. Similarly, an epitaxial film 90 is formed on the bonded wafer 86, and a device structure 91 is formed on the epitaxial film 90. A wafer consisting of the bonded wafer 86, the epitaxial film 90, and the device structure 91 is referred to as a bonded wafer 92.

[0106] Thereafter, the bonded wafer 89 is divided into a device-equipped wafer 93 having a device structure 88 and the single-crystal SiC wafer 83. The device-equipped wafer 93 comprises the divided wafer 81, the epitaxial film 87, and the device structure 88. Similarly, the bonded wafer 92 is divided into a device-equipped wafer 94 having a device structure 91 and the single-crystal SiC wafer 84. The device-equipped wafer 94 comprises the divided wafer 82, the epitaxial film 90, and the device structure 91.

[0107] Here, it is desirable that the device-equipped wafers 93, 94 do not include the bonding surfaces between the divided wafers 81, 82 and the single-crystal SiC wafers 83, 84. Therefore, taking into consideration the thickness of the device structures 88, 91, the bonding surfaces between the divided wafers 81, 82 and the single-crystal SiC wafers 83, 84 in the bonded wafers 85, 86 are preferably located at a depth of 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more, from the surface of the bonded wafers 85, 86. In other words, the thickness of the divided wafers 81, 82 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. This prevents the device-equipped wafers 93, 94 from including the bonding surfaces, thereby eliminating the influence of the bonding surfaces on the devices.

[0108] According to the above method, by using single crystal SiC wafers 83, 84 as support substrates, it is possible to form device structures 88, 91 on a plurality of divided wafers 81, 82 separated from a SiC wafer. Furthermore, single crystal SiC wafers 83, 84 separated from bonded wafers 89, 92 can be reused as support substrates for other divided wafers.

[0109] The thickness of the single crystal SiC wafers 83, 84 separated from the bonded wafers 89, 92 may be different from the thickness of the original single crystal SiC wafers 83, 84. That is, when separating the single crystal SiC wafers 83, 84 from the bonded wafers 89, 92, it is not necessary to separate the wafers at the bonding surfaces between the separated wafers 81, 82 and the single crystal SiC wafers 83, 84. The bonding surfaces may be removed by removing damaged layers from the separated single crystal SiC wafers 83, 84. The bonding surfaces may remain in the separated single crystal SiC wafers 83, 84.

[0110] 12, one SiC wafer 80 is divided into two divided wafers 81 and 82. However, one SiC wafer 80 may be divided into three or more divided wafers.

[0111] Instead of the SiC wafer 80, a wafer made of another material as mentioned in the first embodiment may be used. In that case, it is desirable that the wafer used as the support substrate and the divided wafers be made of the same material in order to ensure bonding strength.

[0112] <B-3. Effects> The semiconductor device manufacturing method according to the second embodiment includes the steps of: (a) dividing a wafer in the thickness direction to obtain divided wafers; (b) bonding the divided wafers to a single-crystal support substrate to obtain a bonded wafer; and (c) forming a device structure on the bonded wafer. This makes it possible to manufacture semiconductor devices by reusing wafers with high productivity while suppressing cracking of the wafers.

[0113] Furthermore, the bonded wafer according to the second embodiment is a bonded wafer obtained by bonding divided wafers, which do not include device structures separated from a wafer, to a support substrate, and it is desirable that the bonding surface between the divided wafers and the support substrate is located at a depth of 50 μm or more from the surface. In this case, when a device structure is formed on the bonded wafer and a wafer with a device structure including the device structure is subsequently separated from the bonded wafer, the bonded wafer does not include the bonding surface, thereby eliminating any influence of the bonding surface on the device.

[0114] When the split wafers shown in embodiment 1 are used as support substrates (e.g., the process shown in FIG. 10 ), wafers serving as support substrates are manufactured by splitting them from normal wafers, which may limit the thickness of the support substrate or result in waste when removing the support substrate or split wafers to obtain a bonded wafer with the desired film thickness. In this embodiment, the support substrate is manufactured by splitting it directly from an ingot. Therefore, there are no thickness limitations, and single crystal wafers of the required thickness for the support substrate can be directly manufactured, thereby reducing waste. This enables significant cost reduction. Furthermore, by using low-quality crystals with many crystal defects that are unsuitable for device manufacturing as support substrates, it is also possible to reduce material loss throughout the entire manufacturing process.

[0115] C. Third Embodiment In the second embodiment, a bonded wafer is formed by bonding one divided wafer to a single crystal wafer that is not a divided wafer. In contrast, in the third embodiment, a bonded wafer is formed by bonding one divided wafer to a polycrystalline wafer that is not a divided wafer.

[0116] <C-1. Basic Process> Fig. 13 is a schematic diagram showing a basic process in the method for manufacturing a semiconductor device in accordance with the third embodiment. Hereinafter, the method for manufacturing a semiconductor device in accordance with the third embodiment will be described with reference to Fig. 13 .

[0117] First, a SiC wafer 103 and a polycrystalline SiC wafer 107 are prepared. The SiC wafer 103 is formed by forming an epitaxial film 101 on a SiC wafer 100, and further forming a device structure 102 on the epitaxial film 101.

[0118] Next, the SiC wafer 103 is divided into a device-equipped wafer 105 having the device structure 102 and a divided wafer 106 without the device structure 102. The device-equipped wafer 105 is composed of a SiC wafer 104 divided from the SiC wafer 100, an epitaxial film 101 on the SiC wafer 104, and a device structure 102 on the epitaxial film 101.

[0119] Damaged layers due to the division are generated on the back surface of the device-equipped wafer 105 and on the front surface of the divided wafer 106. These damaged layers are removed by grinding or polishing.

[0120] Next, the divided wafer 106 is bonded to the polycrystalline SiC wafer 107, thus forming a bonded wafer 108. The divided wafer 106 is the front side of the bonded wafer 108, and the polycrystalline SiC wafer 107 is the back side of the bonded wafer 108. In this way, the polycrystalline SiC wafer 107 is used as a support substrate for the divided wafer 106.

[0121] Thereafter, an epitaxial film 109 is formed on the bonded wafer 108, and a device structure 110 is further formed on the epitaxial film 109. A wafer consisting of the bonded wafer 108, the epitaxial film 109, and the device structure 110 is referred to as a bonded wafer 111.

[0122] Next, the bonded wafer 111 is divided into a device-equipped wafer 112 having a device structure 110 and a polycrystalline SiC wafer 107. In this way, the polycrystalline SiC wafer 107 is used as a support substrate when forming the device structure 110 on the divided wafer 106. After being divided from the bonded wafer 111, the polycrystalline SiC wafer 107 can be reused as a support substrate for another divided wafer. Here, the support substrate may not have a structure, such as warpage, surface roughness, or surface irregularities, suitable for bonding with the SiC wafer. Therefore, before bonding the SiC wafer and the support substrate, the surface of the SiC wafer to be bonded to the support substrate may be ground, polished, or processed by CMP, or the SiC wafer may be subjected to pressure or heat treatment, thereby forming a structure, such as warpage, surface roughness, or surface irregularities, suitable for bonding with the support substrate on the SiC wafer, the support substrate, or both. This can improve bonding between the SiC wafer and the support substrate.

[0123] The thickness of the polycrystalline SiC wafer 107 separated from the bonded wafer 111 may be different from the thickness of the original polycrystalline SiC wafer 107. That is, when separating the polycrystalline SiC wafer 107 from the bonded wafer 111, the separation may be performed at the bonding surface between the separated wafer 106 and the polycrystalline SiC wafer 107, but this is not necessary. The bonding surface may be removed by removing a damaged layer of the polycrystalline SiC wafer 107 after separation. The bonding surface may remain in the polycrystalline SiC wafer 107 after separation.

[0124] The bonded wafer 108 includes the bonding surface between the divided wafer 106 and the polycrystalline SiC wafer 107. The device-equipped wafer 112 preferably does not include this bonding surface. Therefore, the depth of the bonding surface between the divided wafer 106 and the polycrystalline SiC wafer 107 in the bonded wafer 108 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. In other words, the thickness of the divided wafer 106 separated from the SiC wafer 103 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. This prevents the device-equipped wafer 112 from including the bonding surface, thereby eliminating the influence of the bonding surface on the devices.

[0125] 13, one SiC wafer 103 is divided into one wafer with devices 105 and one divided wafer without a device structure. However, one SiC wafer 103 may be divided into one wafer with devices 105 and multiple divided wafers without a device structure.

[0126] Instead of the SiC wafer 63, a wafer made of another material as mentioned in the first embodiment may be used. In that case, it is desirable that the wafer used as the support substrate and the divided wafers be made of the same material in order to ensure bonding strength.

[0127] Bonded wafers, which are formed by bonding split wafers and a support substrate, may have different amounts of crystal defects, such as threading dislocations, across the bonded surface depending on the state of each wafer. In this case, the density of crystal defects present in the surface layer on the device structure-forming side of the bonded wafer may differ from that on the opposite side, or the density of crystal defects present near the bonded interface may differ. Furthermore, threading dislocations, which are continuous from the front to back surface in a normal wafer, become discontinuous at the bonded interface in a bonded wafer. However, even if the amount of various defects differs between multiple wafers, the impact of this on device processing or device characteristics is negligible. Here, by appropriately selecting the device structure, split wafers, or support substrate, the impact of the above-mentioned defect discontinuities on device processing or device characteristics can be further reduced. Furthermore, by excluding the bonded surface from a wafer with devices, the impact of the above-mentioned defect discontinuities on device characteristics can be eliminated.

[0128] <C-2. Modification> Figure 14 is a schematic diagram showing the basic process of a semiconductor device manufacturing method according to a modification of the third embodiment. In this modification, the SiC wafer is divided before the epitaxial film is formed. Alternatively, the SiC wafer may be divided after the epitaxial film is formed and before the device structure is formed. Hereinafter, the semiconductor device manufacturing method according to the modification of the third embodiment will be described with reference to Figure 14.

[0129] First, a SiC wafer 120 and two polycrystalline SiC wafers 123 and 124 are prepared.

[0130] Next, the SiC wafer 120 is divided into two divided wafers 121 and 122 .

[0131] Damaged layers caused by the division are generated on the rear surface of divided wafer 121 and the front surface of divided wafer 122. These damaged layers are removed by grinding, polishing, or the like.

[0132] Thereafter, divided wafer 121 and polycrystalline SiC wafer 123 are bonded to form bonded wafer 125, and divided wafer 122 and polycrystalline SiC wafer 124 are bonded to form bonded wafer 126. In this manner, polycrystalline SiC wafer 123 is used as a support substrate for divided wafer 121, and polycrystalline SiC wafer 124 is used as a support substrate for divided wafer 122.

[0133] Next, an epitaxial film 127 is formed on bonded wafer 125, and a device structure 128 is formed on epitaxial film 127. A wafer consisting of bonded wafer 125, epitaxial film 127, and device structure 128 is referred to as bonded wafer 129. Similarly, an epitaxial film 130 is formed on bonded wafer 126, and a device structure 131 is formed on epitaxial film 130. A wafer consisting of bonded wafer 126, epitaxial film 130, and device structure 131 is referred to as bonded wafer 132.

[0134] The bonded wafers 125, 126 include the bonding surfaces between the divided wafers 121, 122 and the polycrystalline SiC wafers 123, 124. The device-equipped wafers 133, 134 preferably do not include these bonding surfaces. Therefore, the depth of the bonding surfaces between the divided wafers 121, 122 and the polycrystalline SiC wafers 123, 124 in the bonded wafers 125, 126 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. In other words, the thickness of the divided wafers 121, 122 separated from the SiC wafer 120 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. This prevents the device-equipped wafers 133, 134 from including the bonding surfaces, thereby eliminating the influence of the bonding surfaces on the devices.

[0135] Thereafter, bonded wafer 129 is divided into device-included wafer 133 having device structure 128 and polycrystalline SiC wafer 123. Device-included wafer 133 comprises divided wafer 121, epitaxial film 127, and device structure 128. Similarly, bonded wafer 132 is divided into device-included wafer 134 having device structure 131 and polycrystalline SiC wafer 124. Device-included wafer 134 comprises divided wafer 122, epitaxial film 130, and device structure 131.

[0136] According to the above method, by using the polycrystalline SiC wafers 123, 124 as support substrates, it is possible to form device structures 128, 131 on a plurality of divided wafers 121, 122 separated from a SiC wafer. Furthermore, the polycrystalline SiC wafers 123, 124 separated from the bonded wafers 129, 132 can be reused as support substrates for other divided wafers.

[0137] The thickness of the polycrystalline SiC wafers 123, 124 separated from the bonded wafers 129, 132 may be different from the thickness of the original polycrystalline SiC wafers 123, 124. That is, when the polycrystalline SiC wafers 123, 124 are separated from the bonded wafers 129, 132, the separation does not need to be along the bonding surfaces between the separated wafers 121, 122 and the polycrystalline SiC wafers 123, 124. The bonding surfaces may be removed by removing damaged layers of the polycrystalline SiC wafers 123, 124 after separation. The bonding surfaces may also remain in the polycrystalline SiC wafers 123, 124 after separation.

[0138] 14, one SiC wafer 120 is divided into two divided wafers. However, one SiC wafer 120 may be divided into three or more divided wafers.

[0139] 14 , the method for manufacturing a semiconductor device according to the third embodiment includes the steps of: (a) dividing SiC wafer 120 in the thickness direction to obtain divided wafers 121, 122 having a thickness of 50 μm or more; (b) bonding divided wafers 121, 122 to polycrystalline SiC wafers 123, 124, which serve as support substrates, to obtain bonded wafers 125, 126; and (c) forming device structures 128, 131 on bonded wafers 125, 126. This makes it possible to manufacture semiconductor devices by reusing wafers with high productivity while suppressing cracking of the wafers.

[0140] 14 , the bonded wafer according to the third embodiment is a bonded wafer obtained by bonding divided wafers 121, 122, which do not include a device structure separated from SiC wafer 120, to polycrystalline SiC wafers 123, 124, which serve as support substrates, and the bonded surfaces between divided wafers 121, 122 and polycrystalline SiC wafers 123, 124 are located at a depth of 50 μm or more from the surface. This makes it possible to manufacture semiconductor devices by reusing wafers with high productivity while suppressing cracking of the wafers.

[0141] When the split wafers shown in embodiment 1 are used as support substrates (e.g., the process shown in FIG. 10 ), wafers serving as support substrates are manufactured by splitting them from normal wafers, which may limit the thickness of the support substrate or result in waste when removing the support substrate or split wafers to obtain a bonded wafer with the desired film thickness. In this embodiment, the support substrate is manufactured by splitting it directly from an ingot. Therefore, there are no thickness limitations, and single crystal wafers of the required thickness for the support substrate can be directly manufactured, thereby reducing waste. This enables significant cost reduction. Furthermore, by using low-quality crystals with many crystal defects that are unsuitable for device manufacturing as support substrates, it is also possible to reduce material loss throughout the entire manufacturing process.

[0142] Furthermore, compared with the case where a single crystal wafer is used for the support substrate shown in the second embodiment, a polycrystalline substrate can be manufactured at low cost, and therefore, a cost reduction effect can be obtained.

[0143] It should be noted that the embodiments can be freely combined, appropriately modified, or omitted. The above description is illustrative in all respects. It is understood that countless variations not illustrated can be envisioned. For example, the processes of dividing, bonding, and related wafer front and back processing shown in embodiment 1, or the features of the divided wafers, bonded wafers, and device-equipped wafers, can be combined, appropriately modified, or omitted in the embodiments using the support substrate shown in embodiments 2 and 3.

[0144] 10, 13 SiC wafer, 11, 15, 25 epitaxial film, 12, 16, 26 device structure, 19, 22, 29 wafer with device, 20, 23, 30, 66, 106 divided wafer, 67 single crystal SiC substrate, 107 polycrystalline SiC substrate.

Claims

1. (a) obtaining at least one first divided wafer not including a device structure from each of a plurality of first wafers by dividing each of the first wafers in a thickness direction; (b) bonding a plurality of the first divided wafers obtained from different first wafers to obtain a first bonded wafer that is a bonded wafer; (c) forming a device structure on a surface of the first bonded wafer. A method for manufacturing a semiconductor device.

2. The step (a) is a step of dividing each of the first wafers having a device structure formed on a surface thereof into a first device-equipped wafer which is a device-equipped wafer including the device structure and at least one of the first divided wafers. The method for manufacturing a semiconductor device according to claim 1 .

3. (d) dividing the first bonded wafer on which the device structure has been formed into a second device-equipped wafer which is a device-equipped wafer including the device structure and at least one second divided wafer not including the device structure, The method for manufacturing a semiconductor device according to claim 1 or 2.

4. (e) after the step (d), the step (b) to the step (d) are further included in a step of repeating the steps (b) to (d) at least once using the second divided wafer as a new first divided wafer. The method for manufacturing a semiconductor device according to claim 3 .

5. At least one of the first wafers is a bonded wafer formed by bonding a plurality of wafers. The method for manufacturing a semiconductor device according to claim 1 .

6. When the wafer from which the device-equipped wafer is to be divided is a bonded wafer formed by bonding a plurality of wafers, the device-equipped wafer does not include a bonding surface included in the bonded wafer from which the device-equipped wafer is to be divided. The method for manufacturing a semiconductor device according to claim 3 .

7. the material of the first wafer is SiC; The method for manufacturing a semiconductor device according to claim 1 .

8. the material of the first wafer is single crystal SiC; The method for manufacturing a semiconductor device according to claim 7 .

9. The thickness of the first divided wafer is 50 μm or more. The method for manufacturing a semiconductor device according to claim 1 .

10. The device structure is a SiC power device structure. The method for manufacturing a semiconductor device according to claim 1 .

11. A bonded wafer obtained by bonding a plurality of divided wafers that do not include a device structure divided from different wafers, The bonding surfaces of the plurality of split wafers are located at a depth of 50 μm or more from the surface. Bonded wafer.

12. the material of the wafer is SiC; The bonded wafer of claim 11.

13. The material of the wafer is single crystal SiC; The bonded wafer of claim 12.

14. The wafer is of N-type or P-type conductivity, or semi-insulating; The bonded wafer of claim 11.

15. An amorphous layer is present on the bonding surfaces of the plurality of split wafers. The bonded wafer of claim 11.

16. (a) obtaining split wafers by splitting a wafer that is not a bonded wafer in a thickness direction; (b) after the step (a), bonding the divided wafers to a support substrate to obtain a bonded wafer; (c) after step (b), forming a device structure on the bonded wafer. A method for manufacturing a semiconductor device.

17. The bonding surface between the divided wafers and the support substrate in the bonded wafer is located at a depth of 50 μm or more from the surface of the bonded wafer. The method for manufacturing a semiconductor device according to claim 16.

18. The support substrate is single crystal SiC or single crystal GaN; A method for manufacturing a semiconductor device according to claim 16 or 17.

19. The support substrate is a polycrystalline substrate. A method for manufacturing a semiconductor device according to claim 16 or 17.

20. A bonded wafer obtained by bonding a divided wafer not including the device structure, which is divided from a wafer that is not a bonded wafer, to a support substrate, A bonding surface between the divided wafer and the support substrate is present at a depth of 50 μm or more from the surface. Bonded wafer.

21. The material of the wafer and the support substrate is single crystal SiC or single crystal GaN; The bonded wafer of claim 20.

22. the material of the wafer is polycrystalline SiC; The bonded wafer of claim 20.

23. The wafer is of N-type or P-type conductivity, or semi-insulating; The bonded wafer of claim 20.

24. an amorphous layer is present on the bonding surface between the divided wafer and the support substrate; The bonded wafer of claim 20.