Power conversion device

Abstract

First and second semiconductor switching elements (Q1, Q2) are connected in series between first positive electrode wiring (122) and an output node (Nd) via second positive electrode wiring (132). Third and fourth semiconductor switching elements (Q3, Q4) are connected in series between the output node (Nd) and first negative electrode wiring (123) via second negative electrode wiring (133). A flying capacitor (131) is connected between the second positive electrode wiring (132) and the second negative electrode wiring (133). An impedance reduction element (200) including a capacitor (201) is connected between a first node (Nd) and a second node (Nf) in parallel with the flying capacitor (131). The wiring length of a path to the first node (Nd) and the second node (Nf) via the impedance reduction element (200) is shorter than the wiring length of a path to the first node (Nd) and the second node (Nf) via the flying capacitor (131).

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] In recent years, there has been much discussion about the construction of power transmission and distribution networks that utilize diverse energy sources, including renewable energy. Among these, attention has been focused on the benefits of replacing conventional power transmission and distribution networks with higher-voltage direct current (DC) transmission and distribution.

[0003] DC power transmission and distribution is well suited to semiconductor power converters, and by reducing the number of converter stages, it is possible to reduce power conversion losses when repeatedly transmitting and receiving power over various paths. Furthermore, it also leads to a reduction in transmission losses when transmitting power over long distances, allowing for more efficient energy utilization.

[0004] To achieve higher voltages, semiconductor switching elements must be made to withstand higher voltages, but due to physical limitations, the increased voltage leads to an exponential degradation in performance. To solve this problem, a series connection of semiconductor switching elements and other configurations in which multiple semiconductor switching elements are connected in series are being considered.

[0005] For example, Japanese Patent Laid-Open Publication No. 2022-145778 (Patent Document 1) describes a circuit configuration of a power conversion device including a plurality of semiconductor switching elements connected in series and a flying capacitor. Patent Document 1 describes a configuration in which a snubber circuit is provided for each semiconductor switching element to address the problem of surge voltage rise that occurs when a plurality of semiconductor switching elements are connected in series.

[0006] Japanese Patent Application Laid-Open No. 2022-145778

[0007] However, in the circuit configuration of Patent Document 1, the increased number of semiconductor switching elements tends to increase the area of ​​the wiring loop that generates parasitic inductance that generates surge voltages during switching operations. The increased parasitic inductance raises concerns about issues such as an increase in surge voltage when the semiconductor switching elements are turned off, and furthermore, an increase in switching loss due to the need to suppress the switching speed in order to suppress surge voltages. There is a limit to how much improvement can be achieved with only the placement of a snubber circuit as in Patent Document 1.

[0008] The present disclosure has been made to solve such problems, and an object of the present disclosure is to reduce the parasitic inductance that affects the on / off switching of semiconductor switching elements in a power conversion device having a main circuit configuration that includes multiple semiconductor switching elements and flying capacitors connected in series.

[0009] In one aspect of the present disclosure, a power conversion device includes an impedance reducing element including two first semiconductor elements (first and second), two second semiconductor elements (first and second), a first capacitor, and a second capacitor. The first and second first semiconductor elements are connected in series between a first positive wiring on the high-voltage side and an output node, arranged in order from the first positive wiring toward the output node. The first and second second semiconductor elements are connected in series between a first negative wiring on the low-voltage side and the output node, arranged in order from the first negative wiring toward the output node. The first capacitor is electrically connected between a second positive wiring connecting the first first semiconductor element and the second first semiconductor element and a second negative wiring connecting the first second semiconductor element and the second second semiconductor element. The impedance-reducing element is electrically connected in parallel with the first capacitor between a first node connected to the second positive wiring and a second node connected to the second negative wiring. The impedance-reducing element is arranged such that the wiring length of a first path from the first node to the second node via the impedance-reducing element is shorter than the wiring length of a second path from the first node to the second node via the first capacitor.

[0010] In another aspect of the present disclosure, a power conversion device includes N first semiconductor elements from a first to an Nth (N: an integer of 2 or greater) first semiconductor elements, N second semiconductor elements from a first to an Nth second semiconductor element, a first capacitor, and an impedance reducing element including a second capacitor. The N first semiconductor elements from the first to the Nth first semiconductor elements are connected in series between a first positive wiring on a high-voltage side and an output node, in order from the first positive wiring toward the output node. The N second semiconductor elements from the first to the Nth second semiconductor elements are connected in series between a first negative wiring on a low-voltage side and the output node, in order from the first negative wiring toward the output node. The first capacitor is connected between a (1+1)th positive wiring connecting an i-th (i: an integer greater than or equal to 1 and less than or equal to (N-1)) first semiconductor element and an (i+1)th first semiconductor element among the N first semiconductor elements, and an (i+1)th negative wiring electrically connecting an i-th second semiconductor element and an (i+1)th second semiconductor element among the N second semiconductor elements. The impedance reducing elements are electrically connected in parallel with each first capacitor between a first node electrically connected to the (1+1)th positive wiring and a second node electrically connected to the (i+1)th negative wiring. The impedance reducing elements are arranged such that the wiring length of a first path from the first node to the second node via the impedance reducing element is shorter than the wiring length of a second path from the first node to the second node via the first capacitor.

[0011] According to the present disclosure, by connecting an impedance reducing element in parallel with a first capacitor, it is possible to reduce the parasitic inductance that affects the on / off of semiconductor switching elements in a power conversion device having a main circuit configuration that includes multiple semiconductor switching elements and flying capacitors connected in series.

[0012] 1 is a schematic configuration diagram of a power conversion device according to embodiment 1. FIG. 2 is a circuit diagram showing a main circuit configuration of the power conversion device shown in FIG. 1. FIG. 3 is a circuit diagram explaining a switching pattern of the power conversion device shown in FIG. 1. FIG. 4 is a waveform diagram explaining switching control of the power conversion device shown in FIG. 1. FIG. 5 is a schematic circuit diagram explaining an arrangement of impedance-reducing elements in the power conversion device according to embodiment 1. FIG. 6 is a first circuit diagram explaining a current path when switching a switching pattern in the power conversion device shown in FIG. 5. FIG. 7 is a second circuit diagram explaining a current path when switching a switching pattern in the power conversion device shown in FIG. 5. FIG. 8 is a second circuit diagram explaining a current path when switching a switching pattern in a power conversion device according to a comparative example. FIG. 9 is an example of an operation waveform diagram of semiconductor switching elements of the power conversion device according to embodiment 1. FIG. 10 is a circuit diagram explaining another configuration example of an impedance-reducing element. FIG. 11 is a schematic configuration diagram of a power conversion device according to embodiment 2.

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0014] First embodiment (general configuration of power conversion device)

[0015] Fig. 1 is a schematic configuration diagram of a power conversion device 100 according to a first embodiment. As shown in Fig. 1, the power conversion device 100 includes semiconductor switching elements Q1 to Q4, and performs power transmission between a DC power source 1 and a DC power source 2. Specifically, the power conversion device 100 includes a bridge circuit 110, a filter reactor 102, a filter capacitor 103, and a controller 210. In Fig. 1, the power conversion device 100 is illustrated as a chopper circuit that is connected between the DC power source 1 and the DC power source 2 and performs DC / DC power conversion between the DC power source 1 and the DC power source 2.

[0016] The bridge circuit 110 is configured by connecting semiconductor switching elements Q1 to Q4 in series between a first positive wiring 122 and a first negative wiring 123. The semiconductor switching element Q1 is electrically connected between the first positive wiring 122 and a second positive wiring 132, and the semiconductor switching element Q2 is electrically connected between the second positive wiring 132 and an output node Nd of the bridge circuit 110.

[0017] The semiconductor switching element Q3 is electrically connected between the output node Nd and the second negative wiring 133 , and the semiconductor switching element Q4 is electrically connected between the first negative wiring 123 and the second negative wiring 133 .

[0018] Each of the semiconductor switching elements Q1 to Q4 can be configured by any self-extinguishing element such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a HEMT (High Electron Mobility Transistor).

[0019] Each of the semiconductor switching elements Q1 to Q4 is connected in anti-parallel to a diode 21. The diode may be an external element for each semiconductor switching element, or may be configured as a body diode built into each semiconductor switching element such as a MOSFET.

[0020] A capacitor 121 is electrically connected between the first positive wiring 122 (node ​​Na) and the first negative wiring 123 (node ​​Ng). That is, the capacitor 121 is connected in parallel with the DC power supply 1. A capacitor 131 corresponding to a "flying capacitor" is connected between the second positive wiring 132 (node ​​Nc) and the second negative wiring 133 (node ​​Ne).

[0021] The filter reactor 102 is connected between the output node Nd of the bridge circuit 110 and the positive electrode of the DC power supply 2. The filter capacitor 103 is connected in parallel with the DC power supply 2.

[0022] The voltage Vd1 of the capacitor 121 is detected by a voltage sensor 151, and the voltage Vd2 of the filter capacitor 103 is detected by a voltage sensor 152. The voltage Vfc of the capacitor 131 is detected by a voltage sensor 153, and the current Io of the filter reactor 102 is detected by a current sensor 155.

[0023] The controller 210 generates on / off drive signals Sd1 to Sd4 for the semiconductor switching elements Q1 to Q4 using the voltages Vd1, Vd2, and Vfc detected by the voltage sensors 151 to 153 and the current Io detected by the current sensor 155. The controller 210 may be configured with a digital electronic circuit that performs arithmetic processing using an FPGA (Field Programmable Gate Array) or the like via an A / D conversion device, or may be configured with analog electronic circuits such as a comparator, an operational amplifier, and a differential amplifier circuit. Alternatively, the controller 210 may be configured with both digital and analog electronic circuits.

[0024] The bridge circuit 110 can be configured as an assembly of a circuit unit 120 for arranging the semiconductor switching elements Q1 and Q4 and a circuit unit 130 for arranging the semiconductor switching elements Q2 and Q3.

[0025] The circuit unit 120 is connected to the first positive wiring 122 and the first negative wiring 123, and includes semiconductor switching elements Q1 and Q4, a capacitor 121, and driver circuits 161 and 162 for turning on and off the semiconductor switching elements Q1 and Q4 in response to on / off drive signals Sd1 and Sd4 from the controller 210. In this embodiment, the circuit unit 120 further includes an impedance reducing element 200 (described in detail below) connected between the semiconductor switching element Q1 (node ​​Nb) and the semiconductor switching element Q4 (node ​​Nf). The semiconductor switching elements Q1 and Q4 are controlled to be turned on and off complementarily.

[0026] Circuit unit 130 is connected to second positive wiring 132 and second negative wiring 133, and includes semiconductor switching elements Q2, Q3, a capacitor 131, and driver circuits 171, 172 for turning on and off semiconductor switching elements Q2, Q3 in response to on / off drive signals Sd2, Sd3 from controller 210. Semiconductor switching elements Q2 and Q3 are controlled to be turned on and off complementarily.

[0027] Each of the semiconductor switching elements Q1 to Q4 is turned on and off by gate signals from driver circuits 161, 162, 171, and 172, thereby changing the output voltage between the positive terminal (drain or collector) and the negative terminal (source or emitter) and the output current generated between the positive terminal and the negative terminal.

[0028] Generally, a gate resistor Rg is connected between the driver circuits 161, 162, 171, and 172 and the gates (control electrodes) of the semiconductor switching elements Q1 to Q4. The gate resistor Rg adjusts the turn-off and turn-on speeds of the semiconductor switching elements Q1 to Q4, thereby suppressing switching surges. However, there is a known trade-off relationship in which slowing down the turn-off and turn-on speeds to suppress surges results in increased switching losses.

[0029] (Switching Control in Power Converter) Next, the on / off control (switching control) of the semiconductor switching elements Q1 to Q4 in the power converter 100 will be described with reference to FIGS.

[0030] Fig. 2 is a circuit diagram showing a main circuit configuration of the power conversion device 100. Referring to Fig. 2, as described in Fig. 1, semiconductor switching elements Q1 and Q2 are connected between the first positive wiring 122 and the output node Nd via the second positive wiring 132. Similarly, semiconductor switching elements Q3 and Q4 are connected between the output node Nd and the first negative wiring 123 via the second negative wiring 133.

[0031] The capacitor 131 is connected between a second positive wiring 132 that connects the semiconductor switching elements Q1 and Q2 and a second negative wiring 133 that connects the semiconductor switching elements Q3 and Q4, and has the function of maintaining the sum of the output voltages of the semiconductor switching elements Q2 and Q3.

[0032] Capacitor 121 is connected between first positive wiring 122 and first negative wiring 123, and has the function of holding the sum of the output voltages of semiconductor switching elements Q1 to Q4, and in addition to the function of capacitor 121, it also has the secondary function of holding the sum of the output voltages of semiconductor switching elements Q1 and Q4.

[0033] By controlling the voltage Vfc of capacitor 131 to be half the voltage Vd1 of capacitor 121, the total output voltage of semiconductor switching elements Q1 and Q4 and the total output voltage of semiconductor switching elements Q3 are each set to (1 / 2)·Vd1, thereby equalizing the output voltages of semiconductor switching elements Q1 to Q4. This reduces the risk of an overvoltage exceeding the breakdown voltage being applied to semiconductor switching elements Q1 to Q4.

[0034] In this way, the power conversion device 100 has a circuit configuration including a plurality of (two) semiconductor switching elements connected in series between the first positive wiring 122 and the output node Nd, and between the first negative wiring 123 and the output node Nd, and a flying capacitor (capacitor 131).

[0035] Fig. 3 shows a circuit diagram illustrating the switching patterns of the power conversion device 100. As described above, the power conversion device 100 is controlled so that the semiconductor switching elements Q2 and Q3 are turned on and off complementarily and the semiconductor switching elements Q1 and Q4 are turned on and off complementarily, and therefore, switching is controlled in a manner that appropriately combines the four types of switching patterns shown in Figs. 3(a) to (d).

[0036] As shown in FIG. 3A, in a switching pattern in which the semiconductor switching elements Q1 and Q2 are turned on while the semiconductor switching elements Q3 and Q4 are turned off, the first positive wiring 122 is connected to the output node Nd.

[0037] As shown in FIG. 3B, in a switching pattern in which the semiconductor switching elements Q3 and Q4 are turned on while the semiconductor switching elements Q1 and Q2 are turned off, the first negative wiring 123 is connected to the output node Nd.

[0038] As shown in FIG. 3C, in a switching pattern in which the semiconductor switching elements Q1 and Q3 are turned on while the semiconductor switching elements Q2 and Q4 are turned off, the second negative wiring 133 is connected to the output node Nd.

[0039] As shown in FIG. 3D, in a switching pattern in which the semiconductor switching elements Q2 and Q4 are turned on while the semiconductor switching elements Q1 and Q3 are turned off, the second positive electrode wiring 132 is connected to the output node Nd.

[0040] As described above, in this embodiment, the power conversion device 100 operates as a chopper circuit between the DC power source 1 and the DC power source 2. Therefore, basically, power is transmitted between the DC power source 1 (Vd1) and the DC power source 2 (Vd2) by alternately repeating the switching patterns of Fig. 3(a) and Fig. 3(b). As is well known, the voltage ratio (Vd1 / Vd2) can be controlled by controlling the ratio between the period length of the switching pattern of Fig. 3(a) and the period length of the switching pattern of Fig. 3(b).

[0041] Furthermore, in the switching pattern of Fig. 3(c), a current path can be formed from the first positive wiring 122 to the output node Nd, accompanied by charging of the capacitor 131. On the other hand, in the switching pattern of Fig. 3(d), a current path can be formed from the first negative wiring 123 to the output node Nd, accompanied by discharging of the capacitor 131. Therefore, by providing periods of the switching patterns of Fig. 3(c) and Fig. 3(d) to a basic pattern in which the switching patterns of Fig. 3(a) and Fig. 3(b) are alternately repeated, it becomes possible to control the voltage ratio (Vd1 / Vd2) and, in addition, to execute control to maintain the voltage Vfc of the capacitor 131 at (½)·Vd1.

[0042] Fig. 4 is a waveform diagram illustrating the switching control of the power conversion device 100. Fig. 4 shows the switching control waveforms in the circuit unit 120, i.e., the on / off control waveforms of the semiconductor switching elements Q1 and Q4, and the switching control waveforms in the circuit unit 130, i.e., the on / off control waveforms of the semiconductor switching elements Q2 and Q3.

[0043] In circuit unit 120, semiconductor switching elements Q1 and Q4 are turned on and off in a complementary manner. Similarly, in circuit unit 130, semiconductor switching elements Q2 and Q3 are turned on and off in a complementary manner. Although not shown, in each of circuit units 120 and 130, when the on and off states of semiconductor switching elements Q1 and Q4 or Q2 and Q3 are alternated, a dead time is actually provided in which both semiconductor switching elements Q1 and Q4 or Q2 and Q3 are turned off.

[0044] The basic switching pattern of the chopper circuit described above is shown by a solid line in Fig. 4. In the basic switching pattern, the semiconductor switching elements Q1 to Q4 are turned on and off so that the on / off switching (Q1, Q4) in the circuit unit 120 and the on / off switching (Q2, Q3) in the circuit unit 130 occur at the same timing, at times tx and ty.

[0045] Therefore, in the basic switching pattern, the power conversion device 100 is controlled to alternate between the switching patterns of Fig. 3(a) and Fig. 3(b). This basic switching pattern can be applied when the difference between the voltage Vfc of the capacitor 131 and (½)·Vd1 is smaller than a predetermined reference value.

[0046] In contrast, when the voltage Vfc of the capacitor 131 drops below (½)·Vd1 by exceeding the reference value, the charge switching pattern shown by the dotted line in FIG. 4 can be applied. In this charge switching pattern, the on / off switching (Q2, Q3) of the circuit unit 130 occurs at time t1, which is earlier than time tx, while the on / off switching (Q1, Q4) of the circuit unit 120 occurs at time t2, which is later than time tx. As a result, the switching pattern of FIG. 3( c) in which the semiconductor switching elements Q1 and Q3 are turned on between times t1 and t2 (duration ΔT) is applied to charge the capacitor 131, thereby increasing the voltage Vfc.

[0047] Similarly, the on / off switching (Q1, Q4) in circuit unit 120 occurs at time t3, which is earlier than time ty, while the on / off switching (Q2, Q3) in circuit unit 130 occurs at time t4, which is later than time ty, thereby applying the switching pattern of Figure 3(c) in which semiconductor switching elements Q1 and Q3 are turned on.

[0048] Conversely, when the voltage Vfc of the capacitor 131 increases, the switching pattern of Fig. 3(d) in which the semiconductor switching elements Q2 and Q4 are turned on can be applied to discharge the capacitor 131 and reduce the voltage Vfc. Specifically, the switching pattern of Fig. 3(d) can be provided by shifting the timing of the on / off switching (Q1, Q4) in the circuit unit 120 and the timing of the on / off switching (Q2, Q3) in the circuit unit 130 in the direction opposite to the dotted line in Fig. 4 with respect to times tx and ty.

[0049] The controller 210 can perform on / off control (switching control) of the semiconductor switching elements Q1 to Q4 using the voltages Vd1, Vd2, Vfc detected by the voltage sensors 151 to 153 and the current Io detected by the current sensor 155 so that the voltage (Vd1, Vd2) of the DC power supply 1 or the DC power supply 2, the voltage Vfc of the capacitor 131, the integral value of the current Io, etc. become appropriate values.

[0050] (Reduction of Parasitic Inductance in Power Conversion Device 100) When the semiconductor switching elements Q1 to Q4 are alternately turned on and off in accordance with the above-described switching control, a surge voltage (Ls·(di / dt)) due to the parasitic inductance (Ls) is generated. In the power conversion device 100, the surge voltage is suppressed by reducing the parasitic inductance through the arrangement of the impedance reducing element 200 shown in FIG. 1 .

[0051] As shown in FIG. 5 , the capacitor 131 is connected in the circuit unit 130 between a node Nc on the second positive wiring 132 and a node Ne on the second negative wiring 133. The impedance-reducing element 200 is connected in the circuit unit 120 between a node Nb connected to the negative terminal (source) of the semiconductor switching element Q1 and a node Nf connected to the positive terminal (drain) of the semiconductor switching element Q4. Since the node Nb is electrically connected to the second positive wiring 132 and the node Nf is electrically connected to the second negative wiring 133, the impedance-reducing element 200 is electrically connected in parallel with the capacitor 131. The impedance-reducing element 200 includes a capacitor 201 for blocking DC components while passing high-frequency components during switching. The capacitance of the capacitor 201 is smaller than that of the capacitor 131.

[0052] The impedance reducing element 200 is arranged so that the wiring length of the path from node Nb to the impedance reducing element 200 to node Nf is shorter than the wiring length of the path from node Nb to (node ​​Nc) to capacitor 131 to (node ​​Ne) to node Nf. In the power conversion device 100, the capacitor 131 is arranged in the circuit unit 130, while the impedance reducing element 200 is arranged in the circuit unit 120, thereby easily achieving this wiring length relationship.

[0053] In the circuit unit 120, due to the arrangement of the impedance reducing element 200, a loop-shaped path PTH1 is formed by the capacitor 121, the first positive wiring 122, the semiconductor switching element Q1, the impedance reducing element 200, the semiconductor switching element Q4, and the first negative wiring 123.

[0054] In contrast, when the impedance reducing element 200 is not arranged, the circuit unit 120 and the capacitor 131 form a loop-shaped path PTH2 by the capacitor 121, the first positive wiring 122, the semiconductor switching element Q1, the node Nb, the node Nc, the capacitor 131, the node Ne, the node Nf, the semiconductor switching element Q4, and the first negative wiring 123.

[0055] In the power conversion device 100, the wiring length of the path PTH1 due to the arrangement of the impedance reducing element 200 is shorter than the wiring length of the path PTH2. Therefore, the parasitic inductance occurring in the path PTH1 is also smaller than the inductance occurring in the path PTH2.

[0056] In the circuit unit 130, a loop-shaped path PTH3 is formed by the capacitor 131, the second positive wiring 132, the semiconductor switching element Q2, the output node Nd, the semiconductor switching element Q3, and the second negative wiring 133. The circuit unit 130 constitutes a so-called canonical cell. The circuit units 120 and 130 are designed so that the path length (parasitic impedance) of the path PTH1 and the path length (parasitic impedance) of the path PTH3 are the same, which makes it easier to match the switching characteristics between the multiple semiconductor switching elements connected in series.

[0057] Next, the effect of the impedance reducing element when the semiconductor switching element is turned off due to the transition of the switching pattern will be described with reference to FIGS.

[0058] FIG. 6 shows a current path 211 formed in the power conversion device 100 when the switching pattern of FIG. 3B is applied and the semiconductor switching elements Q3 and Q4 are in an on state.

[0059] Fig. 7 shows a current path 212 that is formed immediately after switching the on / off states of the semiconductor switching elements Q1 and Q4 in the circuit unit 120 from the state shown in Fig. 6. Comparing Fig. 7 with Fig. 6, it can be seen that the transition from current path 211 to current path 212 increases the impedance of the current path by the amount of the parasitic impedance of path PTH1 in Fig. 5.

[0060] Fig. 8 shows a comparative example of a power conversion device in which the impedance-reducing element 200 from Fig. 5 has been removed, in a similar situation to Fig. 6 , that is, a current path 213 formed after switching on and off of the semiconductor switching elements Q1 and Q4. Comparing Fig. 8 with Fig. 6 , it can be seen that the transition from the current path 211 to the current path 213 increases the impedance of the current path by the amount of the parasitic impedance of the path PTH2 in Fig. 5 .

[0061] From this, it can be seen that the arrangement of the impedance-reducing element 200 can reduce the amount of change (increase) in parasitic impedance that occurs when the semiconductor switching elements Q1 and Q4 in the circuit unit 120 are switched on and off, compared to the case where the impedance-reducing element 200 is not arranged (Figure 8).

[0062] In the power conversion device 100 according to this embodiment, the current path 212 is formed immediately after the semiconductor switching elements Q1 and Q4 are switched on and off, and then, as the surge component (high-frequency component) attenuates over time, the current path 213 similar to that shown in Fig. 8 is formed. However, a surge voltage due to the high-frequency component is generated when the current path 212 is formed.

[0063] Fig. 9 is an example of an operational waveform diagram of the semiconductor switching element of the power conversion device according to embodiment 1. Fig. 9 shows a schematic waveform example of the output voltage (drain-source voltage) of semiconductor switching element Q1 when semiconductor switching element Q1 is turned off, more specifically, when the switching pattern transitions from Fig. 3(a) to Fig. 3(b) or Fig. 3(c) while power is being transmitted from DC power source 1 to DC power source 2.

[0064] In Figure 9, an example waveform for the power conversion device 100 in which the impedance reducing element 200 is installed is shown by a solid line, while an example waveform for the comparative example (the power conversion device of Figure 8) in which the impedance reducing element 200 is not installed is shown by a dotted line.

[0065] 9, it can be seen that the placement of the impedance-reducing element 200 reduces the maximum value of the output voltage, i.e., the peak value of the first oscillation component, and suppresses surge voltage. Furthermore, by suppressing surge voltage, the withstand voltage of the semiconductor switching element can be ensured even if the resistance value of the gate resistor Rg is lowered to increase the switching speed in order to reduce switching loss. Therefore, switching loss can also be reduced compared to a configuration in which the impedance-reducing element 200 is not placed.

[0066] Thus, according to the power conversion device of embodiment 1, in a circuit configuration in which multiple semiconductor switching elements are connected in series and a flying capacitor (capacitor 131) is arranged, the parasitic inductance that affects the on / off of the semiconductor switching elements Q1 to Q4 can be reduced by arranging the impedance reducing element 200.

[0067] Furthermore, in the comparative example (the power conversion device of FIG. 8 ) in which the impedance reducing element 200 is not provided, in order to reduce the parasitic inductance that affects the on / off of the semiconductor switching elements, it is necessary to shorten the wiring length between the nodes Nf and Nc and between the nodes Nf and Ne for connecting the circuit unit 120 and the capacitor 131. This raises concerns that restrictions will be placed on the layout of the bridge circuit 110 configured to include the circuit units 120 and 130.

[0068] In particular, in each of the circuit units 120 and 130, a compact arrangement is preferable to shorten the wiring length of the paths PTH1 and PTH3 in FIG. 6 in order to reduce parasitic inductance, but there is a concern that it may be difficult to achieve both such a compact arrangement and shortening the connecting wiring length of the circuit unit 120 and the capacitor 131 described above.

[0069] In contrast, the power conversion device 100 including the impedance reducing element 200 can eliminate the influence of parasitic impedance due to the wiring connecting the circuit unit 120 and the capacitor 131. This not only eliminates the need for the layout constraints described above, but also makes it easier to align the switching characteristics between multiple semiconductor switching elements connected in series by aligning the path lengths (parasitic impedances) of the paths PTH1 and PTH3 between the circuit units 120 and 130. This makes it possible to avoid imbalances in surge voltages between switching patterns and suppress the maximum value of surge voltages among the multiple semiconductor switching elements.

[0070] 10 is a circuit diagram illustrating another example of the configuration of the impedance-reducing element 200. As shown in FIG. 10, the impedance-reducing element 200 can be configured to include a capacitor 201 and a resistor 202 connected in series.

[0071] As can be seen from FIG. 1 etc., by connecting capacitor 201 as impedance reducing element 200 in parallel with capacitor 131, an LC circuit is formed by capacitors 131 and 151 and the parasitic inductance of the wiring connecting them, and therefore, depending on the constants of the LC circuit, a resonance phenomenon may occur in the LC circuit at the switching frequency of semiconductor switching elements Q1 to Q4.

[0072] By configuring the impedance reducing element 200 to have the resistive element 202 connected in series with the capacitor 201, the Q value of the resonance can be suppressed even when a resonance phenomenon occurs, thereby preventing malfunction of the semiconductor switching element due to the resonance phenomenon.

[0073] Second Embodiment In the first embodiment, the power conversion device in which two semiconductor switching elements are connected in series has been described, but the number of semiconductor switching elements connected in series can be any number equal to or greater than three.

[0074] FIG. 11 is a schematic configuration diagram of a power conversion device 100X according to the second embodiment.

[0075] As shown in FIG. 11, the power conversion device 100X according to the second embodiment further includes a circuit unit 140 in addition to the circuit units 120 and 130 similar to those in FIG. 1 (power conversion device 100).

[0076] Like the circuit unit 130, the circuit unit 140 has two semiconductor switching elements (Q3, Q4) that constitute a canonical cell, and a capacitor 201. The circuit unit 140 further has driver circuits 181, 182 that turn the two switching elements on and off in accordance with gate drive signals (Sd3, Sd4) from the controller 210.

[0077] The circuit units 120 to 140 are arranged such that three semiconductor switching elements Q1 to Q3 are connected in series between the first positive wiring 122 and the output node Nd, and three semiconductor switching elements Q4 to Q6 are connected in series between the output node Nd and the first negative wiring 123. That is, the positive side semiconductor switching elements of the circuit units 120 to 130 are connected in series as the semiconductor switching elements Q1 to Q3, and the negative side semiconductor switching elements of the circuit units 120 to 130 are connected in series as the semiconductor switching elements Q4 to Q6.

[0078] Capacitor 131 of circuit unit 130 is connected as a flying capacitor between second positive wiring 132 connecting semiconductor switching elements Q1 (negative terminal) and Q2 (positive terminal) and second negative wiring 133 connecting semiconductor switching elements Q5 (negative terminal) and Q6 (positive terminal). In circuit unit 120, impedance reducing element 200 is electrically connected in parallel with capacitor 131 in the same manner as in FIG. 1 .

[0079] Capacitor 141 of circuit unit 140 serves as a flying capacitor and is connected between a node Np on a third positive wiring 142 that connects semiconductor switching elements Q2 (negative terminal) and Q3 (positive terminal), and a node Nq on a third negative wiring 143 that connects semiconductor switching elements Q4 (negative terminal) and Q5 (positive terminal). A voltage sensor 154 is disposed on capacitor 141. This allows the controller 210 to detect the voltage Vfc1 (voltage sensor 153) of capacitor 131 and the voltage Vfc2 of capacitor 141.

[0080] An impedance-reducing element 205 is electrically connected to the circuit unit 130 in parallel with the capacitor 141. Like the impedance-reducing element 200, the impedance-reducing element 205 includes a capacitor 206 having a capacitance value smaller than that of the capacitor 141. In the impedance-reducing element 205, a resistive element connected in series with the capacitor 206 may also be further disposed, like in FIG. 10 .

[0081] The impedance reducing element 205 is connected between a node Nx connected to the negative terminal (source) of the semiconductor switching element Q2 and a node Ny connected to the positive terminal (drain) of the semiconductor switching element Q5 in the circuit unit 130. The node Nx is electrically connected to the third positive wiring 142, and the node Ny is electrically connected to the third negative wiring 143, so that the impedance reducing element 205 is electrically connected in parallel with the capacitor 141.

[0082] The impedance reducing element 205 is also arranged so that the wiring length of the path from node Nx to impedance reducing element 205 to node Ny is shorter than the wiring length of the path from node Nx to (node ​​Np) to capacitor 141 to (node ​​Nq) to node Ny.

[0083] This makes it possible to eliminate the influence of parasitic impedance due to wiring (between nodes Nx and Np and between nodes Ny and Nq) for connecting capacitor 141 as a flying capacitor on turning on and off the semiconductor switching element.

[0084] As a result, in the power conversion device of embodiment 2, in a circuit configuration in which multiple (three) semiconductor switching elements are connected in series and two flying capacitors (capacitors 131, 141) are arranged, the parasitic inductance that affects the on / off of the semiconductor switching elements Q1 to Q6 can be reduced by arranging impedance reducing elements 200, 205.

[0085] In this way, the power conversion device of this embodiment can achieve the same effect by electrically connecting the above-mentioned impedance reducing elements (200, 205) in parallel to each flying capacitor in a circuit configuration in which any N (N: integer greater than or equal to 2) semiconductor switching elements are connected in series and (N-1) flying capacitors are provided.

[0086] In the configuration example (power conversion device 100) of FIG. 1 , N=2, and for the semiconductor switching elements Q1 and Q2 corresponding to the "two first semiconductor switching elements," in order from the outside (the first positive wiring 122 side), the semiconductor switching element Q2 corresponds to an example of the "first first semiconductor switching element," and the semiconductor switching element Q1 corresponds to an example of the "second first semiconductor switching element."

[0087] Similarly, with regard to the semiconductor switching elements Q3 and Q4 corresponding to the "two second semiconductor switching elements," from the outside (the first negative wiring 123 side), the semiconductor switching element Q4 corresponds to an example of the "first second semiconductor switching element," and the semiconductor switching element Q3 corresponds to an example of the "second second semiconductor switching element." Furthermore, the impedance reducing element 200 is arranged such that the node Nb corresponds to an example of the "first node," and the node Nf corresponds to an example of the "second node."

[0088] In the configuration example (power conversion device 100X) of Figure 11, N = 3, and for the semiconductor switching elements Q1 to Q3 corresponding to the "three first semiconductor switching elements," in order from the outside (the first positive wiring 122 side), semiconductor switching element Q1 corresponds to an example of the "first first semiconductor switching element," semiconductor switching element Q2 corresponds to an example of the "second first semiconductor switching element," and semiconductor switching element Q3 corresponds to an example of the "third first semiconductor switching element."

[0089] Similarly, with regard to semiconductor switching elements Q4 to Q6 corresponding to the “three second semiconductor switching elements,” in order from the outside (the first negative wiring 123 side), semiconductor switching element Q6 corresponds to an example of the “first second semiconductor switching element,” semiconductor switching element Q5 corresponds to an example of the “second second semiconductor switching element,” and semiconductor switching element Q4 corresponds to an example of the “third second semiconductor switching element.” Furthermore, impedance reducing elements 200, 205 are arranged such that nodes Nb, Nx each correspond to an example of the “first node,” and nodes Nf, Ny each correspond to an example of the “second node.”

[0090] In the present embodiment, an example has been described in which the power conversion device 100, 100X equipped with the bridge circuit 110 operates as a chopper circuit. However, even when the power conversion device 100, 100X having a similar configuration operates as a multilevel power conversion device as in Patent Document 1, the same effect can be obtained by arranging an impedance reducing element.

[0091] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0092] 1, 2 DC power supply, 21 Diode, 100, 100X Power conversion device, 102 Filter reactor, 103 Filter capacitor, 110 Bridge circuit, 120, 130, 140 Circuit unit, 121, 131, 141, 201, 206 Capacitor, 122 First positive wiring, 123 First negative wiring, 132 Second positive wiring, 133 Second negative wiring, 142 Third positive wiring, 143 Third negative wiring, 151 to 154 Voltage sensor, 155 Current sensor, 161, 162, 171, 172, 181, 182 Driver circuit, 200, 205 Impedance reduction element, 202 Resistive element, 210 Controller, 211 to 213 Current path, Nd Output node, PTH1 to PTH3 Path, Q1 to Q6 Semiconductor switching element, Rg gate resistor, Sd1 to Sd4 on / off drive signals.

Claims

1. N first semiconductor switching elements, numbered from first to N (N: an integer of 2 or more), arranged in series between a first positive wiring on a high voltage side and an output node, in order from the first positive wiring toward the output node; N second semiconductor switching elements, numbered from first to N, that are arranged in series between a first negative wiring on a low voltage side and the output node in order from the first negative wiring toward the output node; a first capacitor connected between an (i+1)th positive wiring connecting an i-th (i: an integer of 1 or more and (N-1) or less) first semiconductor switching element and an (i+1)th first semiconductor switching element among the N first semiconductor switching elements, and an (i+1)th negative wiring connecting an i-th second semiconductor switching element and an (i+1)th second semiconductor switching element among the N second semiconductor switching elements; an impedance reducing element including a second capacitor electrically connected to the (i+1) positive wiring and the (i+1) negative wiring, in parallel with each of the first capacitors; a power conversion device, wherein the impedance reducing element is arranged such that the wiring length of a first path from a first node connected to the negative terminal of the i-th first semiconductor switching element via the impedance reducing element to a second node connected to the positive terminal of the i-th second semiconductor switching element is shorter than the wiring length of a second path from the first node to the second node via the first capacitor.

2. N is 2, the N first semiconductor switching elements include first and second first semiconductor switching elements that are arranged in series between the first positive wiring and the output node in order from the first positive wiring toward the output node, the N second semiconductor switching elements include first and second second semiconductor switching elements that are arranged in order from the first negative wiring toward the output node and connected in series between the first negative wiring and the output node, the first capacitor is electrically connected between a second positive wiring that connects the first first semiconductor switching element and the second first semiconductor switching element, and a second negative wiring that connects the first second semiconductor switching element and the second second second semiconductor switching element; The impedance reducing element is the second capacitor is electrically connected to the second positive wiring and the second negative wiring in parallel with the first capacitor, the first node is connected to the negative terminal of the first semiconductor switching element; The power conversion device according to claim 1 , wherein the second node is connected to a positive terminal of the first second semiconductor switching element.

3. The power conversion device according to claim 1 , wherein a capacitance value of the second capacitor is smaller than a capacitance value of the first capacitor.

4. The power conversion device according to claim 1 , wherein the impedance reducing element further includes a resistive element connected in series with the second capacitor.