Nitride semiconductor device and method for manufacturing same

Abstract

The nitride semiconductor device (1) is a nitride semiconductor device including an active element (10) and a passive element (20), and includes a nitride semiconductor layer (120) divided into an active region (101) and an inactive region (102) in a planar view, and a metal layer (150) in contact with the nitride semiconductor layer (120) in the inactive region (102). The active element (10) is provided in the active region (101), and the passive element (20) is provided in the inactive region (102). The metal layer (150) includes a coherent state or a metamorphic state with respect to the nitride semiconductor layer (120).

Description

[Technical field]

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses an electronic device including an inductor including a GaN layer, an AlGaN layer provided on the GaN layer, a p-type GaN layer provided on the AlGaN layer, and a metal layer provided on the p-type GaN layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2011 / 038048 Summary of the Invention [Problem to be solved by the invention]

[0004] When the semiconductor layer in contact with the metal layer contains carriers, a depletion layer is formed in the semiconductor layer, extending from the interface with the metal layer. The formed depletion layer causes an increase in parasitic capacitance. The parasitic capacitance may cause wiring delays when the device is operated at high frequencies. In addition, when the carrier density changes due to the state of voltage application to the device, the magnitude of the parasitic capacitance also changes. As a result, variations in high frequency operation may occur. Thus, in the conventional technology, there is a risk of degradation of high frequency characteristics.

[0005] Therefore, the present disclosure provides a nitride semiconductor device having excellent high-frequency characteristics and a manufacturing method thereof. [Means for solving the problem]

[0006] A nitride semiconductor device according to one aspect of the present disclosure is a nitride semiconductor device including an active element and a passive element, and includes a nitride semiconductor layer divided into an active region and an inactive region in a planar view, and a metal layer in contact with the nitride semiconductor layer in the inactive region, wherein the active element is provided in the active region, the passive element is provided in the inactive region, and the metal layer includes a coherent state or a metamorphic state with respect to the nitride semiconductor layer.

[0007] A manufacturing method for a nitride semiconductor device according to one aspect of the present disclosure is a manufacturing method for a nitride semiconductor device including an active element and a passive element, and includes a step of forming a nitride semiconductor layer that is divided into an active region and an inactive region in a planar view, and a step of forming a metal layer in contact with the nitride semiconductor layer in the inactive region, wherein the active element is provided in the active region, the passive element is provided in the inactive region, and the metal layer includes a coherent state or a metamorphic state with respect to the nitride semiconductor layer. Effect of the Invention

[0008] According to the present disclosure, it is possible to provide a nitride semiconductor device having excellent high-frequency characteristics and a method for manufacturing the same. [Brief description of the drawings]

[0009] [Figure 1A] FIG. 1A is a cross-sectional view of a nitride semiconductor device according to a first embodiment including a capacitor as a passive element. [Figure 1B] FIG. 1B is a cross-sectional view showing the nitride semiconductor device according to the first embodiment including a resistor element as a passive element. [Figure 1C] FIG. 1C is a cross-sectional view showing a nitride semiconductor device according to the first embodiment including an inductor as an active element. [Figure 2A] FIG. 2A is a diagram showing a hexagonal close-packed crystal structure. [Figure 2B] FIG. 2B is a diagram showing a crystal structure of a face-centered cubic lattice structure. [Figure 3A]FIG. 3A is a cross-sectional view of a nitride semiconductor device according to a first modification of the first embodiment, including a capacitor as a passive element. [Figure 3B] FIG. 3B is a cross-sectional view showing a nitride semiconductor device according to a first modification of the first embodiment, including a resistor element as a passive element. [Figure 3C] FIG. 3C is a cross-sectional view showing a nitride semiconductor device according to a first modification of the first embodiment, including an inductor as an active element. [Figure 4A] FIG. 4A is a cross-sectional view of a nitride semiconductor device according to a second modification of the first embodiment, including a capacitor as a passive element. [Figure 4B] FIG. 4B is a cross-sectional view showing a nitride semiconductor device according to Modification 2 of Embodiment 1, including a resistor element as a passive element. [Figure 4C] FIG. 4C is a cross-sectional view showing a nitride semiconductor device according to Modification 2 of Embodiment 1 including an inductor as an active element. [Figure 5A] FIG. 5A is a cross-sectional view of a nitride semiconductor device according to a third modification of the first embodiment, including a capacitor as a passive element. [Figure 5B] FIG. 5B is a cross-sectional view showing a nitride semiconductor device according to Modification 3 of Embodiment 1, including a resistor element as a passive element. [Figure 5C] FIG. 5C is a cross-sectional view showing a nitride semiconductor device according to Modification 3 of Embodiment 1, including an inductor as an active element. [Figure 6] FIG. 6 is a flowchart showing a first example of a method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 7A] FIG. 7A is a cross-sectional view illustrating a step included in a first example of a method for manufacturing a nitride semiconductor device according to the first embodiment. [Figure 7B] FIG. 7B is a cross-sectional view illustrating a step included in the first example of the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 7C] FIG. 7C is a cross-sectional view illustrating a step included in the first example of the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 7D] FIG. 7D is a cross-sectional view illustrating a step included in the first example of the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 7E] FIG. 7E is a cross-sectional view illustrating a step included in the first example of the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 7F] FIG. 7F is a cross-sectional view illustrating a step included in the first example of the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a flowchart showing a second example of the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 9A] FIG. 9A is a cross-sectional view illustrating a step included in the second example of a method for manufacturing a nitride semiconductor device according to the first embodiment. [Figure 9B] FIG. 9B is a cross-sectional view illustrating a step included in the second example of the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a flowchart showing a third example of the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view of a nitride semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a cross-sectional view of a nitride semiconductor device according to a modification of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] (Summary of the Disclosure) A nitride semiconductor device according to a first aspect of the present disclosure is a nitride semiconductor device including an active element and a passive element, and includes a nitride semiconductor layer divided into an active region and an inactive region in a planar view, and a metal layer in contact with the nitride semiconductor layer in the inactive region, wherein the active element is provided in the active region, the passive element is provided in the inactive region, and the metal layer includes a coherent state or a metamorphic state with respect to the nitride semiconductor layer.

[0011] This improves the crystallinity of the metal layer, improving the electrical characteristics of the metal layer (e.g., lowering resistance), and improving the high-frequency characteristics. Also, since the metal layer is provided in an inactive region, passive elements including the metal layer are less susceptible to carrier fluctuations during high-frequency operation. Therefore, a nitride semiconductor device with excellent high-frequency characteristics can be realized.

[0012] A nitride semiconductor device according to a second aspect of the present disclosure is the nitride semiconductor device according to the first aspect, wherein the nitride semiconductor layer includes a channel layer and a barrier layer provided above the channel layer, and the active element includes two-dimensional electron gas generated in the vicinity of the interface between the channel layer and the barrier layer.

[0013] This makes it possible to utilize the high electron mobility of the two-dimensional electron gas (2DEG) to operate active elements at high speeds, for example, making it possible to speed up switching operations and improve the high-frequency characteristics of nitride semiconductor devices.

[0014] A nitride semiconductor device according to a third aspect of the present disclosure is the nitride semiconductor device according to the second aspect, wherein in the active region, the carrier density of the channel layer is 1×10 15 cm -3 That's all.

[0015] This makes it possible to utilize the high electron mobility of the 2DEG to operate active elements at high speeds, for example, making it possible to increase the speed of switching operations and improve the high frequency characteristics of nitride semiconductor devices.

[0016] A nitride semiconductor device according to a fourth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to third aspects, wherein the nitride semiconductor layer has a stacked structure made up of a plurality of layers, and in the inactive region, a carrier density of a top layer of the nitride semiconductor layer is 1×10 15 cm -3 Less than.

[0017] This makes it possible to reduce the parasitic capacitance between the metal layer and the nitride semiconductor layer, thereby improving the high frequency characteristics of the passive element.

[0018] A nitride semiconductor device according to a fifth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to fourth aspects, wherein a contact surface between the nitride semiconductor layer and the metal layer in the inactive region is located below a top surface of the nitride semiconductor layer in the active region.

[0019] As a result, in the inactive region, for example, by removing most or all of the barrier layer, it is possible to prevent the generation of 2DEG. This reduces the carrier concentration in the nitride semiconductor layer, thereby reducing the parasitic capacitance between the metal layer and the nitride semiconductor layer. This improves the high frequency characteristics of the passive element.

[0020] A nitride semiconductor device according to a sixth aspect of the present disclosure is the nitride semiconductor device according to any one of the second or third aspects, wherein the nitride semiconductor layer further includes a buffer layer provided below the channel layer, and the metal layer contacts the buffer layer in the inactive region.

[0021] As a result, the buffer layer is generally a high resistance layer with a sufficiently low carrier concentration, which suppresses operational variations and improves the high frequency characteristics of the passive elements.

[0022] A nitride semiconductor device according to a seventh aspect of the present disclosure is the nitride semiconductor device according to any one of the first to sixth aspects, wherein the nitride semiconductor layer includes an impurity region doped with C or Fe, and the metal layer contacts the impurity region in the inactive region.

[0023] This increases the resistance of the impurity regions doped with C or Fe, thereby suppressing operational variations and improving the high frequency characteristics of the passive elements.

[0024] A nitride semiconductor device according to an eighth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to seventh aspects, wherein the metal layer includes a barrier metal layer and a low-resistance metal layer provided above the barrier metal layer and having a lower resistance than the barrier metal layer.

[0025] This suppresses the formation of mixed crystals between the low-resistance metal layer and the nitride semiconductor layer. Since carrier generation in the nitride semiconductor layer is suppressed, the passive elements are less susceptible to the effects of carrier fluctuations. This improves the high-frequency characteristics of the passive elements.

[0026] A nitride semiconductor device according to a ninth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to eighth aspects, wherein the passive element is a resistive element including the metal layer.

[0027] This improves the crystallinity of the metal layer, thereby increasing the resistance to electromigration, and suppresses disconnection or short circuiting of the resistance element, thereby improving the high frequency characteristics of the resistance element.

[0028] A nitride semiconductor device according to a tenth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to eighth aspects, wherein the passive element is a capacitor including the metal layer as a lower electrode.

[0029] This improves the crystallinity of the metal layer, which is the lower electrode, thereby realizing a lower resistance of the lower electrode and reducing losses due to parasitic resistance components. In addition, abnormal growth such as hillocks is suppressed, so that the reduction in coverage of the insulating layer and the concentration of the electric field can be suppressed. Therefore, the reduction in the breakdown voltage of the capacitor can be suppressed.

[0030] A nitride semiconductor device according to an eleventh aspect of the present disclosure is the nitride semiconductor device according to any one of the first to eighth aspects, wherein the passive element is an inductor including the metal layer.

[0031] This improves the crystallinity of the metal layer, thereby reducing the parasitic resistance of the inductor, thereby reducing loss due to the parasitic resistance.

[0032] A nitride semiconductor device according to a twelfth aspect of the present disclosure is the nitride semiconductor device according to the eighth aspect, wherein the lattice constant of the barrier metal layer is larger than the lattice constant of the low-resistance metal layer and is not more than √2 times the lattice constant of the a-axis at the contact surface of the nitride semiconductor layer with the metal layer.

[0033] This makes it possible to reduce dislocations that may occur in the low-resistance metal layer, thereby enabling the resistance of the low-resistance metal layer to be further reduced.

[0034] A nitride semiconductor device according to a thirteenth aspect of the present disclosure is the nitride semiconductor device according to the twelfth aspect, wherein the lattice constants of each of the low-resistance metal layer and the barrier metal layer are 90% or more of √2 times the lattice constant of the a-axis at the contact surface of the nitride semiconductor layer with the metal layer.

[0035] This makes it possible to reduce dislocations that may occur in the low-resistance metal layer, thereby enabling the resistance of the low-resistance metal layer to be further reduced.

[0036] A nitride semiconductor device according to a fourteenth aspect of the present disclosure is the nitride semiconductor device according to the eighth, twelfth or thirteenth aspect, wherein the low-resistance metal layer has a face-centered cubic lattice structure composed of at least one element selected from the group consisting of Al, Cu, Au, Ag and Pt.

[0037] This makes it possible to reduce the resistance of the metal layer while maintaining the crystallinity of the metal layer.

[0038] A nitride semiconductor device according to a fifteenth aspect of the present disclosure is the nitride semiconductor device according to any one of the eighth aspect and the twelfth to fourteenth aspects, wherein the barrier metal layer has a NaCl type structure constituted by at least one element selected from the group consisting of Ti, Ta, W and Hf, and at least one element of N and C.

[0039] This makes it possible to suppress the formation of mixed crystals between the metal layer and the nitride semiconductor layer while maintaining the crystallinity of the metal layer.

[0040] A nitride semiconductor device according to a sixteenth aspect of the present disclosure is the nitride semiconductor device according to any one of the eighth aspect and the twelfth to fifteenth aspects, wherein the metal layer further includes a layer having a hexagonal close-packed structure and composed of at least one element selected from the group consisting of Ti, Ta, W and Hf, provided between the barrier metal layer and the nitride semiconductor layer.

[0041] This makes it possible to improve the adhesion between the metal layer and the nitride semiconductor layer while maintaining the crystallinity of the metal layer.

[0042] A nitride semiconductor device according to a seventeenth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to sixteenth aspects, wherein the active element includes a gate electrode, a source electrode, and a drain electrode, and at least one of the gate electrode, the source electrode, and the drain electrode includes the same material as at least a portion of the metal layer.

[0043] This allows the electrode containing the same material as the metal layer to be formed in the same process as the metal layer.

[0044] A manufacturing method for a nitride semiconductor device according to an eighteenth aspect of the present disclosure is a manufacturing method for a nitride semiconductor device including an active element and a passive element, comprising the steps of forming a nitride semiconductor layer divided into an active region and an inactive region in a planar view, and forming a metal layer in contact with the nitride semiconductor layer in the inactive region, wherein the active element is provided in the active region, the passive element is provided in the inactive region, and the metal layer includes a coherent state or a metamorphic state with respect to the nitride semiconductor layer.

[0045] This allows the formation of a metal layer with good crystallinity, improving the electrical properties of the metal layer (e.g., lowering resistance), and improving high-frequency properties. In addition, since the metal layer is provided in an inactive region, passive elements including the metal layer are less susceptible to carrier fluctuations during high-frequency operation. This allows the manufacture of a nitride semiconductor device with excellent high-frequency properties.

[0046] A manufacturing method for a nitride semiconductor device according to a 19th aspect of the present disclosure is a manufacturing method for a nitride semiconductor device according to the 18th aspect, comprising the steps of forming a first recess portion in the nitride semiconductor layer, forming a source electrode and a drain electrode of the active element in the first recess portion, forming a gate electrode of the active element on the nitride semiconductor layer, and forming a second recess portion in the nitride semiconductor layer before forming the metal layer, wherein in the forming the metal layer, the metal layer is formed on a bottom surface of the second recess portion.

[0047] This makes it possible to easily passivate the nitride semiconductor layer by the second recess portion.

[0048] A method for manufacturing a nitride semiconductor device according to a twentieth aspect of the present disclosure is the method for manufacturing a nitride semiconductor device according to the nineteenth aspect, in which the step of forming the first recess portion and the step of forming the second recess portion are performed simultaneously.

[0049] This allows the first recess portion and the second recess portion to be formed in the same process. By simplifying the manufacturing process, the possibility of manufacturing errors can be reduced, and the yield can be increased.

[0050] A method for manufacturing a nitride semiconductor device according to a twenty-first aspect of the present disclosure is a method for manufacturing a nitride semiconductor device according to the nineteenth or twentieth aspect, in which the step of forming the metal layer and the step of forming the gate electrode are carried out simultaneously.

[0051] This allows the metal layer and the gate electrode to be formed in the same process, and by simplifying the manufacturing process, it is possible to reduce the possibility of manufacturing errors and increase the yield.

[0052] A twenty-second aspect of the present disclosure relates to a method for manufacturing a nitride semiconductor device according to the twenty-first aspect, wherein the passive element is a capacitor including the metal layer as a lower electrode, and the method for manufacturing the nitride semiconductor device further includes a step of forming an insulating layer on the metal layer, and a step of forming an upper electrode on the insulating layer.

[0053] This improves the crystallinity of the metal layer, which is the lower electrode, thereby realizing a lower resistance of the lower electrode and reducing losses due to parasitic resistance components. In addition, abnormal growth such as hillocks is suppressed, so that the reduction in coverage of the insulating layer and the concentration of the electric field can be suppressed. Therefore, the reduction in the breakdown voltage of the capacitor can be suppressed.

[0054] Hereinafter, the embodiment will be specifically described with reference to the drawings.

[0055] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection of the components, manufacturing processes, and the order of the manufacturing processes shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in the independent claims are described as optional components.

[0056] In addition, each figure is a schematic diagram and is not necessarily illustrated precisely. Therefore, for example, the scales in each figure do not necessarily match. In addition, in each figure, substantially the same configurations are given the same reference numerals, and duplicated explanations are omitted or simplified.

[0057] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0058] In the present specification and drawings, the x-axis, y-axis, and z-axis represent three axes of a three-dimensional Cartesian coordinate system. In each embodiment, the z-axis direction is perpendicular to the main surface of the substrate, and the x-axis and y-axis directions are parallel to the main surface of the substrate.

[0059] In this specification, the "principal surface" of a substrate means the main surface of the substrate, for example, the surface having the largest area, or the surface located opposite to the surface having the largest area and having an area equivalent to that of the surface having the largest area. The principal surface is usually flat, but may include minute irregularities or curvatures. The same applies to the "principal surface" of each layer, such as a semiconductor layer, a metal layer, or an insulating layer.

[0060] In addition, in this specification, the terms "upward" and "downward" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked configuration. Specifically, the positive direction of the z axis is considered to be "upward," and the negative direction of the z axis is considered to be "downward." In addition, the terms "upward" and "downward" are applied not only to the case where two components are arranged with a gap between them and another component exists between the two components, but also to the case where two components are arranged closely together and the two components are in contact with each other.

[0061] In this specification, unless otherwise specified, the term "planar view" refers to a view perpendicular to the main surface of the substrate. Specifically, the term "planar view" refers to a view from the positive or negative side of the z axis.

[0062] Additionally, a layer made of one or more elements or compositions, and a layer composed of one or more elements or compositions, mean that the layer contains substantially only one or more elements or compositions, although the layer may contain other elements as impurities, for example elements that are unavoidable during manufacturing, at a rate of 1% or less.

[0063] In addition, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components, unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0064] (Embodiment 1) First, a nitride semiconductor device according to the first embodiment will be described.

[0065] The nitride semiconductor device according to the present embodiment includes an active element and a passive element. The active element is, for example, a transistor or a tunnel diode. The passive element is, for example, a capacitor, a resistive element, an inductor. First, a nitride semiconductor device including a capacitor as a passive element will be described below with reference to FIG. 1A. A configuration including a resistive element or an inductor will be described later with reference to FIG. 1B or FIG. 1C.

[0066] [Nitride semiconductor device with capacitor] 1A is a cross-sectional view of a nitride semiconductor device 1 according to the present embodiment, which includes a capacitor 20 as a passive element. As shown in FIG. 1A, the nitride semiconductor device 1 includes a transistor 10 and the capacitor 20. The nitride semiconductor device 1 also includes a substrate 110 and a nitride semiconductor layer 120.

[0067] The transistor 10 is an example of an active element, and is provided in an active region 101. The capacitor 20 is an example of a passive element, and is provided in an inactive region .

[0068] The active region 101 and the inactive region 102 are regions that do not overlap with each other in a plan view. In this embodiment, the active region 101 and the inactive region 102 are distinguished by the presence or absence of a second recess portion 136. Specifically, the region where the second recess portion 136 is provided is the inactive region 102, and the region where the second recess portion 136 is not provided is the active region 101. In the active region 101, the carrier concentration of the channel layer 124 is 1×10 15 cm -3 In the inactive region 102, the carrier concentration of the channel layer 124 is 1×10 15 cm -3 Less than.

[0069] 1A, the transistor 10 includes a portion of each of the substrate 110 and the nitride semiconductor layer 120 located in the active region 101, a source electrode 140, a drain electrode 142, and a gate electrode 144. In the portion of the nitride semiconductor layer 120 located in the active region 101, a 2DEG 125 is generated near the interface between a channel layer 124 and a barrier layer 126. The transistor 10 is a high electron mobility transistor (HEMT) including the 2DEG 125 as a channel.

[0070] The substrate 110 is a base substrate for forming the nitride semiconductor layer 120. The substrate 110 is, for example, a single crystal Si substrate whose main surface (upper surface) is a (111) surface. For example, the resistivity of the substrate 110 is 1 kΩcm or more, but is not limited to this. The resistivity of the substrate 110 may be 20 Ωcm or less. Furthermore, the substrate 110 is not limited to a single crystal Si substrate, and may be a substrate made of SiC, sapphire, GaN, AlN, or the like.

[0071] The nitride semiconductor layer 120 is a layer made of a group III nitride semiconductor. The nitride semiconductor layer 120 has a stacked structure made of a plurality of layers. Specifically, as shown in FIG. 1A, the nitride semiconductor layer 120 includes a buffer layer 122, a channel layer 124, and a barrier layer 126.

[0072] The nitride semiconductor layer 120 is divided into an active region 101 and an inactive region 102 in a plan view. In the present embodiment, the buffer layer 122 has the same configuration in the active region 101 and the inactive region 102. The channel layer 124 has a thickness in a portion located in the active region 101 that is thicker than a portion located in the inactive region 102. The barrier layer 126 is provided in the active region 101 and is not provided in the inactive region 102.

[0073] The buffer layer 122 is provided above the substrate 110 and below the channel layer 124. Specifically, the buffer layer 122 is provided in contact with the upper surface of the substrate 110 and the lower surface of the channel layer 124. The buffer layer 122 is a layer made of a group III nitride semiconductor. For example, the buffer layer 122 is made of undoped Al x Ga 1-x The buffer layer 122 has a laminated structure of multiple layers made of AlN. Here, x is equal to or greater than 0 and equal to or less than 1. That is, the buffer layer 122 may include an AlN layer or a GaN layer. The buffer layer 122 may include a layer that is doped with C or Fe to increase its resistance. The buffer layer 122 may also include a superlattice structure. The buffer layer 122 may have a single-layer structure of a GaN layer, an AlGaN layer, or an AlN layer. Alternatively, the buffer layer 122 may not be provided.

[0074] The channel layer 124 is provided above the substrate 110. Specifically, the channel layer 124 is provided in contact with the upper surface of the buffer layer 122. The channel layer 124 is a layer made of a Group III nitride semiconductor. For example, the channel layer 124 is a layer made of GaN, but may contain In.

[0075] In this embodiment, the channel layer 124 has a different thickness between the active region 101 and the inactive region 102. Specifically, the thickness of the channel layer 124 in the active region 101 is thicker than the thickness of the channel layer 124 in the inactive region 102. The thickness of the channel layer 124 in the active region 101 is, for example, 150 nm. The thickness of the channel layer 124 in the inactive region 102 is, for example, half or less of the thickness of the channel layer 124 in the active region 101, but may be 10% or less, and is not limited thereto. The channel layer 124 in the inactive region 102 is formed to such a thickness that its upper surface (i.e., the bottom surface of the second recess portion 136, the contact surface 120b shown in FIG. 1A) is lower than the 2DEG 125 generated in the active region 101. The thickness of the channel layer 124 may be uniform between the active region 101 and the inactive region 102.

[0076] The barrier layer 126 is provided above the channel layer 124. For example, the barrier layer 126 is provided in contact with the upper surface of the channel layer 124. The barrier layer 126 is a layer made of a group III nitride semiconductor. For example, the barrier layer 126 is made of Al 0.25 Ga 0.75 The barrier layer 126 may be a layer made of, but is not limited to, N. The Al composition ratio of the AlGaN constituting the barrier layer 126 may be a value selected from the range of 15% to 100%. The barrier layer 126 may also contain In.

[0077] The band gap of the barrier layer 126 is larger than the band gap of the channel layer 124. A 2DEG 125 is generated near the interface between the barrier layer 126 and the channel layer 124. In this embodiment, the barrier layer 126 is not provided in the inactive region 102 but only in the active region 101, so that the 2DEG 125 is not generated in the inactive region 102 but only in the active region 101. The 2DEG 125 generated in the active region 101 functions as the channel of the transistor 10. In the active region 101, the carrier density of the channel layer 124 is 1×10 15 cm -3 That is all. The normal temperature is, for example, 25°C.

[0078] The nitride semiconductor layer 120 is provided with first recessed portions 130 and 132 and a second recessed portion 136. The first recessed portions 130 and 132 and the second recessed portion 136 are each a recess that penetrates the barrier layer 126 and is formed by removing at least a portion of the channel layer 124.

[0079] The first recess portion 130 is provided to reduce the contact resistance between the source electrode 140 and the 2DEG 125. The 2DEG 125 is exposed on the inner surface of the first recess portion 130, and the source electrode 140 comes into direct contact with the exposed 2DEG 125, thereby reducing the contact resistance.

[0080] The first recess portion 132 is provided to reduce the contact resistance between the drain electrode 142 and the 2DEG 125. The 2DEG 125 is exposed on the inner surface of the first recess portion 132, and the drain electrode 142 comes into direct contact with the exposed 2DEG 125, thereby reducing the contact resistance.

[0081] The position of the bottom surface of each of the first recesses 130 and 132 is located below the interface between the channel layer 124 and the barrier layer 126. The difference in the z-axis direction between the bottom surface of each of the first recesses 130 and 132 and the interface between the channel layer 124 and the barrier layer 126 is 10 nm or less.

[0082] The second recess portion 136 is provided to passivate the nitride semiconductor layer 120. A bottom surface (contact surface 120b) of the second recess portion 136 is located below the uppermost surface 120a of the nitride semiconductor layer 120 in the active region 101. Specifically, by providing the second recess portion 136, the barrier layer 126 is removed in the inactive region 102. In the inactive region 102, the channel layer 124 is the uppermost layer of the nitride semiconductor layer 120. As a result, it is possible to prevent the 2DEG 125 from being generated in the channel layer 124, and the carrier density of the channel layer 124 in the inactive region 102 is reduced to 1×10 at room temperature. 15 cm -3The normal temperature is, for example, 25°C.

[0083] The source electrode 140 and the drain electrode 142 are provided at positions spaced apart from each other in a plan view with the gate electrode 144 sandwiched therebetween. The source electrode 140 and the drain electrode 142 are each electrically connected to the 2DEG 125. Specifically, the source electrode 140 is provided in the first recess portion 130 and in contact with the 2DEG 125. The drain electrode 142 is provided in the first recess portion 132 and in contact with the 2DEG 125.

[0084] Both the source electrode 140 and the drain electrode 142 are formed using a metal material that is ohmic-connected to an n-type nitride semiconductor. For example, the source electrode 140 and the drain electrode 142 are multilayer electrode films having a laminated structure of a Ti film having a thickness of 30 nm and an Al film having a thickness of 200 nm provided on the Ti film.

[0085] The thickness of the Ti film may be 2 nm or more and 40 nm or less, and the thickness of the Al film may be 100 nm or more and 200 nm or less. The source electrode 140 and the drain electrode 142 may be a single metal element selected from the group consisting of Ti, Ta, Hf, Zr, Ru, Al, Au, and W, or an alloy of a plurality of selected elements. The source electrode 140 and the drain electrode 142 may include a conductive metal nitride film such as TiN, WN, or TaN. The source electrode 140 and the drain electrode 142 may be formed in the same process, or may be formed in different processes using different materials.

[0086] The gate electrode 144 is provided between the source electrode 140 and the drain electrode 142 in a plan view. In the present embodiment, the gate electrode 144 is provided in contact with the top surface 120a of the nitride semiconductor layer 120.

[0087] The gate electrode 144 is formed using a metal material that is Schottky-connected to the nitride semiconductor layer 120. For example, the gate electrode 144 is a multi-layer electrode film having a laminated structure of a TiN film and an Al film provided on the TiN film. The TiN film and the Al film are the same as the barrier metal layer 152 and the low-resistance metal layer 154 of the capacitor 20, respectively. The gate electrode 144 may be formed using one selected from the group consisting of WN, TaN, HfN, Ni, Ti, Ta, W, Au, Pd, Pt, Hf, Ru, and Cu.

[0088] An insulating layer or a p-type nitride semiconductor layer may be provided between the gate electrode 144 and the top surface 120a of the nitride semiconductor layer 120. The insulating layer has a single layer or a multilayer structure of, for example, SiN, SiO2, SiON, Al2O3, or the like. The p-type nitride semiconductor layer is, for example, p-type GaN or AlGaN, or the like. When a p-type nitride semiconductor layer is provided, the gate electrode 144 may be in ohmic contact with the p-type nitride semiconductor layer.

[0089] Next, a description will be given of the capacitor 20. As shown in FIG 1A, the capacitor 20 includes a lower electrode 150, an insulating layer 160, and an upper electrode 170.

[0090] The lower electrode 150 is an example of a metal layer in contact with the nitride semiconductor layer 120 in the inactive region 102. The lower electrode 150 includes a coherent state or a metamorphic state with respect to the nitride semiconductor layer 120. The coherent state and the metamorphic state will be described later. In this embodiment, the lower electrode 150 includes a barrier metal layer 152 and a low resistance metal layer 154.

[0091] The barrier metal layer 152 is provided to suppress diffusion of a metal element (e.g., Cu) contained in the low-resistance metal layer 154 into the nitride semiconductor layer 120. The barrier metal layer 152 is in contact with the nitride semiconductor layer 120 in the inactive region 102. Specifically, the barrier metal layer 152 is in contact with a contact surface 120b which is the bottom surface of the second recess portion 136 and also a part of the surface of the channel layer 124.

[0092] The barrier metal layer 152 has a NaCl type structure composed of at least one element selected from the group consisting of Ti, Ta, W, and Hf, and at least one element selected from the group consisting of N and C. For example, the barrier metal layer 152 is a single layer film composed of one compound selected from the group consisting of TiN, TaN, WN, HfN, TiC, and TaC, but may be a multilayer film. The thickness of the barrier metal layer 152 is, for example, 5 nm to 200 nm, for example, 20 nm, but is not limited thereto.

[0093] The low-resistance metal layer 154 is provided above the barrier metal layer 152. Specifically, the low-resistance metal layer 154 is provided in contact with an upper surface of the barrier metal layer 152. The low-resistance metal layer 154 is a metal layer having a lower resistance than the barrier metal layer 152. By including the low-resistance metal layer 154 in the lower electrode 150, the parasitic resistance of the lower electrode 150 can be reduced.

[0094] The low-resistance metal layer 154 has a face-centered cubic (fcc) structure composed of at least one element selected from the group consisting of Al, Cu, Au, Ag, and Pt. The low-resistance metal layer 154 is, for example, a single-layer film composed of one element selected from the group consisting of Al, Cu, Au, Ag, and Pt, but may be a laminated film. The thickness of the low-resistance metal layer 154 is larger than the thickness of the barrier metal layer 152, and is, for example, 100 nm to 1000 nm, for example, 500 nm, but is not limited thereto.

[0095] The insulating layer 160 is provided between the lower electrode 150 and the upper electrode 170. The insulating layer 160 is formed using a film having a high dielectric constant and a high dielectric breakdown field. For example, the insulating layer 160 is a single-layer film made of one compound selected from the group consisting of SiN, AlN, HfN, HfO, and Ta2O5, but may be a laminated film. The thickness of the insulating layer 160 is not particularly limited and is determined based on the capacitance value, withstand voltage, etc. required for the capacitor 20.

[0096] The upper electrode 170 is provided above the insulating layer 160. The upper electrode 170 is a single layer film made of at least one element selected from the group consisting of Al, Cu, Au, Ag, and Pt, but may be a laminated film.

[0097] As described above, in the nitride semiconductor device 1 according to the present embodiment, the lower electrode 150 is provided in the inactive region 102, and therefore is less susceptible to the influence of carrier fluctuations during high frequency operation. Therefore, it is possible to realize the capacitor 20 having excellent high frequency characteristics.

[0098] Furthermore, the lower electrode 150 of the capacitor 20 includes a coherent state or a metamorphic state with respect to the nitride semiconductor layer 120. As a result, the crystallinity of the lower electrode 150 is improved, and the high-frequency characteristics of the capacitor 20 are improved. The coherent state and the metamorphic state will be described below.

[0099] The coherent state is a state in which the layer retains the crystalline information of the underlying layer by distorting the lattice of the layer. The metamorphic state is a state in which the layer as a whole retains the crystalline information of the underlying layer by introducing defects into the layer. That is, in both the coherent state and the metamorphic state, the layer (the lower electrode 150 (the barrier metal layer 152)) retains the crystalline information of the underlying layer (the nitride semiconductor layer 120 (the channel layer 124)).

[0100] The barrier metal layer 152 and the low resistance metal layer 154 are each in a coherent state or a metamorphic state with respect to the channel layer 124. In order to achieve a coherent state or a metamorphic state, it is required that the crystal structure and lattice constant satisfy certain conditions.

[0101] The crystal structure of the channel layer 124, which is the underlying layer, is a hexagonal close-packed (hcp) structure as shown in Fig. 2A. Fig. 2A is a diagram showing the crystal structure of the hexagonal close-packed (hcp) structure. Fig. 2B is a diagram showing the crystal structure of a face-centered cubic lattice (fcc) structure.

[0102] The crystal structure that is in a coherent state or metamorphic state with respect to the hcp structure is the fcc structure or the NaCl structure. In this embodiment, the barrier metal layer 152 has the NaCl structure, and the low resistance metal layer 154 has the fcc structure shown in FIG. 2B. The NaCl structure can be considered to be substantially the same as the fcc structure shown in FIG. 2B.

[0103] The (111) plane, which is one of the crystal planes of the barrier metal layer 152, is parallel to and in the same direction as the (0002) plane, which is one of the crystal planes of the channel layer 124. In addition, the (111) plane, which is one of the crystal planes of the low-resistance metal layer 154, is parallel to and in the same direction as the (0002) plane, which is one of the crystal planes of the channel layer 124. Both the barrier metal layer 152 and the low-resistance metal layer 154 are oriented only in the (111) plane.

[0104] Specifically, the barrier metal layer 152 and the low-resistance metal layer 154 are formed so that the six elements located at the vertices and midpoints of each side of the triangle (area shaded with dots) of the (111) plane shown in Fig. 2B correspond to the six elements shown in Fig. 2A. Note that in Fig. 2A, the six elements are represented by the (0001) plane instead of the (0002) plane. In this case, the lattice constants satisfy the following relationship.

[0105] The lattice constant of the barrier metal layer 152 is larger than the lattice constant of the low-resistance metal layer 154 and is equal to or smaller than √2 times the lattice constant of the a-axis of the nitride semiconductor layer 120 at the contact surface 120b with the lower electrode 150. That is, when the lattice constant of the a-axis of the channel layer 124 is "a1", the lattice constant of the barrier metal layer 152 is "a2", and the lattice constant of the low-resistance metal layer 154 is "a3", the following inequality (1) is satisfied.

[0106] (1) a1×√2≧a2>a3

[0107] Note that “√2” represents the square root of 2 (1.4142···).

[0108] In this way, by decreasing the lattice constant of the barrier metal layer 152 and the low-resistance metal layer 154 in this order with respect to √2 times the lattice constant of the a-axis of the nitride semiconductor layer 120 (channel layer 124), it is possible to suppress the occurrence of dislocations in the low-resistance metal layer 154. This makes it possible to reduce the resistance of the lower electrode 150.

[0109] Furthermore, the lattice constant a3 of the low-resistance metal layer 154 and the lattice constant a2 of the barrier metal layer 152 may be 90% or more of √2 times the lattice constant a1 of the a-axis at the contact surface 120b of the channel layer 124. That is, the lattice constants of each layer may further satisfy the following inequalities (2) and (3).

[0110] (2) a3≧a1×√2×0.9 (3) a2≧a1×√2×0.9

[0111] That is, the difference between the lattice constant of the channel layer 124 multiplied by √2 and the lattice constant of the barrier metal layer 152 or the low-resistance metal layer 154 is within ±10%. By satisfying such a relationship, the crystallinity of each of the barrier metal layer 152 and the low-resistance metal layer 154 is further increased. By reducing dislocations contained in the low-resistance metal layer 154, the resistance of the low-resistance metal layer 154 is further reduced. Furthermore, by reducing the resistance of the lower electrode 150, the loss caused by the parasitic resistance component can be reduced. Furthermore, since abnormal growth such as hillocks is suppressed, the reduction in coverage of the insulating layer 160 and the concentration of the electric field can be suppressed. Therefore, the reduction in the breakdown voltage of the capacitor 20 can be suppressed.

[0112] Furthermore, in this embodiment, since the barrier metal layer 152 is provided, the formation of mixed crystals between the low-resistance metal layer 154 and the channel layer 124 is suppressed. This suppresses the generation of carriers in the channel layer 124, making the capacitor 20 less susceptible to the effects of carrier fluctuations during operation. This improves the high-frequency characteristics of the capacitor 20.

[0113] [Nitride semiconductor device with resistor element] Next, a nitride semiconductor device including a resistor element as a passive element will be described with reference to FIG. 1B. FIG. 1B is a cross-sectional view of a nitride semiconductor device 2 including a resistor element 21 as a passive element. As shown in FIG. 1B, the nitride semiconductor device 2 includes a transistor 10 and a resistor element 21. The transistor 10 is the same as the transistor 10 included in the nitride semiconductor device 1 shown in FIG. 1A. The following description will focus on differences from the nitride semiconductor device 1, and descriptions of commonalities will be omitted or simplified.

[0114] The resistive element 21 shown in FIG. 1B includes a metal layer 155. The metal layer 155 is in contact with the nitride semiconductor layer 120 in the inactive region 102. The metal layer 155 includes a coherent state or a metamorphic state with respect to the nitride semiconductor layer 120. The metal layer 155 can be formed using, for example, the same material as the barrier metal layer 152. Alternatively, the metal layer 155 may be formed using the same material as the low resistance metal layer 154. By adjusting the thickness, material, line width, and the like of the metal layer 155, the resistive element 21 having a desired resistance value can be formed.

[0115] According to the nitride semiconductor device 2, the crystallinity of the metal layer 155 is improved, similar to the lower electrode 150 of the nitride semiconductor device 1. This improves the resistance of the metal layer 155 to electromigration. This suppresses breakage or short circuit of the resistance element 21, thereby improving the high frequency characteristics of the resistance element 21.

[0116] [Nitride semiconductor device with inductor] Next, a nitride semiconductor device including an inductor as a passive element will be described with reference to FIG. 1C. FIG. 1C is a cross-sectional view of a nitride semiconductor device 3 including an inductor 22 as a passive element. As shown in FIG. 1C, the nitride semiconductor device 3 includes a transistor 10 and the inductor 22. The transistor 10 is the same as the transistor 10 included in the nitride semiconductor device 1 shown in FIG. 1A. The following description will focus on differences from the nitride semiconductor device 1, and descriptions of commonalities will be omitted or simplified.

[0117] 1C includes a metal layer 156. The metal layer 156 contacts the nitride semiconductor layer 120 in the inactive region 102. The metal layer 156 includes a coherent state or a metamorphic state with respect to the nitride semiconductor layer 120. In the present embodiment, the metal layer 156 includes a barrier metal layer 152 and a low resistance metal layer 158.

[0118] The barrier metal layer 152 is the same as the barrier metal layer 152 included in the nitride semiconductor device 1 shown in FIG. 1A. The low-resistance metal layer 158 is substantially the same as the low-resistance metal layer 154 included in the nitride semiconductor device 1 shown in FIG. 1A, but has a different thickness. Specifically, the low-resistance metal layer 158 is thicker than the low-resistance metal layer 154. For example, the thickness and width of the low-resistance metal layer 158 are both 3 μm or more. This allows the metal layer 156 to have a lower resistance.

[0119] The inductor 22 extends at a certain length on the contact surface 120b of the inactive region 102. For example, the inductor 22 may be formed in a straight line or in a coil shape in a plan view.

[0120] According to the nitride semiconductor device 3, the crystallinity of the metal layer 156 is improved, similar to the lower electrode 150 of the nitride semiconductor device 1. Therefore, the crystallinity of the metal layer 156 is improved, and the parasitic resistance component of the inductor 22 can be reduced. Therefore, the loss caused by the parasitic resistance component can be reduced.

[0121] [Variations] Next, a description will be given of several modified examples of embodiment 1. In the modified examples shown below, the description will be centered on the differences from nitride semiconductor devices 1, 2, and 3 according to embodiment 1, and description of commonalities will be omitted or simplified.

[0122] <Variation 1> 3A is a cross-sectional view of a nitride semiconductor device 1A according to this modification including a capacitor 20 as a passive element. As shown in FIG. 3A, the nitride semiconductor device 1A differs from the nitride semiconductor device 1 in that a second recessed portion 136A is provided instead of the second recessed portion 136.

[0123] The second recessed portion 136A is provided to inactivate the nitride semiconductor layer 120. The bottom surface (contact surface 120b) of the second recessed portion 136A is located lower than the top surface 120a of the nitride semiconductor layer 120 in the active region 101. In this modification, the second recessed portion 136A does not penetrate the barrier layer 126. That is, the barrier layer 126 remains even in the inactive region 102 and is the top layer of the nitride semiconductor layer 120. The contact surface 120b, which is the bottom surface of the second recessed portion 136A, is the surface of the barrier layer 126. The lower electrode 150 of the capacitor 20 is in contact with the barrier layer 126 in the inactive region 102 at a position lower than the top surface 120a of the active region 101 (a position closer to the substrate 110).

[0124] In this modification, by providing the second recess portion 136A, the thickness of the barrier layer 126 in the inactive region 102 is smaller than the thickness of the barrier layer 126 in the active region 101. By reducing the thickness of the barrier layer 126 in the inactive region 102, piezoelectric polarization is suppressed, and therefore the 2DEG 125 is not generated. As a result, the carrier density of the channel layer 124 in the inactive region 102 is reduced to 1×10 at room temperature, as in the first embodiment. 15 cm -3 Therefore, similarly to the first embodiment, the high frequency characteristics of the nitride semiconductor device 1A can be improved.

[0125] The same applies to the case where a resistor element 21 or an inductor 22 is provided instead of the capacitor 20. FIG. 3B is a cross-sectional view of a nitride semiconductor device 2A according to this modification that includes a resistor element 21 as a passive element. FIG. 3C is a cross-sectional view of a nitride semiconductor device 3A according to this modification that includes an inductor 22 as a passive element. As shown in FIGS. 3B and 3C, the nitride semiconductor devices 2A and 3A are different from the nitride semiconductor devices 2 and 3, respectively, in that a second recessed portion 136A is provided instead of the second recessed portion 136. Both the metal layers 155 and 156 are in contact with the barrier layer 126 in the inactive region 102 at a position lower than the uppermost surface 120a of the active region 101 (at a position closer to the substrate 110). The nitride semiconductor devices 2A and 3A that include the resistor element 21 or the inductor 22 can also improve high-frequency characteristics in the same manner as in the first embodiment.

[0126] <Variation 2> 4A is a cross-sectional view of a nitride semiconductor device 1B according to this modification including a capacitor 20 as a passive element. As shown in FIG. 4A, the nitride semiconductor device 1B differs from the nitride semiconductor device 1 in that a second recess portion 136B is provided instead of the second recess portion 136.

[0127] The second recessed portion 136B is provided to inactivate the nitride semiconductor layer 120. The bottom surface (contact surface 120b) of the second recessed portion 136B is located below the top surface 120a of the nitride semiconductor layer 120 in the active region 101. In this modification, the second recessed portion 136B penetrates the barrier layer 126 and the channel layer 124 and reaches the buffer layer 122. The contact surface 120b, which is the bottom surface of the second recessed portion 136B, is the surface of the buffer layer 122. The barrier layer 126 and the channel layer 124 are not provided in the inactive region 102. In the inactive region 102, the buffer layer 122 is the top layer of the nitride semiconductor layer 120. The lower electrode 150 is in contact with the buffer layer 122 in the inactive region 102 at a position lower than the top surface 120a of the active region 101 (a position closer to the substrate 110).

[0128] The buffer layer 122 is an undoped nitride semiconductor layer, and has a carrier density of 1×10 15 cm -3 Therefore, similarly to the first embodiment, the high frequency characteristics of the nitride semiconductor device 1B can be improved.

[0129] The same applies to the case where a resistive element 21 or an inductor 22 is provided instead of the capacitor 20. FIG. 4B is a cross-sectional view of a nitride semiconductor device 2B according to this modification that includes a resistive element 21 as a passive element. FIG. 4C is a cross-sectional view of a nitride semiconductor device 3B according to this modification that includes an inductor 22 as a passive element. As shown in FIGS. 4B and 4C, the nitride semiconductor devices 2B and 3B are different from the nitride semiconductor devices 2 and 3, respectively, in that a second recessed portion 136B is provided instead of the second recessed portion 136. Both the metal layers 155 and 156 are in contact with the buffer layer 122 in the inactive region 102 at a position lower than the uppermost surface 120a of the active region 101 (a position closer to the substrate 110). The nitride semiconductor devices 2B and 3B that include the resistive element 21 or the inductor 22 can also improve the high-frequency characteristics in the same manner as in the first embodiment.

[0130] The buffer layer 122 may include an impurity region doped with C or Fe. The lower electrode 150 may be in contact with the impurity region. The impurity region doped with C or Fe has a high resistance. This suppresses operational variations, thereby improving the high frequency characteristics of the capacitor 20. The doping with C or Fe is performed during crystal growth. This allows the crystal structure to be maintained, unlike the case of ion implantation.

[0131] In this modification, a part of the buffer layer 122 is also removed in the inactive region 102, but the buffer layer 122 does not have to be removed. That is, the contact surface 120b in the inactive region 102 may be at the same height as the interface between the channel layer 124 and the buffer layer 122 in the active region 101.

[0132] <Variation 3> Fig. 5A is a cross-sectional view of a nitride semiconductor device 1C according to this modification including a capacitor 20C as a passive element. As shown in Fig. 5A, the nitride semiconductor device 1C differs from the nitride semiconductor device 1 in that it includes a capacitor 20C instead of the capacitor 20. Compared to the capacitor 20, the capacitor 20C includes a lower electrode 150C instead of the lower electrode 150.

[0133] The lower electrode 150C includes a metal underlayer 159 provided between the barrier metal layer 152 and the nitride semiconductor layer 120. The metal underlayer 159 has a hexagonal close-packed (hcp) structure composed of at least one element selected from the group consisting of Ti, Ta, W, and Hf. The thickness of the metal underlayer 159 is, for example, 2 nm to 50 nm, for example, 10 nm, but is not particularly limited.

[0134] √2 times the lattice constant of the a-axis of the metal underlayer 159 is equal to or greater than the lattice constant of the barrier metal layer 152 and is equal to or less than √2 times the lattice constant of the a-axis of the nitride semiconductor layer 120 at the contact surface 120b with the lower electrode 150C. For example, when the lattice constant of the a-axis of the metal underlayer 159 is "a", the following inequality (4) is satisfied.

[0135] (4) a1×√2≧a4×√2≧a2

[0136] By providing the metal underlayer 159, it is possible to improve the adhesion between the barrier metal layer 152 and the nitride semiconductor layer 120 (channel layer 124) while maintaining the crystallinity of the lower electrode 150C.

[0137] The same applies to the case where a resistive element or an inductor is provided instead of the capacitor 20. Fig. 5B is a cross-sectional view of a nitride semiconductor device 2C according to this modification including a resistive element 21C as a passive element. Fig. 5C is a cross-sectional view of a nitride semiconductor device 3C according to this modification including an inductor 22C as a passive element.

[0138] 5B, a resistor element 21C includes a metal layer 155C. The metal layer 155C includes a metal base layer 159 provided between a barrier metal layer 152 and a channel layer 124. The barrier metal layer 152 is the same as the metal layer 155 included in the nitride semiconductor device 2 according to the first embodiment.

[0139] 5C, an inductor 22C includes a metal layer 156C. The metal layer 156C includes a metal base layer 159 provided between the barrier metal layer 152 and the channel layer .

[0140] Similarly to the nitride semiconductor device 1C, the nitride semiconductor devices 2C and 3C including the resistive element 21C or the inductor 22C can also improve the adhesion of the metal layers 155C and 156C while maintaining the crystallinity of the metal layers 155C and 156C.

[0141] [Manufacturing method] Next, a manufacturing method of the nitride semiconductor device 1 according to the first embodiment will be described.

[0142] Fig. 6 is a flowchart showing a first example of a method for manufacturing the nitride semiconductor device 1 according to the present embodiment. Figs. 7A to 7F are cross-sectional views illustrating each step included in the first example of the method for manufacturing the nitride semiconductor device 1 according to the present embodiment.

[0143] As shown in Figures 6 and 7A, first, a nitride semiconductor layer 120 is formed on a substrate 110 (S10). Specifically, a buffer layer 122, a channel layer 124, and a barrier layer 126 are formed in this order. Each layer is formed by growing a nitride semiconductor crystal by epitaxial growth using a MOCVD (Metal-Organic Chemical Vapor Deposition) method or the like. When forming the buffer layer 122, it may be doped with an impurity such as C or Fe to increase resistance.

[0144] 7B, a first recess portion 130 for the source electrode 140 and a first recess portion 132 for the drain electrode 142 are formed (S11). For example, a resist pattern of a predetermined shape is formed by photolithography, and the barrier layer 126 and a part of the channel layer 124 within a predetermined range are removed by dry etching using the resist pattern, thereby forming the first recess portions 130 and 132.

[0145] 7C, the source electrode 140 and the drain electrode 142 are formed in the first recessed portions 130 and 132, respectively (S12). For example, a metal film is formed by EB (Electron Beam) deposition or sputtering, etc., so as to cover at least the first recessed portions 130 and 132, and the formed metal film is patterned by etching to form the source electrode 140 and the drain electrode 142.

[0146] 7D, the gate electrode 144 is formed on the nitride semiconductor layer 120 (S13). For example, a metal film is formed by EB deposition or sputtering so as to cover at least the region between the source electrode 140 and the drain electrode 142, and the formed metal film is patterned by etching to form the gate electrode 144. Note that the step of forming the gate electrode 144 may be performed before the step of forming the source electrode 140 and the drain electrode 142.

[0147] Next, as shown in FIG. 7E, a second recessed portion 136 for inactivation is formed (S14). For example, a resist pattern of a predetermined shape is formed by photolithography, and the barrier layer 126 and part of the channel layer 124 in the inactive region 102 are removed by dry etching or the like using the resist pattern, thereby forming the second recessed portion 136. In the inactive region 102, by removing the barrier layer 126, the 2DEG 125 in the channel layer 124 is no longer generated, and the carrier density at room temperature is reduced to 1×10 15 cm -3 It can be made smaller.

[0148] Next, as shown in FIG. 7F, a metal layer (specifically, the lower electrode 150) that contacts the nitride semiconductor layer 120 in the inactive region 102 is formed (S15). Specifically, a barrier metal layer 152 and a low-resistance metal layer 154 are formed in this order on the contact surface 120b. For example, a metal film is formed by EB deposition or sputtering or the like so as to cover at least the contact surface 120b in the inactive region 102, and the formed metal film is patterned by etching to form the lower electrode 150. At this time, the lower electrode 150 is formed so as to be in a coherent state or a metamorphic state with respect to the nitride semiconductor layer 120 (channel layer 124). Specifically, the growth rate of the electrode material is slowed down. For example, in the case of sputtering, the power to be supplied is reduced, and in the case of EB deposition, the temperature is lowered, or the distance between the target and the material is increased. This allows the growth rate of the electrode material to be slowed down, and allows the lower electrode 150 to be in a coherent state or a metamorphic state with respect to the nitride semiconductor layer 120 (channel layer 124) to be formed.

[0149] Next, in the inactive region 102, an insulating layer 160 is formed on the metal layer (lower electrode 150), and an upper electrode 170 is formed on the formed insulating layer 160 (S16). The insulating layer 160 is formed, for example, by forming an insulating film so as to cover at least the lower electrode 150 by a plasma CVD (Chemical Vapor Depositino) method or the like, and then removing a part of the formed insulating film by etching. The upper electrode 170 is formed by forming a metal film so as to cover at least the insulating layer 160 by EB deposition or sputtering, and patterning the formed metal film by etching.

[0150] Through the above steps, the nitride semiconductor device 1 including the capacitor 20 shown in FIG. 1A can be manufactured.

[0151] Note that, by omitting the step (S16) of forming the insulating layer 160 and the upper electrode 170, it is possible to manufacture a nitride semiconductor device 3 including the inductor 22. Also, by omitting the step (S16) of forming the insulating layer 160 and the upper electrode 170, and further omitting the formation of the low-resistance metal layer 154 in the step (S15) of forming the metal layer, it is possible to manufacture a nitride semiconductor device 2 including a resistance element 21.

[0152] The above-mentioned methods for manufacturing the nitride semiconductor devices 1, 2 and 3 are merely examples, and the order of the steps, the contents of the steps, etc. may be changed.

[0153] For example, in the step (S14) of forming the second recessed portion 136, only a part of the barrier layer 126 in the inactive region 102 may be removed, leaving the barrier layer 126 of a predetermined thickness. This allows the nitride semiconductor device 1A, 2A or 3A according to Modification 1 to be formed. Alternatively, in the step of forming the second recessed portion 136, the channel layer 124 in the inactive region 102 may be completely removed. Also, a part of the buffer layer 122 in the inactive region 102 may be removed. This allows the nitride semiconductor device 1B, 2B or 3B according to Modification 2 to be formed.

[0154] The second recessed portion 136 may be formed simultaneously with the formation of an alignment mark for positioning. The alignment mark is usually formed between the step of forming the nitride semiconductor layer 120 (S10) and the step of forming the first recessed portions 130 and 132 (S11).

[0155] Furthermore, in the step (S15) of forming the metal layer (lower electrode 150), a metal underlayer 159 may be formed before forming the barrier metal layer 152. The metal underlayer 159 is formed by forming a metal film by, for example, EB deposition or sputtering so as to cover at least the contact surface 120b in the inactive region 102, and patterning the formed metal film by etching. In this way, the nitride semiconductor device 1C, 2C or 3C according to the third modification can be formed.

[0156] Furthermore, the step (S11) of forming the first recessed portions 130 and 132 and the step (S14) of forming the second recessed portion 136 may be performed simultaneously. Fig. 8 is a flowchart showing a second example of a method for manufacturing the nitride semiconductor device 1 according to the present embodiment. Figs. 9A and 9B are cross-sectional views for explaining each step included in the second example of the method for manufacturing the nitride semiconductor device 1 according to the present embodiment.

[0157] 8 and 9A, after the nitride semiconductor layer 120 is formed, a first recess 130 for the source electrode 140, a first recess 132 for the drain electrode 142, and a second recess 136 for passivation are simultaneously formed (S21). For example, a resist pattern of a predetermined shape is formed by photolithography, and a part of each of the barrier layer 126 and the channel layer 124 in a predetermined range in the active region 101 and in the inactive region 102 is removed by dry etching or the like using the resist pattern, thereby simultaneously forming the first recesses 130 and 132 and the second recess 136. Since they are formed simultaneously, the bottom surfaces of the first recesses 130 and 132 and the bottom surface (contact surface 120b) of the second recess 136 are located at the same height.

[0158] Thereafter, as shown in Fig. 9B, a source electrode 140 and a drain electrode 142 are formed in the first recessed portions 130 and 132, respectively (S12). The subsequent processing is the same as that of the first example shown in Fig. 6, except that the process of forming the second recessed portion 136 (S14) is omitted, as shown in Fig. 8.

[0159] By simultaneously forming the first recessed portions 130 and 132 and the second recessed portion 136, the manufacturing process can be simplified, thereby reducing the possibility of manufacturing errors and increasing the yield.

[0160] Furthermore, the step (S15) of forming the metal layer (lower electrode 150) and the step (S13) of forming the gate electrode 144 may be performed simultaneously. Fig. 10 is a flowchart showing a third example of the manufacturing method of the nitride semiconductor device 1 according to the present embodiment.

[0161] As shown in FIG. 10, the process from the formation of the nitride semiconductor layer 120 (S10) to the formation of the source electrode 140 and the drain electrode 142 (S12) is the same as the second example of the manufacturing method shown in FIG. 8. After the source electrode 140 and the drain electrode 142 are formed, the gate electrode 144 and the metal layer (lower electrode 150) are simultaneously formed (S33). The lower electrode 150 is formed at a slow growth rate to make it coherent or metamorphic with respect to the nitride semiconductor layer 120 (channel layer 124). The gate electrode 144 is also formed at the same rate. By simultaneously forming the gate electrode 144 and the lower electrode 150, the configuration shown in FIG. 7F is obtained. Thereafter, the insulating layer 160 and the upper electrode 170 are formed in order, whereby the nitride semiconductor device 1 shown in FIG. 1A can be manufactured.

[0162] By simultaneously forming the gate electrode 144 and the metal layer (lower electrode 150), the manufacturing process can be simplified, making it possible to reduce the possibility of manufacturing errors and the like, and to increase the yield.

[0163] (Embodiment 2) Next, a nitride semiconductor device according to embodiment 2 will be described. The main difference between embodiment 2 and embodiment 1 is that a passivation film that protects the surface of the nitride semiconductor layer is provided. The following description will focus on the differences from embodiment 1, and the description of commonalities will be omitted or simplified.

[0164] Fig. 11 is a cross-sectional view of a nitride semiconductor device 201 according to the present embodiment. As shown in Fig. 11, the nitride semiconductor device 201 differs from the nitride semiconductor device 1 according to the first embodiment in that it includes a capacitor 220 instead of the capacitor 20 and in that it includes passivation films 180 and 182.

[0165] The passivation film 180 is provided to protect the surface of the nitride semiconductor layer 120. Specifically, the passivation film 180 covers the top surface 120a of the nitride semiconductor layer 120 in the active region 101. In the passivation film 180, openings for providing the source electrode 140, the drain electrode 142, and the gate electrode 144 are formed in the active region 101. The openings for the source electrode 140 and the drain electrode 142 are provided at positions overlapping the first recesses 130 and 132 in a plan view. In addition, the top surface 120a of the nitride semiconductor layer 120 is exposed in the opening for the gate electrode 144, and the gate electrode 144 can be provided in contact with the top surface 120a. Note that the opening for the gate electrode 144 does not need to be provided, and the gate electrode 144 may be provided on the passivation film 180. In this case, the passivation film 180 can be used as a gate insulating film.

[0166] The passivation film 182 is provided to protect the surface of the transistor 10. Specifically, the passivation film 182 covers the source electrode 140, the drain electrode 142, and the gate electrode 144, as well as the passivation film 180, in the active region 101. Furthermore, the passivation film 182 covers the inner surface of the second recess portion 136 in the inactive region 102. The passivation film 182 is provided with an opening 183 for exposing the upper surface (contact surface 120b) of the nitride semiconductor layer 120 (channel layer 124) in the inactive region 102.

[0167] The passivation films 180 and 182 are each formed using an insulating material. For example, the passivation films 180 and 182 are each a single layer film or a laminated film of SiN, SiO2, SiC, etc., but are not limited thereto. By providing the passivation films 180 and 182, it is possible to improve the insulation between the electrodes and between the electrode and the metal layer (lower electrode 150), and to suppress leakage current.

[0168] In this embodiment, the capacitor 220 includes a lower electrode 250, an insulating layer 260, and an upper electrode 270. The lower electrode 250 includes a barrier metal layer 252 and a low-resistance metal layer 254. The barrier metal layer 252, the low-resistance metal layer 254, the insulating layer 260, and the upper electrode 270 correspond to the barrier metal layer 152, the low-resistance metal layer 154, the insulating layer 160, and the upper electrode 170 according to the first embodiment, respectively, and are different in shape and position.

[0169] The lower electrode 250 contacts the channel layer 124 exposed in the opening 183 provided in the passivation film 182. A part of the lower electrode 250 (barrier metal layer 252) is provided on the upper surface of the passivation film 182. The length of the lower electrode 250 in the x-axis direction is longer than the length of the opening 183 in the x-axis direction. The part of the lower electrode 250 that overlaps with the passivation film 182 in a planar view is neither in a coherent state nor in a metamorphic state. The lower electrode 250 according to this embodiment includes a coherent state or a metamorphic state in a range that overlaps with the opening 183 of the passivation film 182 in a planar view.

[0170] The upper electrode 270 is smaller than the opening 183 in a plan view. In a plan view, the entire upper electrode 270 is provided within the opening 183. That is, the upper electrode 270 is provided at a position overlapping with a portion of the lower electrode 250 that is in a coherent state or a metamorphic state in a plan view. That is, the upper electrode 270 is provided at a position facing a portion of the lower electrode 250 that has high crystallinity and low resistance, and functions as the capacitor 220. Since abnormal growth such as hillocks is suppressed at a position of the lower electrode 250 that overlaps with the opening 183 in a plan view, it is possible to suppress a decrease in coverage of the insulating layer 260 and electric field concentration. This makes it possible to suppress a decrease in the breakdown voltage of the capacitor 220.

[0171] In this manner, in the nitride semiconductor device 201 according to the present embodiment, it is possible to improve reliability by protecting the transistor 10 while suppressing degradation in the high frequency characteristics of the capacitor 220. That is, according to the present embodiment, it is possible to realize a highly reliable nitride semiconductor device 201 having excellent high frequency characteristics.

[0172] The passivation film 182 can also be used as the insulating layer 260 of the capacitor 220. Fig. 12 is a cross-sectional view of a nitride semiconductor device 201A according to a modification of this embodiment.

[0173] 12, the nitride semiconductor device 201A differs from the nitride semiconductor device 201 according to the second embodiment in that it includes a passivation film 282 and a capacitor 220A instead of the passivation film 182 and the capacitor 220, and in that it is provided with an element isolation region 190. Moreover, in the inactive region 102, a second recessed portion 236 is provided instead of the second recessed portion 136.

[0174] The capacitor 220A includes a lower electrode 251, a passivation film 282, and an upper electrode 270. A part of the passivation film 282 is provided between the lower electrode 251 and the upper electrode 270.

[0175] The lower electrode 251 corresponds to the lower electrode 250, and is different in that it is provided so as to fill the second recessed portion 236. Although not shown, the lower electrode 251 includes a laminated structure of a barrier metal layer and a low-resistance metal layer. The lower electrode 251 contacts the channel layer 124 at the contact surface 120b which is the bottom surface of the second recessed portion 236. As a result, the lower electrode 251 includes a coherent state or a metamorphic state in a range overlapping the bottom surface (contact surface 120b) of the second recessed portion 236 in a plan view.

[0176] 12, the lower electrode 251 also contacts the inner wall surface of the second recess portion 236. Specifically, the lower electrode 251 also contacts the barrier layer 126, and contacts the 2DEG 125 generated in the vicinity of the interface between the barrier layer 126 and the channel layer 124. For this reason, an element isolation region 190 is provided to cut off electrical connection between the lower electrode 251 and the channel of the transistor 10.

[0177] The element isolation region 190 is a region where an impurity such as C or Fe is added to increase the resistance of the nitride semiconductor. The element isolation region 190 is provided at least in the channel layer 124 so as to block the 2DEG 125. For example, the element isolation region 190 is provided by ion implantation so as to be continuous from the outermost surface of the barrier layer 126 to the channel layer 124 and the buffer layer 122. In this modification, the inactive region 102 also includes the element isolation region 190. In other words, the inactive region 102 is regarded as a range that is separated by the element isolation region 190 from the 2DEG 125 of the active region 101 in which the transistor 10 is provided.

[0178] Since the element isolation region 190 is formed by ion implantation, the crystal structure is broken. Therefore, even if the lower electrode 251 is formed on the element isolation region 190, the lower electrode 251 does not enter a coherent state or a metamorphic state with respect to the nitride semiconductor layer 120. In this modification, the second recess 236 is provided to expose a part of the channel layer 124, and the lower electrode 251 is provided on the contact surface 120b, which is the exposed surface of the channel layer 124. This can increase the crystallinity of the lower electrode 251, realize low resistance, and suppress abnormal growth such as hillocks.

[0179] In this modification, the passivation film 282 functions as an insulating layer for the capacitor 220A. This simplifies the manufacturing process compared to forming an insulating layer dedicated to the capacitor 220A. This reduces the possibility of manufacturing errors and increases the yield.

[0180] In the second embodiment and the modification, the nitride semiconductor devices 201 and 201A each include a capacitor as a passive element, but may include a resistive element or an inductor as in the first embodiment. In addition, the modifications applied to the first embodiment can also be applied to the nitride semiconductor devices 201 and 201A.

[0181] (Other embodiments) Although the nitride semiconductor device according to one or more aspects has been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as it does not deviate from the gist of the present disclosure, various modifications conceivable by a person skilled in the art to the present embodiment and forms constructed by combining components in different embodiments are also included within the scope of the present disclosure.

[0182] Also, for example, a plurality of passive elements may be provided in the inactive region 102. For example, a plurality of at least one element selected from the group consisting of a capacitor 20, a resistive element 21, and an inductor 22 may be provided in the inactive region 102. The plurality of passive elements may be electrically connected to each other or may be electrically separated from each other. Similarly, a plurality of active elements may be provided in the active region 101.

[0183] Also, for example, the first recesses 130 and 132 may not be provided, and the source electrode 140 and the drain electrode 142 may not be provided on the upper surface of the barrier layer 126. That is, the source electrode 140 and the drain electrode 142 may not be in contact with the channel layer 124 and the 2DEG 125.

[0184] Also, for example, the nitride semiconductor layer 120 may not include the channel layer 124 and the barrier layer 126. The nitride semiconductor layer 120 may be a nitride semiconductor layer made of GaN, InGaN, or the like to which n-type impurities such as Si are added. In other words, the transistor 10 does not have to be a HEMT, and may be another FET such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0185] Furthermore, for example, a metal layer that is in a coherent state or a metamorphic state with respect to the nitride semiconductor layer 120 may be formed in the same process as the source electrode 140 or the drain electrode 142 .

[0186] Furthermore, each of the above embodiments can be modified, substituted, added, omitted, and the like in various ways within the scope of the claims or their equivalents. [Industrial Applicability]

[0187] A nitride semiconductor device according to the present disclosure can be used, for example, in a power amplifier for high output or high frequency applications, a wireless communication base station or terminal device in which the power amplifier is used, or a wireless power supply device that transmits power using microwaves. [Explanation of symbols]

[0188] 1, 1A, 1B, 1C, 2, 2A, 2B, 2C, 3, 3A, 3B, 3C, 201, 201A Nitride semiconductor device 10. Transistor 20, 20C, 220, 220A capacitors 21, 21C Resistance element 22, 22C inductor 101 Active region 102 Inactive area 110 Substrate 120 Nitride semiconductor layer 120a Top surface 120b Contact surface 122 Buffer Layer 124 Channel Layer 125 2DEG 126 Barrier Layer 130, 132 First recess 136, 136A, 136B, 236 Second recess 140 Source Electrode 142 Drain electrode 144 Gate electrode 150, 150C, 250, 251 Lower electrode 152, 252 Barrier metal layer 154, 158, 254 Low resistance metal layer 155, 155C, 156, 156C metal layer 159 Metal base layer 160, 260 Insulation layer 170, 270 upper electrode 180, 182, 282 Passivation film 183 Aperture 190 Element isolation region

Claims

1. A nitride semiconductor device including an active element and a passive element, a nitride semiconductor layer divided into an active region and an inactive region in a plan view; a metal layer in contact with the nitride semiconductor layer in the inactive region; the active element is provided in the active region, the passive element is provided in the inactive region, The metal layer includes a coherent state or a metamorphic state with respect to the nitride semiconductor layer. Nitride semiconductor devices.

2. the nitride semiconductor layer includes a channel layer and a barrier layer provided above the channel layer, the active element includes a two-dimensional electron gas generated in the vicinity of an interface between the channel layer and the barrier layer; The nitride semiconductor device according to claim 1 .

3. In the active region, the carrier density of the channel layer is 1×10 １５ cm －３ That's all. The nitride semiconductor device according to claim 2 .

4. the nitride semiconductor layer has a laminated structure made up of a plurality of layers, In the inactive region, the carrier density of the uppermost layer of the nitride semiconductor layer is 1×10 １５ cm －３ Less than The nitride semiconductor device according to any one of claims 1 to 3.

5. a contact surface between the nitride semiconductor layer and the metal layer in the inactive region is located lower than a top surface of the nitride semiconductor layer in the active region. The nitride semiconductor device according to any one of claims 1 to 3.

6. the nitride semiconductor layer further includes a buffer layer provided below the channel layer, the metal layer contacts the buffer layer in the inactive region; The nitride semiconductor device according to claim 2 or 3.

7. the nitride semiconductor layer includes an impurity region doped with C or Fe, The metal layer contacts the impurity region in the inactive region. The nitride semiconductor device according to any one of claims 1 to 3.

8. The metal layer is A barrier metal layer; a low-resistance metal layer provided above the barrier metal layer and having a resistance lower than that of the barrier metal layer; The nitride semiconductor device according to any one of claims 1 to 3.

9. the passive element is a resistive element including the metal layer; The nitride semiconductor device according to any one of claims 1 to 3.

10. the passive element is a capacitor including the metal layer as a lower electrode; The nitride semiconductor device according to any one of claims 1 to 3.

11. the passive element is an inductor including the metal layer; The nitride semiconductor device according to any one of claims 1 to 3.

12. a lattice constant of the barrier metal layer is larger than a lattice constant of the low-resistance metal layer and is equal to or smaller than √2 times the lattice constant of the a-axis of the nitride semiconductor layer at a contact surface with the metal layer; The nitride semiconductor device according to claim 8 .

13. the lattice constant of each of the low-resistance metal layer and the barrier metal layer is 90% or more of the √2 times the lattice constant of the a-axis of the nitride semiconductor layer at a contact surface with the metal layer; The nitride semiconductor device according to claim 12.

14. the low-resistance metal layer has a face-centered cubic lattice structure composed of at least one element selected from the group consisting of Al, Cu, Au, Ag, and Pt; The nitride semiconductor device according to claim 8 .

15. the barrier metal layer has a NaCl type structure composed of at least one element selected from the group consisting of Ti, Ta, W, and Hf, and at least one element of N and C; The nitride semiconductor device according to claim 8 .

16. the metal layer further includes a layer having a hexagonal close-packed structure and composed of at least one element selected from the group consisting of Ti, Ta, W, and Hf, the layer being provided between the barrier metal layer and the nitride semiconductor layer; The nitride semiconductor device according to claim 8 .

17. the active element includes a gate electrode, a source electrode, and a drain electrode; At least one of the gate electrode, the source electrode, and the drain electrode comprises the same material as at least a portion of the metal layer. The nitride semiconductor device according to any one of claims 1 to 3.

18. A method for manufacturing a nitride semiconductor device including an active element and a passive element, comprising the steps of: forming a nitride semiconductor layer that is divided into an active region and an inactive region in a plan view; forming a metal layer in contact with the nitride semiconductor layer in the inactive region; the active element is provided in the active region, the passive element is provided in the inactive region, The metal layer includes a coherent state or a metamorphic state with respect to the nitride semiconductor layer. A method for manufacturing a nitride semiconductor device.

19. forming a first recess portion in the nitride semiconductor layer; forming a source electrode and a drain electrode of the active device in the first recess; forming a gate electrode of the active element on the nitride semiconductor layer; forming a second recess portion in the nitride semiconductor layer before forming the metal layer; In the step of forming the metal layer, the metal layer is formed on a bottom surface of the second recessed portion. The method for manufacturing a nitride semiconductor device according to claim 18.

20. The step of forming the first recessed portion and the step of forming the second recessed portion are performed simultaneously. The method for manufacturing a nitride semiconductor device according to claim 19.

21. the step of forming the metal layer and the step of forming the gate electrode are performed simultaneously. The method for manufacturing a nitride semiconductor device according to claim 19 or 20.

22. the passive element is a capacitor including the metal layer as a lower electrode, The method for manufacturing a nitride semiconductor device further comprises: forming an insulating layer on the metal layer; forming an upper electrode on the insulating layer. The method for manufacturing a nitride semiconductor device according to claim 21 .

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