Method of manufacturing a semiconductor device

Abstract

The semiconductor device disclosed herein comprises a circuit board (2), a metal particle sintered body (4) formed on the circuit board and having a mesh-like structure in which metal particles with a melting point of 300°C or more are bonded together, and a bonding layer (3) having a melting point of 300°C or more, the bonding layer including an intermetallic compound region (5) having a melting point of 300°C or more formed of a low-melting point metal with a melting point of 100°C or more and 300°C or less and a metal of the same element as the metal particles, the volume ratio of the voids (6) inside the bonding layer being less than 20% and the volume ratio of the intermetallic compound region being 10% or less, and a semiconductor element (1) formed on the bonding layer.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] In the field of power semiconductors, there is a demand for technology to improve the joint reliability of semiconductor devices. In particular, there is a strong demand for improving the reliability of the joint between a semiconductor element and a circuit board, which have a large difference in thermal expansion coefficient. Conventionally, semiconductor elements have often been made from silicon (Si), and their operating temperatures have been 100°C to 125°C. On the other hand, from the viewpoint of energy conservation, devices based on silicon carbide (SiC) and gallium nitride (GaN) have come to be used as next-generation devices. From the viewpoint of reducing power loss, the operating temperature of these devices is set to 175°C or higher, and it is said that it will reach 250°C in the future.

[0003] Therefore, as a bonding material for next-generation devices, a bonding material that is a mixture of nano- or micro-sized metal particles, called sintered metal or metal paste, and an organic solvent is attracting attention (for example, Patent Document 1). Also, a bonding structure is known in which a metal foam body is sandwiched between materials to be bonded from both sides, brought into contact with each other, and heat-treated, and a low-melting-point metal film, such as a Sn film, that covers the materials to be bonded is melted, and solid-liquid diffusion is performed on the Cu metal foam body to form an alloy layer of an intermetallic compound (for example, Patent Document 2). In this bonding, an example shows that a heat treatment (230°C to 400°C) is performed while applying pressure to the contact surface between the materials to be bonded and the metal foam body. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-054358 A [Patent Document 2] JP 2014-097529 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, when sintering is performed using the sinterable metal shown in Patent Document 1, the solvent evaporates and the metal particles bond together to form a porous bonding layer, but since many gaps are formed between the sintered metal particles, the adhesion between the bonding layer and the bonded parts may not be sufficiently high. In addition, the formation of many gaps in the bonding layer reduces the thermal conductivity of the bonding layer, which may cause thermal runaway during actual operation of the semiconductor element and cause early failure due to crack propagation. In addition, in Patent Document 2, a low-melting point metal film is melted and joined to the joined members via a metal foam, so adhesion to the joined members is ensured. However, because a pre-formed metal foam body is used, adhesion may vary depending on the location if the parallelism with the joined members differs, and cracks may occur in areas with poor adhesion. [Means for solving the problem]

[0007] In addition, the method for manufacturing a semiconductor device according to the present disclosure further comprises: forming a metal film having a melting point of 100° C. or more and 300° C. or less on a first surface of a semiconductor element. Made of low melting point metal A first step of forming a low melting point metal layer and a second step of applying a paste containing metal particles having a melting point of 300° C. or more and a solvent to a second surface of the circuit board. do a second step of forming a coating layer on the second surface; a third step of pressing and pressurizing the semiconductor element while the coating layer and the low-melting point metal layer are in contact with each other; and heating the circuit board with the semiconductor element pressed in in an inert gas at a temperature equal to or higher than the melting point of the low-melting point metal layer and lower than the melting point of the metal particles at normal pressure, The intermetallic compound region is formed of the low melting point metal and a metal of the same element as the metal particles, and the intermetallic compound region is formed of voids. The volume ratio of voids is less than 20%. The volume ratio of the intermetallic compound region is 10% or less. and a fourth step of forming a bonding layer. Effect of the Invention

[0008] According to the present disclosure, when a semiconductor element is bonded to a circuit board, it is possible to prevent excessive voids from being formed in the bonding layer, and it is possible to provide a highly reliable semiconductor device in which the circuit board and the semiconductor element are bonded with a highly heat-resistant and highly reliable bonding layer. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Diagram 2] 1A to 1C are schematic cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment. [Diagram 3] 1A to 1C are schematic cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 1A to 1C are schematic cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment. [Diagram 5] 13 shows SAT image evaluations before and after a temperature cycle test of a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Embodiment Fig. 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to a first embodiment of the present disclosure. As shown in Fig. 1, the semiconductor device according to the present embodiment is formed by bonding a semiconductor element 1 and a circuit board 2 with a bonding layer 3. The bonding layer 3 is composed of a metal particle sintered body 4 in which metal particles are bonded together, and an intermetallic compound region 5 and voids 6 between the metal particle sintered bodies 4, and has a melting point of 300°C or higher.

[0011] The metal particle sintered body 4 has a mesh-like structure formed by sintering metal particles with a melting point of 300°C or higher. The material of the metal particle sintered body 4 is preferably Ag, Cu, or an alloy containing these as main components, which have high thermal conductivity. The metal particles have a particle diameter of 100 nm or more and less than 10 μm.

[0012] The intermetallic compound region 5 is a region made of an intermetallic compound of the constituent elements of the metal particle sintered compact 4 having a melting point of 300°C or more and a low-melting point metal having a melting point of 100°C or more and 300°C or less. The low-melting point metal having a melting point of 100°C or more and 300°C or less is Sn, In, Bi, Ga, or an alloy mainly composed of these, and is the same element as the metal particle sintered compact 4, i.e., the same element as the metal particles. The intermetallic compound region 5 is formed by contacting and heating the metal particles of the constituent elements having a melting point of 300°C or more and the low-melting point metal having a melting point of 100°C or more and 300°C or less.

[0013] As described above, the bonding layer 3 is composed of the metal particle sintered body 4, the intermetallic compound region 5, and the gaps 6, i.e., voids, but the volume ratio of the region excluding the gaps 6 in the bonding layer 3 is 80% or more, and the volume ratio of the intermetallic compound region 5 in the bonding layer 3 is 10% or less. Here, the volume ratio is calculated from the area ratio of a cross-sectional SEM image.

[0014] The semiconductor element 1 is a power semiconductor, and may be one that uses Si as a base material, SiC as a base material, or GaN as a base material. The thickness of the semiconductor element 1 is 100 μm or more to prevent cracking due to external force, and the shape of the semiconductor element 1 viewed from above is rectangular. Also, one side of the size of the semiconductor element 1 viewed from above is, for example, 5 mm or more. An electrode is formed on the bonding surface side of the semiconductor element 1. For example, the electrode is formed from the semiconductor element 1 side in the order of Ni 15 μm thick / Pd 100 nm thick / Au 200 nm thick. Pd is inserted to prevent Ni from diffusing into the bonding surface. The electrode is formed by a sputtering method or the like.

[0015] The circuit board 2 is an insulating substrate formed of ceramic Cu (oxygen-free copper), etc. The ceramic is silicon nitride, alumina, etc.

[0016] Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

[0017] 2, a low-melting-point metal layer 7 made of a low-melting-point metal having a melting point of 100° C. or more and 300° C. or less and constituting the intermetallic compound region 5 is formed on the first surface 1A of the semiconductor element 1 (first step). The low-melting-point metal layer 7 is formed by plating or sputtering. The thickness of the low-melting-point metal layer 7 may be, for example, 1 μm or more and 10 μm or less.

[0018] Next, a paste is prepared by mixing the metal particles 8 constituting the metal particle sintered body 4 with a solvent, and the paste is applied onto the surface of the circuit board 2 on which the Cu wiring is formed, forming a coating layer 9 on the second surface 2A of the circuit board 2, as shown in the schematic cross-sectional view of FIG. 3 (second step). The solvent is selected to have a low boiling point so that the solvent is completely evaporated during heating, which will be described later. The solvent may be Texanol, butyl carbitol, butyl carbitol acetate, hexyl carbitol, or the like. If the paste contains a large amount of solvent, it is possible that the solvent will not completely evaporate during heating, and the intervals between the metal particles 8 may become large, making it difficult to proceed with sintering of the metal particles 8. Therefore, it is preferable that the amount of solvent in the paste is small. The solvent content in the paste is preferably 15 wt% or less.

[0019] The thickness of the coating layer 9 is set to be larger than the thickness of the low-melting point metal layer 7 so that the volume ratio of the intermetallic compound region 5 in the bonding layer 3 is 10% or less. If the thickness of the coating layer 9 is large, the thickness of the bonding layer 3 will be large, and the heat dissipation will be deteriorated. If the thickness of the coating layer 9 is small, the thickness of the bonding layer 3 will be small, and when each material thermally expands due to heat generated during operation of the semiconductor device, the force applied to the bonding layer 3 will be large, and cracks may occur in the bonding layer 3. Therefore, it is desirable to appropriately select the thickness of the coating layer 9 depending on the type of semiconductor element 1, chip size, etc. Moreover, the thickness of the low-melting-point metal layer 7 and the thickness of the coating layer 9 are preferably determined so that the low-melting-point metal layer 7 disappears after heating, which will be described later.

[0020] Next, as shown in the schematic cross-sectional view of FIG. 4, the semiconductor element 1 having the low-melting point metal layer 7 formed thereon and the circuit board 2 having the coating layer 9 formed thereon are laminated so that the low-melting point metal layer 7 and the coating layer 9 face each other, and the semiconductor element 1 is pressed toward the circuit board 2 in the direction of the arrow in FIG. 4 with a pressing force large enough to cause the coating layer 9 to adhere to the entire joining surface of the semiconductor element 1, but not so large that the metal particles 8 do not wet and spread to the side and top surfaces of the semiconductor element 1 that are not the joining surface, i.e., pressed (third step).

[0021] Next, the circuit board 2 into which the semiconductor element 1 was pressed in the previous step is placed in a normal pressure heating furnace filled with an inert gas such as nitrogen, and heated at a temperature of 300°C or less, which is equal to or higher than the melting point of the low melting point metal of the low melting point metal layer 7 and equal to or lower than the melting point of the metal particles 8. The low melting point metal layer 7 is melted by heating, and the metal particles 8 are sintered to form the bonding layer 3 (fourth step). The melting point of the bonding layer 3 is 300°C or higher. At this time, heating in an inert gas such as nitrogen can prevent each part from oxidizing. By setting the heating temperature to 300°C or less, the semiconductor element 1 can be prevented from oxidizing and deforming. In this fourth step, the low melting point metal layer 7 may be removed or may remain. Whether the low melting point metal layer 7 is left or not can be determined depending on how thick the low melting point metal layer 7 is to be. In this manner, the semiconductor device shown in FIG. 1 can be manufactured.

[0022] The bonding layer 3 of the semiconductor device of this embodiment has a volume ratio of voids 6 therein of less than 20%, and the volume ratio of the intermetallic compound region 5 is 10% or less of that. In other words, the volume ratio of voids 6 being less than 20% means that the density is 80% or more. Here, the volume ratio of the region other than voids 6 is called the density.

[0023] The high density of the bonding layer 3 of 80% or more improves heat dissipation and electrical conductivity, inhibits crack propagation during a temperature cycle test (heat cycle (H / C test)), and increases the bonding strength. The volume ratio of the intermetallic compound region 5 in the bonding layer 3 is 10% or less of the bonding layer 3. Intermetallic compounds are hard and brittle, and cracks tend to propagate when the volume ratio of the intermetallic compound region 5 is high. However, the volume ratio of the intermetallic compound region 5 in the bonding layer 3 of the semiconductor device of this embodiment is low, 10% or less, so that cracks do not propagate easily.

[0024] The melting point of the low-melting-point metal of the low-melting-point metal layer 7 is set to 100° C. or higher and 300° C. or lower so that the melting point is lower than the temperature at which the metal particles 8 melt and sinter during the above heating.

[0025] Here, methods for evaluating the density of the bonding layer 3, the volume fraction of the voids 6, and the volume fraction of the intermetallic compound region 5 in the bonding layer 3 will be described. The volume fraction of the voids 6 in the bonding layer 3 and the volume fraction of the intermetallic compound region 5 in the bonding layer 3 were determined by observing the cross section of the bonding layer 3 with a scanning electron microscope (SEM) and calculating the volume fraction of the voids 6 from the area fraction of the voids 6 (voids) in the image, and the volume fraction of the intermetallic compound region 5 from the area fraction of the intermetallic compound region 5 in the image.

[0026] The bonding strength of the bonding layer 3 was evaluated by a shear test. The shear test was performed in accordance with the lead-free solder test method of JIS Z 3198-7. The test speed was 5 mm / min, and the height of the shear tool when evaluating a semiconductor element 1 chip having a thickness of 100 μm was 30 μm from the circuit board 2. In the shear test, a bonding strength of 60 MPa or more was evaluated as "good," and a bonding strength of less than 60 MPa was evaluated as "poor."

[0027] The degree of crack growth after the temperature cycle test of the bonding layer 3 was evaluated by the following method. The temperature cycle test conditions were (-45 / 150°C, 15min / 15min at each temperature, 1000 cycles), and the crack growth length after the temperature cycle test was obtained from SAT (Scanning Acoustic Tomograph) evaluation images. The SAT device used was an ultrasonic imaging device FineSAT manufactured by Hitachi Power Solutions Co., Ltd.

[0028] Specifically, the degree of crack growth in the bonding layer 3 after the temperature cycle test was evaluated by the following method. Figure 5 shows examples of SAT images before and after the temperature cycle test. Figure 5(a) shows the image before the temperature cycle test, and Figure 5(b) shows the image after the temperature cycle test. The frequency of the probe was 25MHz. The prepared sample was placed in a water tank inside the ultrasound imaging device, and ultrasonic waves were propagated through it. The ultrasonic waves were reflected by the voids (cracks) inside the sample, and the voids (cracks) could be detected by measuring the intensity of the reflected ultrasonic waves. The higher the reflected intensity of the ultrasonic waves, the brighter the image that was obtained, so it was assumed that the white areas were voids (cracks).

[0029] The test was performed using a semiconductor element 1 chip with a side length of 10 mm. If a crack occurs in the bonding layer 3 after the temperature cycle test, the four corners of the chip will turn white, as shown in Figure 5(b). These white areas are the crack propagation areas, and four crack propagation areas will occur at each corner per chip. The lengths C1, C2, C3, and C4 of the crack propagation areas at the four corners in Figure 5(b) were measured, and those with an average value Ca of 1 mm or less were marked as "Good", and those with an average value exceeding 1 mm were marked as "Poor".

[0030] The reason why this threshold was set at 1 mm is as follows. Cracks propagate from the four corners, and when they exceed 1 mm, the heat dissipation of the joint decreases. Then, the semiconductor element 1 bonded on top of it heats up more during actual operation. This starts a negative spiral in which further cracks appear in the joint. For this reason, the threshold is set at 1 mm as the point at which thermal runaway begins. Working Example

[0031] The present disclosure will be described in more detail below by way of examples, but the present disclosure is not limited to these examples. Example 1 A 100μm thick SiC semiconductor was used as the semiconductor element 1, and a 3μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 250°C for 60 minutes. After heating, the device was removed from the heating furnace.

[0032] Example 2 A 100μm thick SiC semiconductor was used as the semiconductor element 1, and a 3μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 275°C for 15 minutes. After heating, the device was removed from the heating furnace.

[0033] Example 3 A 100 μm thick SiC semiconductor was used as the semiconductor element 1, and a 3 μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 275° C. for 30 minutes. After heating, the device was removed from the heating furnace.

[0034] Example 4 A 100μm thick SiC semiconductor was used as the semiconductor element 1, and a 3μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 275°C for 60 minutes. After heating, the device was removed from the heating furnace.

[0035] Example 5 A 100μm thick SiC semiconductor was used as the semiconductor element 1, and a 3μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 300°C for 30 minutes. After heating, the device was removed from the heating furnace.

[0036] Example 6 A 100μm thick SiC semiconductor was used as the semiconductor element 1, and a 1μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 275°C for 15 minutes. After heating, the device was removed from the heating furnace.

[0037] Example 7 A 100 μm thick SiC semiconductor was used as the semiconductor element 1, and a 1 μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 275° C. for 30 minutes. After heating, the device was removed from the heating furnace.

[0038] Example 8 A 100μm thick SiC semiconductor was used as the semiconductor element 1, and a 5μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 275°C for 15 minutes. After heating, the device was removed from the heating furnace.

[0039] Example 9 A 100 μm thick SiC semiconductor was used as the semiconductor element 1, and a 5 μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 275° C. for 30 minutes. After heating, the device was removed from the heating furnace.

[0040] Comparative Example 1 A 100μm thick SiC semiconductor was used as the semiconductor element 1, and a 3μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 250°C for 15 minutes. After heating, the device was removed from the heating furnace.

[0041] Comparative Example 2 A 100μm thick SiC semiconductor was used as the semiconductor element 1, and a 3μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 250°C for 30 minutes. After heating, the device was removed from the heating furnace.

[0042] Comparative Example 3 A 100μm thick SiC semiconductor was used as the semiconductor element 1, and a 7μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 275°C for 15 minutes. After heating, the device was removed from the heating furnace.

[0043] Comparative Example 4 A 100μm thick SiC semiconductor was used as the semiconductor element 1, and a 7μm thick Sn layer was formed as the low melting point metal layer 7. In addition, a solution containing Ag particles as metal particles 8 was applied onto the Cu electrodes of the circuit board 2 to form a coating layer 9. After these were pressed into place, the device was placed in a nitrogen-filled normal pressure heating furnace and heated at 275°C for 30 minutes. After heating, the device was removed from the heating furnace.

[0044] Next, the effects of the present disclosure will be described using examples and comparative examples. The results of evaluation of some of Examples 1 to 9 and Comparative Examples 1 to 4 with respect to the density and bonding strength of bonding layer 3, the volume fraction of intermetallic compound region 5, and the degree of crack growth after a temperature cycle test are shown.

[0045] Table 1 shows the results of measuring the density and bonding strength of the bonding layer 3 of the samples of Examples 1 to 4 and Comparative Examples 1 and 2. The reference value for the bonding strength was set to 60 MPa or more. As shown in Table 1, in Examples 1 to 4 where the bonding strength was "good", i.e., 60 MPa or more, the density of the bonding layer 3 was 80% or more, i.e., the volume ratio of the voids 6 in the bonding layer 3 was less than 20%. Also, in Comparative Examples 1 and 2 where the bonding strength was "poor", i.e., less than 60 MPa, the density of the bonding layer 3 was less than 80%, i.e., the volume ratio of the voids 6 in the bonding layer 3 was 20% or more.

[0046] [Table 1]

[0047] From the evaluation results shown in Table 1, it can be seen that the higher the density of the bonding layer 3, the higher the bonding strength. In addition, the higher the density, the better the heat dissipation and electrical conductivity, and the more suppressed the crack growth during the temperature cycle test, so the bonding strength after the temperature cycle test is even greater than that of a layer with a lower density.

[0048] Table 2 shows the results of measuring the volume fraction of the intermetallic compound region 5 in the bonding layer 3 and the crack propagation length after the temperature cycle test for the samples of Examples 2, 3, and 6 to 9 and Comparative Examples 3 and 4. As shown in Table 2, in Examples 2, 3, and 6 to 9 in which the crack propagation length after the temperature cycle test was "good", that is, 1 mm or less, the volume fraction of the intermetallic compound region 5 in the bonding layer 3 was 10% or less. In Comparative Examples 3 and 4 in which the crack propagation length after the temperature cycle test was "poor", the volume fraction of the intermetallic compound region 5 in the bonding layer 3 exceeded 10%. When the volume fraction of the intermetallic compound region 5 in the bonding layer 3 is large as in Comparative Examples 3 and 4, the bonding layer 3 becomes hard and brittle and cracks become more likely to propagate. However, by reducing the volume fraction of the intermetallic compound region 5 in the bonding layer 3 to 10% or less as in Examples 2, 3, and 6 to 9, the bonding layer 3 is prevented from becoming hard and brittle, cracks are less likely to propagate, and a bonding layer 3 with high reliability can be obtained.

[0049] [Table 2]

[0050] The configurations shown in the above embodiments are merely examples, and may be combined with other known technologies. Parts of the configurations may be omitted or modified without departing from the spirit of the invention. [Explanation of symbols]

[0051] 1 semiconductor element, 2 circuit board, 3 bonding layer, 4 metal particle sintered body, 5 intermetallic compound region, 6 void, 7 low melting point metal layer, 8 metal particles, 9 coating layer.

Claims

1. A first step of forming a low melting point metal layer having a melting point of 100°C or higher and 300°C or lower on a first surface of a semiconductor element; A second step of applying a paste containing metal particles having a melting point of 300°C or higher and a solvent onto a second surface of a circuit board to form a coating layer on the second surface; A third step of pushing and pressing the semiconductor element with the coating layer and the low melting point metal layer in contact with each other; A fourth step of heating the circuit board into which the semiconductor element has been pushed at normal pressure in an inert gas at a temperature equal to or higher than the melting point of the low melting point metal layer and equal to or lower than the melting point of the metal particles, to form a bonding layer having a void volume ratio of less than 20%; characterized by comprising A method of manufacturing a semiconductor device.

2. The low melting point metal layer is made of any one of Sn, In, Bi, and Ga, or an alloy containing any of these as a main component. The method of manufacturing a semiconductor device according to Claim 1.

3. In the first step, the low melting point metal layer is formed by an electroplating method or a sputtering method. The method of manufacturing a semiconductor device according to Claim 2.

4. In the second step, the solvent content in the paste is set to 15 wt% or less. The method of manufacturing a semiconductor device according to Claim 1.

5. In the second step, the thickness of the coating layer is made larger than the thickness of the low melting point metal layer. The method of manufacturing a semiconductor device according to any one of Claims 1 to 4.

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