Bidirectional logic element, arithmetic device, and arithmetic method

Abstract

The bidirectional logic element of the present invention comprises a function / inverse function control unit, a forward input unit, a forward information transfer unit, a backward input unit, a backward information transfer unit, a bidirectional function operation unit that performs both a forward logical operation and a backward operation, a forward function transfer unit, and a backward function transfer unit. The arithmetic device and arithmetic method of the present invention use the above bidirectional logic element.

Description

[Technical Field]

[0001] The present invention relates to a bidirectional logic element, an arithmetic unit, and an arithmetic method. [Background technology]

[0002] Conventionally, logic operations have used switch elements that embody Boolean algebra, and these switch elements are classified into branch-type logic elements and gate-type logic elements. Branch-type logic elements using electric / electronic components include, for example, relays, and gate-type logic elements include, for example, DTL, TTL, ECL, and MOS elements (Non-Patent Documents 1 and 2).

[0003] Another branch-type bidirectional logic element was a bidirectional logic element using Esaki diodes. This element was a two-terminal logic element using an Esaki diode pair and a delay element. Its features included a small number of components and the ability to perform high-speed bidirectional calculations by setting appropriate delay operation conditions through excitation. This element required delicate condition setting and has not yet been widely adopted, but current integration technology has made it possible for it to become widespread (Non-Patent Documents 3 and 4). Another method involves looking up a table of memory elements using input combinations appropriate for these calculations. Furthermore, there are bidirectional elements using ferroelectric capacitors. This method can also be realized by replacing it with a Jopsephson effect element (Patent Documents 2 and 3). Recently, branch-type switching elements such as HEMTs, spin Esaki diodes, superconducting elements, and quantum bit elements have become available, and bidirectional logic elements can also be constructed using these elements (Patent Documents 4, 5, and 6; Non-Patent Documents 5, 6, and 7).

[0004] However, the gate-type logic elements that use semiconductors and are currently in widespread use are, by their very nature, configured so that information processing proceeds in one direction, from input to output.

[0005] Meanwhile, a pass transistor that can transmit information bidirectionally has been devised as a branch-type switching element using MOS transistors (Patent Document 1, Non-Patent Document 8). This has previously been used to change the flow of signals inside forward gate type logic elements (Non-Patent Document 9). However, it did not enable bidirectional operation of logic functions.

[0006] There are two types of pass transistors: p-MOS transistors and n-MOS transistors. As a method of complementing their electrical characteristics to operate at high speed, there is a transmission gate in which a p-MOS transistor and an n-MOS transistor are connected in parallel (Patent Document 1). There are also gate-type composite logic elements that combine gate-type MOS transistors and transmission gates (Non-Patent Documents 9, 10, 11).

[0007] However, there were no bidirectional logic elements that could transfer information or perform calculations in both directions among integrated logic elements, nor were there any adder / subtractors or multiplier / dividers, which are typical devices constructed from such elements.

[0008] The above multiplication / division uses AND elements, but mathematically, multiplication / division is not a perfect inverse function. The AND elements used in multiplication / division do not assign zero to the multiplicand / multiplier or dividend / divisor, and the calculation result is "0." These are also mathematically defined as a "0" divide. For example, the calculation result of the combination of two input variables (0, 1) of an AND element is "0," and the information of that one variable, "1," is lost, so the calculation result of the divisor value "1" for the combination of the inverse function of "0 × 1 = 0," "0 ÷ 1 = 0," cannot be obtained.

[0009] Therefore, in the array multiplier / divider, the above combination is set to "0" according to the mathematical definition to address the contradiction in its implementation. However, if even one of the multi-digit multiplicands in each row is not "0", it is set to "1". This resolves the contradiction in the arithmetic operation (Non-Patent Document 12).

[0010] Furthermore, in conventional arithmetic operations, addition / subtraction and multiplication / division are implemented using gate-type technology. This means that arithmetic, control, or information processing is configured to proceed in one direction, from input to output. Therefore, the inverse functions of multiplication / division do not hold, and in principle, it is necessary to configure and arrange adders, multipliers, subtractors, and dividers separately. This requires a large number of components, a large area, and power consumption. However, for addition / subtraction, a method has been realized in which addition / subtraction is integrated into one operation using an adder that adds complements. Subtraction and division cells that use complements have also been realized (Non-Patent Document 13).

[0011] In the field of general-purpose computers, advances in integration technology have led to a demand for high-precision, high-speed floating-point arithmetic units, such as 32-bit (single precision) and 64-bit (double precision) units. Various configurations and algorithms have been devised to achieve higher speeds and higher integration (Non-Patent Documents 13, 14, 15). Furthermore, a redundant binary arithmetic algorithm has been proposed as a high-speed arithmetic algorithm (Patent Document 5, Non-Patent Document 16). Furthermore, a 64-bit floating-point arithmetic unit based on this algorithm has been put into practical use (Non-Patent Documents 17, 18).

[0012] Subsequently, the IEEE754_2008 IEEE Standard for Floating-Point Arithmetic was standardized as a method for arithmetic processing. In particular, division requires a trial-and-error approach, which is also described in this standard method. Currently, representative CPUs use the IEEE754 standard method (Non-Patent Document 20).

[0013] Division produces a quotient and a remainder, but in digital division the error is 2 1 Rounding is required at this point. A trial-and-error selection is required, as shown in the Robertson diagram, which converges the error (Non-Patent Document 19).

[0014] The present invention's method is also compatible with the IEEE754 format, and when arithmetic operations are frequently used in AI, for example, in the case of multiplication / division, the bidirectional multiplier / divider of the present invention can be applied to the multiplier / divider part of the mantissa, and the bidirectional adder / subtractor of the present invention can be applied to the exponent part in floating-point multiplication / division. Another method is to repeat multiplications and converge to the quotient by trial and error. The present invention's method does not require trial and error selection for division. [Prior art documents] [Patent documents]

[0015] [Patent Document 1] U.S. Patent No. 3,457,435 [Patent Document 2] International Publication No. 2006 / 115062 Pamphlet [Patent Document 3] U.S. Patent No. 3,953,749 [Patent Document 4] Japanese Patent Application Laid-Open No. 2003-69418 [Patent Document 5] Japanese Patent Application Publication No. 63-25729 [Patent Document 6] U.S. Patent No. 4,097,765 [Non-patent literature]

[0016] [Non-Patent Document 1] MA HARRISON introduction to switching and automata theory 1965 [Non-patent document 2] DLDietmeyer:Logic Design of Digital System 1978 [Non-patent document 3] Kubota, Yajima: Bidirectional logic circuits using Esaki diodes, Materials from the Institute of Electronics and Communication Engineers, Electronic Computer Research Group, 1967 [Non-patent document 4] Yajima, Kamibayashi: "Synthesis of Bidirectional Logic Circuits," Transactions of the Institute of Electronics and Communication Engineers, 1986 [Non-Patent Document 5] Takashi Mimura: High Electron Mobility Technology (HEMT), Journal of the HEMT Society, 1982 [Non-licensed Document 6] LD Anh, PN Hai, and M. Tanaka :Electrical tuning of the band alignment and magnetoconductance in an n-type ferromagnetic semiconductor (In, Fe) As based spin-Esaki diode,Applied Physics Letters 2018 [Non-licensed Document 7] M. TANAKA, K. TAKAGI, N.TAKAGI: High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed Digit Representation, IEICE TRANS. ELECTRON. 2016 [Non-licensed Document 8] RCA: CMOS / MOS Integrated Circuits Manual 1972 [Non-licensed Document 9] MOTOROLA: McMOS HANDBOOK 1974 [Non-licensed Document 10] C. Mead L. Conway: INTRODUCTION TO VLSI SYSTEMS ADDISON-WESLEY 1980 [Non-licensed Document 11] Neil HE Weste K. Eshrghian: PRINCIPLES OF CMOS VSLI DESIGN A Systems Perspective ADDISON-WESLEY 1985 [Non-licensed Document 12] S. MacLANE G. BIRKHOFF: ALGEBRA Macmillan 1967

Non-Patent Document 13

Non-Patent Document 14

Non-Patent Document 15

Non-Patent Document 16

Non-Patent Document 17

Non-Patent Document 18

Non-Patent Document 19

Non-Patent Document 20

Non-Patent Document 21

Summary of the Invention

[0017] An object of the present invention is to provide a bidirectional logic element capable of performing operations bidirectionally, and an arithmetic device and an arithmetic method using the bidirectional logic element. [Means for solving the problem]

[0018] The gist and configuration of the present invention are as follows. (1) a function / inverse function control unit that controls the direction of operation of the logic element to switch between a function, which is a forward operation, and an inverse function, which is a reverse operation; a forward input unit for inputting data in the case of a forward operation; a forward information transfer unit that transfers the input from the forward input unit; a reverse direction input unit for inputting data in the case of a reverse operation; a backward information transfer unit that transfers the input from the backward input unit; a bidirectional function operation unit that performs a forward logical operation using an input from the forward information transfer unit as an input signal in the case of a forward operation, and performs a backward logical operation using an input from the backward information transfer unit as an input signal in the case of a backward operation; a forward function transfer unit that transfers an output from the bidirectional function operation unit as a forward output in the case of a forward operation; a backward function transfer unit that transfers an output from the bidirectional function operation unit in the case of a backward operation as a backward output. In the detailed description of the invention, the explanation is mainly focused on those used for arithmetic operations.

[0019] (2) The bidirectional logic element according to (1), wherein the bidirectional function operation unit is configured with a branch-type logic element.

[0020] (3) The bidirectional logic element according to (1) or (2), wherein the bidirectional function operation unit is configured using a transmission gate.

[0021] (4) The bidirectional logic element according to (3), wherein the bidirectional function calculation unit uses two-rail logic.

[0022] (5) The bidirectional logic element according to (3), wherein the bidirectional function calculation unit uses single-wire logic.

[0023] (6) The bidirectional function calculation unit has two or more. The bidirectional logic element according to (1) or (2), wherein two or more of the bidirectional function operation units are connected in parallel or in series to function as one or more operation units that perform bidirectional operation.

[0024] (7) An arithmetic unit including an adder and subtractor and / or a multiplier and divider in which the bidirectional logic elements according to (1) or (2) are connected in parallel or in series.

[0025] (8) including the multiplier and divider; The arithmetic device according to (7), further comprising a zero divide processing unit that performs zero divide processing by setting the value to 1 if any of the dividends is 1, setting the value to 0 if all of the dividends are 0, and setting the divisor to 1 if the dividend is 1.

[0026] (9) A calculation method for performing a bidirectional calculation using the bidirectional logic element according to (1) or (2). [Effects of the Invention]

[0027] According to the present invention, it is possible to provide a bidirectional logic element capable of performing operations in both directions, as well as an arithmetic device and an arithmetic method using the bidirectional logic element. [Brief explanation of the drawings]

[0028] [Figure 1A] FIG. 1 is a typical configuration diagram for explaining a bidirectional logic element according to an embodiment of the present invention. [Figure 1B] FIG. 1B is a diagram illustrating an example in which a pull-down element is added to the configuration of FIG. 1A. [Figure 2A] FIG. 10 is a diagram showing a list of representative operations of the bidirectional function operation unit. [Figure 2B] FIG. 10 is a diagram showing a list of representative operations of the bidirectional function operation unit. [Figure 2C] FIG. 10 is a diagram illustrating a configuration example of a transmission gate that realizes a bidirectional switch. [Figure 3A] 1 is a symbolic diagram of an Exclusive-OR (XOR) logic element. [Figure 3B] FIG. 1 is a circuit diagram of an Exclusive-OR (XOR) logic element. [Figure 3C] FIG. 1 is a more detailed circuit diagram of an Exclusive-OR (XOR) logic element. [Figure 3D] FIG. 4 is a diagram showing an example in which a pull-down element is added to FIGS. 3B and 3C. [Figure 3E] FIG. 1 is a symbolic diagram of an AND logic element. [Figure 3F] FIG. 1 is a circuit diagram of an AND logic element. [Figure 4A] FIG. 1 is a symbolic diagram of a half adder / subtractor. [Figure 4B] FIG. 1 is a circuit diagram of a half adder / subtractor. [Figure 5A] This is a symbolic diagram of a full adder / subtractor. [Figure 5B] FIG. 1 is a circuit diagram of a full adder / subtractor. [Figure 6A] This is a symbolic diagram of an n-digit adder / subtractor. [Figure 6B] This is a circuit diagram of an n-digit adder / subtractor. [Figure 7A] FIG. 1 is a symbolic diagram of a multiplier / divider. [Figure 7B] FIG. 1 is a circuit diagram of a multiplier / divider. [Figure 8A] FIG. 1 is a diagram illustrating the configuration concept of an n-digit multiplier / divider. [Figure 8B] FIG. 10 is a flow diagram of state allocation for a multiplier / divider. [Figure 8C] 8B is a diagram showing an example of a partial product of an n-digit multiplier / divider configured using the multiplier / divider shown in FIG. 8A. FIG. [Figure 8D] This is a conceptual diagram of an n-digit parallel multiplier / divider. [Figure 9] 1 is a symbolic diagram of a redundant binary adder / subtractor. [Figure 10] FIG. 10 is a diagram showing a truth table of a two-way XOR. [Figure 11] FIG. 10 is a diagram showing a truth table of a two-way AND. [Figure 12] FIG. 10 is a diagram showing a truth table of a bidirectional half adder / subtractor. [Figure 13] FIG. 10 is a diagram illustrating a truth table of a bidirectional full adder / subtractor. [Figure 14] FIG. 10 is a diagram illustrating a truth table of a multiplier / divider. [Figure 15] FIG. 10 is a diagram showing a truth table of a three-state buffer. DETAILED DESCRIPTION OF THE INVENTION

[0029] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, with examples mainly focusing on elements required for arithmetic operations.

[0030] <Bidirectional logic element> 1A is a typical configuration diagram for explaining a bidirectional logic element according to one embodiment of the present invention. As shown in FIG. 1A, the bidirectional logic element of this embodiment includes function / inverse function control units 1 and 1', a forward input unit 2, a forward information transfer unit 3, a backward input unit 5, a backward information transfer unit 3', a bidirectional function calculation unit 4, a forward function transfer unit 7, and a backward function transfer unit 6.

[0031] The function / inverse function control units 1, 1' are configured to control the direction of operation of the logic elements so as to switch between a function, which is a forward operation, and an inverse function, which is a reverse operation.

[0032] The forward input unit 2 is configured to perform input in the case of forward calculation.

[0033] The forward information transfer unit 3 is configured to transfer the input from the forward input unit 2 (to the bidirectional function calculation unit 4 in the example of FIG. 1A).

[0034] The bidirectional function calculation unit 4 is configured to perform a forward logical calculation using the input from the forward information transfer unit 3 as an input signal in the case of a forward calculation.

[0035] The forward function transfer unit 7 is configured to transfer the output from the bidirectional function calculation unit 4 in the forward direction as a forward output.

[0036] The backward input unit 5 is configured to perform input for backward calculations.

[0037] The backward information transfer unit 3 ′ is configured to transfer the input from the backward input unit 5 to the bidirectional function calculation unit 4 .

[0038] The bidirectional function calculation unit 4 is configured to also perform a logical calculation in the reverse direction using the input from the reverse information transmission unit 3' as an input signal in the case of a calculation in the reverse direction.

[0039] The reverse direction function transfer unit 6 is configured to transfer the output from the bidirectional function calculation unit 4 in the reverse direction as a reverse direction output.

[0040] 1B is a configuration diagram showing an example in which pull-down elements are added to the configuration of FIG. 1A. In the illustrated example, pull-down elements 31 and 31' are respectively placed between the forward information transfer unit 3 and the bidirectional function operation unit 4, and between the backward information transfer unit 3' and the bidirectional function operation unit 4. These pull-down elements 31 and 31' can ground an open path generated in the bidirectional function operation unit 4 at the output unit, thereby reducing stray capacitance. 1B, the bidirectional function calculation unit 4 further includes zero-divide processing units 41 and 41'. The zero-divide processing units will be described later.

[0041] 2A and 2B show a list of representative operations of the bidirectional function calculation unit. As shown in the first column of FIGS. 2A and 2B, the logical operation of the bidirectional function calculation unit 4 can be, for example, AND, NAND, OR, NOR, XOR, XNOR, and NOT, but is not limited to these examples. As indicated by "In / Out" in the symbol diagrams in the second column of FIGS. 2A and 2B, the bidirectional function calculation unit 4 is controlled to switch between a function, which is a forward operation, and an inverse function, which is a reverse operation. Symbols are shown in general except for "In / Out." The third column of FIGS. 2A and 2B shows a truth table, but both the function and the inverse function are the same as a standard truth table. The fourth column of FIGS. 2A and 2B shows an example of a circuit diagram capable of executing each logic for a function (or inverse function). The fifth column of FIGS. 2A and 2B shows a circuit diagram expanded from the fourth column to have bidirectional functionality. In the present application, the configuration is a bidirectional logic element, but it is also possible to configure and implement a unidirectional logic element so that it can be selected in both directions. As shown by the dashed lines in the third to fifth columns, when the input B, which is the operand, is a value of "0," the path of the operand A may become open. If this happens, the output may not be sufficiently "0" due to stray capacitance in the path, or the delay time may become longer. In such cases, it is desirable to connect pull-down resistors or pull-down transistors as pull-down elements to both ends of the transfer gate that constitutes the bidirectional function calculation unit 4, as shown in FIG. 1B.

[0042] FIG. 2C is a diagram showing an example of the configuration of a transmission gate that realizes a bidirectional switch. The bidirectional switch is configured using a pMOS enhancement transistor and an nMOS enhancement transistor. As shown in the figure, control signals are input to the gates of the pMOS enhancement transistor and the nMOS enhancement transistor. The sources of the pMOS enhancement transistor and the nMOS enhancement transistor are connected to each other and the drains are connected to each other. This enables logical operations as shown in the truth table.

[0043] Figure 3A is a symbolic diagram of an Exclusive-OR (XOR) logic element. In addition to the usual XOR symbol, "N / R" has been added to indicate switching between forward and reverse operations ("N" stands for "Normal" which indicates forward operation, and "R" stands for "Reverse" which indicates reverse operation). For forward operation, inputs are represented by "A" and "B", and outputs are represented by "S", and for reverse operation, inputs are represented by "S". R ", "B", the output is "A R " is expressed as:

[0044] 3B and 3C are circuit diagrams of an Exclusive-OR (XOR) logic element and more detailed circuit diagrams of the Exclusive-OR (XOR) logic element. As shown in Figures 3B and 3C, this logic element includes function / inverse function control units 1, 1', a forward input unit 2, a forward (inverse) logic information transfer unit 3 (3'), a bidirectional function calculation unit 4, a forward function transfer unit 7, a backward input unit 5, and a backward function transfer unit 6.

[0045] <Function / inverse function control section> As described above, the function / inverse function control sections 1, 1' control the direction of operation of the logic elements to switch between the function and the inverse function. The function / inverse function control unit 1 has a three-state buffer that controls the forward direction (on the lower left side of the figure) and a three-state buffer that controls the reverse direction (on the upper left side of the figure). When the control signal is Normal (High), the three-state buffer that controls the forward direction is turned on (signal transmission state) and the three-state buffer that controls the reverse direction is turned off (disconnected state Z: High Impedance), so that signal A is input to the forward direction input unit 2. On the other hand, when the control signal is Reverse (Low), the forward direction three-state buffer is turned off and the reverse direction three-state buffer is turned on, so that signal A is output to the left of the figure. Similarly, the function / inverse function control unit 1' has a forward tri-state buffer (on the upper right side of the figure) and a reverse tri-state buffer (on the lower right side of the figure). When the control signal is Normal (High), the forward tri-state buffer is turned on and the reverse tri-state buffer is turned off, causing a signal to be output from the forward function transfer unit 7 to the right of the figure as signal S. On the other hand, when the control signal is R (Low), the forward tri-state buffer is turned off and the reverse tri-state buffer is turned on, causing signal S to be input to the reverse input unit 5. In this way, by switching the control signal, the direction of operation of the logic element can be switched. In addition, since the function / inverse function control units 1 and 1' control the output in the forward and reverse directions, when no output is made as bus coupling, coupling is made with high impedance to avoid the influence of the selection of the function / inverse function.

[0046] TIFF0007802253000001.tif106170

[0047] TIFF0007802253000002.tif34170

[0048] TIFF0007802253000003.tif48170

[0049] TIFF0007802253000004.tif35170TIFF0007802253000005.tif84170

[0050] <Forward function transfer section> When a Normal (High) control signal is input to the function inverse function control units 1, 1' and the direction of operation of the logic element is forward, the forward function transmission unit 7 transmits the outputs S1, S2 from the bidirectional function operation unit 4 (in this example, two wires are combined into one wire) as a forward output S. The truth table is shown in FIG. 10. In this example, the forward function transmission unit 7 is configured with an OR circuit, as shown in FIG. 3B. FIG. 3C shows details of an OR circuit for converting two-wire logic to single-wire logic, and as an example, an OR circuit can be configured with a circuit as shown.

[0051] TIFF0007802253000006.tif99170

[0052] TIFF0007802253000007.tif28170

[0053] TIFF0007802253000008.tif20170TIFF0007802253000009.tif27170

[0054] TIFF0007802253000010.tif99170

[0055] <Reverse function transfer section> When a Reverse (Low) control signal is input to the function / inverse function control units 1 and 1' and the direction of operation of the logic element is reverse, the reverse function transfer unit 6 transfers the output A from the bidirectional function operation unit 4. R 1. A R 2 (in this example, combine two wires into one wire) R The truth table is shown in Figure 10, where A in the input is replaced with S, and S in the output is replaced with A. R In this example, the backward function transfer unit 6 is configured with an OR circuit, as shown in Fig. 3B. Fig. 3C shows details of an OR circuit for converting two-rail logic to single-rail logic, and as an example, the OR circuit can be configured with a circuit such as the one shown in the figure.

[0056] According to the logic elements shown in FIGS. 3B to 3D, the bidirectional function operation unit 4 can switch between forward and reverse operations, so that a predetermined operation (XOR) can be performed bidirectionally.

[0057] Figure 3E is a symbolic diagram of an AND logic element. In addition to the usual AND symbol, "N / R" has been added to indicate switching between forward and reverse operations ("N" stands for "Normal" which indicates the forward direction, and "R" stands for "Reverse" which indicates the reverse direction). For the forward direction, inputs are represented by "A" and "B", and outputs are represented by "P", and for the reverse direction, inputs are represented by "P" and "B". R ", "B", the output is "A R " is expressed as:

[0058] 3F is a circuit diagram of an AND logic element. As shown in FIG. 3F, this logic element includes function / inverse function control units 1 and 1', a forward input unit 2, information transfer units 3 and 3', a bidirectional function calculation unit 4, a forward function transfer unit 7, a backward input unit 5, and a backward function transfer unit 6.

[0059] The function / inverse function control units 1, 1', forward input unit 2, forward function transfer unit 7, backward input unit 5, and backward function transfer unit 6 are the same as in the XOR example, so we will not explain them again and will instead explain the information transfer units 3, 3' and bidirectional function calculation unit 4.

[0060] TIFF0007802253000011.tif14170

[0061] TIFF0007802253000012.tif42170

[0062] FIG. 11 shows a truth table of AND in the bidirectional function calculation unit 4. When input A is 0 and input B is 0, the gate of the first transmission gate is turned off and the gate of the second transmission gate is also turned off, so that the output S becomes "0". When input A is 1 and input B is 0, the gate of the first transmission gate is turned off and the gate of the second transmission gate is turned on, so that the output S is "0". When input A is 0 and input B is 1, the gate of the first transmission gate is turned on and the gate of the second transmission gate is turned off, so that the output S is "0". When input A is 1 and input B is 1, the gate of the first transmission gate is turned on and the gate of the second transmission gate is also turned on, so that the output S becomes "1". In this way, first, in the case of the forward direction, the bidirectional function operation unit 4 has an AND logical operation function.

[0063] TIFF0007802253000013.tif13170

[0064] When input S is 0 and input B is 0, the gate of the first transmission gate is turned off, and the gate of the second transmission gate is also turned off, so that its output A R will be "0". When input S is 1 and input B is 0, the gate of the first transmission gate is turned off and the gate of the second transmission gate is turned on, so that its output A R will be "0". When input S is 0 and input B is 1, the gate of the first transmission gate is turned on and the gate of the second transmission gate is turned off, so that its output A R will be "0". When input S is 1 and input B is 1, the gate of the first transmission gate is turned on, and the gate of the second transmission gate is also turned on, so that its output A R will result in "1". In this way, even in the case of the reverse direction, the bidirectional function operation unit 4 has the AND logical operation function.

[0065] According to the logic elements shown in FIGS. 3E and 3F, the bidirectional function operation unit 4 can switch between forward and reverse operations, so that a predetermined operation (AND) can be performed bidirectionally.

[0066] In the above example, XOR and AND are illustrated, but the present invention can be applied to the other logic elements shown in FIGS. 2A and 2B, as well as various other logic elements.

[0067] The bidirectional function operation unit 4 is preferably configured with branch-type logic elements, and in particular, it is preferable that the bidirectional function operation unit 4 is configured using transmission gates.

[0068] As in the above example, the bidirectional function calculation unit 4 preferably uses two-rail logic. However, in the present disclosure, the bidirectional function calculation unit 4 may also use one-rail logic. In the present disclosure, it is also preferable that the bidirectional logic element has two or more bidirectional function calculation units 4, and the two or more bidirectional function calculation units 4 are connected in parallel or in series to function as one or more calculation units that perform bidirectional calculations.

[0069] <Arithmetic device> Figure 4A is a symbolic diagram of a half adder / subtractor (half adder and subtractor). As with a normal half adder / subtractor, it is basically configured with a parallel connection of an XOR circuit that receives two inputs A and B and outputs an output S (sum), and an AND circuit that receives two inputs A and B and outputs an output Cout (carry). Since the XOR uses the bidirectional XOR logic element mentioned above, "N / R" has been added to indicate switching between forward and reverse operations. Here, "N" stands for "Normal" which indicates the forward direction, and "R" stands for "Reverse" which indicates the reverse direction. Here, the forward direction represents addition, and the reverse direction represents subtraction. The inputs for the forward direction are represented by "A" and "B", and the outputs by "S" and "Cout". The input for the reverse direction is represented by "S" R ", "B", the output is "A R "," and "Cout".

[0070] FIG. 4B is a circuit diagram of a half adder / subtractor. The half adder / subtractor shown in FIG. 4B differs from FIG. 3A in that an AND circuit is provided in parallel to the bidirectional XOR circuit shown in FIG. 3B, as indicated by the difference in the symbols between FIG. 3A and FIG. 4A. For example, in the forward direction, inputs A and B are also input to the AND circuit. The output of the AND circuit is Cout, which corresponds to the carry output. The parts common to the circuit in FIG. 3B have already been explained, so a repeated explanation will be omitted.

[0071] The truth table for the bidirectional half adder / subtractor is shown in FIG. (Forward direction) When input A is 0 and input B is 0, output S of the XOR circuit is 0, as in Fig. 3B. Also, output Cout of the AND circuit is 0. When input A is 0 and input B is 1, output S of the XOR circuit is 1, as in FIG. When input A is 1 and input B is 0, output S of the XOR circuit is 1, as in FIG. When input A is 1 and input B is 1, output S of the XOR circuit is 0, as in FIG. Thus, first, in the forward direction, the bidirectional half adder / subtractor has the logic operation function of a half adder / subtractor.

[0072] (in the reverse direction) Input S R is 0 and input B is 0, output A of the XOR circuit R is 0, as in FIG. 3B. Also, the output Cout of the AND circuit is 0. Input S R is 0 and input B is 1, output A of the XOR circuit R is 1, as in FIG. 3B. Also, the output Cout of the AND circuit is 0. Input S R is 1 and input B is 0, output A of the XOR circuit Ris 1, as in FIG. 3B. Also, the output Cout of the AND circuit is 0. Input S R is 1 and input B is 1, output A of the XOR circuit R is 0, as in FIG. 3B. Also, the output Cout of the AND circuit is 1. In this way, the bidirectional half adder / subtractor has the logic operation function of a half adder / subtractor even in the reverse direction.

[0073] According to the logic element shown in FIG. 4B, the bidirectional function operation unit can be used to switch between forward and reverse operations, so that a predetermined operation (addition / subtraction) can be performed bidirectionally.

[0074] Figure 5A is a symbolic diagram of a full adder / subtractor (full adder and subtractor). Like a normal full adder / subtractor, it can be configured using two half adders / subtractors and an OR circuit (using the same connection that normally configures a full adder / subtractor). It differs from a normal full adder / subtractor in that the two half adders / subtractors are the bidirectional half adders / subtractors that use the bidirectional XOR described above. For this reason, "N / R" has been added to indicate switching between forward and reverse operations. Here, "N" stands for "Normal" which indicates the forward direction, and "R" stands for "Reverse" which indicates the reverse direction. Here, the forward direction represents addition, and the reverse direction represents subtraction. The inputs in the forward direction are represented by "A" and "B", and the outputs are represented by the sum "S" and the carry "Cout". Also, the input in the reverse direction is represented by "S" R ", "B", the output is "A R "," and "Cout".

[0075] TIFF0007802253000014.tif20170TIFF0007802253000015.tif21170

[0076] The truth table for a bidirectional full adder / subtractor is shown in FIG. (Forward direction) When input A is 0, input B is 0, and input Ci is 0, the output of the front-stage XOR circuit and the output of the rear-stage XOR circuit are both 0, so S is 0. Also, the output of the front-stage AND circuit is 0, and the output of the rear-stage AND circuit is also 0, so Cout is 0. When input A is 0, input B is 0, and input Ci is 1, the output of the XOR circuit in the previous stage is 0 and the output of the XOR circuit in the next stage is 1, so S becomes 1. Also, the output of the AND circuit in the previous stage is 0 and the output of the AND circuit in the next stage is also 0, so Cout becomes 0. When input A is 0, input B is 1, and input Ci is 0, the output of the XOR circuit in the previous stage is 1 and the output of the XOR circuit in the next stage is 1, so S becomes 1. Also, the output of the AND circuit in the previous stage is 0 and the output of the AND circuit in the next stage is also 0, so Cout becomes 0. When input A is 0, input B is 1, and input Ci is 1, the output of the front-stage XOR circuit is 1 and the output of the rear-stage XOR circuit is 0, so S is 0. Also, the output of the front-stage AND circuit is 0 and the output of the rear-stage AND circuit is 1, so Cout is 1.

[0077] When input A is 1, input B is 0, and input Ci is 0, the output of the XOR circuit in the previous stage is 1 and the output of the XOR circuit in the next stage is 1, so S becomes 1. Also, the output of the AND circuit in the previous stage is 0 and the output of the AND circuit in the next stage is also 0, so Cout becomes 0. When input A is 1, input B is 0, and input Ci is 1, the output of the XOR circuit in the previous stage is 1 and the output of the XOR circuit in the next stage is 0, so S is 0. Also, the output of the AND circuit in the previous stage is 0 and the output of the AND circuit in the next stage is 1, so Cout is 1. When input A is 1, input B is 1, and input Ci is 0, the output of the front-stage XOR circuit is 0 and the output of the rear-stage XOR circuit is 0, so S is 0. Also, the output of the front-stage AND circuit is 1 and the output of the rear-stage AND circuit is 0, so Cout is 1. When input A is 1, input B is 1, and input Ci is 1, the output of the XOR circuit in the previous stage is 0 and the output of the XOR circuit in the next stage is 1, so S is 1. Also, the output of the AND circuit in the previous stage is 1 and the output of the AND circuit in the next stage is 0, so Cout is 1. Thus, first, in the forward direction, the bidirectional full / subtract adder has the logic operation function of a full adder / subtractor.

[0078] Next, the case of the reverse direction will be described. (in the reverse direction) Input S R is 0, and input Ci is 0, and input B is 0, the output of the XOR circuit in the previous stage (the previous stage in the reverse direction (hereinafter the same in this paragraph and the next paragraph)) and the output of the XOR circuit in the subsequent stage are 0, so A R is 0. As in the forward direction (same below), the output of the AND circuit in the previous stage is 0 and the output of the AND circuit in the next stage is also 0, so Cout is 0. Input S R When input Ci is 1 and input B is 0, the output of the XOR circuit in the previous stage is 0 and the output of the XOR circuit in the next stage is 0. R is 0. In addition, the output of the front-stage AND circuit is 0, and the output of the rear-stage AND circuit is also 0, so Cout is 0. Input S R When input Ci is 0 and input B is 1, the output of the XOR circuit in the previous stage is 1 and the output of the XOR circuit in the next stage is 0. R becomes 0. Also, since the output of the front-stage AND circuit is 0 and the output of the rear-stage AND circuit is 0, Cout becomes 0. Input S R If input Ci is 1 and input B is 1, the output of the XOR circuit in the previous stage is 1 and the output of the XOR circuit in the next stage is 0. R is 0. Also, since the output of the AND circuit in the previous stage is 0 and the output of the AND circuit in the next stage is 1, Cout is 1.

[0079] Input S RIf is 1, and input Ci is 0, and input B is 0, the output of the front-stage XOR is 1, and the output of the rear-stage XOR is 1, so A R is 1. Also, since the output of the AND circuit in the previous stage is 0 and the output of the AND circuit in the next stage is 0, Cout is 0. Input S R When input Ci is 1 and input B is 0, the output of the XOR circuit in the previous stage is 1 and the output of the XOR circuit in the next stage is 1. R becomes 1. Also, the output of the AND circuit in the previous stage becomes 0 and the output of the AND circuit in the next stage becomes 1, so Cout becomes 1. Input S R If is 0, and input Ci is 0, and input B is 1, the output of the previous XOR circuit is 0 and the output of the next XOR circuit is 1. R becomes 1. Also, the output of the AND circuit in the previous stage becomes 1 and the output of the AND circuit in the next stage becomes 0, so Cout becomes 1. Input S R If the input Ci is 1 and the input B is 1, the output of the XOR circuit in the previous stage is 0 and the output of the XOR circuit in the next stage is 1. R becomes 1. Also, the output of the AND circuit in the previous stage becomes 1 and the output of the AND circuit in the next stage becomes 0, so Cout becomes 1. In this way, even in the reverse direction, the bidirectional full adder / subtractor has the logical operation function of a full adder / subtractor.

[0080] According to the logic element shown in FIG. 5B, the bidirectional function operation unit can be used to switch between forward and reverse operations, so that a predetermined operation (full addition / subtraction) can be performed bidirectionally.

[0081] FIG. 6A is a symbolic diagram of an n-digit adder / subtractor. FIG. 6B is a circuit diagram of the n-digit adder / subtractor. Addition / subtraction control can be switched in association with the forward (N) / reverse (R) control of FIG. 1A, as with a full adder. An example of the configuration of an n-digit adder / subtractor using the bidirectional logic elements of the present disclosure can be achieved by connecting in the same way as when a normal full adder / subtractor is implemented for n digits. To perform carry at high speed, various carry methods, such as a look-ahead carry method, can be applied.

[0082] FIG. 7A is a symbolic diagram of a multiplier / divider (multiplication and division circuit). FIG. 7B is a circuit diagram of the multiplier / divider. As shown in FIG. 7A, the multiplier / divider can be implemented using the bidirectional AND element described above. FIG. 14 shows the truth table of the multiplier / divider. The information loss of the AND circuit is corrected by precharging it to "1" in FIG. 8A.

[0083] FIG. 8A is a diagram showing the configuration concept of an n-digit multiplier / divider. "M / D" in the diagram indicates switching between multiplication and division. The "M / D" part in the diagram corresponds to switching between the 0-divide processing units 41, 41' in FIG. 1B, and its control can be switched in relation to the forward (N) / reverse control (R) in FIG. 1B. Since there is no carry in the least significant digit, multiplication can be calculated using only an AND element. For division, the operand a0 is obtained from this, and based on this, arithmetic operation processing is performed, and the most significant digits are calculated in parallel to obtain the quotient b0 to b n However, due to mathematical definitions, a divide-by-0 process is required when the dividend a0 or divisor b0 is "0". Furthermore, it is also possible to check that the carry in multiplication and the carry in division are the same.

[0084] 8B is a flow diagram of state assignment for a multiplier / divider. In the present disclosure, an inverse function can be defined by the flow shown in FIG. 8B. That is, when an n-digit multiplicand is a1, a2, . . . and multipliers are b1, b2, . . ., it is first determined whether at least one digit of the multiplicand is "1." (1) When all digits of the multiplicand are 0 ("State A000" in Figure 8B) By mathematical definition, the multiplier is determined to be "0". (2) If at least one digit of the multiplicand is "1" (2-1) When the product is "0" and the multiplicand is "1" ("State D010" in FIG. 8B) Arithmetically, the multiplier is determined to be "0". (2-2) When the product is "0" and the multiplicand is "0" (2-2-1) ("When 1 / 0=0" ("State C110" in Figure 8B)) Arithmetically, the multiplier is determined to be "0". (2-2-2) ("1 / 0=0" ("State B111" in Figure 8B)) Arithmetically, the multiplier is determined to be "1".

[0085] Fig. 8C is a diagram showing an example of partial products of an n-digit multiplier / divider configured with the multiplier / divider shown in Fig. 8A. Fig. 8D is a conceptual diagram of an n-digit parallel multiplier / divider. The area surrounded by the two-dot chain line in the figure performs the above-mentioned zero divide processing.

[0086] Figure 9 is a symbolic diagram of a redundant binary adder / subtractor (redundant binary adder and subtractor). In redundant binary, the operands are coded, making the inverse operation complicated. However, once the operand of the two input variables is determined, calculations can be performed easily, just like with a general bidirectional arithmetic element. Here, the configuration of the addition / subtraction elements is shown symbolically, but multiplication / division can be configured using AND elements and half adders, so the bidirectional addition / subtraction or multiplication / division techniques described above can be implemented in the same way by replacing them with these elements.

[0087] In one embodiment, the arithmetic unit of the present disclosure may include adders and subtractors and / or multipliers and dividers in which the bidirectional logic elements described above are connected in parallel or in series. In one embodiment, the arithmetic device of the present disclosure preferably includes the above-mentioned multiplier and divider, and further includes a zero divide processing unit that performs zero divide processing in division by setting the value to 0 if any of the dividends is 0, setting the value to 1 if all of the dividends are 1, and setting the divisor to 1 if the dividend is 1.

[0088] <Calculation method> In one embodiment, the computing method of the present disclosure uses the bidirectional logic elements described above to perform bidirectional computations.

[0089] In one embodiment, the bidirectional logic element has a bidirectional function operation unit configured with transmission gates and two-rail logic. In one embodiment, the technique disclosed herein is a practical, optimal, and effective technique for realizing two-variable functions / inverse functions. Furthermore, by combining these with multiple variables or multiple stages, functions equivalent to those of widely used gate-type logic elements can be synthesized, and inverse function operations can also be realized.

[0090] In addition, in this disclosure, a bidirectional function calculation unit using dual-rail logic can be configured, for example, a full adder can be configured by connecting two half adders. A parallel multiplier / divider can save area when the second digit is integrated by combining a multiplier / divider unit with a full adder. Furthermore, it can also detect errors in operation or inverse operation.

[0091] The present disclosure can also be applied to floating-point arithmetic and redundant binary arithmetic, enabling faster calculations with a smaller area. Furthermore, the disclosed method can be used for general bidirectional function calculations, and in particular, can combine addition / subtraction and multiplication / division into a single operation by utilizing the function / inverse function relationship. Multiplication / division, which requires parallel processing for high speed, can be achieved at high speeds by significantly reducing the integrated area, number of elements, and power consumption.

[0092] Furthermore, although this disclosure uses partial functions realized using bidirectional logic elements, it is also possible to prevent information loss and realize a complete inverse function by encoding, transmitting, and processing the calculation results including the information necessary for the calculation to make the necessary variables bidirectional.

[0093] Furthermore, the bidirectional logic element of the present disclosure is suitable for arithmetic operations. Generally, arithmetic operations are performed to obtain a result from two values, an operand and an operand. In particular, when there is one variable, the bidirectional logic element is compatible with the bidirectional logic element and can be realized efficiently, quickly, and simply. Furthermore, it can be applied to high-speed algorithms or redundant binary notation, such as high-speed carry, which are already in practical use.

[0094] There are two types of number representations used in computer arithmetic processing: fixed-point and floating-point representations. Floating-point format operations consist of a mantissa and an exponent, with the mantissa being multiplied / divided and the exponent being added / subtracted. This disclosure can also be performed by combining similar operations. There are also various methods, such as signed numeric representation, and this disclosure can be applied to all of them.

[0095] According to this disclosure, bidirectional logic elements can perform general logic function calculations and, in addition, can perform inverse calculations of one variable. In particular, the four arithmetic operations of addition / subtraction and multiplication / division are in a relationship of operation / inverse operation, respectively, and can be realized with approximately half the integrated area and power consumption. Furthermore, since the inverse function can be obtained directly, a simple calculation method can be provided without the need for complex hardware algorithms. Furthermore, this method can also be applied to conventional hardware algorithms.

[0096] In the method for configuring a bidirectional logic element of the present disclosure, each unit is configured bidirectionally, and one or more of these are combined to perform bidirectional operation as a whole device. In addition, in a configuration in which multiple units are combined in parallel or series, each unit other than the combined bidirectional operation unit can be configured as a single unit as a whole device.

[0097] The disclosed technique can also be implemented bidirectionally using two sets of conventional elements.

[0098] Additionally, the disclosed technique does not require a trial-and-error approach to division when there are no partial products in multiplication. [Explanation of symbols]

[0099] 1,1´: Function / inverse function control section, 2: Forward input section 3: forward information transmission unit, 4: Bidirectional function calculation unit, 5: reverse input section, 3': backward information transmission unit, 6: Reverse function transfer section, 7: Forward function transfer section, 31, 31': pull-down element, 41, 41´:0 divide processing section

Claims

1. a function / inverse function control unit that controls the direction of operation of the logic element to switch between a function, which is a forward operation, and an inverse function, which is a reverse operation; a forward input unit for inputting data in the case of a forward operation; a forward information transfer unit that transfers the input from the forward input unit; a reverse direction input unit for inputting data in the case of a reverse operation; a backward information transfer unit that transfers the input from the backward input unit; a bidirectional function operation unit that performs a forward logical operation using an input from the forward information transfer unit as an input signal in the case of a forward operation, and performs a backward logical operation using an input from the backward information transfer unit as an input signal in the case of a backward operation; a forward function transfer unit that transfers an output from the bidirectional function operation unit as a forward output in the case of a forward operation; a backward function transfer unit that transfers an output from the bidirectional function operation unit in the case of a backward operation as a backward output.

2. 2. The bidirectional logic element according to claim 1, wherein said bidirectional function operation unit is composed of a branch-type logic element.

3. 3. The bidirectional logic element according to claim 1, wherein the bidirectional function operation unit is configured using a transmission gate.

4. 4. The bidirectional logic element according to claim 3, wherein said bidirectional function operation unit uses a two-rail logic.

5. 4. The bidirectional logic element according to claim 3, wherein said bidirectional function operation unit uses single-wire logic.

6. The bidirectional function calculation unit has two or more of the above-mentioned two-way function calculation units, 3. The bidirectional logic element according to claim 1, wherein two or more of the bidirectional function operation units are connected in parallel or in series to function as one or more operation units that perform bidirectional operation.

7. 3. An arithmetic unit comprising an adder and subtractor and / or a multiplier and divider, each of which is formed by connecting the bidirectional logic elements according to claim 1 or 2 in parallel or series.

8. said multiplier and divider; 8. The arithmetic device according to claim 7, further comprising a zero divide processing unit that performs zero divide processing in division by setting the value to 1 when any of the dividends is 1, setting the value to 0 when all of the dividends are 0, and setting the divisor to 1 when the dividend is 1.

9. A calculation method for performing bidirectional calculations using the bidirectional logic element according to claim 1 or 2.