Power Conversion Equipment

Abstract

In a power conversion device (100) including one or more single-phase inverters (INV(n)) connected in series to supply power to a load (10) and a control unit (20) that controls semiconductor switches (Q1(n) to Q4(n)) of the single-phase inverters (INV(n)), the control unit (20) controls between a first control state in which the semiconductor switch (Q1(n)) and the semiconductor switch (Q3(n)) are in an on state and the semiconductor switch (Q2(n)) and the semiconductor switch (Q4(n)) are in an off state and a second control state in which the semiconductor switch (Q2(n)) and the semiconductor switch (Q4(n)) are in an on state and the semiconductor switch (Q1(n)) and the semiconductor switch (Q3(n)) are in an off state, and the control unit (20) selects the first control state or the second control state when outputting zero voltage to the single-phase inverter (INV(n)).

Description

[Technical field]

[0001] The present disclosure relates to a power conversion device. [Background technology]

[0002] If losses are concentrated in a specific semiconductor switching element in an inverter or multiple inverter series circuits, a larger heat sink is required to dissipate the heat, which leads to larger equipment and higher costs. For this reason, it is necessary to distribute the losses generated in the semiconductor switching elements.

[0003] A drive control device is disclosed that dissipates heat generated in semiconductor switching elements in an inverter that converts DC power into AC power and supplies it to a load by changing the path through which current flows during the return period of the inverter. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-121129 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the drive control device of Patent Document 1, since the reflux period is divided equally within one control cycle, uniform heat dispersion cannot be achieved depending on the load and waveform. Also, since the voltage application time is divided into two within one control cycle, there are problems in that the switching loss increases with the increase in the number of switching operations, and waveform distortion occurs due to dead time.

[0006] The present disclosure discloses techniques for solving the problems described above, and aims to provide a power conversion device that can disperse heat generated in semiconductor switching elements by devising inverter control in a single-phase inverter circuit or a multi-series inverter circuit. [Means for solving the problem]

[0007] In the power conversion device disclosed herein, in a single-phase inverter INV(n), where n is an integer equal to or greater than 1, one end of a semiconductor switch Q1(n) and one end of a semiconductor switch Q3(n) are connected to a high-potential terminal of a DC power supply V(n), one end of a semiconductor switch Q2(n) and one end of a semiconductor switch Q4(n) are connected to a low-voltage terminal of the DC power supply V(n), the other end of the semiconductor switch Q1(n) and the other end of the semiconductor switch Q2(n) are connected in series at a first midpoint P1(n), and the other end of the semiconductor switch Q3(n) and the The present invention includes a single-phase inverter INV(n) having a configuration in which the other end of a semiconductor switch Q4(n) is connected in series at a second midpoint P2(n), a load connected to a first midpoint P1(1) of the single-phase inverter INV(1) and the second midpoint P2(n) of the single-phase inverter INV(n) and supplied with DC power or AC power, and a control unit that controls the semiconductor switch Q1(n), the semiconductor switch Q2(n), the semiconductor switch Q3(n) and the semiconductor switch Q4(n), and the control unit controls the semiconductor switch Q1(n). a first control state in which the semiconductor switch Q2(n) and the semiconductor switch Q3(n) are in an on state and the semiconductor switch Q2(n) and the semiconductor switch Q4(n) are in an off state, and a second control state in which the semiconductor switch Q2(n) and the semiconductor switch Q4(n) are in an on state and the semiconductor switch Q1(n) and the semiconductor switch Q3(n) are in an off state, and the control unit controls the semiconductor switch Q1(n) and the semiconductor switch Q4(n) to an on state and the semiconductor switch Q2(n) and the semiconductor switch Q3(n) are in an off state. The inverters are controlled to a first conduction state in which the semiconductor switch Q3(n) is turned off, and a second conduction state in which the semiconductor switch Q2(n) and the semiconductor switch Q3(n) are turned on and the semiconductor switch Q1(n) and the semiconductor switch Q4(n) are turned off, and when zero voltage is output between the first midpoint P1(n) and the second midpoint P2(n) in at least one of the single-phase inverters INV(n), either the first control state or the second control state is selected. Effect of the Invention

[0008] According to the power conversion device of the present disclosure, in a single-phase inverter circuit or a multi-series inverter circuit, by devising inverter control, a power conversion device can be obtained that can realize dispersion of heat generated in semiconductor switching elements. [Brief description of the drawings]

[0009] [Figure 1] 1 is an overall configuration diagram of a power conversion device according to a first embodiment. [Diagram 2] Fig. 2A is a diagram illustrating an operation state of the single-phase inverter according to embodiment 1. Fig. 2B is a diagram illustrating an operation state of the single-phase inverter according to embodiment 1. Fig. 2C is a diagram illustrating an operation state of the single-phase inverter according to embodiment 1. Fig. 2D is a diagram illustrating an operation state of the single-phase inverter according to embodiment 1. [Diagram 3] FIG. 2 is an operation state transition diagram of the single-phase inverter according to the first embodiment. [Figure 4] FIG. 2 is an operation state transition diagram of the single-phase inverter according to the first embodiment. [Diagram 5] Fig. 5A is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. Fig. 5B is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. Fig. 5C is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. [Figure 6] Fig. 6A is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. Fig. 6B is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. Fig. 6C is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. Fig. 6D is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. [Figure 7]Fig. 7A is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. Fig. 7B is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. Fig. 7C is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. Fig. 7D is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. Fig. 7E is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. [Figure 8] FIG. 8A is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 8B is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 8C is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 8D is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 8E is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. FIG. 8F is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 2. [Figure 9] 9A is a diagram illustrating an operation state of a plurality of single-phase inverters according to embodiment 3. FIG. 9B is a diagram illustrating an operation state of a plurality of single-phase inverters according to embodiment 3. [Figure 10] Fig. 10A is a diagram illustrating an operation state of a plurality of single-phase inverters according to embodiment 3. Fig. 10B is a diagram illustrating an operation state of a plurality of single-phase inverters according to embodiment 3. [Figure 11] Fig. 11A is a diagram showing an arrangement of semiconductor switches of a plurality of single-phase inverters according to embodiment 4. Fig. 11B is a diagram showing an arrangement of semiconductor switches of a plurality of single-phase inverters according to embodiment 4. [Figure 12] Fig. 12A is a diagram showing an arrangement of semiconductor switches of a plurality of single-phase inverters according to embodiment 4. Fig. 12B is a diagram showing an arrangement of semiconductor switches of a plurality of single-phase inverters according to embodiment 4. [Figure 13] Fig. 13A is a diagram showing an arrangement of semiconductor switches of a plurality of single-phase inverters according to embodiment 4. Fig. 13B is a diagram showing an arrangement of semiconductor switches of a plurality of single-phase inverters according to embodiment 4. [Figure 14]Fig. 14A is a diagram showing an arrangement of semiconductor switches of a plurality of single-phase inverters according to embodiment 4. Fig. 14B is a diagram showing an arrangement of semiconductor switches of a plurality of single-phase inverters according to embodiment 4. [Figure 15] Fig. 15A is a diagram showing an arrangement of semiconductor switches of a plurality of single-phase inverters according to embodiment 4. Fig. 15B is a diagram showing an arrangement of semiconductor switches of a plurality of single-phase inverters according to embodiment 4. [Figure 16] Fig. 16A is a diagram showing an arrangement of semiconductor switches of a plurality of single-phase inverters according to embodiment 4. Fig. 16B is a diagram showing an arrangement of semiconductor switches of a plurality of single-phase inverters according to embodiment 4. [Figure 17] 2 is a diagram showing an example of a hardware configuration of a control unit. [Figure 18] 4 is an explanatory diagram of transition timing of the single-phase inverter according to the first embodiment. FIG. [Figure 19] FIG. 4 is an explanatory diagram of transition timing of the single-phase inverter according to the first embodiment. [Figure 20] FIG. 4 is an explanatory diagram of transition timing of the single-phase inverter according to the first embodiment. [Figure 21] 4 is an explanatory diagram of transition timing of the single-phase inverter according to the first embodiment. FIG. [Figure 22] 4 is an explanatory diagram of transition timing of the single-phase inverter according to the first embodiment. FIG. [Figure 23] FIG. 4 is an explanatory diagram of transition timing of the single-phase inverter according to the first embodiment. [Figure 24] FIG. 4 is an explanatory diagram of transition timing of the single-phase inverter according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Embodiment 1 In the first embodiment, in a power conversion device including one or more single-phase inverters connected in series to supply power to a load, and a control unit that controls a semiconductor switch of the single-phase inverter, the control unit controls the semiconductor switch to a first control state and a second control state, and selects the first control state or the second control state when outputting zero voltage to the single-phase inverter.

[0011] The configuration and operation of the power conversion device of embodiment 1 will be described below with reference to FIG. 1 which is an overall configuration diagram of the power conversion device, FIGS. 2A and 2B which are explanatory diagrams of the operating states of the single-phase inverter, FIGS. 3 and 4 which are operating state transition diagrams of the single-phase inverter, and FIGS. 18 to 24 which are explanatory diagrams of the transition timing of the single-phase inverter.

[0012] The overall configuration of the power conversion device and the configuration of the single-phase inverter according to the first embodiment will be described with reference to FIG. The power conversion device 100 includes an inverter unit 1 and a control unit 20, and supplies AC power or DC power to a load 10.

[0013] First, the configuration and operation of the inverter unit 1 of the power conversion device 100 will be described. The inverter unit 1 is composed of single-phase inverters INV(1), INV(2), INV(3), ..., INV(n) (n is an integer equal to or greater than 1). In the figure, for example, INV(n) is written as INVn.

[0014] Next, the configuration of each single-phase inverter will be described using the single-phase inverter INV(n) as a representative. The single-phase inverter INV(n) is composed of a full-bridge circuit made up of self-extinguishing semiconductor switching elements Q1(n), Q2(n), Q3(n), and Q4(n), which are semiconductor switching elements such as multiple IGBTs (Insulated Gate Bipolar Transistors) each consisting of multiple diodes connected in anti-parallel, and a DC power supply V(n). For simplicity, the diodes of the semiconductor switching elements are omitted in Fig. 1 and are represented as switches. In the figure, for example, Q1(n) is written as Q1n, Q2(n) as Q2n, Q3(n) as Q3n, Q4(n) as Q4n, and V(n) as Vn. The semiconductor switching elements are also referred to as semiconductor switches. The semiconductor switching elements may be transistors, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), etc. Although the examples shown are each composed of a single component, each semiconductor switching element may be composed of a plurality of semiconductor switching elements connected in series, in parallel, or in series-parallel in order to ensure the withstand voltage and withstand current.

[0015] One end of the semiconductor switch Q1(n) and one end of the semiconductor switch Q3(n) are connected to the high-potential terminal of the DC power supply V(n), and one end of the semiconductor switch Q2(n) and one end of the semiconductor switch Q4(n) are connected to the low-voltage terminal of the DC power supply V(n). The other end of the semiconductor switch Q1(n) and the other end of the semiconductor switch Q2(n) are connected in series at a first midpoint P1(n), and the other end of the semiconductor switch Q3(n) and the other end of the semiconductor switch Q4(n) are connected in series at a second midpoint P2(n). In the figure, for example, P1(n) is written as P1n.

[0016] Next, the internal configuration of the inverter unit 1 and the relationship between the inverter unit 1, the load 10, and the control unit 20 will be described. The outputs of the single-phase inverters INV(n) are connected in series. Specifically, for example, the second midpoint P2(1) of the single-phase inverter INV(1) is connected to the first midpoint P1(2) of the single-phase inverter INV(2). Also, the second midpoint P2(2) of the single-phase inverter INV(2) is connected to the first midpoint P1(3) of the single-phase inverter INV(3). The load 10 is connected to the first midpoint P1(1) of the single-phase inverter INV(1) and the second midpoint P2(n) of the single-phase inverter INV(n). The control unit 20 controls the semiconductor switch Q1(n), the semiconductor switch Q2(n), the semiconductor switch Q3(n), and the semiconductor switch Q4(n) of each single-phase inverter INV(n). The load 10 may be any of a resistive load, an inductive load, and a capacitive load. Note that FIG. 1 shows a typical example of a circuit, and appropriate modifications can be made, such as adding a semiconductor switch drive circuit, a snubber circuit, an input capacitor, or an output filter.

[0017] Next, the operating state of the single-phase inverter INV(n) will be described with reference to the operating state explanatory diagrams of the single-phase inverter in FIG. 2A to FIG. 2D. Each single-phase inverter INV(n) has the following four operation states (first control state, second control state, first conduction state, second conduction state). In the first control state (see FIG. 2A), the control unit 20 turns on the semiconductor switches Q1(n) and Q3(n) and turns off the semiconductor switches Q2(n) and Q4(n). The first control state is a state in which zero voltage is output between the first midpoint P1(n) and the second midpoint P2(n). In the second control state (see FIG. 2B), the control unit 20 turns on the semiconductor switches Q2(n) and Q4(n) and turns off the semiconductor switches Q1(n) and Q3(n). The second control state is a state in which zero voltage is output between the first midpoint P1(n) and the second midpoint P2(n). In the first conduction state (see FIG. 2C), the control unit 20 turns on the semiconductor switches Q1(n) and Q4(n) and turns off the semiconductor switches Q2(n) and Q3(n). The first conduction state is a state in which a voltage of Vn is output between the first midpoint P1(n) and the second midpoint P2(n). In the second conduction state (see FIG. 2D), the control unit 20 turns on the semiconductor switches Q2(n) and Q3(n) and turns off the semiconductor switches Q1(n) and Q4(n). The second conduction state is a state in which a voltage of -Vn is output between the first midpoint P1(n) and the second midpoint P2(n). In each figure, the thick solid lines indicate the paths through which current flows.

[0018] Next, transitions of the operating states of the single-phase inverter INV(n), in particular transitions between the first control state and the second control state which are characteristic of the power conversion device 100 of the first embodiment, will be described with reference to the operating state transition diagrams of the single-phase inverter in FIGS. 3 and 4. First, a basic operation state transition (switching of selection) that is usually performed will be described with reference to FIG. The control unit 20 can arbitrarily select the first control state or the second control state. By arbitrarily selecting the first control state or the second control state, it is possible to distribute the conduction loss that occurs in the semiconductor switch. As shown in Fig. 3, the transition between the first control state and the second control state is basically performed via the first conduction state or the second conduction state. That is, the transition of the control state is performed after transition (switching the selection) to the first conduction state or the second conduction state at least once. By not transitioning directly from the first control state to the second control state (or from the second control state to the first control state), it is possible to suppress an increase in switching loss that occurs due to an increase in the number of switching operations of the semiconductor switch, and it is also possible to suppress waveform distortion that occurs due to the dead time required during the transition. It is not necessary for the control state to transition from the first control state to the second control state (or from the second control state to the first control state) every control period. The timing of the transition (switching) of the control state will be described later.

[0019] Next, a case where a transition is made directly between the first control state and the second control state will be described with reference to FIG. As shown in FIG. 4, the transition between the first control state and the second control state is made without passing through the first conduction state or the second conduction state. This direct transition (i.e., switching of selection) between the first control state and the second control state is effective when the period of the first control state or the period of the second control state is long (i.e., when no transition to the first conduction state or the second conduction state occurs) by switching the control state at least once, thereby enabling effective heat dispersion.

[0020] Next, the timing of the transition (switching of selection) from the first control state to the second control state (from the second control state to the first control state) and the effect thereof will be described. The transition timing will be explained using the examples shown in Fig. 18 to Fig. 24. Fig. 18 to Fig. 24 show an example of the operation of INV(m) that outputs a voltage of magnitude V. For simplification, in Fig. 18 to Fig. 24, the output states (INV states) of the four INV(m) are indicated as A to D, that is, the first control state is indicated as A, the second control state is indicated as B, the first conduction state is indicated as C, and the second conduction state is indicated as D. Method (1): Method (1) switches between the first control state and the second control state every control period of the control unit 20 or every integer multiple of the control period. In the example shown in Fig. 18, the state of INV when outputting 0 voltage is switched between the first control state (A) and the second control state (B) every control period. Method (1) is a method that enables heat dispersion with a simple configuration. Method (2): Method (2) switches between the first and second control states in the period of the AC power waveform output to the load 10 or an integer multiple thereof. In the example shown in FIG. 19, in the first output power period, the state of the INV at zero voltage output is set to the first control state (A), and in the next output power period, the state of the INV at zero voltage output is switched to the second control state (B). Like method (1), method (2) is a method that enables heat dispersion with a simple configuration. Furthermore, as shown in FIG. 19, it is a method that enables equal heat dispersion even under conditions where the off time changes periodically. Method (3): In method (3), the first control state and the second control state are selected and switched after a certain time has elapsed. In the example shown in Fig. 20, the time is measured, and when a certain time has elapsed (when a threshold has been reached), the state of the INV at 0 voltage output is switched from the first control state (A) to the second control state (B). Like method (1), method (3) is a method that enables heat dispersion with a simple configuration. It is also a method that enables equal heat dispersion even under conditions where the off time changes. Note that Fig. 20 shows an example of a method in which the first control state (A) and the second control state (B) are not switched directly. Therefore, the first control state (A) and the second control state (B) are switched after passing through the first conductive state (C). In Fig. 20, the time measurement is started when the measurement time reaches the threshold and the state is switched to the first conductive state (C), but the measurement timing is not limited to this. For example, the measurement may be performed immediately when the threshold is reached, or may be started from the time when the state is switched to the second control state (B). Method (4): Method (4) measures the time during the first or second control state, and when this total time reaches a certain value, the selection between the first and second control states is switched. In the example shown in FIG. 21, the time during zero voltage output is measured, and when a certain time is reached (when a threshold value is reached), the state of INV during zero voltage output is switched from the first control state (A) to the second control state (B). Compared to method (3), method (4) can distribute the off time more evenly between the first and second control states, making it possible to disperse heat more precisely. Note that FIG. 21 shows an example of a method that does not directly switch between the first control state (A) and the second control state (B). Method (5): Method (5) switches between the first and second control states when the output voltage and output current waveforms output to load 10 become zero current or zero voltage. In the example shown in Figure 22, the INV state at zero voltage output is switched from the first control state (A) to the second control state (B) when the output current becomes zero. Method (5) can reduce losses in the semiconductor switch by using zero current switching or zero voltage switching. Methods (1) to (5) can be used in any combination. For example, method (3) may be used under certain output conditions, and method (2) may be used when the output conditions change. For example, method (1) may be used normally, and when a timing for switching to method (5) occurs, the method may be set to switch to method (5).

[0021] It should be noted that methods (1) to (5) can be applied to both cases where a transition between the first control state and the second control state is made directly and where a transition is not made directly. The method (4) will be explained as an example. 23 shows a case where the transition between the first control state and the second control state is not performed directly. After a predetermined time has elapsed, the state is switched to another state, and then the state is switched to. Figure 24 shows a case where the transition between the first control state and the second control state is performed directly. The switching is performed immediately after a predetermined time has elapsed. When the zero voltage output time shown in Figures 23 and 24 is long, if direct switching is not performed, the time in the first control state or the second control state will be long, and heat generation may be concentrated. Therefore, when the zero voltage output time is long, it is desirable to perform direct switching. On the other hand, if direct switching is performed in the example of Figure 21, the number of switching operations will increase, and heat generation due to switching losses will increase, so it is preferable not to perform switching. It is desirable to select whether or not to perform direct switching by taking into consideration the heat generation caused by an increase in the number of switching operations and the influence of heat concentration caused by maintaining the same control state.

[0022] The above switching of the control unit 20 is intended to cover the operation during the period excluding the dead time period. Specifically, assuming that the semiconductor switch is a MOSFET, the switching operation of the control unit 20 is defined to cover the period during which the semiconductor switch is on and the gate voltage is applied between the gate and source of the MOSFET to turn the MOSFET on.

[0023] Although not described in this embodiment, when a transition is made from a certain control state or conduction state to a different control state or conduction state, a dead time period is inserted in which the upper and lower MOSFETs are simultaneously turned off in order to prevent a short circuit between the semiconductor switches arranged above and below. The current path during this dead time period is determined by the direction of the current, and may form a current path different from the first and second control states and the first and second conduction states described above, or may be the same path as the first and second control states or the first and second conduction states. For example, when a direct state transition is made from the first control state to the second control state, a period may occur during the dead time period in which the current path is the same as the first conduction state or the second conduction state.

[0024] The switching operation of the control unit 20 in this embodiment covers a period excluding the dead time period. In the above example of switching from the first control state to the second control state, even if the first conduction state or the second conduction state occurs during the dead time, it is treated as switching from the first control state to the second control state. The reason for excluding the dead time period is that the dead time period is generally sufficiently small compared to the on time and off time, and can be considered not to contribute to the heat dispersion that is the subject of this example. Note that if the proportion of the dead time period is large and the operation during the dead time period affects heat dissipation, the switching operation of the control unit may be performed including the dead time state.

[0025] As described above, the power conversion device of embodiment 1 includes one or more single-phase inverters connected in series to supply power to a load, and a control unit that controls the semiconductor switches of the single-phase inverters, and the control unit controls the semiconductor switches to a first control state and a second control state, and selects the first control state or the second control state when outputting zero voltage to the single-phase inverter. Therefore, the power conversion device of the first embodiment can realize dispersion of heat generated in the semiconductor switches in a single-phase inverter circuit or a multi-series inverter circuit by devising control of the inverter. Dispersing the heat allows the size of the heat sink to be reduced, which in turn allows the size of the device to be reduced. It also makes it possible to reduce the mounting area of ​​the single-phase inverter. A smaller mounting area allows for a reduction in wiring inductance caused by the wiring length. This reduces the surge voltage generated by the switching operation of the semiconductor switch. If a low-voltage semiconductor switch with good characteristics can be used, this allows for a further reduction in heat generation.

[0026] Embodiment 2 The power conversion device of the second embodiment aims to dissipate heat from the semiconductor switches by appropriately arranging the semiconductor switches.

[0027] The power conversion device of embodiment 2 will be described focusing on the differences from embodiment 1, based on Figures 5A to 5C which are semiconductor switch arrangement diagrams (basic arrangement) of a single-phase inverter, Figures 6A to 6D which are semiconductor switch arrangement diagrams (single-row arrangement) of a single-phase inverter, Figures 7A to 7C which are semiconductor switch arrangement diagrams (L-shaped arrangement) of a single-phase inverter, Figures 7D and 7E which are semiconductor switch arrangement diagrams (two-row arrangement) of a single-phase inverter, and Figures 8A to 8F which are semiconductor switch arrangement diagrams (modified example) of a single-phase inverter. In the configuration diagram of the second embodiment, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals.

[0028] In the power conversion device of the second embodiment, when semiconductor switches are arranged in one single-phase inverter INV(n), an appropriate arrangement method for achieving heat dispersion will be described. The present disclosure is characterized in that heat is dispersed by arranging, at a distance, semiconductor switch Q1(n) and semiconductor switch Q3(n), through which a current flows in a first control state of single-phase inverter INV(n), and semiconductor switch Q2(n) and semiconductor switch Q4(n), through which a current flows in a second control state. The basic layout of semiconductor switches in this disclosure is shown in FIGS. 5A to 5C. 5A shows an arrangement method for arranging the semiconductor switches in a row. By sandwiching the semiconductor switch Q2(n) or Q4(n), through which a current flows in the second control state, between the semiconductor switch Q1(n) and semiconductor switch Q3(n), through which a current flows in the first control state, the distance between the semiconductor switches that generate heat in the same control state can be increased. Figure 5B shows a layout method for arranging in two rows. Semiconductor switch Q1(n) and semiconductor switch Q3(n), or semiconductor switch Q2(n) and semiconductor switch Q4(n), are arranged diagonally across from each other in a rectangle with the semiconductor switches as vertices. This makes it possible to distance the distance between semiconductor switches that generate heat under the same control conditions. Figure 5C shows an arrangement in the case of an L-shape. Semiconductor switch Q2(n) or semiconductor switch Q4(n) is placed at the corner of the L-shape, and semiconductor switch Q1(n) and semiconductor switch Q3(n) are placed at the remaining part of the L-shape. This makes it possible to distance the semiconductor switches that generate heat under the same control conditions. In the second embodiment, by selecting and combining the above three arrangement methods, the distance between semiconductor switches that generate heat in the same control state is increased, thereby achieving dispersion of heat generation. In addition, since there is a possibility of dielectric breakdown and short circuit, it is common to arrange the semiconductor switches with a space between them, rather than arranging one side of the semiconductor switch in contact with one side of another semiconductor switch as shown in Figures 6A to 6D described later. For simplification, the spaces between the switches are ignored in the description of this disclosure. The shape of the semiconductor switch does not have to be a square as shown in the figures, and can be modified according to the package shape of the semiconductor switch.

[0029] The following describes combinations and variations of the above three arrangement methods. Figures 6A to 6D show examples of arrangements when four semiconductor switches are arranged in a row. In all of Figures 6A to 6D, semiconductor switch Q2(n) or Q4(n) is arranged between semiconductor switch Q1(n) and semiconductor switch Q3(n), and semiconductor switch Q1(n) and semiconductor switch Q3(n) are arranged between semiconductor switch Q2(n) and semiconductor switch Q4(n). This makes it possible to distance the semiconductor switches that generate heat under the same control state.

[0030] 7A to 7C are examples of arrangements when four semiconductor switches are arranged in an L shape. FIG. 7A is an example of a combination of a line arrangement and an L shape arrangement, in which semiconductor switch Q2(n) is arranged at the corner of the L shape, so that semiconductor switch Q1(n) and semiconductor switch Q3(n) are arranged at a distance from each other. In addition, semiconductor switch Q3(n) is sandwiched between semiconductor switch Q2(n) and semiconductor switch Q4(n), so that semiconductor switch Q2(n) and semiconductor switch Q4(n) are arranged at a distance from each other. FIG. 7B is also an example of a combination of a line arrangement and an L shape arrangement. It differs from FIG. 7A in that semiconductor switch Q3(n) is arranged at the corner of the L shape, but like FIG. 7A, it is possible to increase the distance between semiconductor switches that generate heat in the same control state. Figure 7C shows an example of a combination of an L-shaped arrangement and an L-shaped arrangement. By combining an L-shaped arrangement in which semiconductor switch Q2(n) is placed at a corner with an L-shaped arrangement in which semiconductor switch Q3(n) is placed at a corner, the distance between the semiconductor switches that generate heat under the same control state can be increased.

[0031] Figures 7D and 7E show examples of four semiconductor switches arranged in two rows. In both Figures 7D and 7E, semiconductor switch Q1(n) and semiconductor switch Q3(n) or semiconductor switch Q2(n) and semiconductor switch Q4(n) are arranged diagonally in a rectangle with the semiconductor switches as vertices. This makes it possible to distance the semiconductor switches that generate heat in the same control state.

[0032] Figures 8A to 8F are diagrams showing modified examples of Figures 6A to 6D and 7A to 7E. Even if the semiconductor switches are shifted up, down, left, or right, or even if the spaces between the semiconductor switches are not uniform, they can be regarded as being arranged in a single row, double rows, or an L-shape. Although Fig. 5A shows a single row arrangement, it may be considered a linear arrangement, and Fig. 5B shows a double row arrangement, but it may be considered a square, rectangle, or parallelogram.

[0033] As described above, the power conversion device of the second embodiment aims to dissipate heat from the semiconductor switches by appropriately arranging the semiconductor switches. Therefore, in the power conversion device of the second embodiment, in a single-phase inverter circuit or a multi-series inverter circuit, the heat generated in the semiconductor switches can be dispersed by devising the control of the inverter. Furthermore, the heat can be dispersed by appropriately arranging the semiconductor switches of the inverter.

[0034] Embodiment 3 The power conversion device of the third embodiment relates to selection of a first control state and a second control state among a plurality of single-phase inverters.

[0035] The power conversion device of embodiment 3 will be described with a focus on the differences from embodiment 1, based on Figures 9A and 9B which are explanatory diagrams of the operating state of multiple single-phase inverters (current path agreement) and Figures 10A and 10B which are explanatory diagrams of the operating state of multiple single-phase inverters (current path inversion). In the configuration diagram of the third embodiment, the same or corresponding parts as those in the first embodiment are given the same reference numerals.

[0036] In the power conversion device of the third embodiment, two single-phase inverters INV(i) and INV(k) will be described, where i and k are integers equal to or greater than 1, and i≠k. In the case where the inverter is composed of two or more single-phase inverters INV(n), the zero voltage output state (first control state and second control state) of one single-phase inverter INV(i) is linked to the zero voltage output state (first control state and second control state) of another single-phase inverter INV(k). In this case, the single-phase inverter INV(i) and the single-phase inverter INV(k) may select the same zero voltage output state (current path coincidence) or may select the opposite zero voltage output state (current path reversal).

[0037] First, a case where the single-phase inverters INV(i) and INV(k) select the same zero voltage output state (current path agreement) will be described with reference to Figs. 9A and 9B. Specifically, when the single-phase inverter INV(i) selects the first control state, the single-phase inverter INV(k) also selects the first control state, and when the single-phase inverter INV(i) selects the second control state, the single-phase inverter INV(k) also selects the second control state. In Fig. 9A, both of the single-phase inverters INV(i) and INV(k) select the first control state, whereas in Fig. 9B, both of the single-phase inverters INV(i) and INV(k) select the second control state.

[0038] A case where the single-phase inverters INV(i) and INV(k) select the opposite zero voltage output state (current path reversal) will be described with reference to Figs. 10A and 10B. Specifically, when the single-phase inverter INV(i) selects the first control state, the single-phase inverter INV(k) selects the second control state, and when the single-phase inverter INV(i) selects the second control state, the single-phase inverter INV(k) selects the first control state. In Fig. 10A, the single-phase inverter INV(i) selects the first control state, and the single-phase inverter INV(k) selects the second control state. In Fig. 10B, the single-phase inverter INV(i) selects the second control state, and the single-phase inverter INV(k) selects the first control state.

[0039] By selecting the first control state or the second control state as described above in a plurality of single-phase inverters, the process of selecting the first control state or the second control state by the control unit 20 is simplified. Therefore, the load on the control unit 20 can be reduced.

[0040] As described above, the power conversion device of the third embodiment is configured such that the first control state and the second control state are selected as current path coincidence or current path inversion in a plurality of single-phase inverters. Therefore, the power conversion device of the third embodiment can realize dispersion of heat generated in the semiconductor switching elements in a single-phase inverter circuit or a multi-series inverter circuit by devising inverter control. Also, the load on the control unit can be reduced.

[0041] Embodiment 4 The power conversion device of the fourth embodiment aims to dissipate heat by appropriately arranging semiconductor switches in a plurality of single-phase inverters.

[0042] The power conversion device of embodiment 4 will be described based on Figures 11A, 11B, 12A, 12B, 13A, and 13B, which are semiconductor switch arrangement diagrams (current path coincidence) of multiple single-phase inverters, and Figures 14A, 14B, 15A, 15B, 16A, and 16B, which are semiconductor switch arrangement diagrams (current path inversion) of multiple single-phase inverters, focusing on the differences from embodiment 1. In the configuration diagram of the fourth embodiment, the same or corresponding parts as those of the first embodiment are given the same reference numerals.

[0043] In the power conversion device of the fourth embodiment, two single-phase inverters INV(i) and INV(k) will be described, where i and k are integers equal to or greater than 1, and i≠k. In the case where the inverter is composed of two or more single-phase inverters INV(n), the zero voltage output state (first control state and second control state) of one single-phase inverter INV(i) is linked to the zero voltage output state (first control state and second control state) of another single-phase inverter INV(k). In this case, the single-phase inverter INV(i) and the single-phase inverter INV(k) may select the same zero voltage output state (current path coincidence) or may select the opposite zero voltage output state (current path reversal). In either case, in order to prevent the heat generated by the semiconductor switches from concentrating, the semiconductor switches that simultaneously generate heat are arranged at a distance from each other in the single-phase inverter INV(i) and the single-phase inverter INV(k). Methods of arranging the electrodes at a distance include the single-row arrangement, double-row arrangement, and L-shaped arrangement described in embodiment 2. Embodiment 4 is characterized in that the single-row arrangement, double-row arrangement, and L-shaped arrangement, or a combination of these, are extended and applied to two electrodes, INV(i) and INV(k).

[0044] First, the arrangement of the semiconductor switches when the single-phase inverters INV(i) and INV(k) select the same zero voltage output state (current paths coincident) will be described. For example, assume that both single-phase inverters INV(i) and INV(k) select the first control state. In this case, the semiconductor switches Q1(i) and Q3(i) of the single-phase inverter INV(i) generate heat, and the semiconductor switches Q1(k) and Q3(k) of the single-phase inverter INV(k) also generate heat. For this reason, the semiconductor switches Q1(i) and Q3(i) of the single-phase inverter INV(i) are arranged at a distance from the semiconductor switches Q1(k) and Q3(k) of the single-phase inverter INV(k) so that they are not adjacent to each other. For example, assume that both single-phase inverters INV(i) and INV(k) select the second control state. In this case, the semiconductor switches Q2(i) and Q4(i) of the single-phase inverter INV(i) generate heat, and the semiconductor switches Q2(k) and Q4(k) of the single-phase inverter INV(k) generate heat. For this reason, the semiconductor switches Q2(i) and Q4(i) of the single-phase inverter INV(i) and the semiconductor switches Q2(k) and Q4(k) of the single-phase inverter INV(k) are arranged at a distance from each other.

[0045] As a specific example of a case where single-phase inverters INV(i) and INV(k) select the same zero voltage output state (current path coincidence), examples of the arrangement of the semiconductor switches of single-phase inverter INV(i) and the semiconductor switches of single-phase inverter INV(k) will be described with reference to Figures 11A, 11B, 12A, 12B, 13A, and 13B. In Fig. 11A, the semiconductor switches of the single-phase inverters INV(i) and INV(k) are arranged in a row, and the single-phase inverters INV(i) and INV(k) are also arranged in a row. The semiconductor switch Q4(i) and the semiconductor switch Q2(k), which generate heat at the same time, can be separated by sandwiching the semiconductor switch Q1(k) between them. Similarly, the semiconductor switch Q3(i) and the semiconductor switch Q1(k), which generate heat at the same time, can be separated by sandwiching the semiconductor switch Q4(i) between them. In FIG. 11B, the semiconductor switches of the single-phase inverters INV(i) and INV(k) are arranged in one row, and the single-phase inverters INV(i) and INV(k) are arranged in two rows. By arranging the semiconductor switches Q1(i) and Q3(k) and the semiconductor switches Q2(i) and Q4(k) which generate heat at the same time as diagonal corners of a rectangle with the semiconductor switches as vertices, they can be arranged at a distance. Similarly, by arranging the semiconductor switches Q3(i) and Q3(k) and the semiconductor switches Q2(i) and Q2(k) which generate heat at the same time as diagonal corners of a rectangle with the semiconductor switches as vertices, they can be arranged at a distance. Similarly, by arranging the semiconductor switches Q3(i) and Q1(k) and the semiconductor switches Q4(i) and Q2(k) which generate heat at the same time as diagonal corners of a rectangle with the semiconductor switches as vertices, they can be arranged at a distance.

[0046] In Fig. 12A, the semiconductor switches of the single-phase inverters INV(i) and INV(k) are arranged in a row, and the single-phase inverters INV(i) and INV(k) are arranged at right angles (L-shape). By placing semiconductor switch Q1(k) at the corner of the L-shape, the distance between semiconductor switch Q4(i) and semiconductor switch Q2(k), which generate heat at the same time, can be increased. In FIG. 12B, the semiconductor switches of the single-phase inverters INV(i) and INV(k) are arranged in a row, and the single-phase inverters INV(i) and INV(k) are arranged in two rows with a staggered arrangement. By arranging the semiconductor switch Q3(i) at the corner of the L shape, the distance between the semiconductor switch Q2(i) and the semiconductor switch Q4(k), which generate heat at the same time, can be increased. In addition, by arranging the semiconductor switch Q3(k) at the corner of the L shape, the distance between the semiconductor switch Q4(i) and the semiconductor switch Q2(k), which generate heat at the same time, can be increased. In addition, by arranging the semiconductor switches Q3(i) and Q3(k) and the semiconductor switches Q4(i) and Q4(k), which generate heat at the same time, at diagonals of a rectangle with the semiconductor switches as vertices, the distance between them can be increased.

[0047] 13A, the semiconductor switches of the single-phase inverters INV(i) and INV(k) are arranged in two rows, and the single-phase inverters INV(i) and INV(k) are arranged in a row. The semiconductor switches Q2(i) and Q4(k), and the semiconductor switches Q3(i) and Q1(k), which generate heat at the same time, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be arranged at a distance from each other. 13B, the semiconductor switches of the single-phase inverter INV(i) are arranged in a single row, and the semiconductor switches of INV(k) are arranged in two rows, with the single-phase inverters INV(i) and INV(k) arranged in a single row. By placing the semiconductor switch Q1(k) at the corner of the L shape, the distance between the semiconductor switch Q4(i) and the semiconductor switch Q2(k), which generate heat at the same time, can be increased.

[0048] 11A, 11B, 12A, 12B, 13A, and 13B are merely examples, and the single-phase inverters may be arranged in a single row, in two rows, or in an L-shape. The single-phase inverters may also be arranged in a single row, in two rows, in an L-shape, or offset from one another. Although not shown, the intervals do not have to be constant. As described in the second embodiment, the semiconductor switches within the same single-phase inverter are arranged so that heat-generating semiconductor switches are spaced apart from each other.

[0049] Next, the arrangement of the semiconductor switches when the single-phase inverters INV(i) and INV(k) select the opposite zero voltage output state (current path reversal) will be described. For example, assume that the single-phase inverter INV(i) selects the first control state and INV(k) selects the second control state. In this case, the semiconductor switch Q1(i) and the semiconductor switch Q3(i) of the single-phase inverter INV(i) generate heat, and the semiconductor switch Q2(k) and the semiconductor switch Q4(k) of the single-phase inverter INV(k) generate heat. Therefore, the semiconductor switch Q2(k) and the semiconductor switch Q4(k) of the single-phase inverter INV(k) are arranged at a distance from the semiconductor switch Q1(i) and the semiconductor switch Q3(i) of the single-phase inverter INV(i) so that they are not adjacent to each other. For example, assume that the single-phase inverter INV(i) selects the second control state and INV(k) selects the first control state. In this case, the semiconductor switch Q2(i) and the semiconductor switch Q4(i) of the single-phase inverter INV(i) generate heat, and the semiconductor switch Q1(k) and the semiconductor switch Q3(k) of the single-phase inverter INV(k) generate heat. For this reason, the semiconductor switch Q2(i) and the semiconductor switch Q4(i) of the single-phase inverter INV(i) are arranged at a distance from the semiconductor switch Q1(k) and the semiconductor switch Q3(k) of the single-phase inverter INV(k).

[0050] As a specific example of a case where single-phase inverters INV(i) and INV(k) select different zero voltage output states (current path reversal), examples of the arrangement of the semiconductor switches of single-phase inverter INV(i) and the semiconductor switches of single-phase inverter INV(k) are shown in Figures 14A, 14B, 15A, 15B, 16A, and 16B. In Fig. 14A, single-phase inverters INV(i) and INV(k) are arranged in a line, with semiconductor switches arranged in different orders in a straight line. Semiconductor switches Q3(i) and Q4(k), which generate heat at the same time, can be spaced apart by sandwiching semiconductor switch Q4(k) between them. Similarly, semiconductor switches Q3(i) and Q4(k), which generate heat at the same time, can be spaced apart by sandwiching semiconductor switch Q4(i) between them. In Fig. 14B, single-phase inverters INV(i) and INV(k) are arranged in a line, with semiconductor switches arranged in a different order in a straight line. However, the order of the semiconductor switches in the single-phase inverter INV(k) is changed from that in Fig. 14A. The semiconductor switch Q4(i) and the semiconductor switch Q1(k), which generate heat at the same time, can be separated by sandwiching the semiconductor switch Q2(k) between them. Similarly, the semiconductor switch Q3(i) and the semiconductor switch Q2(k), which generate heat at the same time, can be separated by sandwiching the semiconductor switch Q4(i) between them.

[0051] In FIG. 15A, single-phase inverters INV(i) and INV(k) are arranged in two rows, with semiconductor switches arranged in different arrangement orders in one row. The semiconductor switches Q1(i) and Q4(k), and the semiconductor switches Q2(i) and Q1(k), which generate heat at the same time, are arranged diagonally when a rectangle is considered with the semiconductor switches as vertices, so that they can be arranged at a distance. Similarly, the semiconductor switches Q2(i) and Q3(k), and the semiconductor switches Q3(i) and Q4(k), which generate heat at the same time, are arranged diagonally when a rectangle is considered with the semiconductor switches as vertices, so that they can be arranged at a distance. Similarly, the semiconductor switches Q3(i) and Q2(k), and the semiconductor switches Q4(i) and Q3(k), which generate heat at the same time, are arranged diagonally when a rectangle is considered with the semiconductor switches as vertices, so that they can be arranged at a distance. In FIG. 15B, the single-phase inverters INV(i) and INV(k) are arranged in two rows, with the semiconductor switches arranged in a row in a different order. However, the order of the semiconductor switches of the single-phase inverter INV(k) is changed from that in FIG. 15A. The semiconductor switches Q1(i) and Q2(k), and the semiconductor switches Q2(i) and Q1(k), which generate heat at the same time, are arranged diagonally in a rectangle with the semiconductor switches as vertices, so that they can be arranged at a distance. Similarly, the semiconductor switches Q2(i) and Q3(k), and the semiconductor switches Q3(i) and Q2(k), which generate heat at the same time, are arranged diagonally in a rectangle with the semiconductor switches as vertices, so that they can be arranged at a distance. Similarly, the semiconductor switches Q3(i) and Q4(k), and the semiconductor switches Q4(i) and Q3(k), which generate heat at the same time, are arranged diagonally in a rectangle with the semiconductor switches as vertices, so that they can be arranged at a distance.

[0052] 16A shows single-phase inverters INV(i) and INV(k) in which semiconductor switches with different arrangement orders are arranged in a row at right angles (L-shape). By arranging semiconductor switch Q4(k) at the corner of the L-shape, the distance between semiconductor switch Q4(i) and semiconductor switch Q1(k), which generate heat at the same time, can be increased. In Fig. 16B, single-phase inverters INV(i) and INV(k) with semiconductor switches arranged in a row with different arrangement orders are arranged at right angles (L-shape). However, the arrangement order of the semiconductor switches of single-phase inverter INV(k) is changed from that of Fig. 16A. By arranging semiconductor switch Q2(k) at the corner of the L-shape, the distance between semiconductor switch Q4(i) and semiconductor switch Q3(k), which generate heat at the same time, can be increased.

[0053] As described above, the power conversion device of the fourth embodiment aims to dissipate heat by appropriately arranging the semiconductor switches in a plurality of single-phase inverters. Therefore, the power conversion device of the fourth embodiment can realize dispersion of heat generated in the semiconductor switching elements by devising inverter control in a single-phase inverter circuit or a multiple inverter series circuit. Furthermore, in a plurality of single-phase inverters, heat can be further dispersed by an appropriate arrangement of the semiconductor switches.

[0054] 17, an example of hardware of the control unit 20 is configured with a processor 1000 and a storage device 1001. The storage device 1001 includes a volatile storage device such as a random access memory, and a non-volatile auxiliary storage device such as a flash memory, both of which are not shown. Also, an auxiliary storage device such as a hard disk may be provided instead of a flash memory. The processor 1000 executes a program input from the storage device 1001. In this case, the program is input from the auxiliary storage device to the processor 1000 via a volatile storage device. The processor 1000 may output data such as a calculation result to a volatile storage device of the storage device 1001, or may store the data in the auxiliary storage device via the volatile storage device.

[0055] Although the present disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not exemplified are assumed within the scope of the technology disclosed in this specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component and combining it with a component of another embodiment. [Explanation of symbols]

[0056] 1 inverter unit, 10 load, 20 control unit, 100 power conversion device, 1000 processor, 1001 storage device, INV(1), INV(2), INV(3), INV(i), INV(k), INV(n) single-phase inverter, Q1(1), Q2(1), Q3(1), Q4(1), Q1(2), Q2(2), Q3(2), Q4(2), Q1(3), Q2(3), Q3(3), Q4(3), Q1(4), Q2(4), Q3(4), Q4(4), Q1(i), Q2(i), Q3(i), Q4(i), Q1(k), Q2(k), Q3(k), Q4(k), Q1(n), Q2(n), Q3(n), Q4(n) semiconductor switch, V(1), V(2), V(3), V(n) DC power supply, P1(1), P1(2), P1(3), P1(n) first midpoint, P2(1), P2(2), P2(3), P2(n) second midpoint.

Claims

1. In a single-phase inverter INV(n) where n is an integer greater than or equal to 1, One end of semiconductor switch Q1(n) and one end of semiconductor switch Q3(n) are connected to the high-potential terminal of the DC power supply V(n). One end of semiconductor switch Q2(n) and one end of semiconductor switch Q4(n) are connected to the low-voltage terminal of the DC power supply V(n). The other end of the semiconductor switch Q1(n) and the other end of the semiconductor switch Q2(n) are connected in series at the first midpoint P1(n). A single-phase inverter INV(n) is configured such that the other end of the semiconductor switch Q3(n) and the other end of the semiconductor switch Q4(n) are connected in series at the second midpoint P2(n), A load connected to the first midpoint P1(1) of the single-phase inverter INV(1) and the second midpoint P2(n) of the single-phase inverter INV(n), to which DC power or AC power is supplied, The semiconductor switches Q1(n), Q2(n), Q3(n), and Q4(n) are controlled by a control unit, The control unit has a first control state in which the semiconductor switch Q1(n) and the semiconductor switch Q3(n) are turned on, and the semiconductor switch Q2(n) and the semiconductor switch Q4(n) are turned off. The semiconductor switches Q2(n) and Q4(n) are turned on, and the semiconductor switches Q1(n) and Q3(n) are turned off, and the system is controlled to a second control state. The control unit sets semiconductor switch Q1(n) and semiconductor switch Q4(n) to an ON state and semiconductor switch Q2(n) and semiconductor switch Q3(n) to an OFF state in a first conductive state, The semiconductor switches Q2(n) and Q3(n) are controlled to an ON state, and the semiconductor switches Q1(n) and Q4(n) are controlled to an OFF state, creating a second conductive state. A power converter that selects either the first control state or the second control state when at least one of the single-phase inverters INV(n) outputs a zero voltage between the first midpoint P1(n) and the second midpoint P2(n).

2. The control unit controls at least one of the single-phase inverters INV(n), In a state in which either the first control state or the second control state is selected, After switching the semiconductor switch Q1(n) to the semiconductor switch Q4(n) at least once to the first conducting state or the second conducting state, Select either the first control state or the second control state. The power conversion device according to claim 1.

3. The control unit controls at least one of the single-phase inverters INV(n), From a state in which either the first control state or the second control state is selected, After switching the semiconductor switch Q1(n) to the semiconductor switch Q4(n) from the first conductive state to the second conductive state, Select the other of the first control state or the second control state. The power conversion device according to claim 2.

4. The control unit controls at least one of the single-phase inverters INV(n), During at least one period in which a zero voltage is output between the first midpoint P1(n) and the second midpoint P2(n) of the single-phase inverter INV(n), The first control state and the second control state are switched at least once. The power conversion device according to claim 1.

5. In at least one of the single-phase inverters INV(n), at least three of the semiconductor switches Q1(n), Q2(n), Q3(n), and Q4(n) are arranged in a row, and either the semiconductor switch Q2(n) or the semiconductor switch Q4(n) is placed between the semiconductor switch Q1(n) and the semiconductor switch Q3(n). Alternatively, either semiconductor switch Q1(n) or semiconductor switch Q3(n) is placed between semiconductor switch Q2(n) and semiconductor switch Q4(n). A power conversion device according to any one of claims 1 to 4.

6. In at least one of the single-phase inverters INV(n), the semiconductor switches Q1(n), Q2(n), Q3(n), and Q4(n) are arranged in two rows, and the semiconductor switches Q1(n) and Q3(n) and Q2(n) and Q4(n) are arranged diagonally when considering a rectangle with each of the semiconductor switches as its vertices. A power conversion device according to any one of claims 1 to 4.

7. In at least one of the single-phase inverters INV(n), at least three of the semiconductor switches Q1(n), Q2(n), Q3(n), and Q4(n) are arranged in an L-shape, with one semiconductor switch Q1(n) or Q3(n) placed at the corner of the L-shape, and two semiconductor switches Q2(n) or Q4(n) placed on the other two sides of the L-shape. Alternatively, semiconductor switch Q2(n) or semiconductor switch Q4(n) may be placed at the corner of the L-shape, and semiconductor switch Q1(n) or semiconductor switch Q3(n) may be placed on two different sides of the L-shape. A power conversion device according to any one of claims 1 to 4.

8. Let n be an integer greater than or equal to 2, and i and k be integers greater than or equal to 1 such that i ≠ k. The control unit, when at least two single-phase inverters INV(n) output zero voltage simultaneously, If one single-phase inverter INV(i) has selected the first control state, the remaining single-phase inverter INV(k) also selects the first control state. The power conversion device according to any one of claims 1 to 4, wherein if one of the single-phase inverters INV(i) selects the second control state, the remaining single-phase inverters INV(k) also select the second control state.

9. Let n be an integer greater than or equal to 2, and i and k be integers greater than or equal to 1 such that i ≠ k. The control unit, when at least two single-phase inverters INV(n) output zero voltage simultaneously, If one single-phase inverter INV(i) has selected the first control state, then at least one of the remaining single-phase inverters INV(n), INV(k), has selected the second control state. The power converter according to any one of claims 1 to 4, wherein if one of the single-phase inverters INV(i) selects the second control state, at least one of the remaining single-phase inverters INV(n) selects the first control state.

10. When n is an integer of 2 or more, i and k are integers of 1 or more, and i ≠ k, In the case where, for at least two of the one or more single-phase inverters INV(n), at least a portion of the semiconductor switches Q1(n) to Q4(n) included in each single-phase inverter INV(n) are arranged in a single row, a double row, or an L-shape, and each of the single-phase inverters INV(n) simultaneously outputs zero voltage, If one single-phase inverter INV(i) has selected the first control state, then the other single-phase inverter INV(k) also selects the first control state. If one of the single-phase inverters INV(i) selects the second control state, the other single-phase inverter INV(k) also selects the second control state. When the first control state is selected, the semiconductor switches Q1(n) and Q3(n) of the single-phase inverter INV(n) generate heat. When the second control state is selected, the semiconductor switches Q2(n) and Q4(n) of the single-phase inverter INV(n) generate heat. At least a portion of the semiconductor switches of one single-phase inverter INV(n) and the semiconductor switches of the other single-phase inverter INV(n) are arranged in a single row, a double row, or an L-shape. In the arrangement between different single-phase inverters INV(n), the semiconductor switches that generate heat in the first control state or the second control state are arranged so that they are not adjacent to each other, with the semiconductor switch that generates heat in the other first control state or the second control state being sandwiched in between. A power conversion device according to any one of claims 1 to 4.

11. When n is an integer of 2 or more, i and k are integers of 1 or more, and i ≠ k, In the case where, for at least two of the one or more single-phase inverters INV(n), at least a portion of the semiconductor switches Q1(n) to Q4(n) included in each single-phase inverter INV(n) are arranged in a single row, a double row, or an L-shape, and each single-phase inverter INV(n) simultaneously outputs zero voltage, If one single-phase inverter INV(i) selects the first control state, the other single-phase inverter INV(k) selects the second control state. When one of the single-phase inverters INV(i) selects the second control state, the other single-phase inverter INV(k) selects the first control state. When the first control state is selected, the semiconductor switches Q1(n) and Q3(n) of the single-phase inverter INV(n) generate heat. When the second control state is selected, the semiconductor switches Q2(n) and Q4(n) of the single-phase inverter INV(n) generate heat. At least a portion of the semiconductor switches of one single-phase inverter INV(n) and the semiconductor switches of the other single-phase inverter INV(n) are arranged in a single row, a double row, or an L-shape. In the arrangement between different single-phase inverters INV(n), the semiconductor switches that generate heat in the first control state or the second control state are arranged so that they are not adjacent to each other, with the semiconductor switch that generates heat in the other first control state or the second control state being sandwiched in between. A power conversion device according to any one of claims 1 to 4.

12. The control unit switches between selecting the first control state or the second control state for at least one of the single-phase inverters at intervals equal to or an integer multiple of the control unit's control cycle. A power conversion device according to any one of claims 1 to 4.

13. In a single-phase inverter that supplies AC power to the aforementioned load, The control unit controls the period of the AC power waveform output to the load from one or more single-phase inverters. For at least one of the single-phase inverters, The selection of the first control state or the second control state is switched at intervals that are integer multiples of the period of the AC power waveform. A power conversion device according to any one of claims 1 to 4.

14. The control unit switches the selection of the first control state or the second control state for at least one of the single-phase inverters after a certain period of time has elapsed. A power conversion device according to any one of claims 1 to 4.

15. The control unit switches the selection of the first control state or the second control state for at least one of the single-phase inverters when the total time during which the first control state or the second control state is selected matches the specified time. The power conversion device according to claim 14.

16. In a single-phase inverter that supplies AC power to the aforementioned load, The control unit switches between the first control state and the second control state for at least one of the single-phase inverters when the waveform supplied to the load is zero current or zero voltage. A power conversion device according to any one of claims 1 to 4.

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