Three-dimensional memory device and method of forming three-dimensional memory device

Abstract

Embodiments of a three-dimensional (3D) memory device and a method for forming the 3D memory device are disclosed. In the example, the 3D memory device includes a film stack having a plurality of pairs of conductive and dielectric layers stacked vertically on a substrate. Each pair of conductive and dielectric layers includes a dielectric layer and a conductive layer. The 3D memory device also includes a stepped region having a first stepped structure and a second stepped structure formed in the film stack, wherein both the first and second stepped structures extend laterally in a first direction and include a plurality of pairs of conductive and dielectric layers. The stepped region also includes stepped bridges connecting the first and second stepped structures.

Description

Three-dimensional memory device and method for forming a three-dimensional memory device The present disclosure relates generally to the field of semiconductor technology, and more particularly to methods for forming three-dimensional (3D) memory devices. As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells. In 3D NAND memory, storage cells can be stacked vertically to increase the storage capacity per unit area, where the storage cells can be addressed from a common word line. In order to access the word lines of the vertically stacked storage cells, a staircase structure can be formed at one or both edges of the storage array. However, in order to further increase the storage capacity of 3D NAND memory, the number of storage cells and the size of the storage array have been greatly increased. As a result, the distance between the storage cells in the middle of the storage array and the electrical connections at the ends of the word lines is increased, resulting in greater parasitic resistance and slower read / write speeds. Therefore, there is a need to improve the staircase structure in 3D NAND memory to achieve higher storage density without sacrificing performance. Embodiments of three-dimensional (3D) memory devices and methods of forming the same are described in this disclosure. One aspect of the present disclosure provides a three-dimensional (3D) memory device. In an example, the 3D memory device includes a film stack having a plurality of pairs of conductive layers and dielectric layers stacked vertically on a substrate. Each pair of conductive layers and dielectric layers includes a dielectric layer and a conductive layer. The 3D memory device also includes a stepped region having a first stepped structure and a second stepped structure formed in the film stack, wherein the first stepped structure and the second stepped structure both extend laterally in a first direction and include a plurality of pairs of conductive layers and dielectric layers. The stepped region also includes a stepped bridge connecting the first stepped structure and the second stepped structure. In some embodiments, the step bridge includes a plurality of pairs of conductive layers and dielectric layers. In some embodiments, the step bridge is configured to electrically connect a conductive layer in each pair of conductive layers and dielectric layers in the first stepped structure with a conductive layer in a corresponding pair of conductive layers and dielectric layers in the second stepped structure. In some embodiments, the step bridge extends laterally in the first direction and has a width that is smaller than a width of the first step structure and the second step structure. In some embodiments, the step bridge extends laterally in a second direction perpendicular to the first direction and has a first surface that is longer than a second surface opposite the first surface. In some embodiments, the 3D memory device further includes a plurality of storage strings vertically penetrating the film stack layer, wherein each of the plurality of storage strings includes a core-fill film, a channel layer surrounding the core-fill film, and a storage film surrounding the channel layer. In some embodiments, the plurality of storage strings are distributed on opposite sides of the first stepped region. In some embodiments, the first stepped structure and the second stepped structure are symmetrical to each other along the first direction. In some embodiments, the 3D memory device further includes a plurality of contact structures electrically connected to the conductive layers of the first and second stepped structures. In some embodiments, a first subset of the plurality of contact structures is formed on the conductive layer of the first stepped structure, and a second subset of the plurality of contact structures is formed on the conductive layer of the second stepped structure, wherein the second subset of the plurality of contact structures is different from the first subset of the plurality of contact structures. In some embodiments, the first stepped region is centered in the memory array of the 3D memory device. In some embodiments, the 3D memory device further comprises one or more bottom select gate (BSG) cuts that divide the memory array into two or more sub-blocks, each sub-block comprising a sub-BSG. In some embodiments, the one or more BSG cuts vertically penetrate the pair of one or more conductive layers and dielectric layers at the bottom portion of the film stack. In some embodiments, the 3D memory device further includes a second stepped region having a third stepped structure and a fourth stepped structure formed in the film stack layer. The third stepped structure and the fourth stepped structure extend laterally in the first direction. The 3D memory device further includes a second stepped bridge connecting the third stepped structure and the fourth stepped structure. The stepped bridge and the second stepped bridge are on opposite sides of the first stepped region and the second stepped region, respectively. Another aspect of the present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes providing an alternating dielectric material stack on a substrate, wherein the alternating dielectric material stack includes a plurality of dielectric layer pairs. Each dielectric layer pair includes a first dielectric layer and a second dielectric layer different from the first dielectric layer. The method also includes forming a first dielectric step, a second dielectric step, and a dielectric bridge in the alternating dielectric material stack, wherein the first dielectric step and the second dielectric step are connected by a dielectric bridge. In some embodiments, the method further includes replacing a second dielectric layer in the alternating stack of dielectric materials with a conductive layer to form a film stack of alternating conductive and dielectric layers. In some embodiments, the method further includes forming a plurality of contact structures on the conductive layer of the film stack. In some embodiments, the method further includes: providing a first dielectric layer and a second dielectric layer on the substrate before providing the alternating dielectric material stack layers; and forming one or more bottom select gate (BSG) cuts extending vertically through the first dielectric layer and the second dielectric layer into the substrate. In some embodiments, the method further includes forming a plurality of storage strings vertically penetrating the alternating dielectric material stack layers, wherein the plurality of storage strings each include a core fill film, a channel layer surrounding the core fill film, and a storage film surrounding the channel layer. In some embodiments, forming the plurality of storage strings includes forming the plurality of storage strings on opposite sides of the first dielectric step and the second dielectric step. Those skilled in the art can understand other aspects of the present disclosure based on the description, patent application scope and drawings of the present disclosure. Although specific configurations and arrangements have been discussed, it will be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications. Note that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it would be within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described. Generally, terms can be understood based, at least in part, on their use in context. For example, depending, at least in part, on the context, the terms "one or more" as used herein can be used to describe any feature, structure, or characteristic in the singular sense, or can be used to describe a combination of features, structures, or characteristics in the plural sense. Similarly, depending, at least in part, on the context, terms such as "one" or "the" can likewise be understood to convey singular usage or to convey plural usage. Additionally, also depending, at least in part, on the context, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and can instead allow for the presence of additional factors that are not necessarily clearly described. It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers. Furthermore, “above” or “over” means not only “above” or “over” something, but also includes “above” or “over” something with no intervening features or layers (i.e., directly on something). Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as depicted in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or process steps in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly in a similar manner. As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate includes a "top" surface and a "bottom" surface. Unless otherwise indicated, the top surface of the substrate is typically where the semiconductor device is formed, and thus the semiconductor device is formed at the top side of the substrate. The bottom surface is opposite the top surface, and thus the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer. As used herein, the term "layer" refers to a portion of a material comprising a region having a thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer may extend over the entire underlying or overlying structure, or may have an extent smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, or / and along a tapered surface. A substrate may be a single layer, may include one or more layers therein, and / or may have one or more layers thereon, above, or / and below it. A layer may comprise multiple layers. For example, an interconnect layer may include one or more conductive layers and a contact layer (in which contacts, interconnects, or / and vertical interconnect accesses (VIAs) are formed), and one or more dielectric layers. In this disclosure, for ease of description, the term "step" is used to refer to elements with substantially uniform heights along the vertical direction. For example, a word line and the underlying gate dielectric layer may be referred to as a "step," a word line and the underlying insulating layer may be collectively referred to as a "step," and word lines of substantially uniform height may be referred to as "word line steps," or similar. As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter of a component or process step set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​may be attributable to minor variations in the manufacturing process or tolerances. As used herein, the term "approximately" indicates a value of a given amount that may vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "approximately" may indicate a value of a given amount that varies within, for example, 10%-30% of the value (e.g., ±10%, ±20%, or ±30% of the value). In this disclosure, the terms “horizontal / horizontally / lateral / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “perpendicularly” mean nominally perpendicular to the lateral surface of the substrate. As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "string," such as a NAND string) on ​​a laterally oriented substrate, such that the string extends in a vertical direction relative to the substrate. FIG1 shows a top view of an exemplary three-dimensional (3D) memory device 100 according to some embodiments of the present disclosure. The 3D memory device 100 can be a memory chip (package), a memory die, or any portion of a memory die, and can include one or more memory planes 101. Each memory plane 101 can include a plurality of memory blocks 103. Identical and parallel operations can be performed on each memory plane 101. A memory block 103, which can be megabytes (MB) in size, is the minimum size for performing erase operations. As shown in FIG1 , the exemplary 3D memory device 100 includes four memory planes 101, with each memory plane 101 including six memory blocks 103. Each memory block 103 can include a plurality of memory cells, each of which can be addressed via interconnects such as bit lines and word lines. The bit lines and word lines can be arranged vertically (e.g., in columns and rows, respectively), forming an array of metal lines. In FIG1 , the directions of the bit lines and word lines are labeled "BL" and "WL." In this disclosure, the storage block 103 is also referred to as a “storage array” or “array.” The storage array is the core area of ​​a memory device that performs storage functions. 3D memory device 100 also includes a peripheral region 105, which is the area surrounding memory plane 101. Peripheral region 105 includes a number of digital, analog, and / or mixed-signal circuits used to support the functions of the memory array, such as page buffers, row and column decoders, and sense amplifiers. As will be apparent to those skilled in the art, the peripheral circuits utilize active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, and the like. It should be noted that the arrangement of the storage planes 101 in the 3D memory device 100 and the arrangement of the storage blocks 103 in each storage plane 101 shown in FIG. 1 are merely examples and do not limit the scope of the present disclosure. Referring to FIG. 2 , an enlarged top view of region 108 in FIG. 1 is shown according to some embodiments of the present disclosure. Region 108 of the 3D memory device 100 may include a step region 210 and a channel structure region 211 . The channel structure region 211 may include an array of storage strings 212 each including a plurality of stacked storage cells. The step region 210 may include a step structure (see FIG. 3 ) and an array of contact structures 214 formed on the step structure. In some embodiments, a plurality of slit structures 216 extending across the channel structure region 211 and the step region 210 in the WL direction may divide the storage block into a plurality of storage fingers 218 . At least some of the slit structures 216 may serve as a common source contact for the array of storage strings 212 in the channel structure region 211 . A top select gate cutout 220 can be provided, for example, in the middle of each storage finger 218 to divide the top select gate (TSG) of the storage finger 218 into two parts, thereby dividing the storage finger into two storage slices 224, wherein the storage cells in the storage slice 224 that share the same word line form a programmable (read / write) storage page. Although the erase operation of the 3D NAND memory can be performed at the storage block level, the read and write operations can be performed at the storage page level. The size of the storage page can be kilobytes (KB). In some embodiments, the area 108 also includes a dummy storage string 222 for controlling process variations during manufacturing and / or for additional mechanical support. FIG3 shows a perspective view of a portion of an exemplary three-dimensional (3D) memory array structure 300 according to some embodiments of the present disclosure. Memory array structure 300 includes a substrate 330, an insulating film 331 above substrate 330, a step of a lower select gate (LSG) 332 above insulating film 331, and a plurality of steps of control gates (also referred to as "word lines (WL)"), such as word line 333. The steps of the plurality of control gates (such as word line 333) are stacked on top of LSG 332 to form a film stack 335 of alternating conductive and dielectric layers. For clarity, the dielectric layer adjacent to the steps of the control gates is not shown in FIG3. The control gates of each step are separated by gap structures 216-1 and 216-2 that extend through the film stack 335. The memory array structure 300 also includes a step of top select gates (TSGs) 334 above the stack of control gates (e.g., word lines 333). The stack of TSGs 334, control gates (e.g., word lines 333), and LSGs 332 is also referred to as a "gate electrode." The memory array structure 300 also includes memory strings 212 and doped source line regions 344 in the portion of substrate 330 between adjacent LSGs 332. Each memory string 212 includes a channel hole 336 extending through the insulating film 331 and the film stack 335 of alternating conductive and dielectric layers. The memory strings 212 also include a storage film 337 on the sidewalls of the channel hole 336, a channel layer 338 above the storage film 337, and a core fill film 339 surrounded by the channel layer 338. A memory cell 340 can be formed at the intersection of a control gate (e.g., word line 333) and a memory string 212. The portion of the channel layer 338 below the control gate (e.g., word line 333) is also referred to as the channel of the memory cell 340. The memory array structure 300 also includes a plurality of bit lines (BLs) 341 connected to the memory strings 212 above the TSGs 334. The memory array structure 300 also includes a plurality of metal interconnects 343 connected to the gate electrodes via a plurality of contact structures 214. The edges of the film stack 335 are configured in a stepped shape to allow electrical connection to each step of the gate electrode. In FIG. 3 , for illustrative purposes, steps of three control gates (e.g., word line 333-1, word line 333-2, and word line 333-3) are shown along with a step of a TSG 334 and a step of an LSG 332. In this example, each storage string 212 can include three storage cells 340-1, 340-2, and 340-3 corresponding to the control gates (e.g., word line 333-1, word line 333-2, and word line 333-3), respectively. In some embodiments, the number of control gates and the number of storage cells can be greater than three to increase storage capacity. The storage array structure 300 can also include other structures, such as TSG cutouts, common source contacts, and dummy storage strings. For clarity, these structures are not shown in FIG. 3 . To pursue higher storage capacity in 3D memory, the number of memory cells 340 and the size of the memory block 103 (in FIG. 1 ) or the channel structure region 211 (in FIG. 3 ) have been significantly increased. As a result, the distance from the memory cell 340 in the middle of the memory block 103 or the channel structure region 211 to the contact structure 214 at the end of the word line 333 has also increased, leading to greater parasitic resistance and slower read / write speeds. To address this issue, a staircase structure can be formed in the middle of the memory block 103 (or the channel structure region 211), wherein a set of contact structures 214 and metal interconnects 343 can be formed for each set of staircase structures. However, the layout of the metal interconnects 343 is complex to electrically connect the word line 333 located in the middle of the memory block 103 and the word line driver circuitry located in the peripheral region 105, causing wiring congestion and increasing manufacturing costs. The present disclosure provides a staircase structure for 3D NAND memory that can be placed in the center of a memory array with reduced wiring congestion and better area efficiency. Thus, the number of metal interconnects and manufacturing costs can be reduced. FIG4 shows a perspective view of a 3D memory structure 400 according to some embodiments of the present disclosure. 3D memory structure 400 includes a stepped region similar to the stepped region 210 discussed above with reference to FIG2 and FIG3. FIG5 shows a top view of a 3D storage array 500 according to some embodiments of the present disclosure. The stepped region 210 of the 3D memory structure 400 can be arranged in the middle of the 3D storage array 500. The 3D storage array 500 can be any portion of the storage block 103 in FIG1. Referring to FIG. 4 , a 3D memory structure 400 includes a substrate (e.g., substrate 330 in FIG. 3 ) and a film stack of alternating conductive and dielectric layers (e.g., film stack 335 in FIG. 3 ) disposed on the front surface 330 f of substrate 330. In some embodiments, substrate 330 may provide a platform for forming subsequent structures. In some embodiments, subsequent structures are formed in a vertical direction (e.g., the z-direction perpendicular to the front surface of substrate 330). In FIG. 4 , the x- and y-directions are along a plane parallel to the front surface 330 f of the substrate and parallel to the corresponding word line (WL) and bit line (BL) directions shown in FIG. 1 through FIG. 3 . In some embodiments, substrate 330 may be any suitable semiconductor substrate comprising any suitable semiconductor material (e.g., single crystal, polycrystalline, or monocrystalline semiconductor). For example, substrate 330 may include silicon, silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, substrate 330 may include a layer of semiconductor material formed on a handle wafer, such as glass, plastic, or another semiconductor substrate. The front surface 330f of the substrate 330 is also referred to herein as the "major surface" or "top surface" of the substrate. Layers of material may be disposed on the front surface 330f of the substrate 330. The "topmost" or "upper layer" is the layer that is farthest or further from the front surface 330f of the substrate. The "bottommost" or "lower layer" is the layer that is closest or closer to the front surface 330f of the substrate. In some embodiments, film stack 335 includes a plurality of conductive layers 454 and dielectric layers 456 stacked alternately on top of each other. Film stack 335 may extend in a lateral direction parallel to front surface 330 f of substrate 330 , while conductive layers 454 and dielectric layers 456 may alternate in a vertical direction. In other words, except for the layer at the bottom of film stack 335 , each conductive layer 454 may be sandwiched between two dielectric layers 456 , and each dielectric layer 456 may be sandwiched between two conductive layers 454 . Conductive layers 454 may all have the same thickness or different thicknesses. Similarly, dielectric layers 456 may all have the same thickness or different thicknesses. In some embodiments, conductive layers 454 may include a conductive material such as W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, silicide (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof. Dielectric layer 456 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, dielectric layer 456 may also include a high-k dielectric material such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or / and any combination thereof. The formation of film stack 335 can include configuring dielectric layers 456 to all have the same thickness or to have different thicknesses. Exemplary thicknesses of dielectric layers 456 can range from 10 nm to 500 nm, preferably about 25 nm. Similarly, conductive layers 454 can all have the same thickness or to have different thicknesses. Exemplary thicknesses of conductive layers 454 can range from 10 nm to 500 nm, preferably about 35 nm. It should be understood that the number of conductive layers 454 and dielectric layers 456 in FIG. 4 is for illustrative purposes only, and that film stack 335 can include any suitable number of layers. In some embodiments, film stack 335 can include layers other than conductive layers 454 and dielectric layers 456, and can be made of different materials and / or have different thicknesses. In some embodiments, similar to the memory cells 340 and memory strings 212 in FIG. 3 , the 3D memory structure 400 may also include a plurality of memory cells stacked vertically into a string. As shown in FIG. 4 , the strings 212 extend through a film stack 335 , where each string 212 may include a core-fill film 339 , a channel layer 338 , and a storage film 337 (similar to those in FIG. 3 ). The core-fill film 339 may be at the center of the string 212 . The channel layer 338 surrounds the core-fill film 339 , and the storage film 337 surrounds the channel layer 338 . In some embodiments, the channel layer 338 comprises silicon, such as amorphous silicon, polycrystalline silicon, or single-crystalline silicon. In some embodiments, the storage film 337 is a composite layer comprising a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. Each string 212 may have a cylindrical shape (e.g., a pillar). In some embodiments, the channel layer 338, tunneling layer, storage layer, and barrier layer may be arranged in this order, extending from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon nitride, or any combination thereof. The barrier layer may include silicon oxide, silicon nitride, a high-k dielectric material, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the storage film 337 includes an ONO dielectric material (e.g., a tunneling layer including silicon oxide, a storage layer including silicon nitride, and a barrier layer including silicon oxide). In some embodiments, conductive layer 454 can serve as a control gate or word line 333 for memory cell 340. As shown in FIG. 4 , memory string 212 can also include one or more lower select gates 332 (e.g., source select gates or bottom select gates) at the lower end (i.e., source terminal) of the memory string 212. String 212 can also include one or more top select gates 334 (e.g., drain select gates) at the upper end (i.e., drain terminal) of the memory string 212. As used herein, the "upper end" of a component (e.g., a memory string 212) is the end vertically farther from substrate 330, and the "lower end" of a component (e.g., a memory string 212) is the end vertically closer to substrate 330. As shown in FIG. 4 , for each memory string 212, a top select gate 334 can be above the lower select gate 332. FIG. 4 illustrates one lower select gate 332 and one top select gate 334 in the film stack 335. It should be understood that any suitable number of conductive layers 454 in the film stack 335 may serve as the lower select gate 332 and one top select gate 334 . In some embodiments, the 3D memory structure 400 may include one or more stepped structures in the stepped region 210, wherein each of the conductive layers 454 terminates at a different length in the horizontal x-direction. In some embodiments, the top select gate 334 is the shortest and the lower select gate 332 is the longest. In some embodiments, the 3D memory structure 400 further includes a plurality of contact structures similar to the contact structures 214 in Figures 2 and 3. The top selection gate 334, the word line 333, and the lower selection gate 332 can be electrically connected to one or more contact structures 214. The metal interconnect lines formed in the back-end process can be electrically connected to each conductive layer 454 through the contact structure 214. Therefore, by using a stepped structure, each storage cell 340 in the 3D memory structure 400 can be controlled to perform a read, write, or erase operation through the corresponding word line 333. In some embodiments, the contact structure 214 can include any suitable conductive material, for example, W, Ti, TiN, Cu, TaN, Al, Co, Ni, or any combination thereof. In some embodiments, the stepped region 210 can include two stepped structures 210-L and 210-R that are symmetrical to each other along the y-direction. In some embodiments, a first subset of contact structures is formed on the conductive layer of the first stepped structure, and a second subset of contact structures is formed on the conductive layer of the second stepped structure. The second subset of contact structures is different from the first subset of contact structures. In some embodiments, a contact structure 214 can be formed for each other conductive layer 454 in each stepped structure. For example, for the stepped structure 210-R, the contact structure 214 can be formed to electrically contact the odd-numbered word lines 333-1, 333-3, 333-5, 333-7, 333-9..., and for the stepped structure 210-L, the contact structure 214 can be formed to electrically contact the even-numbered word lines 333-2, 333-4, 333-6, 333-8... As a result, the minimum spacing between the contact structures 214 on different word lines 333 can be increased (e.g., doubled). s. Therefore, the process tolerance of the contact structure 214 can be increased and the manufacturing yield can be improved. It should be noted that each stepped structure can include any suitable number of contact structures 214 on the conductive layer 454 and is not limited to one contact structure as shown in FIG. 4 . In some embodiments, the stepped region 210 can be located anywhere within the storage array. In some embodiments, the stepped region 210 can be located at the center of the storage array. For example, the stepped region 210 can be placed within a 3D storage array 500, where the 3D storage array 500 can be any portion of the storage block 103 in FIG. 1 . Referring to FIG. 4 and FIG. 5 , the storage strings 212 within the channel structure region 211 can be distributed on opposite sides of the stepped region 210 along the x-direction. In some embodiments, the 3D memory structure 400 further includes a ladder bridge 450 extending along the x-direction parallel to the word lines 333. In the x-direction, the ladder bridge 450 is longer at the top and shorter at the bottom, where the top and bottom are relative to the distance from the substrate. The ladder bridge 450 has a width w in the y-direction that is less than the total width of the ladder structure 210-L and the ladder structure 210-R. The ladder bridge 450 can connect corresponding word lines 333 between the ladder structure 210-L and the ladder structure 210-R. For example, a word line 333 in the ladder structure 210-L and a corresponding word line 333 in the ladder structure 210-R can be electrically connected via the ladder bridge 450, where the word lines 333 are formed from the same conductive layer 454. Therefore, for each staircase region 210, only a set of word line drivers having a set of interconnecting metal lines is required to address each word line 333, where each word line 333 can be electrically connected to at least one contact structure 214 from either staircase structure 210-L or staircase structure 210-R. In some embodiments, a step bridge 450 may also be formed in the film stack 335 and may further include a plurality of conductive layers 454 and a plurality of dielectric layers 456. In this example, the step bridge 450 may be vertically disposed on the stepped structure 210-L and the stepped structure 210-R, wherein the bottom of the step bridge 450 may contact the bottom select gate 332. In some embodiments, the step bridge 450 connects only the word line 333 between the stepped structure 210-L and the stepped structure 210-R. In some embodiments, the step bridge 450 may also connect the top select gate 334 between the stepped structure 210-L and the stepped structure 210-R. In some embodiments, step bridge 450 can include a different conductive material than conductive layer 454. In some embodiments, step bridge 450 can include a different thickness than conductive layer 454. In some embodiments, the 3D memory structure 400 further includes one or more back select gate (BSG) cutouts 446. These cutouts 446 can separate the lower select gate 332 (also referred to as a back select gate) into two or more sub-BSGs 332-1, 332-2, 332-3, ..., wherein the sub-BSGs 332-1, 332-2, 332-3, ... are electrically isolated from each other. Referring to FIG. 4 and FIG. 5 , in some embodiments, the BSG cutouts 446 and the sub-BSGs 332-1, 332-2, 332-3, ... extend along the x-direction and can partition the memory array 500 into a plurality of sub-blocks 448. By introducing the BSG cuts 446, the storage blocks of the 3D memory device (e.g., the storage block 103 in FIG. 1 and the storage array 500 in FIG. 5) can have improved bottom select transistors (BSTs) due to the reduced parasitic capacitance and coupling effects between the BSG 332 and the adjacent dielectric layers. In addition, the partitioned BSG structure allows erasing of specific sub-blocks rather than the entire storage block 103. Therefore, the erase time and data transfer time can be significantly reduced, and data storage efficiency can also be improved. For illustrative purposes only, FIG. 4 and FIG. 5 show two BSG cuts 446 and three sub-blocks 448. Note that the BSG cuts 446 and sub-blocks 448 can have any suitable number and are not limited thereto. As shown in the example of FIG. 5 , in some embodiments, the step bridge 450 has a width of w is smaller than the width of sub-block 448 d, so that at least one contact structure 214 (eg, contact structure 214 -L) may be formed on each of the sub-BSGs 332 - 1 , 332 - 2 , 332 - 3 . . . in the stepped region 210 . In some embodiments, the 3D memory structure 400 may further include one or more top select gate (TSG) cutouts 220. The TSG cutouts 220 may separate the TSG 334 into two or more sub-TSGs 334-1, 334-2, 334-3, ..., and may divide each memory block 103 into memory slices 224. As shown in the example of FIG. 4 , in some embodiments, the 3D memory structure 400 may have the same number of TSG cutouts 220 and BSG cutouts 446, and the TSG cutouts 220 and BSG cutouts 446 may be aligned with each other. In some embodiments, such as in the 3D memory array 500 of FIG. 5 , the 3D memory structure 400 may have more TSG cutouts 220 than BSG cutouts 446. In this example, the TSG cutouts 220 may further divide the sub-block 448 into two or more memory slices 224. In some embodiments, for each stepped structure 210-L / 210-R, a contact structure 214-T can be formed on each sub-TSG 334-1, 334-2, 334-3, ... In some embodiments, a step bridge 450 can also be formed to electrically connect one or more sub-TSGs 334 of the two stepped structures 210-L and the stepped structure 210-R. In some embodiments, each storage slice 224 can be read or programmed independently by controlling the corresponding sub-TSG. In this way, the reading / programming time can be reduced, and the data transmission and storage efficiency can be improved. For illustrative purposes, three TSG cuts 220 in each stepped structure are shown in FIG. 4. It should be noted that the TSG cuts 220 can have any suitable number and are not limited thereto. In some embodiments, the 3D memory structure 400 may be filled with any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, SiOCN, or any combination thereof. For example, the insulating material may be filled between the contact structures 214 and within the BSG cutout 446 and TSG cutout 220 in the step region 210. For simplicity, all insulating materials are omitted in FIG. 4 . The step bridge 450 may be provided anywhere in the step region 210. Figures 4 and 5 illustrate a configuration in which the step bridge 450 is provided on a sub-block 448-1 near the gap structure 216 or near the edge of the storage array 500. In some embodiments, the step bridge 450 may be provided at the center of the step region 210, such as in the sub-block 448-2. To reduce resistance, in some embodiments, the width of the step bridge 450 is w can be designed to be wider than the width shown in Figures 4 and 5. In this example, when the width of the step bridge 450 is w is close to the width of sub-block 448 d, the process tolerance for forming the contact structure 214 -L on one or more sub-BSGs 332 may be too small. FIG6 shows a top view of a 3D storage array 600 according to some embodiments of the present disclosure. The 3D storage array 600 may include two or more step regions 210-1, 210-2, ..., wherein the step regions 210-1, 210-2, ... may be arranged at the center of the 3D storage array 600. The 3D storage array 600 may be any portion of the storage block 103 in FIG1. ​​The storage strings 212 and the channel structure regions 211 may be arranged on opposite sides of the step regions 210-1, 210-2, ... along the x-direction. In this example, the width of the step bridge 450 is w is close to or greater than the width of sub-block 448 d. Step bridges 450 can be provided on different sub-blocks 448 in two or more step regions, so that at least one contact structure 214 can be formed for each sub-BSG. For example, as shown in FIG. 6 , step bridge 450-1 in step region 210-1 can be provided in sub-block 448-1, and step bridge 450-2 in step region 210-2 can be provided in sub-block 448-3. Thus, at least one contact structure 214-L can be formed on each sub-BSG in each sub-block 448. It should be noted that the configuration of 3D memory array 600 in FIG. 6 is exemplary. Other arrangements of step regions 210 can also be formed in 3D memory array 600. In some embodiments, the step bridge 450 may be implemented in various stepped structures to form a stepped region in the center of the storage array. 7A and 7B illustrate a stepped structure 700A and a stepped structure 700B according to some embodiments of the present disclosure, wherein for the 3D storage array 600 shown in FIG. 6 , the stepped structure 700A may be used for the stepped region 210 - 1 and the stepped structure 700B may be used for the stepped region 210 - 2 , or vice versa. In this example, stepped structure 700A can provide electrical connection to word lines 333 in the upper portion of film stack 335, and stepped structure 700B can provide electrical connection to word lines 333 in the lower portion of film stack 335. Stepped structure 700A includes a first set of stepped steps 760, and stepped structure 700B includes a second set of stepped steps 762 that are vertically offset relative to the first set of stepped steps by a distance V. 偏移量 For example, when there are When there are n word lines, the upper portion of the film stack layer 335 may be The n / 2 word lines 333 form a first set of stair steps 760 and may be in the lower portion of the film stack 335. The n / 2 word lines 333 form a second set of stair steps 762. Therefore, contact structures (omitted from FIG. 7A and FIG. 7B for clarity) may be formed on the stair structures 700A and 700B to provide access to the corresponding stair steps. Electrical connection of n / 2 word lines. Similar to 3D memory structure 400, 3D memory array 500, and 3D memory array 600, stair bridges 450 can also be formed for stair structures 700A and 700B to connect word lines 333 at the same step (i.e., formed from the same conductive layer in film stack 335). In some embodiments, similar to the stair structure in FIG. 4, stair bridge 450 also includes the conductive layer and dielectric layer of film stack 335. In some embodiments, stair structures 700A and 700B can also include TSG cuts and BSG cuts similar to TSG cuts 220 and BSG cuts 446 discussed previously. 8A and 8B illustrate a stepped structure 800A and a stepped structure 800B according to some embodiments of the present disclosure, wherein for the 3D storage array 600 shown in FIG. 6 , the stepped structure 800A may be used for the stepped region 210 - 1 and the stepped structure 800B may be used for the stepped region 210 - 2 , or vice versa. Similar to the staircase structures 700A and 700B in FIG. 7A and FIG. 7B , the staircase structures 800A and 800B may also have a vertical offset V 偏移量 In addition to the stair steps in the x-direction, stair structure 800A and stair structure 800B also include stair steps in the y-direction. Details of stair structures having stair steps in both the x-direction and the y-direction can be found in co-pending U.S. patent application Ser. No. 16 / 458,401, filed on July 1, 2019, entitled “Three-Dimensional Memory Device and Fabrication Methods Thereof,” and U.S. patent application Ser. No. 16 / 422,434, filed on May 24, 2019, entitled “Staircase Structure with Multiple Divisions for Three-Dimensional Memory,” both of which are incorporated herein by reference in their entireties. In some embodiments, the stepped structure 800A and the stepped structure 800B may have n in the y direction. y Steps are formed, wherein each step in the y direction exposes one conductive layer in the film stack layer 335. In some embodiments, the stepped structure 800A and the stepped structure 800B may have n steps in the x direction. x steps, wherein each step in the x direction has a step height equal to (n y +1) The thickness of the conductive layer and the dielectric layer are the same. In some embodiments, the staircase structures 800A and 800B may further include staircase bridges 450. Similarly, staircase bridges 450 extend in the x-direction and connect conductive layers (or word lines) on the same staircase steps (at the same level of the staircase steps). In this example, contact structures for the word lines may be formed on the staircase steps in both the x-direction and the y-direction. FIG. 9 illustrates an exemplary fabrication process 900 for forming a 3D memory structure similar to the 3D memory structure 400 shown in FIG. 4 according to some embodiments of the present disclosure. It should be understood that the process steps shown in fabrication process 900 are not exhaustive, and other process steps may be performed before, after, or between any of the process steps shown. In some embodiments, some process steps of exemplary fabrication process 900 may be omitted, or other process steps not described herein for simplicity may be included. In some embodiments, the process steps of fabrication process 900 may be performed in a different order and / or varied. Figures 10A to 10C, Figures 11A to 11B, Figures 12A to 12B, Figures 13A to 13B, Figures 14A to 14C, Figures 15A to 15B, Figure 16, and Figures 17A to 17B are cross-sectional views or top views of 3D memory devices at various process steps according to some embodiments of the present disclosure. As shown in FIG. 9 , fabrication process 900 begins at process step S910 , where a bottom select gate (BSG) cut 446 may be formed in dielectric layer pair 1066 . FIG. 10A and FIG. 10B illustrate cross-sectional views of an exemplary structure 1000 along the x-direction and the y-direction, respectively, according to some embodiments of the present disclosure. FIG. 10C illustrates a top view of structure 1000 . The cross-sections in FIG. 10A and FIG. 10B are taken along lines BB' and AA'. As shown in FIG. 1 , FIG. 2 , FIG. 5 , and FIG. 6 , the x-direction and the y-direction are along the wordline and bitline directions. Structure 1000 includes dielectric layer pair 1066 disposed on substrate 330 . In some embodiments, structure 1000 may include a plurality of dielectric layer pairs 1066 , each of which includes a dielectric layer 456 (also referred to as a first dielectric layer) and a sacrificial layer 1068 (also referred to as a second dielectric layer) distinct from dielectric layer 456 . Dielectric layer 456 can be similar to the dielectric layer discussed above with reference to FIG. 4 . In some embodiments, dielectric layer 456 comprises any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide with F doping, C doping, N doping, or / and H doping. Dielectric layer 456 can also comprise a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide. In some embodiments, dielectric layer 456 can be any combination of the above materials. Forming the dielectric layer 456 on the substrate 330 may include any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), rapid thermal chemical vapor deposition (RTCVD), low-pressure chemical vapor deposition (LPCVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high-density plasma CVD (HDP-CVD), thermal oxidation, nitridation, any other suitable deposition method, or / and combinations thereof. In some embodiments, sacrificial layer 1068 comprises any suitable material that is different from dielectric layer 456 and that can be selectively removed relative to dielectric layer 456. For example, sacrificial layer 1068 can include silicon oxide, silicon oxynitride, silicon nitride, TEOS, polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, or any combination thereof. In some embodiments, sacrificial layer 1068 also comprises an amorphous semiconductor material, such as amorphous silicon or amorphous germanium. Sacrificial layer 1068 can be provided using techniques similar to those used for dielectric layer 456, such as CVD, PVD, ALD, thermal oxidation, nitridation, or any combination thereof. In some embodiments, dielectric layer 456 may be silicon oxide and sacrificial layer 1068 may be silicon nitride. The thickness of dielectric layer 456 and sacrificial layer 1068 may be in a range between 10 nm and 500 nm. In some embodiments, one or more BSG cuts 446 may be formed in dielectric layer pair 1066 extending vertically into substrate 330. BSG cuts 446 extend laterally in the x-direction with a width t 1 is in the range of 50 nm to 500 mm. Forming BSG cut 446 includes, but is not limited to, forming one or more trenches in dielectric layer pair 1066 extending into substrate 330; and filling the one or more trenches with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, SiOCN, or any combination thereof. In some embodiments, forming BSG cut 446 further includes forming a coplanar surface using chemical mechanical polishing (CMP). In some embodiments, peripheral devices (not shown) may be formed in the peripheral region 105 (see FIG. 1 ) on the front surface 330 f of the substrate 330 . In some embodiments, an active device region (not shown) may also be formed in the storage block 103 (see FIG. 1 ) on the front surface 330 f of the substrate 330 . In some embodiments, the substrate 330 may further include an insulating film 331 (not shown in FIG. 4 ) on the front surface 330 f. The insulating film 331 may be made of the same material as or a different material from the alternating dielectric material stack 1164 . Peripheral devices may include any suitable semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), diodes, resistors, capacitors, etc. Peripheral devices may be used to design digital, analog, and / or mixed-signal circuits that support the storage functions of the memory core, such as row and column decoders, drivers, page buffers, sense amplifiers, timing, and control sections. The active device region in the memory block is surrounded by an isolation structure such as shallow trench isolation. Doped regions such as p-type doped wells and / or n-type doped wells may be formed in the active device region according to the function of the array device in the memory block. In some embodiments, the structure 1000 of the 3D memory device may include a stepped region 210 and a channel structure region 211. In some embodiments, the channel structure region 211 may be arranged on opposite sides of the stepped region 210 along the x-direction. The channel structure region 211 may be used to form a storage string 212 in a subsequent process, and the stepped region 210 may be used to form a stepped structure in a subsequent process. At process step S920, a plurality of dielectric layer pairs 1066 may be disposed on the substrate 330 to form alternating dielectric material stack layers 1164. FIG. 11A and FIG. 11B illustrate cross-sectional views of an exemplary structure 1100 along the x-direction and the y-direction, respectively, according to some embodiments of the present disclosure. The alternating dielectric material stack layers 1164 extend in a lateral direction parallel to the front surface 330 f of the substrate 330. In the alternating dielectric material stack layers 1164, the dielectric layers 456 and the sacrificial layers 1068 may be alternately stacked on top of each other. In other words, each sacrificial layer 1068 may be sandwiched between two dielectric layers 456, and each dielectric layer 456 may be sandwiched between two sacrificial layers 1068 (except for the bottommost and topmost layers). The formation of alternating dielectric material stacks 1164 may include configuring dielectric layers 456 to have the same thickness or different thicknesses. Exemplary thicknesses of dielectric layers 456 may range from 10 nm to 500 nm, preferably about 25 nm. Similarly, sacrificial layers 1068 may all have the same thickness or different thicknesses. Exemplary thicknesses of sacrificial layers 1068 may range from 10 nm to 500 nm, preferably about 35 nm. It should be understood that the number of dielectric layer pairs 1066 in FIG. 11A and FIG. 11B is for illustrative purposes only, and any suitable number of layers may be included in alternating dielectric material stacks 1164. In some embodiments, alternating dielectric material stack layers 1164 may include layers other than dielectric layer 456 and sacrificial layer 1068 and may be made of different materials and / or have different thicknesses. At process step S930, a top select gate (TSG) cut 220 may be formed in the upper portion of the alternating dielectric material stack 1164. FIG. 12A illustrates a cross-sectional view of an exemplary structure 1200 along the y-direction according to some embodiments of the present disclosure. FIG. 12B illustrates a top view of the structure 1200, wherein the cross-section in FIG. 12A is along line AA' in FIG. 12B. In some embodiments, one or more TSG cuts 220 may extend vertically through one or more dielectric layer pairs 1066. The TSG cuts 220 may extend laterally in the x-direction, wherein the width t 2 is in the range of 50 nm to 500 nm. Forming TSG cut 220 includes, but is not limited to, forming one or more trenches in one or more dielectric layer pairs 1066 in the upper portion of the alternating dielectric material stack 1164; and filling the one or more trenches with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, SiOCN, or any combination thereof. In some embodiments, forming TSG cut 220 further includes forming a coplanar surface using chemical mechanical polishing (CMP). At process step S940, a hard mask 1378 may be provided on the alternating dielectric material stack 1164. FIG13A illustrates a cross-sectional view of an exemplary structure 1300 at process step S940, wherein FIG13B illustrates a top view of the structure 1300. The cross-sectional view in FIG13A is taken along line CC' in the y-direction. In some embodiments, hard mask 1378 may comprise a dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, silicon-containing antireflective coating (SiARC), amorphous silicon, polycrystalline silicon, high-k dielectric material, or any combination thereof. Hard mask 1378 may be used to form a step bridge in subsequent steps. Hard mask 1378 may define the width and length of the step bridge. Hard mask 1378 may comprise a sufficient thickness to protect the underlying alternating dielectric material stack layers 1164 during subsequent etching processes. Hard mask 1378 may be deposited on alternating dielectric material stack layers 1164 using CVD, ALD, PVD, thermal oxidation or nitridation, evaporation, sputtering, spin coating, or any suitable thin film deposition process. The hard mask may then be patterned using a lithography process and an etching process such as reactive ion etching (RIE). At process step S950, a first dielectric step 1470 and a second dielectric step 1472 may be formed in the stepped region 210, wherein the first and second dielectric steps may be connected by a dielectric bridge 1474. FIG. 14A and FIG. 14B illustrate cross-sectional views of an exemplary structure 1400 along the x-direction and the y-direction, respectively, according to some embodiments of the present disclosure. FIG. 14C illustrates a top view of the structure 1400, wherein the cross-sections in FIG. 14A and FIG. 14B are taken along lines BB' and CC'. In some embodiments, the stepped region 210 may be disposed in the middle of the alternating dielectric material stack 1164. In first dielectric step 1470 and second dielectric step 1472, step steps 1476 or "step layers" refer to stacks of layers having the same lateral dimensions in a surface parallel to substrate surface 330f. Each step step 1476 terminates shorter than the step below it by the lateral dimension "a" shown in FIG. 14A. In some embodiments, each step step 1476 includes one dielectric layer pair 1066. In some embodiments, each step step 1476 may include two or more dielectric layer pairs 1066. The first dielectric step 1470 and the second dielectric step 1472 can be formed by applying a repeated etch trim process to the alternating dielectric material stack 1164 using a patterned mask 1480 (see FIG. 14C ). In some embodiments, the patterned mask 1480 can include a photoresist or a carbon-based polymer material. In some embodiments, the patterned mask 1480 can also include a hard mask such as silicon oxide, silicon nitride, TEOS, silicon-containing anti-reflective coating (SiARC), amorphous silicon, polysilicon, or any combination thereof. The etching process includes an etching process and a trimming process. During the etching process, the portion of each step step 1476 having an exposed surface can be removed. The remaining portion of each step step 1476 that is covered by the upper level of the step step or by the patterned mask is not etched. The etching depth is the thickness of the step step 1476. In some embodiments, the thickness of the step step 1476 is the thickness of one dielectric layer pair 1066. The etching process for the dielectric layer 456 can have high selectivity for the sacrificial layer 1068, or / and vice versa. Therefore, the underlying dielectric layer pair 1066 can act as an etching stop layer. By switching the etching process for each layer, the step step 1476 can be etched during one etching loop. And as a result, one step step 1476 is formed during each etching trimming loop. In some embodiments, the stair step 1476 can be etched using an anisotropic etch process such as reactive ion etching (RIE) or other dry etching processes. In some embodiments, the dielectric layer 456 is silicon oxide. In this example, the etching of the silicon oxide may include using a fluorine-based gas (e.g., carbon fluoride (CF 4) Hexafluoroethane (C 2F 6) CHF 3. or C 3F 6, or / and any other suitable gas). In some embodiments, the silicon oxide layer can be removed by a wet chemical such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etching method can be used. In some embodiments, the sacrificial layer 1068 is silicon nitride. In this example, the etching of the silicon nitride can include using O 2. N 2. CF 4. NF 3. Cl 2. HBr, BCl 3. RIE or / and combinations thereof. The method and etchant for removing a single layer stack should not be limited by the embodiments of the present disclosure. The trimming process involves applying a suitable etch process (e.g., an isotropic dry etch or wet etch) to the patterned mask, allowing the patterned mask to be laterally pulled back. The lateral pullback dimension determines the lateral dimension "a" of each step of the first and second dielectric steps 1470, 1472. After the patterned mask is trimmed, a portion of the topmost step 1476 is exposed, while another portion of the topmost step 1467 remains covered by the patterned mask. The next cycle of the etch trimming process begins again with the etching process. In some embodiments, the patterned mask trimming process may include dry etching, for example, using O 2. Ar, N 2nd grade RIE. In some embodiments, the topmost step 1476 may be covered by the dielectric layer 456. In some embodiments, the topmost step 1476 may also be covered by other dielectric materials. A process step to remove the dielectric layer 456 and / or other dielectric materials may be added to the etching process of each etch trim loop to form the first dielectric step 1470 and the second dielectric step 1472. In some embodiments, dielectric bridges 1474 can be formed simultaneously with first dielectric step 1470 and second dielectric step 1472, wherein dielectric bridges 1474 can be defined by hard mask 1378. During the etch trim process, portions of alternating dielectric material stack layers 1164 beneath hard mask 1378 can be protected and not etched. As a result, for each stair step 1476, dielectric layer 456 and sacrificial layer 1068 in first dielectric step 1470 and second dielectric step 1472 can be connected by dielectric bridges 1474. In some embodiments, the hard mask 1378 and the patterned mask used for the etch trim process may be removed after process step S950 . At process step S960, according to some embodiments of the present disclosure, a plurality of storage strings 212 may be formed in the alternating dielectric material stack layers 1164 in the channel structure region 211. FIG. 15A illustrates a cross-sectional view of an exemplary structure 1500 at process step S960. FIG. 15B illustrates a top view of the structure 1500. The cross-sectional view in FIG. 15A is taken along line BB' in the x-direction. The storage strings 212 are similar to those previously discussed with reference to FIG. 3 and FIG. 4. In some embodiments, prior to forming a plurality of storage strings 212, an insulating layer 1582 may be disposed over the first dielectric step 1470 and the second dielectric step 1472. The insulating layer 1582 may include any suitable insulator, such as spin-on-glass, silicon oxide, a low-k dielectric material (e.g., carbon-doped oxide (CDO, SiOC, or SiOC:H), or fluorine-doped oxide (SiOF)). The insulating layer 1582 may be disposed by CVD, PVD, sputtering, spin coating, or the like. In some embodiments, a planarization process such as RIE etch-back or chemical mechanical polishing (CMP) may be performed to form a coplanar surface parallel to the surface 330 f of the substrate 330. To form the plurality of storage strings 212 , a plurality of channel holes (eg, channel holes 336 ) may first be formed in the alternating dielectric material stack layers 1164 , the plurality of channel holes penetrating the entire alternating dielectric material stack layers 1164 and extending into the substrate 330 . After forming the channel holes 336, a storage film 337 may be disposed on the sidewalls of each channel hole 336. In some embodiments, the storage film 337 may be a composite layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. Next, a channel layer 338 and a core-fill film 339 may be disposed inside the channel holes 336. The channel layer 338 covers the sidewalls of the storage film 337 inside the channel holes 336. The channel layer 338 may be any suitable semiconductor material, such as silicon. The core-fill film 339 may be any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, boron- or phosphorus-doped silicon oxide, carbon-doped oxide (CDO or SiOC or SiOC:H), fluorine-doped oxide (SiOF), or any combination thereof. In some embodiments, dummy strings (e.g., dummy strings 222 in FIG. 2 ) may also be formed in alternating dielectric material stack layers 1164 adjacent to strings 212 and / or in the stepped region. While strings 212 may be used for memory storage, dummy strings 222 may be used to provide structural support and improve process uniformity during manufacturing. In some embodiments, dummy strings 222 may also include a core fill film 339 and may be formed using similar techniques as strings 212. At process step S970, a film stack 335 of alternating conductive and dielectric layers can be formed by replacing sacrificial layer 1068 in alternating dielectric material stack 1164 in FIG. 15A with conductive layer 454. FIG. 16 illustrates a cross-sectional view of an exemplary structure 1600 according to some embodiments of the present disclosure. Film stack 335 is similar to the film stack previously discussed with reference to FIG. 3 and FIG. 4. After replacing the sacrificial layer with the conductive layer, stepped structures 210-L and 210-R can be formed in stepped region 210. Film stack 335 of alternating conductive and dielectric layers includes conductive layer 454 sandwiched between dielectric layers 456. In structure 1600, each stair step 1686 includes a conductive and dielectric layer pair 1684. In some embodiments, each stair step 1686 may include two or more conductive and dielectric layer pairs, each conductive and dielectric layer pair having one conductive layer 454 and one dielectric layer 456. To form stepped structures 210-L and 210-R, sacrificial layer 1068 in alternating dielectric material stack 1164 in FIG. 15A can be selectively removed above dielectric layer 456 to form a plurality of horizontal tunnels. Selective etching of sacrificial layer 1068 can include wet or dry chemical etching. Then, conductive layer 454 can be disposed in the horizontal tunnels. Conductive layer 454 may include any suitable conductive material suitable for a gate electrode, such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or / and any combination thereof. The conductive material may be deposited by CVD, PVD, ALD, sputtering, evaporation, or the like. In some embodiments, conductive layer 454 may also be a polycrystalline semiconductor, such as polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, or / and combinations thereof. In some embodiments, the polycrystalline material may be combined with any suitable type of dopant (e.g., boron, phosphorus, or arsenic). In some embodiments, conductive layer 454 may also be an amorphous semiconductor. In some embodiments, a gate dielectric layer may be provided in the horizontal tunnel before the conductive layer 454 to reduce leakage current between adjacent word lines (gate electrodes) and / or between the gate and the channel. The gate dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, or / and any suitable combination thereof. The gate dielectric layer may also include a high-k dielectric material such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or / and any combination thereof. The gate dielectric layer may be provided by one or more suitable deposition processes such as CVD, PVD, and / or ALD. Conductive layer 454 functions as a gate electrode at the intersection with storage string 212. It should be noted that the number of storage strings and gate electrodes in FIG16 is shown for illustrative purposes and can be any suitable number to increase storage capacity. At process step S980, contact structure 214 is formed on step structure 210-L and step structure 210-R. FIG. 17A illustrates a cross-sectional view of exemplary structure 1700 at process step S980. FIG. 17B illustrates a top view of structure 1700. The cross-sectional view in FIG. 17A is taken along line BB' in the x-direction. Contact structure 214 may be similar to the contact structures previously discussed with reference to FIG. 2 through FIG. 4. Forming the contact structure 214 includes forming a plurality of contact holes through the insulating layer 1582 and disposing a conductive material in the plurality of contact holes. In some embodiments, a photoresist or polymer material can be used as a mask layer to etch contact holes 1788. One or more masking and patterning processes can be used to form contact holes 1788. In some embodiments, insulating layer 1582 can include an etch stop layer (not shown) that protects underlying structures until all contact holes 1788 are formed on each stair step 1686. Contact holes 1788 extend through insulating layer 1582, exposing conductive layer 454. Contact structure 214 may be formed by providing a conductive material in contact hole 1788. In some embodiments, contact structure 214 may include a metal or metal compound, such as tungsten, cobalt, nickel, copper, aluminum, titanium, tantalum, tantalum nitride (TaN), or / and any combination thereof. The metal or metal compound may be formed by any suitable deposition method, such as sputtering, thermal evaporation, electron beam evaporation, ALD, PVD, or / and any combination thereof. In some embodiments, contact structure 214 may also include a metal silicide, such as WSi x 、CoSi x 、NiSi x , or AlSi x wait. In some embodiments, the contact structure 214 may be made coplanar with the insulating layer 1582 using a planarization process (eg, a CMP process). Through the contact structure 214 , conductive paths for the vertically stacked conductive layers 454 can be routed up to the surface, thereby enabling various interconnections for the 3D memory device in back-end processing. In some embodiments, contact structure 214-T and contact structure 214-L may be formed on gate electrodes for top select gate (TSG) 334 and lower select gate (LSG) or bottom select gate (BSG) 332, respectively. In some embodiments, one or more contact structures 214 may be formed on the same TSG 334, word line 333, and BSG 332. After sacrificial layer 1068 is replaced with conductive layer 454, dielectric bridge 1474 in FIG. 15B is converted into step bridge 450 in FIG. 17B . As a result, conductive layer 454 of step structure 210-L and step structure 210-R can be connected via step bridge 450. Thus, each word line 333 can be electrically connected to either step structure 210-L or step structure 210-R. In some embodiments, contact structures 214 can be formed on odd-numbered word lines 333 in step structure 210-L and even-numbered word lines 333 in step structure 210-R. In this configuration, the spacing between the contact structures can be increased at adjacent stair steps 1686. In summary, this disclosure describes various embodiments of 3D memory devices and methods of fabricating the same. One aspect of the present disclosure provides a three-dimensional (3D) memory device. In one example, the 3D memory device includes a film stack having a plurality of pairs of conductive and dielectric layers stacked vertically on a substrate. Each pair of conductive and dielectric layers includes a dielectric layer and a conductive layer. The 3D memory device also includes a stepped region having first and second stepped structures formed in the film stack, wherein each of the first and second stepped structures extends laterally in a first direction and includes a plurality of pairs of conductive and dielectric layers. The stepped region also includes a stepped bridge connecting the first and second stepped structures. Another aspect of the present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes providing an alternating dielectric material stack on a substrate, wherein the alternating dielectric material stack includes a plurality of dielectric layer pairs. Each dielectric layer pair includes a first dielectric layer and a second dielectric layer different from the first dielectric layer. The method also includes forming a first dielectric step, a second dielectric step, and a dielectric bridge in the alternating dielectric material stack, wherein the first and second dielectric steps are connected by the dielectric bridge. The foregoing description of specific embodiments will therefore sufficiently reveal the general nature of the present disclosure to allow others to readily modify and / or adapt the present disclosure to various applications (e.g., specific embodiments) by applying knowledge within the art without undue experimentation and without departing from the general concepts of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments based on the disclosure and guidance set forth herein. It should be understood that the phraseology or terminology herein is for purposes of description and not limitation, such that the phraseology or terminology of this specification will be interpreted by a skilled artisan in light of the present disclosure and guidance. The embodiments of the present disclosure have been described above by illustrating the functional building blocks of the implementation of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. As long as the specific functions and their relationships are properly performed, alternative boundaries can be defined. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the scope of the present disclosure and the appended claims in any way. The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention. 100: Three-dimensional memory device 101: Storage plane 103: Storage block 105: Peripheral region 108: Region 210: Step region 210-1: Step region 210-2: Step region 210-L: Step structure 210-R: Step structure 211: Channel structure region 212: Storage string 214: Contact structure 214-L: Contact structure 214-T: Contact structure 216: Gap structure 216-1: Gap structure 216-2: Gap structure 218: Storage finger 220: Top selection gate cutout 222: Virtual storage string 224: Storage sheet 300: Storage array structure 330: Substrate 330f: Front surface 331: Insulating film 332: Lower selection gate 332-1: Sub-BSG 332-2: Sub-BSG 332-3: Sub-BSG 333: word line 333-1: word line 333-2: word line 333-3: word line 333-4: word line 333-5: word line 333-6: word line 333-7: word line 333-8: word line 333-9: word line 334: top select gate 334-1: sub-TSG 334-2: sub-TSG 334-3: sub-TSG 335: Membrane stack layer 336: Channel hole 337: Storage film 338: Channel layer 339: Core fill film 340: Storage cell 340-1: Storage cell 340-2: Storage cell 340-3: Storage cell 341: Bit line 343: Metal interconnect line 344: Source line region 400: 3D memory structure 446: Back selection gate cut 448-1: Sub-block 448-2: Sub-block 448-3: Sub-block 450: Step bridge 450-1: Step bridge 450-2: Step bridge 454: Conductive layer 456: Dielectric layer 500: 3D storage array 600: 3D storage array 700A: Step structure 700B: Step structure 760: First set of steps 762: Second set of steps 800A : Stepped structure 800B: Stepped structure 900: Fabrication process 1000: Structure 1066: Dielectric layer pair 1068: Sacrificial layer 1100: Structure 1164: Alternating dielectric material stack 1200: Structure 1300: Structure 1378: Hard mask 1400: Structure 1470: First dielectric step 1472: Second dielectric step 1474: Dielectric bridge 1476: Step 1480: Patterned mask 1500: Structure 1582: Insulating layer 1600: Structure 1684: Pair of conductive and dielectric layers 1686: Step 1700: Structure 1788: Contact hole a: Lateral dimension d: Width s: Minimum spacing S910: Process step S920: Process step S930: Process stepS940: process step S950: process step S960: process step S970: process step S980: process step t 1: Width t 2: Width V 偏移量 :Vertical offset w:width The drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable one skilled in the relevant art to make and use the present disclosure. FIG1 illustrates a schematic top view of an exemplary three-dimensional (3D) memory die according to some embodiments of the present disclosure. FIG2 illustrates a schematic top view of a region of a 3D memory die according to some embodiments of the present disclosure. FIG3 illustrates a perspective view of a portion of an exemplary 3D storage array structure according to some embodiments of the present disclosure. FIG4 illustrates a perspective view of an exemplary 3D memory structure according to some embodiments of the present disclosure. FIG5 and FIG6 illustrate top views of a 3D memory structure according to some embodiments of the present disclosure. FIG7A, FIG7B, FIG8A, and FIG8B illustrate perspective views of a 3D memory structure according to some embodiments of the present disclosure. FIG9 illustrates a flow chart of an exemplary method for forming a 3D memory structure according to some embodiments of the present disclosure. FIG10A and FIG10B illustrate cross-sectional views of a 3D memory structure at a particular process step according to some embodiments of the present disclosure. FIG10C illustrates a top view of the 3D memory structure in FIG10A and FIG10B according to some embodiments of the present disclosure. FIG11A and FIG11B illustrate cross-sectional views of the 3D memory structure at a certain process step according to some embodiments of the present disclosure. FIG12A illustrates a cross-sectional view of the 3D memory structure at a certain process step according to some embodiments of the present disclosure. FIG12B illustrates a top view of the 3D memory structure in FIG12A according to some embodiments of the present disclosure. FIG13A illustrates a cross-sectional view of the 3D memory structure at a certain process step according to some embodiments of the present disclosure. FIG13B illustrates a top view of the 3D memory structure in FIG13A according to some embodiments of the present disclosure. FIG14A and FIG14B illustrate cross-sectional views of the 3D memory structure at a certain process step according to some embodiments of the present disclosure. FIG14C illustrates a top view of the 3D memory structure in FIG14A and FIG14B according to some embodiments of the present disclosure. FIG15A illustrates a cross-sectional view of the 3D memory structure at a certain process step according to some embodiments of the present disclosure. FIG. 15B shows a top view of the 3D memory structure in FIG. 15A according to some embodiments of the present disclosure. FIG. 16 shows a cross-sectional view of the 3D memory structure at a certain process step according to some embodiments of the present disclosure. FIG. 17A shows a cross-sectional view of the 3D memory structure at a certain process step according to some embodiments of the present disclosure. FIG. 17B shows a top view of the 3D memory structure in FIG. 17A according to some embodiments of the present disclosure. The features and advantages of the present invention will become more apparent from the detailed description set forth below in conjunction with the drawings, in which similar figure labels always identify corresponding elements.In the drawings, similar figure numbers generally indicate identical, functionally similar, or / and structurally similar elements. The figure in which an element first appears is indicated by the leftmost digit(s) in the corresponding figure number. Embodiments of the present disclosure will be described with reference to the drawings. 210: Stepped area 210-L: Ladder structure 210-R: Stepped structure 211: Channel structure area 212: Storage string 214: Contact structure 214-L: Contact structure 214-T: Contact structure 220: Top selection gate cut 330: Base 330f: front surface 332: Lower selection gate 332-1: Sub-BSG 332-2: Sub-BSG 332-3: Sub-BSG 333: Character Line 333-1: Character Line 333-2: Character Line 333-3: Character Line 333-4: Character Line 333-5: Character Line 333-6: Character Line 333-7: Character Line 333-8: Character Line 333-9: Character Line 334: Top selection gate 334-1: Sub-TSG 334-2: Sub-TSG 334-3: Sub-TSG 335: membrane stack layer 337: Storage membrane 338: Channel layer 339: Core filling membrane 340: Storage unit 400:3D memory structure 446: Back selection gate cut 450: Step Bridge 454: conductive layer 456: dielectric layer d: width s: minimum interval w: width

Claims

1. A three-dimensional (3D) memory device comprising: a film stack comprising a plurality of vertically stacked conductive layer and dielectric layer pairs, wherein each conductive layer and dielectric layer pair comprises a dielectric layer and a conductive layer; and a first stepped region, the first stepped region comprising: a first stepped structure; A second stepped structure, wherein the first stepped structure and the second stepped structure both extend laterally in a first direction and include pairs of conductive layers and dielectric layers; and a first stepped bridge connecting the first stepped structure and the second stepped structure, wherein the first stepped region is in the middle of the storage array of the three-dimensional memory device, and the width of the first stepped bridge along a second direction is less than the total width of the first stepped structure and the second stepped structure, and the second direction is perpendicular to the first direction.

2. The three-dimensional memory device according to claim 1 further includes a top selection gate (TSG) cutout extending along the first direction and vertically passing through an upper portion of the film stack layer.

3. The three-dimensional memory device according to claim 2, wherein a width of the first step bridge along the second direction is less than twice a distance between adjacent TSG cuts.

4. The three-dimensional memory device according to claim 2, wherein a width of the TSG cut along the second direction is between 50 nm and 500 nm.

5. The three-dimensional memory device according to claim 1, further comprising: a second step region, the second step region being located on one side of the first step region along the first direction, the second step region comprising: a third step structure and a fourth step structure, wherein the third step structure and the fourth step structure extend laterally in the first direction; and a second step bridge connecting the third step structure and the fourth step structure, wherein the first step bridge and the second step bridge are respectively located on opposite sides of the first step region and the second step region.

6. The three-dimensional memory device according to claim 1, wherein the first step bridge comprises the pairs of conductive layers and dielectric layers.

7. The 3D memory device of claim 6, wherein the first ladder bridge is configured to connect the conductive layer in each conductive layer and dielectric layer pair of the first ladder structure to the conductive layer in the corresponding conductive layer and dielectric layer pair of the second ladder structure.

8. The 3D memory device according to claim 1, further comprising: A plurality of storage strings vertically penetrate the membrane stack layer, each of the storage strings comprising: a core-fill membrane; a channel layer surrounding the core-fill membrane; and a storage membrane surrounding the channel layer.

9. The 3D memory device of claim 8, wherein the storage strings are distributed on opposite sides of the first stepped region.

10. The 3D memory device according to claim 1, further comprising: A plurality of contact structures are electrically connected to the conductive layer of the first stepped structure and the second stepped structure.

11. A 3D memory device as described in claim 10, wherein a first subset of the contact structures is formed on the conductive layer of the first stepped structure; and a second subset of the contact structures is formed on the conductive layer of the second stepped structure, wherein the second subset of the contact structures is different from the first subset of the contact structures.