Latch circuit and memory device

By employing an enable signal to set the clock signal to a 'hold' state in latch circuits, the issue of continued power consumption in disabled latches is addressed, resulting in reduced power usage and improved timing in electronic devices.

US12184285B2Active Publication Date: 2024-12-31TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD +1
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Patent Information

Application Number
US18/362322
Authority / Receiving Office
US · United States
Patent Type
Patents(United States)
Current Assignee / Owner
Priority Date
2019-12-26
Filing Date
2023-07-31
Publication Date
2024-12-31
Estimated Expiration
2040-02-20

AI Technical Summary

Technical Problem

In electronic devices, latches continue to consume power even when their corresponding functions or circuits are disabled, leading to unnecessary power consumption due to signal passing during disabling periods.

Method used

An enable signal is used to configure the clock generator to set the clock signal to a 'hold' state when the function or circuit is to be disabled, preventing unnecessary power consumption by keeping the latch output unchanged during disabling periods, and this is achieved through a latch clock generator and input latch configuration using standard logic elements like OR gates and NAND gates.

Benefits of technology

This approach reduces power consumption by holding the latch output unchanged during disabling periods, thereby minimizing unnecessary power usage and coupling noise, with a potential reduction in power pin usage by 79-94% and timing improvement by 11%.

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Abstract

A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.
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Citation Information

Patent Citations

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    CN104769841A

  • Integrated clock gating cell using a low area and a low power latch

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  • Signal transmission control method and apparatus, and signal latch apparatus

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  • Semiconductor integrated circuit device, and design apparatus and design method thereof

    JP2007329586A

  • Low power and stable filp flop

    KR1020010005004A