Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises: a display area (100) and an edge area (300). The display substrate further comprises: a substrate (10) and a power supply line (310) disposed on the substrate (10) and located in the edge area (300). The power supply line (310) comprises: a first power supply portion (310A) and a second power supply portion (310B) connected to each other, the second power supply portion (310B) being located on the side of the first power supply portion (310A) distant from the substrate (10). The display area (100) comprises a plurality of display units. At least one display unit comprises: a pixel driving circuit and a light-emitting device, the pixel driving circuit being electrically connected to an anode of the light-emitting device, and the power supply line (VSS) being electrically connected to a cathode of the light-emitting device. An orthographic projection of the second power supply portion (310B) on the substrate (10) at least partially overlaps with an orthographic projection of the first power supply portion (310A) on the substrate (10). The distance between the end of the second power supply portion (310B) distant from the display area (100) and the display area (100) is greater than or equal to the distance between the end of the first power supply portion (310A) distant from the display area (100) and the display area (100).

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become a mainstream product in the display field.

[0003] SUMMARY OF THE INVENTION

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure further provides a display substrate, comprising: a display area and an edge area located on a side of the display area; the display substrate further comprising: a base and a power line disposed on the base and located in the edge area, the power line comprising: a first power supply portion and a second power supply portion connected to each other, the second power supply portion being located on a side of the first power supply portion away from the base;

[0006] The display area includes: a plurality of display units, at least one display unit includes: a pixel driving circuit and a light emitting device, the pixel driving circuit is electrically connected to the anode of the light emitting device, and the power line is electrically connected to the cathode of the light emitting device.

[0007] The orthographic projection of the second power supply unit on the substrate at least partially overlaps with the orthographic projection of the first power supply unit on the substrate, and the distance between the end of the second power supply unit away from the display area and the display area is greater than or equal to the distance between the end of the first power supply unit away from the display area and the display area.

[0008] In some possible implementations, the edge region includes a circuit region and an isolation dam region sequentially arranged in a direction away from the display region, and the circuit region includes: a first circuit region, a second circuit region, and a third circuit region sequentially arranged in a direction away from the display region;

[0009] The pixel driving circuit includes: a writing transistor, a compensation transistor, a light-emitting transistor, a first scanning signal line, a second scanning signal line, and a light-emitting signal line; the first scanning signal line is electrically connected to the control electrode of the writing transistor, the second scanning signal line is electrically connected to the control electrode of the compensation transistor, and the light-emitting signal line is electrically connected to the control electrode of the light-emitting transistor; the writing transistor and the compensation transistor are of different transistor types;

[0010] The display substrate further includes: a first driving circuit located in the first circuit area, a second driving circuit located in the second circuit area, and a third driving circuit located in the third circuit area and the isolation dam area;

[0011] The first driving circuit is electrically connected to the first scanning signal line, the second driving circuit is electrically connected to the second scanning signal line, and the third driving circuit is electrically connected to the light emitting signal line;

[0012] The first power supply unit is located in the isolation dam area, and the second power supply unit is located in the isolation dam area and the circuit area;

[0013] The orthographic projection of the second power supply unit on the substrate at least partially overlaps with the orthographic projection of the third driving circuit on the substrate, and has no overlapping area with the orthographic projection of the second driving circuit on the substrate.

[0014] In some possible implementations, the device further includes: a crack detection line located in the isolation dam area, the crack detection line being provided in the same layer as the first power supply unit and being located on a side of the first power supply unit away from the display area;

[0015] A distance between the first power supply unit and the crack detection line is greater than or equal to 1 micrometer and less than or equal to 6 micrometers.

[0016] In some possible implementations, a distance between the first power supply unit and the third driving circuit is greater than or equal to 1 micrometer and less than or equal to 6 micrometers.

[0017] In some possible implementations, the device further includes: a first planarization layer located in the display area, the circuit area, and the isolation dam area; and a first protection layer located in the isolation dam area; the first planarization layer is located between the first power supply unit and the second power supply unit and is provided on the same layer as the first protection layer;

[0018] The orthographic projection of the first protective layer on the substrate covers the orthographic projection of the crack detection line on the substrate, and at least partially overlaps with the orthographic projection of the first power supply unit on the substrate.

[0019] In some possible implementations, the third driving circuit includes: a clock signal line located in the isolation dam area; the clock signal line is provided on the same layer as the first power supply unit and is located on a side of the first power supply unit close to the display area;

[0020] The orthographic projection of the first planar layer on the substrate covers the orthographic projection of the clock signal line on the substrate, and has no overlapping area with the orthographic projection of the first power supply unit on the substrate.

[0021] In some possible implementations, the second power supply unit is provided with a plurality of second via holes exposing the first planar layer, and the plurality of second via holes are arranged in a matrix;

[0022] The orthographic projections of the plurality of second via holes on the substrate at least partially overlap with the orthographic projection of the third driving circuit on the substrate.

[0023] In some possible implementations, the further comprising: a second planar layer located in the display area and the circuit area, and a second protective layer located in the isolation dam area;

[0024] The second flat layer is located on a side of the second power supply unit away from the substrate and is provided on the same layer as the second protective layer;

[0025] The orthographic projection of the second protection layer on the substrate covers the orthographic projection of the first protection layer on the substrate, and the orthographic projection of the second flat layer on the substrate covers the orthographic projection of the second via on the substrate.

[0026] In some possible implementations, the device further includes: an auxiliary power line located in the edge region; the anode is located on a side of the second flat layer away from the substrate and is disposed in the same layer as the auxiliary power line;

[0027] The auxiliary power line is electrically connected to the second power supply unit;

[0028] The orthographic projection of the auxiliary power line on the substrate at least partially overlaps with the orthographic projections of the first driving circuit, the second driving circuit, and the third driving circuit on the substrate.

[0029] In some possible implementations, the auxiliary power line is provided with a plurality of fifth vias exposing the second planar layer, and the plurality of fifth vias are arranged in a matrix;

[0030] The plurality of fifth vias are located in the first circuit area, the second circuit area, and the third circuit area;

[0031] The orthographic projection of the fifth via hole located in the third circuit area on the substrate at least partially overlaps with the orthographic projection of the second via hole on the substrate.

[0032] In some possible implementations, the device further includes: a pixel definition layer located in the display area and an isolation layer located in the circuit area; the pixel definition layer is located on one side of the anode and the substrate and is disposed on the same layer as the isolation layer;

[0033] The distance between the end of the isolation layer away from the display area and the display area is less than or equal to the distance between the end of the second flat layer away from the display area and the display area, and the orthographic projection of the isolation layer on the substrate covers the orthographic projection of the fifth via hole on the substrate.

[0034] In some possible implementations, the device further includes: an organic light-emitting layer located in the display area and a cathode located in the display area and the circuit area, which are sequentially stacked on the substrate;

[0035] The cathode is electrically connected to the auxiliary power line.

[0036] In some possible implementations, the isolation dam area further includes: a first isolation dam and a second isolation dam;

[0037] The second isolation dam is located on a side of the first isolation dam away from the display area, and is located on a side of the second protection layer close to the display area.

[0038] In some possible implementations, the further comprising: a first dam foundation, a third dam foundation, a fifth dam foundation, and a seventh dam foundation located in the isolation dam area;

[0039] The first dam is provided on the same layer as the first flat layer, the third dam is provided on the same layer as the second flat layer, the fifth dam is provided on the same layer as the pixel definition layer, and the seventh dam is located on a side of the pixel definition layer away from the substrate;

[0040] The second power supply unit covers the first dam foundation, the third dam foundation is provided on the second power supply unit covering the first dam foundation, and the orthographic projection of the third dam foundation on the substrate covers the orthographic projection of the first dam foundation on the substrate, the fifth dam foundation is provided on the third dam foundation, and the orthographic projection of the fifth dam foundation on the substrate covers the orthographic projection of the third dam foundation on the substrate, and the seventh dam foundation is provided on the fifth dam foundation, and the orthographic projection of the fifth dam foundation on the substrate covers the orthographic projection of the seventh dam foundation on the substrate;

[0041] The auxiliary power line partially covers the third dam base;

[0042] The first dam, the second power supply portion covering the first dam, the third dam, the fifth dam, and the seventh dam form a second isolation dam.

[0043] In some possible implementations, the further comprising: a second dam foundation, a fourth dam foundation, and a sixth dam foundation located in the isolation dam area;

[0044] The second dam base is provided on the same layer as the second planar layer, the fourth dam base is provided on the same layer as the pixel definition layer, and the sixth dam base is provided on the same layer as the seventh dam base;

[0045] The second dam base is provided on the second power supply unit, the fourth dam base is provided on the auxiliary power line covering the second dam base, and the orthographic projection of the fourth dam base on the substrate covers the orthographic projection of the second dam base on the substrate, and the sixth dam base is provided on the fourth dam base, and the orthographic projection of the fourth dam base on the substrate covers the orthographic projection of the sixth dam base on the substrate;

[0046] The second dam, the auxiliary power line covering the second dam, the fourth dam, and the sixth dam form a first isolation dam.

[0047] In some possible implementations, an orthographic projection of the first isolation dam on the substrate at least partially overlaps with the clock signal line.

[0048] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0049] In a third aspect, the present disclosure further provides a method for preparing a display substrate, which is configured to prepare the above-mentioned display substrate, wherein the display substrate comprises: a display area and an edge area located on the side of the display area, and the method comprises:

[0050] providing a substrate;

[0051] A first power supply unit and a second power supply unit are sequentially formed on the substrate to form a power line located in the edge area, an orthographic projection of the second power supply unit on the substrate at least partially overlaps with an orthographic projection of the first power supply unit on the substrate, and a distance between an end of the second power supply unit away from the display area and the display area is greater than or equal to a distance between an end of the first power supply unit away from the display area and the display area.

[0052] In some possible implementations, sequentially forming a first power supply unit and a second power supply unit on the substrate includes:

[0053] A pixel driving circuit in the display area, a first driving circuit in the circuit area, a second driving circuit, a third driving circuit in the third circuit area, and a first power supply unit and a crack detection line in the isolation dam area are formed on the substrate;

[0054] forming a first planarization layer located in the display area and the circuit area, and a first dam base and a first protective layer located in the isolation dam area on the substrate forming the first power supply unit;

[0055] forming a connection electrode located in the display area and a second power supply portion located in the circuit area and the isolation dam area on the substrate on which the first flat layer is formed;

[0056] forming a second planar layer located in the display area and the circuit area, a second dam base located in the isolation dam area, a third dam base and a second protective layer on the substrate forming the second power supply unit;

[0057] forming an anode located in a display area and an auxiliary power supply line located in an edge area on the substrate on which the second flat layer is formed;

[0058] forming a pixel definition layer in the display area, an isolation layer in the circuit area, and a fourth dam base and a fifth dam base in the isolation dam area on the substrate on which the auxiliary power line is formed;

[0059] An organic light emitting layer in the display area, a cathode in the display area and the circuit area, and a sixth dam base and a seventh dam base in the isolation dam area are formed on the substrate on which the pixel definition layer is formed.

[0060] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0061] Summary of the Figures

[0062] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0063] FIG1 is a schematic structural diagram of a display substrate;

[0064] FIG2 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0065] FIG3 is a schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0066] FIG4 is a top view of a display substrate provided in an embodiment of the present disclosure;

[0067] FIG5 is a top view of a portion of a film layer of a display substrate provided by an embodiment of the present disclosure;

[0068] FIG6 is a schematic structural diagram of a display substrate provided by an exemplary embodiment;

[0069] FIG7 is a schematic diagram after forming a display circuit layer;

[0070] FIG8 is a cross-sectional view taken along line AA of FIG7 ;

[0071] FIG9 is a schematic diagram after forming the first organic layer;

[0072] FIG10 is a cross-sectional view taken along line AA of FIG9 ;

[0073] FIG11 is a schematic diagram after forming a second source / drain metal layer;

[0074] FIG12 is a schematic diagram of FIG11 along the AA direction;

[0075] FIG13 is a schematic diagram after forming a second organic layer;

[0076] FIG14 is a cross-sectional view taken along line AA of FIG13;

[0077] FIG15 is a schematic diagram after forming a transparent conductive layer;

[0078] FIG16 is a cross-sectional view taken along line AA of FIG15;

[0079] FIG17 is a schematic diagram after forming a third organic layer;

[0080] FIG18 is a schematic diagram of FIG17 along the AA direction;

[0081] FIG19 is a schematic diagram after forming an organic light-emitting layer;

[0082] FIG20 is a cross-sectional view taken along line AA of FIG19;

[0083] FIG21 is a schematic diagram after forming a cathode;

[0084] FIG22 is a cross-sectional view of FIG21 along the AA direction.

[0085] Details

[0086] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0087] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0088] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0089] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0090] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0091] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0092] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0093] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0094] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0095] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0096] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0097] In a low-temperature polycrystalline oxide display product, a power line provides a low-voltage signal to the display area. Due to the impedance of the power line, there is a voltage drop during voltage signal transmission. This voltage loss in the power line reduces the uniformity of the display brightness and increases the power consumption of the display product, becoming a significant factor affecting high-quality display.

[0098] FIG1 is a schematic diagram of the structure of a display substrate. As shown in FIG1 , the display substrate may include a display area 100 , a binding area 200 located on one side of the display area 100 , and an edge area 300 located on the other side of the display area 100 .

[0099] In an exemplary embodiment, the display area 100 includes at least a plurality of regularly arranged display units (sub-pixels).

[0100] In an exemplary embodiment, within a plane perpendicular to the display substrate, the display unit may include a driving structure layer disposed on a base, a light-emitting device disposed on the driving structure layer, and an encapsulation layer disposed on the light-emitting device. The driving structure layer may include a pixel driving circuit, the light-emitting device being connected to the pixel driving circuit, the light-emitting device being configured to emit light, and the pixel driving circuit being configured to drive the light-emitting device to emit light.

[0101] In an exemplary embodiment, the pixel driving circuit may include multiple thin film transistors (TFTs) and storage capacitors, such as 3T1C, 4T1C, 5T1C, 6T1C, or 7T1C, etc., which is not limited in the present disclosure.

[0102] Figure 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in Figure 2, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7), a storage capacitor C, and seven signal lines (data signal line D, first scan signal line S1, second scan signal line S2, third scan signal line S3, light emitting signal line E, initial signal line INIT, first power line VDD, and second power line VSS).

[0103] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0104] In an exemplary embodiment, a control electrode of the first transistor T1 is connected to the third scan signal line S3, a first electrode of the first transistor T1 is connected to the initialization signal line INIT, and a second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the third scan signal line S3, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3, thereby initializing the charge amount of the control electrode of the third transistor T3.

[0105] In an exemplary embodiment, the control electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. The second transistor T2 can be called a compensation transistor. When an on-level scan signal is applied to the second scan signal line S2, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0106] In an exemplary embodiment, the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode.

[0107] In an exemplary embodiment, a control electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a write transistor. When an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs a data voltage of the data signal line D to the pixel driving circuit.

[0108] In one exemplary embodiment, the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light-emitting device to emit light.

[0109] In an exemplary embodiment, a control electrode of the seventh transistor T7 is connected to the third scan signal line S3, a first electrode of the seventh transistor T7 is connected to the initialization signal line INIT, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When an on-level scan signal is applied to the third scan signal line S3, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0110] In an exemplary embodiment, the cathode of the light emitting device is connected to the second power line VSS.

[0111] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the second power line VSS continuously provides a low-level signal.

[0112] In an exemplary embodiment, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

[0113] In an exemplary embodiment, the first transistor T1 and the second transistor T2 are N-type metal oxide transistors, and the third transistor T3 to the seventh transistor T7 are P-type low-temperature polysilicon thin film transistors.

[0114] In one exemplary embodiment, the write transistor and the compensation transistor are of different transistor types.

[0115] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the light emitting signal line E and the initial signal line INIT extend along a first direction, the second power line VSS, the first power line VDD and the data signal line D extend along a second direction, and the first direction and the second direction intersect.

[0116] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED), comprising a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). The anode of the light emitting device is connected to a pixel driving circuit.

[0117] The display substrate provided in the embodiment of the present disclosure may be a low-temperature polycrystalline oxide display substrate.

[0118] In an exemplary embodiment, the binding area 200 includes at least an isolation dam and a binding circuit that connects the signal lines of multiple display units to an external driving device, and the edge area 300 includes at least an isolation dam, a gate driving circuit and a power line that transmits voltage signals to multiple display units. The isolation dams of the binding area 200 and the edge area 300 form a ring structure surrounding the display area 100.

[0119] Figure 3 is a schematic diagram of the structure of a display substrate provided by an embodiment of the present disclosure. Figure 3 is an enlarged view of area C in Figure 1. Figure 4 is a top view of a display substrate provided by an embodiment of the present disclosure. Figure 3 is a cross-sectional view of Figure 4 along the AA direction. Figure 5 is a top view of a portion of the film layer of a display substrate provided by an embodiment of the present disclosure. As shown in Figures 3 to 5, within a plane parallel to the display substrate, the edge region 300 includes a circuit region 301 and an isolation dam region 302, which are sequentially arranged in a direction away from the display region 100. The circuit region 301 includes a first circuit region 301A, a second circuit region 301B, and a third circuit region 301C, which are sequentially arranged in a direction away from the display region 100.

[0120] In an exemplary embodiment, the circuit area 301 includes at least a gate driving circuit, wherein the gate driving circuit is electrically connected to the first scanning signal line, the second scanning signal line, and the light emitting signal line of the pixel driving circuit 101 in the display area 100 .

[0121] In an exemplary embodiment, the gate driving circuit located in the edge region 300 may include: a first driving circuit 201 , a second driving circuit 202 and a third driving circuit 203 .

[0122] In an exemplary embodiment, the first driving circuit 201 is electrically connected to the first scan signal line.

[0123] In an exemplary embodiment, the second driving circuit 202 is electrically connected to the second scanning signal line. The second driving circuit 202 may further include a clock signal line CLK.

[0124] In an exemplary embodiment, the third driving circuit 203 is electrically connected to the light emitting signal line, and the third driving circuit 203 may further include a clock signal line ECLK.

[0125] In an exemplary embodiment, the first driving circuit 201 may be an 8T2C circuit structure, or other circuit structures.

[0126] In an exemplary embodiment, the second driving circuit 202 may be a 10T3C or 13T3C circuit structure, which is not limited in the present disclosure.

[0127] In an exemplary embodiment, the first driving circuit 201 is located in the first circuit region 301A, the second driving circuit 202 is located in the second circuit region 301B, and the third driving circuit 203 is located in the third circuit region 301C and the isolation dam region 302 .

[0128] In an exemplary embodiment, the isolation dam area 302 includes at least a power line 310 connected to the cathode of the light emitting device, a first isolation dam 410 , a second isolation dam 420 , a crack detection line 320 , and a clock signal line ECLK of the third driving circuit 203 .

[0129] In an exemplary embodiment, the power line 310 extends in a direction parallel to the edge of the display area and is connected to the second power line VSS of the pixel driving circuit 101 in the display area 100 .

[0130] In an exemplary embodiment, the power line 310 includes a first power portion 310A and a second power portion 310B connected to each other, and the second power portion 310B is located on a side of the first power portion 310A away from the substrate.

[0131] In an exemplary embodiment, the orthographic projection of the second power supply unit 310B on the substrate at least partially overlaps with the orthographic projection of the first power supply unit 310A on the substrate, and the distance between the end of the second power supply unit 310B away from the display area 100 and the display area 100 is greater than or equal to the distance between the end of the first power supply unit 310A away from the display area 100 and the display area 100.

[0132] In an exemplary embodiment, the first power supply unit 310A is located in the isolation dam region 302 .

[0133] In an exemplary embodiment, the second power supply unit 310B is located at least in the isolation dam area 302 and the third circuit area 301C. The second power supply unit 310B may also be located in the second circuit area 301B, wherein the orthographic projection of the second power supply unit 310B on the substrate at least partially overlaps with the orthographic projection of the third driving circuit 203 on the substrate, and does not overlap with the orthographic projection of the second driving circuit 202 on the substrate.

[0134] In an exemplary embodiment, the second driving circuit includes a clock signal line CLK. The distance between the end of the second power supply unit 310B closer to the display area 100 and the display area 100 is greater than the distance between the end of the clock signal line CLK farther from the display area 100 and the display area 100, that is, the orthographic projection of the second power supply unit 310B on the substrate does not overlap with the orthographic projection of the clock signal line CLK on the substrate.

[0135] In an exemplary embodiment, the crack detection line 320 extends in a direction parallel to the edge of the display area and is located on a side of the power line 310 away from the display area 100. The crack detection line is configured to detect whether there is a crack on the display substrate.

[0136] In an exemplary embodiment, the first isolation dam 410 and the second isolation dam 420 extend in a direction parallel to the edge of the display area and are configured to block moisture from entering the display area 100 from the edge area 300 .

[0137] In an exemplary embodiment, the distance between the first isolation dam 410 and the display area 100 is smaller than the distance between the second isolation dam 420 and the display area 100 , that is, the second isolation dam 420 is disposed on a side of the first isolation dam 410 away from the display area 100 .

[0138] In an exemplary embodiment, the low voltage required by the light-emitting device connected to the pixel driving circuit in the display area 100 is introduced from the binding pad of the binding area 200, enters the edge area 300 after passing through the binding area 200, and is transmitted to the second power line VSS of each pixel driving circuit through the ring-shaped power line 310 in the edge area 300.

[0139] In the present disclosure, Figure 3 illustrates a cross-sectional structure of a top-emitting OLED display area and a peripheral area. According to the light emission direction, OLEDs can be divided into bottom-emitting, top-emitting and double-sided emitting types. Compared with bottom-emitting OLEDs, top-emitting OLEDs have the advantages of high aperture ratio, high color purity, and easy realization of high resolution (Pixels Per Inch, abbreviated as PPI), and have gradually become the current mainstream structure. For top-emitting OLEDs, since the light emission direction is on the cathode side, in order to ensure good light transmittance, the cathode is required to be very thin, so the voltage drop of the power line that provides low voltage to the cathode has a relatively important influence on improving the uniformity of display brightness.

[0140] 3 to 6 , and in combination with FIG. 7 to FIG. 22 , the display substrate of the exemplary embodiment of the present disclosure includes a display area 100 and an edge area 300 . The edge area 300 includes a circuit area 301 and an isolation dam area 302 sequentially arranged in a direction away from the display area 100 .

[0141] In an exemplary embodiment, the display area 100 of the display substrate includes:

[0142] Base 10;

[0143] a first insulating layer 11 disposed on the substrate 10;

[0144] An active layer is provided on the first insulating layer 11, wherein the active layer at least includes a first active layer;

[0145] a second insulating layer 12 covering the active layer;

[0146] A first gate metal layer, a third insulating layer 13, a second gate metal layer and a fourth insulating layer 14 are sequentially arranged on the second insulating layer 12, and the first gate metal layer includes at least a first gate electrode; the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14 are provided with vias exposing the first active layer.

[0147] a first source-drain metal layer disposed on the fourth insulating layer 14, the first source-drain metal layer including at least a first source electrode and a first drain electrode, the first source electrode and the first drain electrode being respectively connected to the first active layer through via holes exposing the first active layer;

[0148] A first organic layer is provided on the first source-drain metal layer, the first organic layer at least comprising: a first planar layer 15 covering the first source-drain metal layer, the first planar layer 15 being provided with a first via hole exposing the first drain electrode;

[0149] A second source-drain electrode layer is provided on the first organic layer, the second source-drain metal layer at least includes a connecting electrode 17 provided on the first planar layer 15, and the connecting electrode 17 is connected to the first drain electrode through a first via hole;

[0150] A second organic layer is provided on the second source-drain electrode layer, the second organic layer at least comprising: a second planar layer 16 covering the connecting electrode 17 and provided with a second via hole exposing the connecting electrode 17;

[0151] A transparent conductive layer is provided on the second organic layer, the transparent conductive layer at least comprising: an anode 21 provided on the second planar layer 16, the anode 21 being connected to the connection electrode 17 through a second via hole;

[0152] a third organic layer disposed on the transparent conductive layer, the third organic layer comprising at least: a pixel definition layer 22 disposed on the anode 21, wherein the pixel definition layer 22 is provided with a fifth via hole exposing the anode 21;

[0153] an organic light-emitting layer 24 disposed in the fifth via hole, the organic light-emitting layer 24 being connected to the anode 22;

[0154] An organic light-emitting layer 24 and a cathode 25 are provided on the pixel definition layer 22 , and the cathode 25 is connected to the organic light-emitting layer 24 .

[0155] In an exemplary embodiment, the edge region 300 of the display substrate includes:

[0156] Base 10;

[0157] a first insulating layer 11 disposed on the substrate 10;

[0158] An active layer is provided on the first insulating layer 11, the active layer at least including a second active layer, a third active layer and a fourth active layer located in the circuit area 301;

[0159] a second insulating layer 12 covering the active layer;

[0160] A first gate metal layer is provided on the second insulating layer 12, the first gate metal layer at least including a second gate electrode and a first capacitor electrode located in the first circuit area 301A, a third gate electrode and a second capacitor electrode located in the second circuit area 301B, and a fourth gate electrode and a third capacitor electrode located in the third circuit area 301C;

[0161] a third insulating layer 13 covering the first gate metal layer;

[0162] A second gate metal layer is provided on the third insulating layer 13, the second gate metal layer at least including a fourth capacitor electrode located in the first circuit region 301A, a fifth capacitor electrode located in the second circuit region 301B, and a sixth capacitor electrode located in the third circuit region 301C;

[0163] a fourth insulating layer 14 covering the second gate metal layer, wherein the fourth insulating layer 14 in the circuit region 301 is provided with a plurality of via holes exposing the second active layer, the third active layer, and the fourth active layer;

[0164] a first source-drain metal layer disposed on the fourth insulating layer 14, the first source-drain metal layer including at least a second source electrode, a second drain electrode, a third source electrode, and a third drain electrode located in the circuit region 301, a fourth source electrode and a fourth drain electrode, and a first power supply portion 310A, a clock signal line ECLK, and a crack detection line 320 located in the isolation dam region 302; the second source electrode and the second drain electrode are respectively connected to the second active layer via vias exposing the second active layer, the third source electrode and the third drain electrode are respectively connected to the third active layer via vias exposing the third active layer, and the fourth source electrode and the fourth drain electrode are respectively connected to the fourth active layer via vias exposing the fourth active layer;

[0165] A first organic layer is provided on the first source / drain metal layer, the first organic layer comprising at least: a first planarization layer 15 located in the circuit region 301 and the isolation dam region 302, and a first dam base 421 and a first protective layer 431 formed in the isolation dam region 302; the first dam base 421 of the isolation dam region 302 is provided on the first power supply portion 310A, the first protective layer 431 is provided on the crack detection line 320 and the first power supply portion 310A, the first protective layer 431 covers the crack detection line 320 and covers an end of the first power supply portion 310A away from the display area; the first planarization layer 15 covers the clock signal line ECLK;

[0166] A second source-drain electrode layer is provided on the first organic layer, the second source-drain metal layer at least including a second power portion 310B located in the isolation dam area 302, the second power portion 310B covers the first dam base 421, and a second via hole is provided on the second power portion 310B to expose the first planar layer;

[0167] A second organic layer is provided on the second source-drain electrode layer, the second organic layer comprising at least: a second planar layer 16 in the circuit region 301, and a second dam base 411, a third dam base 422, and a second protective layer 432 provided in the isolation dam region 302, the third dam base 422 being provided on the second power supply portion 310B covering the first dam base 421, the second dam base 411 being provided on the second power supply portion 310B on a side of the first dam base 421 adjacent to the display region 100, the second protective layer 432 being provided on the first protective layer 431 and covering an end of the second power supply portion 310B away from the display region, and a fourth via hole being provided in the second planar layer 16 to expose the second power supply portion 310B;

[0168] A transparent conductive layer is provided on the second organic layer, the transparent conductive layer comprising at least: an auxiliary power line 330 located in the circuit area 301 and the isolation dam area 302, wherein the auxiliary power line 330 located in the circuit area 301 is provided with a plurality of fifth vias; the auxiliary power line 330 in the isolation dam area 302 covers the second dam base 411 and partially covers the third dam base 422; the auxiliary power line 330 located on the side of the second dam base 411 adjacent to the display area 100 and the auxiliary power line 330 located on the side of the second dam base 402 away from the display area 100 are both connected to the second power supply portion 310B;

[0169] A third organic layer is arranged on the transparent conductive layer, and the third organic layer includes at least: an isolation layer 23 located in the circuit area 301 and a fourth dam base 412 and a fifth dam base 423 located in the isolation dam area 302, the isolation layer 23 is provided with a seventh via hole exposing the auxiliary power line 330, the fourth dam base 412 is arranged on the auxiliary power line 330 covering the second dam base 411, and the fifth dam base 423 is arranged on the third dam base 422.

[0170] A cathode 25 is provided in the circuit area 301 and is electrically connected to the auxiliary power line 330 through a seventh via hole;

[0171] The sixth dam base 413 and the seventh dam base 424 are provided in the isolation dam area 302 . The sixth dam base 413 is located on the fourth dam base 412 , and the seventh dam base 424 is located on the fifth dam base 423 .

[0172] In an exemplary embodiment, the sixth dam 413 and the seventh dam 424 can be reused as isolation pillars.

[0173] The second dam 402 , the auxiliary power line 330 covering the second dam, the fourth dam 412 and the sixth dam 413 form a first isolation dam 410 .

[0174] In an exemplary embodiment, the first dam 421 , the second power supply part 310B covering the first dam, the third dam 422 , the fifth dam 423 , and the seventh dam 424 form the second isolation dam 420 .

[0175] Figure 6 is a schematic diagram of the structure of a display substrate provided by an exemplary embodiment. As shown in Figure 6, the display substrate provided by an exemplary embodiment may further include an encapsulation layer 26. Encapsulation layer 26 may include a first encapsulation layer 261, a second encapsulation layer 262, and a third encapsulation layer 263, sequentially stacked on a substrate. The encapsulation layer in the display area 100 and the circuit area 301 has a stacked structure of first encapsulation layer / second encapsulation layer / third encapsulation layer, while the encapsulation layer in the isolation dam area 302 has a stacked structure of first encapsulation layer / third encapsulation layer.

[0176] The following is an illustrative explanation using the preparation process of a display substrate. The "patterning process" mentioned in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spraying, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, which are not limited in this disclosure. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0177] In one exemplary embodiment, as shown in Figures 7 to 22 , a display substrate includes a display area 100 and an edge area 300. The edge area 300 includes a circuit area 301 and an isolation dam area 302, which are sequentially arranged away from the display area 100. The circuit area 301 includes a first circuit area 301A, a second circuit area 301A, and a third circuit area 301C, which are sequentially arranged away from the display area 100. The display area 100 includes a pixel driving circuit 101. The first circuit area 301A includes a first driving circuit 201, the second circuit area 301A includes a second driving circuit 202, and the isolation dam area 302 and the third circuit area 301C include a third driving circuit 203. The pixel driving circuit 101, the first driving circuit 201, the second driving circuit 202, and the third driving circuit 203 each include at least a plurality of transistors and at least one capacitor. Figures 7 to 22 only illustrate one transistor in the pixel driving circuit, and one transistor and one capacitor in each of the first to third driving circuits.

[0178] An exemplary embodiment provides a process for preparing a display substrate, which may include:

[0179] (1) A substrate 10 is provided, and a display circuit layer pattern is prepared on the substrate 10. The display circuit layer pattern includes: a driving structure layer located in the display area 100 and a circuit structure layer pattern located in the peripheral area 300. The driving structure layer of the display area 100 includes a pixel driving circuit 101, and the circuit structure layer of the peripheral area 300 includes a first driving circuit 201 located in a first circuit area 301A, a second driving circuit 202 located in a second circuit area 301B, and a third driving circuit 203 located in a third circuit area 301C. It also includes a first power supply unit 310A located in the isolation dam area 302, a clock signal line ECLK of the third driving circuit 203, and a crack detection line 320, as shown in Figures 7 and 8. Figure 7 is a schematic diagram after the display circuit layer is formed, and Figure 8 is a cross-sectional view along the AA direction of Figure 7.

[0180] In an exemplary embodiment, the substrate 10 may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). After this process, both the display area 100 and the peripheral area 300 include the substrate 10.

[0181] In an exemplary embodiment, the preparation process of the display circuit layer may include:

[0182] A first insulating film and a semiconductor film are sequentially deposited on a substrate 10, and the semiconductor film is patterned through a patterning process to form a first insulating layer 11 covering the entire substrate 10, and a semiconductor layer pattern arranged on the first insulating layer 11. The semiconductor layer pattern includes at least a first active layer located in the display area 100, a second active layer located in the first circuit area 301A, a third active layer located in the second circuit area 301B, and a fourth active layer located in the third circuit area 301C.

[0183] Subsequently, a second insulating film and a first metal film are deposited in sequence, and the first metal film is patterned through a patterning process to form a second insulating layer 12 covering the semiconductor layer pattern and the entire substrate, and a first gate metal layer pattern arranged on the second insulating layer 12. The first gate metal layer pattern includes at least a first gate electrode located in the display area 100, a second gate electrode and a first capacitor electrode located in the first circuit area 301A, a third gate electrode and a second capacitor electrode located in the second circuit area 301B, and a fourth gate electrode and a third capacitor electrode located in the third circuit area 301C.

[0184] Subsequently, a third insulating film and a second metal film are deposited in sequence, and the second metal film is patterned through a patterning process to form a third insulating layer 13 covering the first gate metal layer pattern and the entire substrate, and a second gate metal layer pattern arranged on the third insulating layer 13. The second gate metal layer pattern includes at least a fourth capacitor electrode located in the first circuit area 301A, a fifth capacitor electrode located in the second circuit area 301B, and a sixth capacitor electrode located in the third circuit area 301C.

[0185] In an exemplary embodiment, an orthographic projection of the first capacitor electrode on the substrate at least partially overlaps with an orthographic projection of the fourth capacitor electrode on the substrate, and the first capacitor electrode and the fourth capacitor electrode constitute a capacitor in the first driving circuit.

[0186] In an exemplary embodiment, an orthographic projection of the second capacitor electrode on the substrate at least partially overlaps with an orthographic projection of the fifth capacitor electrode on the substrate, and the second capacitor electrode and the fifth capacitor electrode constitute a capacitor in the second driving circuit.

[0187] In an exemplary embodiment, an orthographic projection of the third capacitor electrode on the substrate at least partially overlaps with an orthographic projection of the sixth capacitor electrode on the substrate, and the third capacitor electrode and the sixth capacitor electrode constitute a capacitor in the third driving circuit.

[0188] Subsequently, a fourth insulating film is deposited and patterned through a patterning process to form a fourth insulating layer 14 that covers the second gate metal layer pattern and the entire substrate. The second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 have vias in the display area 100 that expose the first active layer, a via in the first circuit area 301A that exposes the second active layer, a via in the second circuit area 301B that exposes the third active layer, and a via in the third circuit area 301C that exposes the fourth active layer.

[0189] Subsequently, a third metal film is deposited and patterned through a patterning process to form a first source-drain metal layer pattern on the fourth insulating layer 14. The first source-drain metal layer pattern includes at least: a first source electrode and a first drain electrode located in the display area 100, a second source electrode and a second drain electrode located in the first circuit area 301A, a third source electrode and a third drain electrode located in the second circuit area 301B, a fourth source electrode and a fourth drain electrode located in the third circuit area 301C, and a first power supply part 310A formed in the isolation dam area 302, a clock signal line ECLK of the third driving circuit, and a crack detection line 320.

[0190] In an exemplary embodiment, the first power supply unit 310A formed in the isolation dam area 302, the clock signal line ECLK of the third driving circuit, and the crack detection line 320 are arranged on the fourth insulating layer 14. The crack detection line 320 is arranged at the end of the first power supply unit 310A away from the display area 100, and the clock signal line ECLK of the third driving circuit is located at the end of the first power supply unit 310A close to the display area 100.

[0191] In an exemplary embodiment, the first source electrode and the first drain electrode are connected to the first active layer through the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14 via holes, respectively; the second source electrode and the second drain electrode are connected to the second active layer through the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14, respectively; the third source electrode and the third drain electrode are connected to the third active layer through the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14, respectively; and the fourth source electrode and the fourth drain electrode are connected to the fourth active layer through the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14, respectively.

[0192] At this point, the display circuit layer pattern is completed on the substrate.

[0193] In an exemplary embodiment, the first active layer may include the active layers of all transistors in the pixel driving circuit, the first gate electrode may include: the gate electrode of the active layers of all transistors in the pixel driving circuit, the first source electrode may include: the source electrode of all transistors in the pixel driving circuit, and the first drain electrode may include: the drain electrode of all transistors in the pixel driving circuit.

[0194] In an exemplary embodiment, the second active layer may include the active layers of all transistors in the first driving circuit, the second gate electrode may include: the gate electrode of the active layers of all transistors in the first driving circuit, the second source electrode may include: the source electrode of all transistors in the first driving circuit, and the second drain electrode may include: the drain electrode of all transistors in the first driving circuit.

[0195] In an exemplary embodiment, the third active layer may include the active layers of all transistors in the second driving circuit, the third gate electrode may include: the gate electrode of the active layers of all transistors in the second driving circuit, the third source electrode may include: the source electrode of all transistors in the second driving circuit, and the third drain electrode may include: the drain electrode of all transistors in the second driving circuit.

[0196] In an exemplary embodiment, the fourth active layer may include the active layers of all transistors in the third driving circuit, the fourth gate electrode may include: the gate electrode of the active layers of all transistors in the third driving circuit, the fourth source electrode may include: the source electrode of all transistors in the third driving circuit, and the fourth drain electrode may include: the drain electrode of all transistors in the third driving circuit.

[0197] In an exemplary embodiment, the distance L1 between the first power supply unit 310A and the third driving circuit 203 is greater than or equal to 3 microns and less than or equal to 5 microns. For example, the distance between the first power supply unit 310A and the third driving circuit 203 can be 4 microns, and this disclosure does not impose any limitation on this.

[0198] In an exemplary embodiment, the distance L1 between the first power supply unit 310A and the third driving circuit 203 may refer to the shortest distance between the first power supply unit and the clock signal line ECLK of the third driving circuit.

[0199] In an exemplary embodiment, the distance L2 between the first power supply unit 310A and the crack detection line 320 is greater than or equal to 3 microns and less than or equal to 5 microns. For example, the distance between the first power supply unit 310A and the crack detection line 320 can be 4 microns, and the present disclosure does not impose any limitation on this.

[0200] In an exemplary embodiment, the distance L1 between the first power supply unit 310A and the third driving circuit 203 and the distance L2 between the first power supply unit 310A and the crack detection line 320 may be equal or unequal, which is not limited in the present disclosure.

[0201] In an exemplary embodiment, the thickness of the first source / drain metal layer may be approximately 700 nm to 1000 nm. For example, the thickness of the first source / drain metal layer may be approximately 860 nm.

[0202] (2) A first organic film is coated on the substrate on which the aforementioned pattern is formed, and the first flat film is patterned by a patterning process to form a first organic layer pattern. The first organic layer pattern includes: a first flat layer 15 located in the display area 100, the circuit area 301, and the isolation dam area 302, and a first dam base 421 and a first protective layer 431 located in the isolation dam area 302, as shown in Figures 9 and 10. Figure 9 is a schematic diagram after the first organic layer is formed, and Figure 10 is a cross-sectional view of Figure 9 along the AA direction.

[0203] In an exemplary embodiment, the first planar layer 15 is provided with a first via hole V1 exposing the first drain electrode.

[0204] In an exemplary embodiment, the orthographic projection of the first planar layer 15 on the substrate covers the orthographic projection of the clock signal line ECLK of the third driving circuit on the substrate, and has no overlapping area with the orthographic projection of the first power supply unit 310A on the substrate.

[0205] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the first via hole V1 can be a triangle, a rectangle, a polygon, a circle, an ellipse, or the like.

[0206] In an exemplary embodiment, the shape of the first via hole V1 may be a rectangle, the length of the rectangle may be approximately 10 μm to 40 μm, the width of the rectangle may be approximately 10 μm to 40 μm, and the distance between adjacent first via holes V5 may be approximately 10 μm to 40 μm.

[0207] In an exemplary embodiment, the surface of the first planar layer located in the isolation dam region 302 is uneven. The first planar layer located in the isolation dam region 302 includes a first sub-planar layer and a second sub-planar layer. The first sub-planar layer P1 is located on a side of the second sub-planar layer P2 away from the display area 100. The thickness of the first sub-planar layer P1 is less than that of the second sub-planar layer P2.

[0208] In an exemplary embodiment, the orthographic projection of the second sub-planar layer P2 on the substrate covers the third driving circuit 203 .

[0209] In an exemplary embodiment, the thickness of the first sub-planar layer P1 may be equal to the thickness of the first power supply part 310A, and the thickness of the second sub-planar layer P2 may be equal to the thickness of the first planar layer located in the display area 100 .

[0210] In an exemplary embodiment, the first dam 421 is located on a side of the first power supply unit 310A away from the substrate, and an orthographic projection of the first power supply unit 310A on the substrate at least partially overlaps with an orthographic projection of the first dam 421 on the substrate.

[0211] In an exemplary embodiment, the length of the first dam base 421 along the first direction is less than the length of the first power supply unit 310A along the first direction, that is, the first power supply unit 310A is exposed on both the side of the first dam base 421 close to the display area and the side away from the display area.

[0212] In an exemplary embodiment, the first protection layer 431 is located on a side of the first dam 421 away from the display area 100 .

[0213] In an exemplary embodiment, the orthographic projection of the first protective layer 431 on the substrate covers the orthographic projection of the crack detection line 320 on the substrate, and at least partially overlaps with the orthographic projection of the first power supply unit 310A on the substrate, that is, the first protective layer 431 covers the crack detection line 320 and the end of the first power supply unit 310A away from the display area 100.

[0214] In an exemplary embodiment, the length of the first dam 421 along the first direction may be approximately 20 μm to 60 μm, and the first dam 421 is configured to form a second isolation dam.

[0215] In one exemplary embodiment, the cross-sectional shape of the first dam 421 in a plane perpendicular to the display substrate may be trapezoidal or rectangular. When the cross-sectional shape of the first dam 421 is trapezoidal, the length of the surface away from the substrate is shorter than the length of the surface close to the substrate. The length of the surface away from the substrate may be approximately 20 μm to 40 μm.

[0216] (3) A fourth metal film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth metal film is patterned through a patterning process to form a second source-drain metal layer pattern. The second source-drain metal layer pattern includes at least a connecting electrode 17 located in the display area 100 and a second power supply portion 310B located in the circuit area 301 and the isolation dam area 302, as shown in Figures 11 and 12. Figure 11 is a schematic diagram after the second source-drain metal layer is formed, and Figure 12 is a schematic diagram of Figure 11 along the AA direction.

[0217] In an exemplary embodiment, the connection electrode 17 is electrically connected to the first drain electrode through the first via hole V1 .

[0218] In an exemplary embodiment, the second power supply unit 310B is located at least in the isolation dam region 302 and the third circuit region 301C.

[0219] In an exemplary embodiment, the second power supply unit 310B may also be located in the second circuit region 301B.

[0220] In an exemplary embodiment, the orthographic projection of the second power supply unit 310B on the substrate covers the orthographic projections of the first power supply unit 310A and the third driving circuit 203 on the substrate, and partially overlaps with the orthographic projection of the first protection layer 431 on the substrate.

[0221] In an exemplary embodiment, the distance between the end of the second power supply unit 310B away from the display area and the display area can be greater than or equal to the distance between the end of the first power supply unit 310A away from the display area and the display area. Figure 12 illustrates an example in which the distance between the end of the second power supply unit 310B away from the display area and the display area is equal to the distance between the end of the first power supply unit 310A away from the display area and the display area.

[0222] In an exemplary embodiment, the orthographic projection of the second power supply unit 310B on the substrate does not overlap with the orthographic projection of the second drive circuit 202 on the substrate. The distance between the end of the second power supply unit 310B closest to the display area 100 and the display area 100 is greater than the distance between the clock signal line in the second drive circuit 202 and the display area 100. In other words, the orthographic projection of the second power supply unit 310B on the substrate does not overlap with the orthographic projection of the clock signal line in the second drive circuit 202 on the substrate. This non-overlapping orthographic projection of the second power supply unit 310B on the substrate and the clock signal line in the second drive circuit 202 on the substrate ensures the display effect of the display substrate.

[0223] In an exemplary embodiment, the second power supply unit 310B covers the surface of the first dam base 421, and the second power supply unit 310B is arranged on the first power supply unit 310A exposed on both sides of the first dam base 421, so as to realize the connection between the second power supply unit 310B and the first power supply unit 310A.

[0224] In an exemplary embodiment, the distance between the end of the crack detection line 320 close to the display area and the display area is greater than the distance between the end of the second power supply unit 310B away from the display area and the display area, that is, the orthographic projection of the second power supply unit 310B on the substrate does not overlap with the orthographic projection of the crack detection line 320 on the substrate.

[0225] In an exemplary embodiment, the second power supply unit 310B is provided with a plurality of second vias V2 that expose the first planarization layer 15. The second vias V2 are configured to release gas from the first planarization layer 15, thereby forming a degassing channel. This channel discharges gas generated by the planarization film during the process, thereby preventing peeling of the film and improving process quality.

[0226] In an exemplary embodiment, there are multiple second via holes V2 , and the multiple second via holes V2 are arranged in a matrix, so as to evenly release the gas in the first planar layer 15 .

[0227] In this way, the first power supply part 310A of the first source-drain metal layer and the second power supply part 310B of the second source-drain metal layer form a double-layer power supply line in the edge area 300, and the double-layer power supply line with a parallel structure is realized by overlapping in the isolation dam area 302, thereby reducing the resistance of the power supply line in the edge area 200, minimizing the voltage drop of the voltage signal, improving the uniformity of the display brightness in the display area, and improving the display quality.

[0228] In an exemplary embodiment, the second via hole may be in a triangular, rectangular, polygonal, circular, or elliptical shape. In an exemplary embodiment, the second via hole may be in a rectangular shape, the length of the rectangle may be approximately 10 μm to 40 μm, the width of the rectangle may be approximately 10 μm to 40 μm, and the distance between adjacent second via holes may be approximately 10 μm to 40 μm.

[0229] In an exemplary embodiment, the first dam base 421 includes a first surface, a first proximal side surface, and a first distal side surface. The second power supply unit 310B covering the surface of the first dam base 421 may mean that the second power supply unit 310B completely covers the first surface, the first proximal side surface, and the first distal side surface of the first dam base 401, i.e., the second power supply unit 310B wraps around the first surface, the first proximal side surface, and the first distal side surface of the first dam base 401.

[0230] In an exemplary embodiment, the thickness of the second source / drain metal layer may be approximately 700 nm to 1000 nm. In some possible implementations, the thickness of the second source / drain metal layer may be approximately 860 nm.

[0231] (4) A second organic film is coated on the substrate on which the aforementioned pattern is formed, and the second organic film is patterned through a patterning process to form a second organic layer pattern. The second organic layer pattern includes: a second flat layer 16 located in the display area 100 and the circuit area 301, a second dam base 411 located in the isolation dam area 302, a third dam base 422, and a second protective layer 432, as shown in Figures 13 and 14. Figure 13 is a schematic diagram after the second organic layer is formed, and Figure 14 is a cross-sectional view of Figure 13 along the AA direction.

[0232] In an exemplary embodiment, the second planar layer 16 is formed with a third via hole V3 exposing the connection electrode 17 and a fourth via hole V4 exposing the surface of the second power supply unit 310B.

[0233] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate does not overlap with the orthographic projection of the second via hole V2 on the substrate.

[0234] In an exemplary embodiment, a width W1 of the fourth via hole V4 along the first direction is smaller than a distance W2 between two adjacent second via holes arranged along the first direction.

[0235] In an exemplary embodiment, in a plane parallel to the display substrate, the shapes of the third via hole V3 and the fourth via hole V4 may be triangular, rectangular, polygonal, circular, elliptical, or the like.

[0236] In an exemplary embodiment, the shape of the third via V3 and the fourth via V4 may be a rectangle, the length of the rectangle may be approximately 10 μm to 40 μm, the width of the rectangle may be approximately 10 μm to 40 μm, and the distance between adjacent third vias and adjacent fourth vias may be approximately 10 μm to 40 μm.

[0237] In an exemplary embodiment, the second planar layer 16 covers an end of the second power supply portion 310B close to the display area 100 , and an orthographic projection of the second planar layer 16 on the substrate covers an orthographic projection of the second via hole on the substrate.

[0238] In an exemplary embodiment, the distance between the end of the second flat layer 16 away from the display area 100 and the display area 100 is smaller than the distance between the end of the third driving circuit 203 away from the display area 100 and the display area 100, and the distance between the end of the second flat layer 16 away from the display area 100 and the display area 100 is smaller than the distance between the end of the first flat layer 15 away from the display area 100 and the display area 100.

[0239] In an exemplary embodiment, the second dam 411 is disposed on the second power supply part 310B on a side of the first dam 421 adjacent to the display area 100 .

[0240] In an exemplary embodiment, an orthographic projection of the second dam 411 on the substrate at least partially overlaps with an orthographic projection of the clock signal line of the third driving circuit on the substrate.

[0241] In an exemplary embodiment, both a side of the second dam 411 adjacent to the display area 100 and a side of the second dam 411 away from the display area 100 expose the second power supply part 310B.

[0242] In one exemplary embodiment, the cross-sectional shape of the second dam 411 in a plane perpendicular to the display substrate may be trapezoidal or rectangular. When the cross-sectional shape of the second dam 411 is trapezoidal, the length of the surface away from the substrate is shorter than the length of the surface close to the substrate. The length of the surface away from the substrate may be approximately 20 μm to 40 μm.

[0243] In an exemplary embodiment, the length of the second dam 411 along the first direction may be approximately 20 μm to 60 μm, and the second dam 411 is configured to form a first isolation dam.

[0244] In an exemplary embodiment, the third dam 422 is disposed on the second power supply part 310B covering the first dam 421 , and an orthographic projection of the third dam 422 on the substrate covers an orthographic projection of the first dam 421 on the substrate.

[0245] In one exemplary embodiment, the cross-sectional shape of the third dam 422 in a plane perpendicular to the display substrate can be trapezoidal or rectangular. When the cross-sectional shape of the third dam 422 is trapezoidal, the length of the surface away from the substrate is shorter than the length of the surface close to the substrate. The length of the surface away from the substrate can be approximately 20 μm to 40 μm.

[0246] In an exemplary embodiment, the orthographic projection of the second protection layer 432 on the substrate covers the orthographic projection of the first protection layer 431 on the substrate, that is, the second protection layer 432 covers the end of the second power supply unit 310B away from the display area 100 .

[0247] In an exemplary embodiment, the length of the third dam 422 along the first direction may be approximately 20 μm to 60 μm, and the first dam 421 and the third dam 422 are configured to form a second isolation dam.

[0248] (5) A transparent conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the transparent conductive film is patterned through a patterning process to form a transparent conductive layer pattern. The transparent conductive layer pattern includes: an anode 21 located in the display area 100 and an auxiliary power line 330 located in the edge area 300, as shown in Figures 15 and 16. Figure 15 is a schematic diagram after the transparent conductive layer is formed, and Figure 16 is a cross-sectional view of Figure 15 along the AA direction.

[0249] In an exemplary embodiment, the anode 21 is formed on the second planar layer 16 of the display area 100 and is connected to the connection electrode 17 through the third via hole V3.

[0250] In an exemplary embodiment, the auxiliary power line 330 is electrically connected to the second power supply unit 310B, wherein a portion of the auxiliary power line 330 is overlapped on the second power supply unit 310B, and another portion is connected to the second power supply unit 310B through a fourth via V4.

[0251] In an exemplary embodiment, the orthographic projection of the auxiliary power line 330 on the substrate at least partially overlaps with the orthographic projection of the third dam base 422 on the substrate, and the distance between the end of the auxiliary power line 330 away from the display area 100 and the display area 100 is smaller than the distance between the end of the third dam base 422 away from the display area 100 and the display area 100, that is, the auxiliary power line 330 partially covers the third dam base 422.

[0252] In an exemplary embodiment, the third dam base 422 includes a third surface, a third proximal side surface, and a third distal side surface. The auxiliary power line 330 partially covering the third dam base 422 may mean that the auxiliary power line 330 partially covers the third surface of the third dam base 422 and completely covers the second proximal side surface of the third dam base.

[0253] In an exemplary embodiment, the orthographic projection of the auxiliary power line 330 on the substrate covers the orthographic projection of the second dam base 411 on the substrate, that is, the auxiliary power line 330 covers the second dam base 411 .

[0254] In an exemplary embodiment, the second dam base 411 includes a second surface, a second proximal side, and a second distal side. The auxiliary power line 330 covering the second dam base 411 may mean that the auxiliary power line 330 completely covers the second surface, the second proximal side, and the second distal side of the second dam base 411. In other words, the auxiliary power line 330 wraps around the second surface, the second proximal side, and the second distal side of the second dam base 411.

[0255] In one exemplary embodiment, the orthographic projection of the auxiliary power line 330 at least partially overlaps with the orthographic projection of the second power supply portion 310B exposed on both sides of the second dam base 411 on the substrate. That is, the auxiliary power line 330 covers the second power supply portion 310B exposed on both sides of the second dam base 411 and is electrically connected to the second power supply portion 310B exposed on both sides of the second dam base 411. Since the auxiliary power line 330 is connected to the second power supply portion 310B, the auxiliary power line 330 is connected to the power line 310.

[0256] In an exemplary embodiment, the orthographic projection of the auxiliary power line 330 on the substrate at least partially overlaps with the orthographic projections of the first driving circuit 201 , the second driving circuit 202 , and the third driving circuit 203 on the substrate.

[0257] In an exemplary embodiment, the auxiliary power line 330 is provided with a fifth via hole V5 exposing the second planar layer 16 , and the fifth via hole V5 is located in the first circuit area 301A, the second circuit area 301B, and the third circuit area 301C.

[0258] In an exemplary embodiment, an orthographic projection of the fifth via hole V5 located in the third circuit region 301C on the substrate at least partially overlaps with an orthographic projection of the second via hole V2 on the substrate.

[0259] In an exemplary embodiment, the fifth via V5 is configured to release gas in the second planar layer 16 to form a degassing channel to discharge gas generated by the planarization film during the process, thereby avoiding peeling of the film layer and improving process quality.

[0260] In an exemplary embodiment, there are multiple fifth via holes V5 , and the multiple fifth via holes V5 are arranged in a matrix, so as to evenly release the gas in the second planar layer 16 .

[0261] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the fifth via hole V5 can be a triangle, a rectangle, a polygon, a circle, an ellipse, or the like.

[0262] In an exemplary embodiment, the fifth via hole V5 may be rectangular in shape, the length of the rectangle may be approximately 10 μm to 40 μm, the width of the rectangle may be approximately 10 μm to 40 μm, and the distance between adjacent fifth via holes V5 may be approximately 10 μm to 40 μm.

[0263] (6) A third organic film is coated on the substrate on which the aforementioned pattern is formed, and the third organic film is patterned through a patterning process to form a third organic layer pattern. The third organic layer pattern includes: a pixel definition layer 22 located in the display area 100, an isolation layer 23 located in the circuit area 301, and a fourth dam base 412 and a fifth dam base 423 located in the isolation dam area 302. FIG17 is a schematic diagram after the third organic layer is formed, and FIG18 is a schematic diagram along the AA direction of FIG17.

[0264] In an exemplary embodiment, a sixth via hole V6 exposing the anode 21 is formed on the pixel definition layer 22 .

[0265] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the sixth via hole V6 may be a triangle, a rectangle, a polygon, a circle, an ellipse, or the like.

[0266] In an exemplary embodiment, the sixth via hole V6 may be rectangular in shape, the length of the rectangle may be approximately 10 μm to 40 μm, the width of the rectangle may be approximately 10 μm to 40 μm, and the distance between adjacent sixth via holes V6 may be approximately 10 μm to 40 μm.

[0267] In an exemplary embodiment, the distance between the end of the isolation layer 23 closer to the display area 100 and the display area 100 is equal to the distance between the end of the pixel definition layer 22 away from the display area 100 and the display area 100, and the distance between the end of the isolation layer 23 away from the display area 100 and the display area 100 is less than or equal to the distance between the end of the second planar layer 16 away from the display area 100 and the display area 100.

[0268] In an exemplary embodiment, the distance between the end of the isolation layer 23 away from the display area and the display area is less than or equal to the distance between the end of the second planar layer away from the display area and the display area.

[0269] In an exemplary embodiment, the orthographic projection of the isolation layer 23 on the substrate covers the orthographic projection of the fifth via hole on the substrate.

[0270] In an exemplary embodiment, the isolation layer 23 is provided with a plurality of seventh vias V7 that expose the auxiliary power line 330. The plurality of seventh vias V7 may be arranged in an array, or the plurality of seventh vias may be interconnected. FIG17 and FIG18 illustrate the case where the plurality of seventh vias may be interconnected.

[0271] In an exemplary embodiment, the plurality of seventh vias V7 are located in the first circuit region 301A, the second circuit region 301B, and the third circuit region 301C.

[0272] In an exemplary embodiment, an orthographic projection of the seventh via V7 located in the third circuit region 301C on the substrate at least partially overlaps with an orthographic projection of the fourth via V4 on the substrate.

[0273] In an exemplary embodiment, the fourth dam base 412 is disposed on the auxiliary power line 330 covering the second dam base 411 , and the orthographic projection of the fourth dam base 412 on the substrate covers the orthographic projection of the second dam base 411 on the substrate.

[0274] In an exemplary embodiment, the length of the fourth dam 412 along the first direction may be approximately 20 μm to 60 μm.

[0275] In one exemplary embodiment, the cross-sectional shape of the fourth dam 412 in a plane perpendicular to the display substrate may be trapezoidal or rectangular. When the cross-sectional shape of the fourth dam 412 is trapezoidal, the length of the surface away from the substrate is shorter than the length of the surface close to the substrate. The length of the surface away from the substrate may be approximately 20 μm to 40 μm.

[0276] In an exemplary embodiment, the fifth dam base 423 is disposed on the third dam base 422 , and the orthographic projection of the fifth dam base 423 on the substrate covers the orthographic projection of the third dam base 422 on the substrate.

[0277] In an exemplary embodiment, the fifth dam 423 may be approximately 20 μm to 60 μm in thickness along the first direction.

[0278] In one exemplary embodiment, the cross-sectional shape of the fifth dam 423 in a plane perpendicular to the display substrate may be trapezoidal or rectangular. When the cross-sectional shape of the fifth dam 423 is trapezoidal, the length of the surface away from the substrate is shorter than the length of the surface close to the substrate. The length of the surface away from the substrate may be approximately 20 μm to 40 μm.

[0279] In an exemplary embodiment, the auxiliary power line 330 is exposed between the fourth dam 412 and the fifth dam 423 , and the auxiliary power line 330 is exposed on a side of the fourth dam 412 close to the display area 100 .

[0280] (7) An organic light-emitting layer 24 is formed on the substrate having the aforementioned pattern, as shown in FIG19 and FIG20 . FIG19 is a schematic diagram after the organic light-emitting layer is formed, and FIG20 is a cross-sectional view along the AA direction of FIG19 .

[0281] In an exemplary embodiment, the organic light-emitting layer 24 is formed in the sixth via hole V6 of the pixel defining layer of the display area 100, thereby connecting the organic light-emitting layer 24 to the anode 21. Since the anode 21 is connected to the connection electrode 17, and the connection electrode 17 is connected to the first drain electrode, the organic light-emitting layer 24 is connected to the first drain electrode.

[0282] In an exemplary embodiment, the organic light-emitting layer 24 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0283] (8) A cathode 25 located in the display area 100 and the circuit area 301 and a sixth dam base 413 and a seventh dam base 424 located in the isolation dam area 302 are formed on the substrate on which the aforementioned pattern is formed, as shown in FIG21 and FIG22 . FIG21 is a schematic diagram after the cathode is formed, and FIG22 is a cross-sectional view of FIG21 along the AA direction.

[0284] In an exemplary embodiment, the distance between the end of the cathode 25 away from the display region 100 and the display region 100 is smaller than the distance between the side of the isolation layer 23 away from the display region 100 and the display region 100 .

[0285] In an exemplary embodiment, a portion of the cathode 25 is formed on the organic light emitting layer 24 of the display area 100 and connected to the organic light emitting layer 24 , and another portion of the cathode 25 is connected to the auxiliary power line 330 through a seventh via hole.

[0286] In an exemplary embodiment, since the cathode 25 is connected to the auxiliary power line 330 , and the auxiliary power line 330 is electrically connected to the second power supply portion 310B of the power line 310 , the connection between the cathode 25 and the power line 310 is achieved.

[0287] In an exemplary embodiment, the cathode may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.

[0288] In an exemplary embodiment, the sixth dam base 413 is disposed on the fourth dam base 412 , and the orthographic projection of the fourth dam base on the substrate covers the orthographic projection of the sixth dam base 413 on the substrate.

[0289] In an exemplary embodiment, the sixth dam 413 may be approximately 20 μm to 60 μm in thickness along the first direction.

[0290] In one exemplary embodiment, the cross-sectional shape of the sixth dam 413 in a plane perpendicular to the display substrate may be trapezoidal or rectangular. When the cross-sectional shape of the sixth dam 413 is trapezoidal, the length of the surface away from the substrate is shorter than the length of the surface close to the substrate. The length of the surface away from the substrate may be approximately 20 μm to 40 μm.

[0291] In an exemplary embodiment, the second dam 402 , the auxiliary power line 330 covering the second dam, the fourth dam 411 , and the sixth dam 413 form a first isolation dam 410 .

[0292] In an exemplary embodiment, the seventh dam base 424 is disposed on the fifth dam base 423 , and the orthographic projection of the fifth dam base 423 on the substrate covers the orthographic projection of the seventh dam base 424 on the substrate.

[0293] In an exemplary embodiment, the seventh dam 424 may be approximately 20 μm to 60 μm in thickness along the first direction.

[0294] In one exemplary embodiment, the cross-sectional shape of the seventh dam 424 in a plane perpendicular to the display substrate can be trapezoidal or rectangular. When the cross-sectional shape of the seventh dam 424 is trapezoidal, the length of the surface away from the substrate is shorter than the length of the surface close to the substrate. The length of the surface away from the substrate can be approximately 20 μm to 40 μm.

[0295] In an exemplary embodiment, the first dam 421 , the second power supply part 310B covering the first dam, the third dam 422 , the fifth dam 423 , and the seventh dam 424 form the second isolation dam 420 .

[0296] In an exemplary embodiment, a distance between the first isolation dam 410 and the display area 100 is smaller than a distance between the second isolation dam 420 and the display area 100 .

[0297] In an exemplary embodiment, the length of the orthographic projection of the first isolation dam 410 and the second isolation dam 420 on the substrate along the first direction may be approximately 20 μm to 60 μm, and the distance between the first isolation dam 410 and the second isolation dam 420 may be approximately 20 μm to 60 μm.

[0298] In an exemplary embodiment, in a plane perpendicular to the display substrate, the cross-sectional shape of the first isolation dam 410 and the second isolation dam 420 may be trapezoidal.

[0299] In an exemplary embodiment, the sixth dam 413 and the seventh dam 424 are an integrally formed structure. The cathode 25 can be formed before the sixth dam 413 and the seventh dam 424, or after the sixth dam 413 and the seventh dam 424.

[0300] In an exemplary embodiment, an orthographic projection of the first isolation dam 410 on the substrate at least partially overlaps with an orthographic projection of the clock signal line of the third driving circuit on the substrate.

[0301] (9) On the basis of forming the aforementioned pattern, the encapsulation layer 26 is formed. The encapsulation layer 26 is formed in the display area 100 , the circuit area 301 and the isolation dam area 302 , as shown in FIG. 5 .

[0302] In an exemplary embodiment, the encapsulation layer 26 of the display area 100 and the circuit area 301 adopts a stacked structure of a first encapsulation layer 261 , a second encapsulation layer 262 and a third encapsulation layer 263 , and the encapsulation layer 26 of the isolation dam area 302 adopts a stacked structure of a first encapsulation layer 261 and a third encapsulation layer 263 .

[0303] In one exemplary embodiment, the first encapsulation layer may be made of an inorganic material, covering the cathode 25 in the display area 100, covering the spacer column layer 23 in the circuit area 301, and encapsulating the first isolation dam 410 and the second isolation dam 420 in the isolation dam area 302. The second encapsulation layer may be made of an organic material and disposed in the display area 100 and the circuit area 301. The third encapsulation layer may be made of an inorganic material, covering the second encapsulation layer in the display area 100 and the circuit area 301, and the first encapsulation layer in the isolation dam area 302. That is, the encapsulation layer 26 in the display area 100 and the circuit area 301 adopts a laminated structure of inorganic material / organic material / inorganic material, with the organic material layer disposed between the two inorganic material layers, and the encapsulation layer 26 in the isolation dam area 302 adopts a laminated structure of inorganic material / inorganic material.

[0304] In one exemplary embodiment, the first, second, third, and fourth insulating layers may be formed of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single layers, multiple layers, or composite layers. The first insulating layer is referred to as a buffer layer, which is used to improve the substrate's resistance to water and oxygen. The second and third insulating layers are referred to as gate insulating (GI) layers, and the fourth insulating layer is referred to as an interlayer dielectric (ILD) layer.

[0305] In an exemplary embodiment, the first metal film, the second metal film, the third metal film, and the fourth metal film can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The transparent conductive film can include indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel definition layer can be made of polyimide, acrylic, or polyethylene terephthalate. The active layer film can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0306] The exemplary embodiment of the present disclosure forms a first power supply portion 310A of the power supply line 310 through a first source-drain metal layer, and forms a second power supply portion 310B of the power supply line 310 through a second source-drain metal layer, so as to form a double-layer power supply line 310 in the edge area 300, thereby realizing a double-layer power supply line with a parallel structure, reducing the resistance of the power supply line in the edge area 300, minimizing the voltage drop of the voltage signal, improving the display brightness uniformity of the display area 100, and improving the display quality.

[0307] In an exemplary embodiment, the distance between the first power supply unit 310A and the third driving circuit 203 is greater than or equal to 1 micron and less than or equal to 6 microns. For example, the distance between the first power supply unit 310A and the third driving circuit 203 can be 4 microns, and this disclosure does not impose any limitation on this.

[0308] In an exemplary embodiment, the distance between the first power supply unit 310A and the crack detection line 320 is greater than or equal to 1 micron and less than or equal to 6 microns. For example, the distance between the first power supply unit 310A and the crack detection line 320 can be 4 microns, and the present disclosure does not impose any limitation on this.

[0309] In the present disclosure, the distance setting between the first power supply unit 310A and the third driving circuit 203 and the distance setting between the first power supply unit 310A and the crack detection line 320 make the width of the first power supply unit 310A large enough while ensuring the exposure, etching and other processes and signal interference requirements of the display substrate, thereby reducing the voltage drop of the power line, improving the display uniformity of the display substrate, and reducing the power consumption of the display substrate.

[0310] In the present disclosure, the distance between the first power supply unit 310A and the third driving circuit 203 and the distance between the first power supply unit 310A and the crack detection line 320 may be equal or unequal, and the present disclosure does not impose any limitation on this.

[0311] In the present disclosure, the orthographic projection of the second power supply unit 310B on the substrate 10 covers the orthographic projections of the first power supply unit 310A and the third driving circuit 203 on the substrate 10. The configuration of the second power supply unit 310B in the present disclosure ensures that the length of the second power supply unit 310B along the first direction is sufficiently large, reducing the voltage drop of the power supply line, thereby improving the display uniformity of the display substrate and reducing the power consumption of the display substrate.

[0312] In the present disclosure, the distance between the end of the second power supply unit 310B close to the display area 100 and the display area 100 is greater than the distance between the clock signal line CLK in the second driving circuit 202 and the display area 100, thereby reducing the load of the clock signal line CLK in the second driving circuit 202 and ensuring the normal display of the display unit in the display area 100.

[0313] In the present disclosure, the first protective layer 431 wraps the end of the first power supply unit 310A away from the display area 100, and the second protective layer 432 wraps the end of the second power supply unit 310B away from the display area 100, which can prevent corrosion and dark spots.

[0314] In the present disclosure, the second planar layer 16 covers the second power supply portion located at the edge of the second via hole, which can prevent corrosion and dark spots.

[0315] In the present disclosure, due to the arrangement of the second power supply unit 310B and the second flat layer, the distance between the end of the first isolation dam 410 close to the display area 100 and the end of the second power supply unit 310B close to the display area can be larger, which can improve the packaging reliability of the display substrate.

[0316] In the present disclosure, the auxiliary power line 330 covers the first drive circuit 201, the second drive circuit 202 and the third drive circuit 203, which can reduce the voltage drop of the power line and shield the interference of the external environment or signals on the first drive circuit 201, the second drive circuit 202 and the third drive circuit 203.

[0317] The exemplary embodiment of the present disclosure provides a second via and a fifth via, respectively, on the second power supply unit 310B and the auxiliary power line 330, to form a venting channel. This effectively discharges gases generated by the planarization layer during the process, preventing film delamination and improving process quality. The exemplary embodiment of the present disclosure demonstrates that the substrate preparation process has good process compatibility, simple and easy implementation, high production efficiency, low production cost, and a high yield rate.

[0318] The structure of the substrate and its preparation process shown in this disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and this disclosure does not limit this.

[0319] The present disclosure also provides a method for preparing a display substrate, which is configured to manufacture a display substrate. The display substrate includes: a display area and an edge area. The method for preparing the display substrate provided by the present disclosure may include the following steps:

[0320] Step S1: providing a substrate.

[0321] Step S2: forming a first power supply portion and a second power supply portion in sequence on the substrate to form a power line located in the edge area.

[0322] In an exemplary embodiment, the orthographic projection of the second power supply unit on the substrate at least partially overlaps with the orthographic projection of the first power supply unit on the substrate, and the distance between an end of the second power supply unit away from the display area and the display area is greater than or equal to the distance between an end of the first power supply unit away from the display area and the display area.

[0323] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0324] In an exemplary embodiment, step S2 may include the following steps:

[0325] A pixel driving circuit in the display area, a first driving circuit in the circuit area, a second driving circuit, a third driving circuit in the third circuit area, and a first power supply unit and a crack detection line in the isolation dam area are formed on the substrate;

[0326] forming a first planarization layer located in the display area and the circuit area, and a first dam base and a first protective layer located in the isolation dam area on the substrate forming the first power supply unit;

[0327] forming a connection electrode located in the display area and a second power supply portion located in the circuit area and the isolation dam area on the substrate on which the first flat layer is formed;

[0328] forming a second planar layer located in the display area and the circuit area, a second dam base located in the isolation dam area, a third dam base and a second protective layer on the substrate forming the second power supply unit;

[0329] forming an anode located in a display area and an auxiliary power supply line located in an edge area on the substrate on which the second flat layer is formed;

[0330] forming a pixel definition layer in the display area, an isolation layer in the circuit area, and a fourth dam base and a fifth dam base in the isolation dam area on the substrate on which the auxiliary power line is formed;

[0331] An organic light emitting layer in the display area, a cathode in the display area and the circuit area, and a sixth dam base and a seventh dam base in the isolation dam area are formed on the substrate on which the pixel definition layer is formed.

[0332] An embodiment of the present disclosure further provides a display device, including a display substrate.

[0333] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0334] In an exemplary embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0335] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising: The display substrate comprises a display area and an edge area located at a side of the display area, wherein the display substrate comprises: a base and a power line arranged on the base and located at the edge area, wherein the power line comprises: a first power supply unit and a second power supply unit connected to each other, wherein the second power supply unit is located at a side of the first power supply unit away from the base; The display area includes: a plurality of display units, at least one display unit includes: a pixel driving circuit and a light emitting device, the pixel driving circuit is electrically connected to an anode of the light emitting device, the power line is electrically connected to a cathode of the light emitting device, The orthographic projection of the second power supply unit on the substrate at least partially overlaps with the orthographic projection of the first power supply unit on the substrate, and the distance between an end of the second power supply unit away from the display area and the display area is greater than or equal to the distance between an end of the first power supply unit away from the display area and the display area.

2. The display substrate according to claim 1, wherein: The edge area includes: a circuit area and an isolation dam area arranged in sequence along a direction away from the display area, and the circuit area includes: a first circuit area, a second circuit area and a third circuit area arranged in sequence along a direction away from the display area; The pixel driving circuit comprises: a writing transistor, a compensation transistor, a light emitting transistor, a first scanning signal line, a second scanning signal line and a light emitting signal line; the first scanning signal line is electrically connected to the control electrode of the writing transistor, the second scanning signal line is electrically connected to the control electrode of the compensation transistor, and the light emitting signal line is electrically connected to the control electrode of the light emitting transistor; the writing transistor and the compensation transistor are of different transistor types; The display substrate further comprises: a first driving circuit located in the first circuit area, a second driving circuit located in the second circuit area, and a third driving circuit located in the third circuit area and the isolation dam area; The first driving circuit is electrically connected to the first scanning signal line, the second driving circuit is electrically connected to the second scanning signal line, and the third driving circuit is electrically connected to the light emitting signal line; The first power supply unit is located in the isolation dam area, and the second power supply unit is located in the isolation dam area and the circuit area; The orthographic projection of the second power supply unit on the substrate at least partially overlaps with the orthographic projection of the third driving circuit on the substrate, and has no overlapping area with the orthographic projection of the second driving circuit on the substrate.

3. The display substrate according to claim 2, further comprising: a crack detection line located in the isolation dam area, the crack detection line being arranged in the same layer as the first power supply unit and being located on a side of the first power supply unit away from the display area; A distance between the first power supply unit and the crack detection line is greater than or equal to 1 micrometer and less than or equal to 6 micrometers.

4. The display substrate according to claim 2, wherein: A distance between the first power supply unit and the third driving circuit is greater than or equal to 1 micrometer and less than or equal to 6 micrometers.

5. The display substrate according to claim 3, further comprising: A first planar layer located in the display area, the circuit area and the isolation dam area and a first protective layer located in the isolation dam area; The first planar layer is located between the first power supply unit and the second power supply unit, and is disposed on the same layer as the first protective layer; The orthographic projection of the first protection layer on the substrate covers the orthographic projection of the crack detection line on the substrate, and at least partially overlaps with the orthographic projection of the first power supply unit on the substrate.

6. The display substrate according to claim 5, wherein: The third driving circuit comprises: a clock signal line located in the isolation dam area; the clock signal line is arranged in the same layer as the first power supply unit and is located on a side of the first power supply unit close to the display area; The orthographic projection of the first planar layer on the substrate covers the orthographic projection of the clock signal line on the substrate, and has no overlapping area with the orthographic projection of the first power supply unit on the substrate.

7. The display substrate according to claim 5, wherein: The second power supply unit is provided with a plurality of second via holes exposing the first planar layer, and the plurality of second via holes are arranged in a matrix; The orthographic projections of the plurality of second via holes on the substrate at least partially overlap with the orthographic projection of the third driving circuit on the substrate.

8. The display substrate according to claim 7, further comprising: A second planar layer located in the display area and the circuit area and a second protective layer located in the isolation dam area; The second planar layer is located at a side of the second power supply unit away from the substrate and is arranged on the same layer as the second protective layer; The orthographic projection of the second protection layer on the substrate covers the orthographic projection of the first protection layer on the substrate, and the orthographic projection of the second planar layer on the substrate covers the orthographic projection of the second via on the substrate.

9. The display substrate according to claim 8, further comprising: Auxiliary power lines located in the marginal area; The anode is located on a side of the second flat layer away from the substrate and is arranged in the same layer as the auxiliary power line; The auxiliary power line is electrically connected to the second power supply unit; The orthographic projection of the auxiliary power line on the substrate at least partially overlaps with the orthographic projections of the first drive circuit, the second drive circuit, and the third drive circuit on the substrate.

10. The display substrate according to claim 9, wherein: The auxiliary power line is provided with a plurality of fifth via holes exposing the second flat layer, and the plurality of fifth via holes are arranged in a matrix; The plurality of fifth vias are located in the first circuit area, the second circuit area and the third circuit area; The orthographic projection of the fifth via hole located in the third circuit area on the substrate at least partially overlaps with the orthographic projection of the second via hole on the substrate.

11. The display substrate according to claim 10, further comprising: A pixel definition layer located in the display area and an isolation layer located in the circuit area; The pixel definition layer is located on a side of the anode away from the substrate and is arranged on the same layer as the isolation layer; The distance between one end of the isolation layer away from the display area and the display area is less than or equal to the distance between one end of the second planar layer away from the display area and the display area, and the orthographic projection of the isolation layer on the substrate covers the orthographic projection of the fifth via hole on the substrate.

12. The display substrate according to claim 11, further comprising: An organic light-emitting layer located in the display area and a cathode located in the display area and the circuit area are sequentially stacked on the substrate; The cathode is electrically connected to the auxiliary power line.

13. The display substrate according to claim 12, wherein: The isolation dam area further includes: a first isolation dam and a second isolation dam; The second isolation dam is located on a side of the first isolation dam away from the display area, and is located on a side of the second protection layer close to the display area.

14. The display substrate according to claim 13, further comprising: A first dam foundation, a third dam foundation, a fifth dam foundation and a seventh dam foundation located in the isolation dam area; The first dam is disposed on the same layer as the first flat layer, the third dam is disposed on the same layer as the second flat layer, the fifth dam is disposed on the same layer as the pixel definition layer, and the seventh dam is located on a side of the pixel definition layer away from the substrate; The second power supply unit is covered on the first dam foundation, the third dam foundation is arranged on the second power supply unit covering the first dam foundation, and the orthographic projection of the third dam foundation on the substrate covers the orthographic projection of the first dam foundation on the substrate, the fifth dam foundation is arranged on the third dam foundation, and the orthographic projection of the fifth dam foundation on the substrate covers the orthographic projection of the third dam foundation on the substrate, and the seventh dam foundation is arranged on the fifth dam foundation, and the orthographic projection of the fifth dam foundation on the substrate covers the orthographic projection of the seventh dam foundation on the substrate; The auxiliary power line partially covers the third dam base; The first dam, the second power supply portion covering the first dam, the third dam, the fifth dam, and the seventh dam form a second isolation dam.

15. The display substrate according to claim 14, further comprising: The second dam foundation, the fourth dam foundation and the sixth dam foundation located in the isolation dam area; The second dam is disposed on the same layer as the second flat layer, the fourth dam is disposed on the same layer as the pixel definition layer, and the sixth dam is disposed on the same layer as the seventh dam; The second dam base is arranged on the second power supply unit, the fourth dam base is arranged on the auxiliary power line covering the second dam base, and the orthographic projection of the fourth dam base on the substrate covers the orthographic projection of the second dam base on the substrate, and the sixth dam base is arranged on the fourth dam base, and the orthographic projection of the fourth dam base on the substrate covers the orthographic projection of the sixth dam base on the substrate; The second dam, the auxiliary power line covering the second dam, the fourth dam and the sixth dam form a first isolation dam.

16. The display substrate according to claim 13 or 15, wherein: An orthographic projection of the first isolation dam on the substrate at least partially overlaps with the clock signal line.

17. A display device, comprising: A display substrate as claimed in any one of claims 1 to 16.

18. A method for preparing a display substrate, configured to prepare the display substrate according to any one of claims 1 to 16, wherein the display substrate comprises: A display area and an edge area located on a side of the display area, the method comprising: providing a substrate; A first power supply unit and a second power supply unit are sequentially formed on the substrate to form a power line located in the edge area, an orthographic projection of the second power supply unit on the substrate at least partially overlaps with an orthographic projection of the first power supply unit on the substrate, and a distance between an end of the second power supply unit away from the display area and the display area is greater than or equal to a distance between an end of the first power supply unit away from the display area and the display area.

19. The method according to claim 18, wherein: The sequentially forming a first power supply unit and a second power supply unit on the substrate comprises: A pixel driving circuit in the display area, a first driving circuit in the circuit area, a second driving circuit, a third driving circuit in the third circuit area, and a first power supply unit and a crack detection line in the isolation dam area are formed on the substrate; Forming a first planar layer located in the display area and the circuit area, and a first dam base and a first protective layer located in the isolation dam area on the substrate forming the first power supply unit; forming a connection electrode located in the display area and a second power supply part located in the circuit area and the isolation dam area on the substrate on which the first flat layer is formed; Forming a second flat layer located in the display area and the circuit area, a second dam base, a third dam base and a second protective layer located in the isolation dam area on the substrate forming the second power supply unit; forming an anode located in a display area and an auxiliary power supply line located in an edge area on the substrate on which the second flat layer is formed; A pixel definition layer located in the display area, an isolation layer located in the circuit area, and a fourth dam base and a fifth dam base located in the isolation dam area are formed on the substrate on which the auxiliary power line is formed; An organic light emitting layer located in the display area, a cathode located in the display area and the circuit area, and a sixth dam base and a seventh dam base located in the isolation dam area are formed on the substrate on which the pixel definition layer is formed.

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