Circuit structure and display substrate

Abstract

The present disclosure provides a circuit structure and a display substrate. The circuit structure comprises: a base substrate, and a functional transistor and a signal transmission line which are arranged on the base substrate; the functional transistor comprises a first conductive connecting part, a first electrode, a second electrode, at least two gate patterns, and at least one active pattern; the orthographic projection of the first electrode on the base substrate at least partially overlaps with the orthographic projection of the active pattern on the base substrate; the orthographic projection of the second electrode on the base substrate at least partially overlaps the orthographic projection of the active pattern on the base substrate; the orthographic projections of the at least two gate patterns on the base substrate at least partially overlap the orthographic projection of the active pattern on the base substrate, respectively; the first ends of the at least two gate patterns are coupled; the first conductive connecting part and the gate patterns are arranged in different layers; the first conductive connecting part is coupled to the second ends of the at least two gate patterns; and the signal transmission line is coupled to the first conductive connecting part.

Description

Circuit structure and display substrate Technical Field

[0001] The present disclosure relates to the field of electronic components, and in particular to a circuit structure and a display substrate. Background Art

[0002] Organic Light-Emitting Diode (OLED) display technology is hailed as a next-generation display technology, boasting broad application prospects due to its advantages such as high response, high contrast, and flexibility. Integrating the gate driver circuitry in OLED display products directly into the non-display area of ​​the array substrate replaces the external driver chip required for the array substrate. This design, known as the GOA (Gate Driver on Array) design, offers advantages such as low cost, minimal process steps, and high production capacity.

[0003] Summary of the Invention

[0004] The present disclosure aims to provide a circuit structure and a display substrate.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a circuit structure comprising: a substrate, and a functional transistor and a signal transmission line disposed on the substrate; the functional transistor comprising a first conductive connection portion, a first electrode, a second electrode, at least two gate patterns, and at least one active pattern;

[0007] The orthographic projection of the first electrode on the base substrate at least partially overlaps with the orthographic projection of the active pattern on the base substrate, and the orthographic projection of the second electrode on the base substrate at least partially overlaps with the orthographic projection of the active pattern on the base substrate;

[0008] The orthographic projections of the at least two gate patterns on the base substrate at least partially overlap with the orthographic projections of the active pattern on the base substrate, the first ends of the at least two gate patterns are coupled, and the at least two gate patterns form a non-closed loop structure on the film layer where they are located; the first conductive connection portion and the gate pattern are arranged in different layers, and the first conductive connection portion is coupled to the second ends of the at least two gate patterns; the signal transmission line is coupled to the first conductive connection portion.

[0009] Optionally, a distance between the second ends of adjacent gate patterns is greater than or equal to a distance between middle portions of adjacent gate patterns, where the middle portion is located between the first end and the second end.

[0010] Optionally, the functional transistor further includes a second conductive connection portion, the first ends of the at least two gate patterns are coupled via the second conductive connection portion, and the second conductive connection portion is provided in the same layer and material as the gate pattern.

[0011] Optionally, the first conductive connection portion is provided in the same layer and made of the same material as the first electrode and the second electrode.

[0012] Optionally, the signal transmission line and the first conductive connection portion form an integrated structure.

[0013] Optionally, the signal transmission line and the gate pattern are provided in the same layer and with the same material.

[0014] Optionally, the signal transmission line contacts the second end of one of the gate patterns.

[0015] Optionally, the functional transistor includes at least two active patterns arranged along a first direction, the gate pattern extends along the first direction, the first electrode and the second electrode are opposite to each other along a second direction, and the first direction intersects with the second direction.

[0016] Optionally, the circuit structure includes at least two functional transistors arranged along the second direction, the first conductive connection portions included in the at least two functional transistors form an integrated structure, the second conductive connection portions included in the at least two functional transistors form an integrated structure, and in two adjacent functional transistors, the second electrode of one functional transistor is reused as the first electrode of the other functional transistor.

[0017] Optionally, the circuit structure includes an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer and a source / drain metal layer stacked in sequence on the base substrate in a direction away from the base substrate;

[0018] The active layer includes a plurality of first functional patterns, wherein the first functional patterns include the active pattern;

[0019] The gate metal layer includes a plurality of second functional patterns, and the second functional patterns include the gate pattern;

[0020] The interlayer insulating layer includes a plurality of via holes;

[0021] The source / drain metal layer includes a plurality of third functional patterns, and the third functional patterns include the first electrode and the second electrode.

[0022] Optionally, the width of the first functional pattern in a direction perpendicular to its own extension direction is greater than or equal to a+Xa+Ya, a satisfies: 4.5 μm≤a≤7 μm, Xa satisfies: 0.1 μm≤Xa≤0.5 μm, and Ya satisfies: 0.1 μm≤Ya≤0.5 μm.

[0023] Optionally, a distance between adjacent first functional patterns is greater than or equal to Xa+4 μm.

[0024] Optionally, the width of the second functional pattern in a direction perpendicular to its own extension direction is greater than or equal to g+Xg+Yg+2*d1 / tan(α1), g satisfies: 4.5μm≤g≤6.5μm, Xg satisfies: 0.6μm≤Xg≤2μm, Yg satisfies: 0.6μm≤Yg≤2μm, α1 is the slope angle of the second functional pattern, and d1 satisfies:

[0025] Optionally, a distance between adjacent second functional patterns is greater than or equal to Xg+2 μm.

[0026] Optionally, a width of the third functional pattern in a direction perpendicular to its own extension direction is greater than or equal to s+Xs+Ys+2*d2 / tan(α2), s satisfies: 4.5μm≤g≤6.5μm, Xs satisfies: 0.6μm≤Xs≤2μm, Ys satisfies: 0.6μm≤Ys≤2μm, α2 is the slope angle of the third functional pattern, and d2 satisfies:

[0027] Optionally, a distance between adjacent third functional patterns is greater than or equal to Xs+2 μm.

[0028] Optionally, the third functional pattern is coupled to the first functional pattern through the corresponding via hole, and the third functional pattern is coupled to the second functional pattern through the corresponding via hole; an aperture H of the via hole satisfies: H≥h, and h satisfies: 1μm≤h≤3μm.

[0029] Optionally, a distance between a boundary of an orthographic projection of the first functional pattern on the substrate and a boundary of an orthographic projection of the via hole on the substrate is greater than or equal to H+Xh+Yh; and / or,

[0030] The distance between the boundary of the orthographic projection of the second functional pattern on the substrate and the boundary of the orthographic projection of the via hole on the substrate is greater than or equal to H+Xh+Yh; and / or,

[0031] A distance between a boundary of an orthographic projection of the third functional pattern on the base substrate and a boundary of an orthographic projection of the via hole on the base substrate is greater than or equal to H+Xh+Yh;

[0032] Xh satisfies: 0.1μm≤Xh≤1μm, and Yh satisfies: 0.1μm≤Yh≤1μm.

[0033] Optionally, the distance between the orthographic projection of the first electrode on the substrate and / or the orthographic projection of the second electrode on the substrate and the orthographic projection of the adjacent gate pattern on the substrate is greater than or equal to (Xg+Yg+Xs+Ys) / 2, 0.6μm≤Xg≤2μm, Yg satisfies: 0.6μm≤Yg≤2μm, Xs satisfies: 0.6μm≤Xs≤2μm, and Ys satisfies: 0.6μm≤Ys≤2μm.

[0034] Optionally, the active pattern includes at least two channel portions, and an orthographic projection of the channel portion on the base substrate overlaps with an orthographic projection of a corresponding gate pattern on the base substrate;

[0035] Along the extending direction of the gate pattern, the width W of the channel portion satisfies: 5 μm≤W≤20 μm, and along the direction perpendicular to the extending direction of the gate pattern, the length L of the channel portion satisfies: 2 μm≤L≤4 μm.

[0036] Optionally, the circuit structure includes a gate drive circuit, the gate drive circuit includes a gate drive signal output terminal and a pull-down transistor coupled to the gate drive signal output terminal, and the functional transistor includes the pull-down transistor.

[0037] Optionally, the circuit structure includes a gate drive circuit, the gate drive circuit includes a trigger signal output terminal and an output transistor coupled to the trigger signal output terminal, and the functional transistor includes the output transistor.

[0038] Optionally, the at least two gate patterns are formed by wet etching.

[0039] Based on the technical solution of the above circuit structure, a second aspect of the present disclosure provides a display substrate including the above circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0041] FIG1 is a schematic diagram of a slope angle formed by a Mo dry etching process according to an embodiment of the present disclosure;

[0042] FIG2 is a schematic diagram of a slope angle formed by a Mo wet etching process according to an embodiment of the present disclosure;

[0043] FIG3 is a schematic diagram of a slope angle formed by an Al dry etching process according to an embodiment of the present disclosure;

[0044] FIG4 is a schematic diagram of a slope angle formed by an Al wet etching process according to an embodiment of the present disclosure;

[0045] FIG5 is a first schematic diagram of coupling a functional transistor and a signal transmission line provided by an embodiment of the present disclosure;

[0046] FIG6 is a schematic diagram of the layout of the active layer and the gate metal layer in FIG5 ;

[0047] FIG7 is a schematic diagram of the layout of the gate metal layer in FIG5;

[0048] FIG8 is a schematic diagram of the layout of the source and drain metal layers in FIG5 ;

[0049] FIG9 is a second schematic diagram of coupling a functional transistor and a signal transmission line according to an embodiment of the present disclosure;

[0050] FIG10 is a schematic diagram of the layout of the active layer in FIG9;

[0051] FIG11 is a schematic diagram of the layout of the gate metal layer in FIG9 ;

[0052] FIG12 is a schematic diagram of the layout of the source and drain metal layers in FIG9 ;

[0053] FIG13 is a third schematic diagram of coupling a functional transistor to a signal transmission line according to an embodiment of the present disclosure;

[0054] FIG14 is a schematic diagram of a first circuit structure of a shift register unit provided in an embodiment of the present disclosure;

[0055] FIG15 is a schematic diagram of a second circuit structure of the shift register unit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] In order to further illustrate the circuit structure and display substrate provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0057] The scanning signals driving the pixels in OLED display products are controlled by shift register units (also known as GOA units) in each row. The smallest unit of a GOA unit is a transistor, each with different functions and sizes. Dual-gate transistors effectively reduce leakage current between the source and drain electrodes and are a common structure for LTPS transistors. Because the gate lines are formed on the same film layer, the line spacing must be carefully controlled during the process, otherwise defects such as incomplete etching and etch deviation are likely to occur.

[0058] As the market embraces narrow-bezel displays, the non-display area of ​​the GOA unit has had to be reduced, increasing transistor density and line density. Furthermore, high-resolution displays place stringent requirements on the line density of transistors within pixels. This increased line density presents new challenges for dual-gate transistors.

[0059] Under the requirement of high resolution, the space of each pixel is compressed to the process limit. The etching process of transistor manufacturing has etching accuracy deviation and position deviation. During design, these deviation ranges must be taken into account. The range of design values ​​needs to be able to cover the impact of these deviations, otherwise it is easy to cause incomplete etching and fail to achieve the expected results. The etching process of transistors mainly includes dry etching and wet etching. In addition to the difference in etching accuracy, the slope angles of these two processes are also different. As shown in Figures 1 to 4, taking Mo as an example, the slope angle a3 of dry etching is smaller than the slope angle a4 of wet etching. For general metals, such as Al, the slope angle a5 of dry etching is larger than the slope angle a6 of wet etching. Therefore, the influence of slope angle also needs to be considered when etching high-density line spacing.

[0060] For transistors with a dual-gate structure, it is easy to form a closed-loop structure in the layout design, that is, both ends of the two gate patterns have to be connected. In such a closed-loop structure, etching liquid will remain in the middle area of ​​the ring during wet etching, thereby increasing the etching degree uncontrollably. The actual production line width will be significantly different from the design value, and the expected transistor performance cannot be obtained. Therefore, a new structure is urgently needed to achieve a closed-loop structure while ensuring the production accuracy of the transistor, thereby ensuring the performance of the transistor.

[0061] 5 to 8 , an embodiment of the present disclosure provides a circuit structure including: a substrate, and a functional transistor and a signal transmission line 50 disposed on the substrate; the functional transistor includes a first conductive connection portion 40, a first electrode 301, a second electrode 302, at least two gate patterns 20-T, and at least one active pattern 10-T;

[0062] The orthographic projection of the first electrode 301 on the base substrate at least partially overlaps with the orthographic projection of the active pattern 10-T on the base substrate, and the orthographic projection of the second electrode 302 on the base substrate at least partially overlaps with the orthographic projection of the active pattern 10-T on the base substrate;

[0063] The orthographic projections of the at least two gate graphics 20-T on the base substrate at least partially overlap with the orthographic projections of the active graphics 10-T on the base substrate, the first ends 20-T1 of the at least two gate graphics 20-T are coupled, and the at least two gate graphics are formed as a non-closed loop structure on the film layer where they are located; the first conductive connection portion 40 and the gate graphics 20-T are arranged in different layers, and the first conductive connection portion 40 is coupled to the second ends 20-T2 of the at least two gate graphics 20-T; the signal transmission line 50 is coupled to the first conductive connection portion 40.

[0064] Exemplarily, one of the first electrode 301 and the second electrode 302 serves as the source of the functional transistor, and the other of the first electrode 301 and the second electrode 302 serves as the drain of the functional transistor. The orthographic projection of the first electrode 301 on the substrate overlaps with the orthographic projection of the active pattern 10-T on the substrate. In this overlapping region, the first electrode 301 is coupled to the active pattern 10-T via a via 1. The orthographic projection of the second electrode 302 on the substrate overlaps with the orthographic projection of the active pattern 10-T on the substrate. In this overlapping region, the second electrode 302 is coupled to the active pattern 10-T via a via 1.

[0065] As shown in FIG. 9 , illustratively, when the functional transistor includes a plurality of active patterns 10 -T, the first electrodes 301 are respectively coupled to the plurality of active patterns 10 -T, and the second electrodes 302 are respectively coupled to the plurality of active patterns 10 -T.

[0066] As shown in FIG6 , illustratively, the orthographic projection of each gate pattern 20-T on the substrate at least partially overlaps with the orthographic projection of the active pattern 10-T on the substrate, and the portion of the active pattern 10-T that overlaps with the gate pattern 20-T forms the channel portion 10-Tg of the functional transistor.

[0067] Exemplarily, the plurality of active patterns 10-T are arranged along a first direction, the at least two gate patterns 20-T are arranged along a second direction, and the gate patterns 20-T extend along the first direction. The first electrode 301 and the second electrode 302 are opposed to each other along the second direction. At least a portion of the orthographic projection of the gate pattern 20-T on the base substrate is located between the orthographic projection of the first electrode 301 and the orthographic projection of the second electrode 302 on the base substrate. Exemplarily, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0068] Exemplarily, the orthographic projection of the first conductive connection portion 40 on the substrate has an overlapping area with the orthographic projection of the second end 20-T2 of the gate graphic 20-T on the substrate, and in this overlapping area, the first conductive connection portion 40 is coupled to the second end 20-T2 of the gate graphic 20-T through a via.

[0069] Exemplarily, the signal transmission line 50 is close to the second end 20 - T2 of the gate pattern 20 -T.

[0070] Exemplarily, the at least two gate patterns are formed by wet etching, that is, etching is performed using an etching solution.

[0071] According to the specific structure of the above-described circuit structure, in the circuit structure provided by the embodiment of the present disclosure, the first ends 20-T1 of at least two gate patterns 20-T included in the functional transistor are coupled, and the second ends 20-T2 of the at least two gate patterns 20-T are coupled via a first conductive connection portion 40. Because the first conductive connection portion 40 and the gate patterns 20-T are disposed in different layers, an opening is formed between the second ends 20-T2 of adjacent gate patterns 20-T in the at least two gate patterns 20-T, thereby avoiding the formation of a closed loop structure in the film layer where the gate patterns 20-T are located. In this way, during the etching process to form the gate patterns 20-T, the etching solution between the adjacent gate patterns 20-T can flow out through the opening. This not only avoids the problem of uncontrollable etching degree caused by etching solution remaining between adjacent gate patterns 20-T, which affects actual etching accuracy, but also facilitates the realization of high-density wiring. Therefore, in the circuit structure provided in the embodiment of the present disclosure, a three-dimensional closed-loop structure of the gate graphic 20-T is realized, which not only meets the structure that both ends of the gate graphic 20-T need to be connected together, but also ensures that the size of the actual gate graphic 20-T is consistent with the design value, thereby better ensuring that the functional transistor can achieve the expected performance.

[0072] Furthermore, in the circuit structure provided by the embodiment of the present disclosure, the first conductive connection portion 40 couples the second ends 20-T2 of the at least two gate patterns 20-T, and the signal transmission line 50 is coupled to the first conductive connection portion 40. This not only achieves electrical connection between the signal transmission line 50 and the gate pattern 20-T, but also avoids the problem of high current burning the circuit structure caused by the signal transmission line 50 being electrically connected to only the second end 20-T2 of one gate pattern 20-T. Furthermore, because the signal transmission line 50 is close to the second end 20-T2 of the gate pattern 20-T, coupling the signal transmission line 50 to the first conductive connection portion 40 helps shorten the current transmission path, reduces RC loading on the signal transmission line 50, and improves signal deviation issues.

[0073] As shown in Figure 7, in some embodiments, the distance n1 between the second ends 20-T2 of adjacent gate graphics 20-T is greater than or equal to the distance n2 between the middle parts 20-T3 of adjacent gate graphics 20-T, and the middle part 20-T3 is located between the first end 20-T1 and the second end 20-T2.

[0074] Exemplarily, the width of the second end 20-T2 along the second direction is greater than the width of the middle part 20-T3, which is beneficial to increasing the projected overlapping area between the second end 20-T2 and the first conductive connection part 40, and further beneficial to improving the electrical connection reliability between the first conductive connection part 40 and the second end 20-T2 of the gate graphic 20-T.

[0075] In the circuit structure provided in the above embodiment, by setting the distance between the second ends 20-T2 of adjacent gate graphics 20-T to be greater than or equal to the distance between the middle parts 20-T3 of adjacent gate graphics 20-T, the width of the opening formed between the second ends 20-T2 of adjacent gate graphics 20-T is ensured, thereby ensuring that the etching solution flows out of the opening better.

[0076] As shown in Figure 7, in some embodiments, the functional transistor also includes a second conductive connection portion 201, and the first ends 20-T1 of the at least two gate graphics 20-T are coupled through the second conductive connection portion 201, and the second conductive connection portion 201 is set in the same layer and material as the gate graphics 20-T.

[0077] Exemplarily, the second conductive connection portion 201 and the first ends 20 - T1 of the at least two gate patterns 20 -T form an integral structure.

[0078] Exemplarily, the second conductive connection portion 201 can be reused as a plate of a capacitor coupled to the gate pattern 20 -T of the functional transistor, thereby reducing the risk of burning the connection line between the plate of the capacitor and the gate pattern 20 -T.

[0079] The above configuration can improve the stability of the circuit structure and save the layout space occupied by the circuit structure.

[0080] As shown in FIG. 8 , in some embodiments, the first conductive connection portion 40 is provided in the same layer and made of the same material as the first electrode 301 and the second electrode 302 .

[0081] The above-mentioned setting method enables the first conductive connection part 40 to be formed simultaneously with the first electrode 301 and the second electrode 302 in the same composition process, avoiding the addition of an additional composition process to produce the first conductive connection part 40, thereby effectively simplifying the production process flow of the circuit structure and reducing the production cost.

[0082] As shown in FIG. 8 , in some embodiments, the signal transmission line 50 and the first conductive connection portion 40 are formed into an integral structure.

[0083] The above arrangement not only ensures the reliability of the electrical connection between the first conductive connection portion 40 and the signal transmission line 50 , but also enables the signal line and the first conductive connection portion 40 to be formed simultaneously in the same patterning process.

[0084] As shown in FIG. 9 and FIG. 11 , in some embodiments, the signal transmission line 50 and the gate pattern 20 -T are provided in the same layer and made of the same material.

[0085] Exemplarily, the signal transmission line 50 contacts the second end 20 - T2 of one of the gate patterns 20 -T.

[0086] This arrangement enables the signal transmission line 50 to be formed simultaneously with the gate pattern 20-T during the same patterning process, thereby effectively simplifying the circuit structure manufacturing process and reducing manufacturing costs. Furthermore, the signal transmission line 50 is arranged to contact the second end 20-T2 of one gate pattern 20-T, ensuring that the etching solution can flow out through the opening formed between the second ends 20-T2 of adjacent gate patterns 20-T.

[0087] As shown in Figures 9 to 12, in some embodiments, the functional transistor includes at least two active patterns 10-T arranged along a first direction, the gate pattern 20-T extends along the first direction, the first electrode 301 and the second electrode 302 are opposite to each other along a second direction, and the first direction intersects with the second direction.

[0088] Exemplarily, the material used for the gate pattern 20 -T includes metals such as Mo, Al, and Nd, but is not limited thereto.

[0089] Exemplarily, the materials used for the first electrode 301 and the second electrode 302 include metals such as Cu, Ti, and Al, but are not limited thereto.

[0090] Exemplarily, the materials used for the active pattern 10 -T include IGZO, low-temperature polysilicon, a-Si, etc., but are not limited thereto.

[0091] As shown in Figures 9 to 12, in some embodiments, the circuit structure includes at least two functional transistors arranged along the second direction, the first conductive connection portion 40 included in the at least two functional transistors forms an integrated structure, the second conductive connection portion 201 included in the at least two functional transistors forms an integrated structure, and in two adjacent functional transistors, the second electrode 302 of one functional transistor is reused as the first electrode 301 of the other functional transistor.

[0092] Exemplarily, at least two functional transistors are connected in series, the active pattern 10 -T included in each functional transistor is arranged along the first direction, and the gate pattern 20 -T included in each functional transistor is arranged along the second direction.

[0093] Exemplarily, active patterns 10 -T adjacent to each other along the second direction in each functional transistor are formed into an integrated structure.

[0094] In the circuit structure provided by the above embodiment, setting at least two functional transistors in series can improve the functional transistor's ability to carry large currents. At the same time, the second electrode 302 of one functional transistor in the two adjacent functional transistors is reused as the first electrode 301 of the other functional transistor, which can reduce the overall layout space occupied by the functional transistors in series.

[0095] As shown in FIG5 to FIG12, in some embodiments, the circuit structure includes an active layer ACT, a gate insulating layer, a gate metal layer GT, an interlayer insulating layer and a source / drain metal layer SD stacked sequentially on the substrate in a direction away from the substrate.

[0096] The active layer ACT includes a plurality of first functional patterns, wherein the first functional patterns include the active pattern 10-T;

[0097] The gate metal layer GT includes a plurality of second functional patterns, and the second functional patterns include the gate pattern 20-T;

[0098] The interlayer insulating layer includes a plurality of vias (eg, Via1 and Via2);

[0099] The source / drain metal layer SD includes a plurality of third functional patterns, and the third functional patterns include the first electrode 301 and the second electrode 302 .

[0100] Exemplarily, the first functional pattern may include other functional structures in addition to the active pattern 10 -T.

[0101] Exemplarily, the second functional pattern may include, in addition to the gate pattern 20 -T, other functional structures, such as a second conductive connection portion 201 , a signal transmission line 50 , etc., but is not limited thereto.

[0102] Exemplarily, the third functional pattern may include, in addition to the first electrode 301 and the second electrode 302 , other functional structures, such as a first conductive connection portion 40 , a signal transmission line 50 , etc., but is not limited thereto.

[0103] Exemplarily, the plurality of via holes included in the interlayer insulating layer include via holes for connecting the first functional pattern and the third functional pattern, and also include via holes for connecting the second functional pattern and the third functional pattern.

[0104] As shown in FIG6 and FIG10, in some embodiments, the width n4 of the first functional pattern in the extension direction perpendicular to itself is greater than or equal to a+Xa+Ya, a satisfies: 4.5 μm≤a≤7 μm, Xa satisfies: 0.1 μm≤Xa≤0.5 μm, and Ya satisfies: 0.1 μm≤Ya≤0.5 μm.

[0105] Exemplarily, a represents the minimum width that can be achieved by the first functional pattern, and the values ​​of a may be: 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, etc., but are not limited thereto.

[0106] Xa represents the bilateral etching accuracy of the first functional pattern, and the values ​​of Xa may be: 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, etc., but are not limited thereto.

[0107] Ya represents the exposure position deviation of the first functional pattern, and the values ​​of Ya may be: 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, etc., but are not limited thereto.

[0108] It is worth noting that the width of the first functional pattern in the direction perpendicular to its own extension is related to the material and etching process used, and the width of the first functional pattern in the direction perpendicular to its own extension should not be less than a+Xa+Ya.

[0109] Exemplarily, the thickness of the first functional pattern is to For example, the thickness of the first functional pattern may be: But it’s more than that.

[0110] Exemplarily, the distance between adjacent first functional patterns is greater than or equal to Xa+4 μm.

[0111] As shown in FIG. 10 , illustratively, a spacing n3 between adjacent active patterns 10 -T along the first direction is greater than or equal to Xa+4 μm.

[0112] By setting the width of the first functional pattern and the spacing between adjacent first functional patterns according to the above parameters, while ensuring the reliability and functional characteristics of the first functional pattern, the layout space occupied by the first functional pattern is minimized, which is conducive to high-density wiring and realizes a high-resolution circuit structure.

[0113] As shown in FIG7 , in some embodiments, a width n5 of the second functional pattern in a direction perpendicular to its own extension direction is greater than or equal to g+Xg+Yg+2*d1 / tan(α1), where g satisfies: 4.5 μm ≤ g ≤ 6.5 μm, Xg satisfies: 0.6 μm ≤ Xg ≤ 2 μm, and Yg satisfies: 0.6 μm ≤ Yg ≤ 2 μm, α1 is the slope angle of the second functional pattern, and d1 satisfies:

[0114] Exemplarily, g represents the minimum width that can be achieved by the second functional pattern, and the values ​​of g can be: 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, etc., but are not limited thereto.

[0115] Xg represents the bilateral etching accuracy of the second functional pattern, and Xg can take values ​​such as 0.8 μm, 1 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, etc., but is not limited thereto.

[0116] Yg represents the exposure position deviation of the second functional pattern, and the values ​​of Yg may be: 0.8 μm, 1 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, etc., but are not limited thereto.

[0117] d1 represents the thickness of the second functional pattern, and d1 can take the following values: etc., not limited to this.

[0118] It is worth noting that the width of the second functional pattern in the direction perpendicular to its own extension is related to the material and etching process used, and the width of the second functional pattern in the direction perpendicular to its own extension should not be less than g+Xg+Yg+2*d1 / tan(α1).

[0119] Exemplarily, the distance between adjacent second functional patterns is greater than or equal to Xg+2 μm.

[0120] As shown in FIG. 7 , illustratively, the spacing (eg, n2 ) between adjacent gate patterns 20 -T is greater than or equal to Xg+2 μm.

[0121] By setting the width of the second functional pattern and the spacing between adjacent second functional patterns according to the above parameters, while ensuring the reliability and functional characteristics of the second functional pattern, the layout space occupied by the second functional pattern is minimized, which is conducive to high-density wiring and the realization of a high-resolution circuit structure.

[0122] As shown in FIG8 , in some embodiments, a width n6 of the third functional pattern in a direction perpendicular to its own extension direction is greater than or equal to s+Xs+Ys+2*d2 / tan(α2), s satisfies: 4.5 μm≤g≤6.5 μm, Xs satisfies: 0.6 μm≤Xs≤2 μm, Ys satisfies: 0.6 μm≤Ys≤2 μm, α2 is the slope angle of the third functional pattern, and d2 satisfies:

[0123] Exemplarily, s represents the minimum width that can be achieved by the third functional pattern, and the values ​​of s may be: 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, etc., but are not limited thereto.

[0124] Xs represents the bilateral etching accuracy of the third functional pattern, and Xs may take the following values: 0.8 μm, 1 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, etc., but is not limited thereto.

[0125] Ys represents the exposure position deviation of the third functional pattern, and the values ​​of Ys may be: 0.8 μm, 1 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, etc., but are not limited thereto.

[0126] d2 represents the thickness of the third functional pattern, and d2 can take the following values: etc., not limited to this.

[0127] It is worth noting that the width of the third functional pattern in the direction perpendicular to its own extension is related to the material and etching process used, and the width of the third functional pattern in the direction perpendicular to its own extension should not be less than s+Xs+Ys+2*d2 / tan(α2).

[0128] Exemplarily, the distance between adjacent third functional patterns is greater than or equal to Xs+2 μm.

[0129] As shown in FIG. 8 , illustratively, the interval n7 between adjacent first electrodes 301 and second electrodes 302 is greater than or equal to Xs+2 μm.

[0130] By setting the width of the third functional pattern and the spacing between adjacent third functional patterns according to the above parameters, while ensuring the reliability and functional characteristics of the third functional pattern, the layout space occupied by the third functional pattern is minimized, which is conducive to high-density wiring and the realization of a high-resolution circuit structure.

[0131] It's worth noting that the minimum widths a, g, and s are function-dependent. For example, when the second functional pattern is the gate pattern 20-T, g is 4.5 μm, while when the second functional pattern is the signal transmission line 50, g is 6.5 μm. Reducing the width of the gate pattern 20-T helps reduce the layout space occupied by the circuit structure. Appropriately thickening the signal transmission line 50 helps reduce RC loading.

[0132] As shown in Figures 5 to 12, in some embodiments, the third functional pattern is coupled to the first functional pattern through the corresponding via Via1, and the third functional pattern is coupled to the second functional pattern through the corresponding via Via2; the aperture H of the via satisfies: H≥h, h satisfies: 1μm≤h≤3μm.

[0133] h represents the minimum aperture that can be achieved by the via hole, and the values ​​of h can be: 1.2μm, 1.4μm, 1.6μm, 1.8μm, 2.0μm, 2.1μm, 2.2μm, 2.4μm, 2.6μm, 2.8μm, etc., but not limited to these.

[0134] By setting the aperture of the via hole according to the above parameters, the layout space occupied by the via hole is minimized while ensuring the reliability of the via hole, which is conducive to high-density wiring and the realization of a high-resolution circuit structure.

[0135] In some embodiments, the distance between the boundary of the orthographic projection of the first functional pattern on the substrate and the boundary of the orthographic projection of the via on the substrate is greater than or equal to H+Xh+Yh; and / or, the distance between the boundary of the orthographic projection of the second functional pattern on the substrate and the boundary of the orthographic projection of the via on the substrate is greater than or equal to H+Xh+Yh; and / or, the distance between the boundary of the orthographic projection of the third functional pattern on the substrate and the boundary of the orthographic projection of the via on the substrate is greater than or equal to H+Xh+Yh; Xh satisfies: 0.1μm≤Xh≤1μm, and Yh satisfies: 0.1μm≤Yh≤1μm.

[0136] Xh represents the etching accuracy, and the possible values ​​of Xh are: 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, etc., but not limited to these.

[0137] Yh represents the exposure position deviation, and the possible values ​​of Yh are: 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, etc., but not limited to these.

[0138] The above-mentioned setting method can better ensure the reliability of the first functional pattern, the second functional pattern, the third functional pattern and the via layout, ensure the connection performance between the third functional pattern and the first functional pattern through the corresponding via, and also ensure the connection performance between the third functional pattern and the second functional pattern through the corresponding via.

[0139] In some embodiments, a distance n8 between the orthographic projection of the first electrode 301 on the substrate and / or the orthographic projection of the second electrode 302 on the substrate and the orthographic projection of the adjacent gate pattern 20-T on the substrate is greater than or equal to (Xg+Yg+Xs+Ys) / 2, 0.6μm≤Xg≤2μm, Yg satisfies: 0.6μm≤Yg≤2μm, Xs satisfies: 0.6μm≤Xs≤2μm, and Ys satisfies: 0.6μm≤Ys≤2μm.

[0140] The above configuration method better ensures the reliability of the functional transistor and ensures that the functional transistor has stable functional characteristics.

[0141] As shown in FIG5 and FIG6, in some embodiments, the active pattern 10-T includes at least two channel portions 10-Tg, and the orthographic projections of the channel portions 10-Tg on the base substrate overlap with the orthographic projections of the corresponding gate patterns 20-T on the base substrate;

[0142] Along the extension direction of the gate pattern 20-T, the width W of the channel portion 10-Tg satisfies: 5μm≤W≤20μm, and along the direction perpendicular to the extension direction of the gate pattern 20-T, the length L of the channel portion 10-Tg satisfies: 2μm≤L≤4μm.

[0143] Illustratively, the width W of the channel portion 10-Tg may be 5 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, etc., but is not limited thereto.

[0144] Exemplarily, the length L of the channel portion 10-Tg may be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, etc., but is not limited thereto.

[0145] It should be noted that the number of channel portions 10-Tg included in the active pattern 10-T is related to the number of gate patterns 20-T overlapped by the active pattern 10-T, that is, when the active pattern 10-T includes two channel portions 10-Tg, the orthographic projections of the two channel portions 10-Tg on the base substrate overlap with the orthographic projections of the two gate patterns 20-T on the base substrate.

[0146] The above arrangement enables the functional pattern to have a more appropriate size while meeting the characteristic requirements, which is conducive to high-density wiring and the realization of a high-resolution circuit structure.

[0147] In some embodiments, the circuit structure includes a gate drive circuit, the gate drive circuit includes a gate drive signal output terminal and a pull-down transistor coupled to the gate drive signal output terminal, and the functional transistor includes the pull-down transistor.

[0148] Exemplarily, the pull-down transistor includes multiple active patterns 10-T. Each active pattern 10-T, its overlapping gate pattern 20-T, first electrode 301, and second electrode 302 form a unit. The pull-down transistor can be composed of these units connected in parallel. The spacing between adjacent active patterns 10-T satisfies a value greater than or equal to Xa + 4 μm. The spacing between adjacent active patterns 10-T is related to the minimum etching process density.

[0149] Exemplarily, the gate driving circuit includes a plurality of cascaded shift register units.

[0150] As shown in FIG14 , the shift register unit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The shift register unit also includes a CLKA signal, a STU signal, a CLKB signal, a VGH signal, a VGL1 signal, a VGL2 signal, an RST signal, a gate drive signal output terminal OUT, a trigger signal output terminal CR, a P node, a Q node, a Q1 node, and a QB node.

[0151] The gate drive signal output terminal OUT is used to output the gate drive signal to the pixel drive circuit in the display area. The trigger signal output terminal CR is used to output the trigger signal to other row shift register units to trigger other shift register units to start working.

[0152] Exemplarily, the pull-down transistor is the seventeenth transistor T17, which is used to pull down the gate drive signal output terminal OUT. Exemplarily, the structure of the seventeenth transistor T17 is two functional transistors connected in series.

[0153] Exemplarily, the width of a channel portion 10-Tg in a functional transistor included in the seventeenth transistor T17 can be 22 μm, and the length of the channel portion 10-Tg can be 2.5 μm. The functional transistor is formed into a dual-gate structure, and the length of all channel portions 10-Tg included in the functional transistor is 2.5 μm*2. The functional transistor includes eight active patterns 10-T arranged along a first direction. The signal transmission line coupled to the QB node, namely the signal transmission line 50, is coupled to the first conductive connection portion 40 and coupled to the gate pattern 20-T of the seventeenth transistor T17.

[0154] In some embodiments, the circuit structure includes a gate drive circuit, the gate drive circuit includes a trigger signal output terminal and an output transistor coupled to the trigger signal output terminal, and the functional transistor includes the output transistor.

[0155] As shown in Figures 13 and 15, the shift register unit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a compensation transistor T12', a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The shift register unit also includes a CLKA signal, a STU signal, a CLKB signal, a VGH signal, a VGL1 signal, a VGL2 signal, an RST signal, a gate drive signal output terminal OUT, a trigger signal output terminal CR, a P node, a Q node, a Q1 node, and a QB node.

[0156] Exemplarily, the output transistor coupled to the trigger signal output terminal is the fourteenth transistor T14.

[0157] For example, the width of the channel portion 10-Tg in the fourteenth transistor T14 can be 22 μm, and the length of the channel portion 10-Tg can be 2.5 μm. The fourteenth transistor T14 is formed into a dual-gate structure, and the length of the entire channel portion 10-Tg included in the fourteenth transistor T14 is 2.5 μm*2. The signal transmission line coupled to the Q1 node, namely the signal transmission line 50, is coupled to the first conductive connection portion 40 and coupled to the gate pattern 20-T of the fourteenth transistor T14.

[0158] The embodiments of the present disclosure further provide a display substrate, comprising the circuit structure provided in the above embodiments.

[0159] In the circuit structure provided by the above embodiment, the functional transistor includes at least two gate patterns whose first ends are coupled, and the second ends of the at least two gate patterns are coupled via a first conductive connection portion. Because the first conductive connection portion is provided in a different layer from the gate pattern, an opening is formed between the second ends of adjacent gate patterns in the at least two gate patterns, thereby avoiding the formation of a closed-loop structure in the film layer where the gate patterns are located. In this way, during the etching process to form the gate patterns, the etching liquid between the adjacent gate patterns can flow out from the opening, which not only avoids the problem of uncontrollable etching degree caused by residual etching liquid between adjacent gate patterns, thereby affecting the actual etching accuracy, but also facilitates the realization of high-density wiring. Therefore, in the circuit structure provided by the above embodiment, a three-dimensional closed-loop structure of the gate pattern is realized, which not only meets the structure that both ends of the gate pattern need to be connected together, but also ensures that the size of the actually manufactured gate pattern is consistent with the design value, thereby better ensuring that the functional transistor can achieve the expected performance. Furthermore, in the circuit structure provided in the above embodiment, the first conductive connection portion couples the second ends of the at least two gate patterns, and the signal transmission line is coupled to the first conductive connection portion. This not only achieves electrical connection between the signal transmission line and the gate patterns, but also avoids the problem of high current burning out the circuit structure caused by the signal transmission line being electrically connected to only the second end of one gate pattern. Furthermore, because the signal transmission line is close to the second end of the gate pattern, coupling the signal transmission line to the first conductive connection portion helps shorten the current transmission path, reduces RC loading on the signal transmission line, and improves signal deviation.

[0160] The display substrate provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when including the above-mentioned circuit structure, which will not be described in detail here.

[0161] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0162] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0163] In the display substrate provided by the above embodiment, the first ends of at least two gate patterns included in the functional transistor are coupled, and the second ends of the at least two gate patterns are coupled via a first conductive connection portion. Because the first conductive connection portion and the gate pattern are arranged in different layers, an opening is formed between the second ends of adjacent gate patterns in the at least two gate patterns, thereby avoiding the formation of a closed-loop structure in the film layer where the gate patterns are located. In this way, during the process of etching to form the gate patterns, the etching liquid between adjacent gate patterns can flow out from the opening, which not only avoids the problem of uncontrollable etching degree caused by residual etching liquid between adjacent gate patterns, thereby affecting the actual etching accuracy, but also facilitates the realization of high-density wiring. Therefore, in the display substrate provided by the above embodiment, a three-dimensional closed-loop structure of the gate pattern is realized, which not only meets the structure that both ends of the gate pattern need to be connected together, but also ensures that the size of the actually manufactured gate pattern is consistent with the design value, thereby better ensuring that the functional transistor can achieve the expected performance. Furthermore, in the display substrate provided in the above embodiment, the first conductive connection portion couples the second ends of the at least two gate patterns, and the signal transmission line is coupled to the first conductive connection portion. This not only achieves electrical connection between the signal transmission line and the gate patterns, but also avoids the problem of high current burning out the circuit structure caused by the signal transmission line being electrically connected to only the second end of one gate pattern. Furthermore, because the signal transmission line is close to the second end of the gate pattern, coupling the signal transmission line to the first conductive connection portion helps shorten the current transmission path, reduces RC loading on the signal transmission line, and improves signal deviation.

[0164] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0165] It should be noted that the signal line extends along a certain direction means that: the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along a certain direction, and the length of the main part extended along the certain direction is greater than the length of the secondary part extended along other directions.

[0166] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0167] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0168] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0169] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0170] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0171] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0172] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A circuit structure comprising: A base substrate, and a functional transistor and a signal transmission line disposed on the base substrate; the functional transistor includes a first conductive connection portion, a first electrode, a second electrode, at least two gate patterns and at least one active pattern; The orthographic projection of the first electrode on the base substrate at least partially overlaps with the orthographic projection of the active pattern on the base substrate, and the orthographic projection of the second electrode on the base substrate at least partially overlaps with the orthographic projection of the active pattern on the base substrate; The orthographic projections of the at least two gate patterns on the base substrate at least partially overlap with the orthographic projections of the active pattern on the base substrate, the first ends of the at least two gate patterns are coupled, and the at least two gate patterns form a non-closed loop structure on the film layer where they are located; the first conductive connection portion and the gate pattern are arranged in different layers, and the first conductive connection portion is coupled to the second ends of the at least two gate patterns; the signal transmission line is coupled to the first conductive connection portion.

2. The circuit structure according to claim 1, wherein: A distance between the second ends of adjacent gate patterns is greater than or equal to a distance between middle portions of adjacent gate patterns, and the middle portion is located between the first end and the second end.

3. The circuit structure according to claim 1, wherein: The functional transistor further includes a second conductive connection portion, the first ends of the at least two gate patterns are coupled via the second conductive connection portion, and the second conductive connection portion is provided in the same layer and material as the gate pattern.

4. The circuit structure according to claim 1, wherein: The first conductive connection portion is provided in the same layer and made of the same material as the first electrode and the second electrode.

5. The circuit structure according to claim 1, wherein: The signal transmission line and the first conductive connection portion form an integral structure.

6. The circuit structure according to claim 1, wherein: The signal transmission line and the gate pattern are provided in the same layer and made of the same material.

7. The circuit structure according to claim 6, wherein: The signal transmission line contacts a second end of one of the gate patterns.

8. The circuit structure according to claim 1, wherein: The functional transistor includes at least two active patterns arranged along a first direction, the gate pattern extends along the first direction, the first electrode and the second electrode face each other along a second direction, and the first direction intersects the second direction.

9. The circuit structure according to claim 8, wherein: The circuit structure includes at least two functional transistors arranged along the second direction, the first conductive connection portions included in the at least two functional transistors form an integrated structure, the second conductive connection portions included in the at least two functional transistors form an integrated structure, and in two adjacent functional transistors, the second electrode of one functional transistor is reused as the first electrode of the other functional transistor.

10. The circuit structure according to any one of claims 1 to 9, wherein: The circuit structure includes an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer and a source / drain metal layer stacked in sequence on the base substrate in a direction away from the base substrate; The active layer includes a plurality of first functional patterns, wherein the first functional patterns include the active pattern; The gate metal layer includes a plurality of second functional patterns, and the second functional patterns include the gate pattern; The interlayer insulating layer includes a plurality of via holes; The source / drain metal layer includes a plurality of third functional patterns, and the third functional patterns include the first electrode and the second electrode.

11. The circuit structure according to claim 10, wherein: The width of the first functional pattern in a direction perpendicular to its own extension direction is greater than or equal to a+Xa+Ya, a satisfies: 4.5μm≤a≤7μm, Xa satisfies: 0.1μm≤Xa≤0.5μm, and Ya satisfies: 0.1μm≤Ya≤0.5μm.

12. The circuit structure according to claim 11, wherein: The distance between adjacent first functional patterns is greater than or equal to Xa+4 μm.

13. The circuit structure according to claim 10, wherein: The width of the second functional pattern in a direction perpendicular to its own extension direction is greater than or equal to g+Xg+Yg+2*d1 / tan(α1), g satisfies: 4.5μm≤g≤6.5μm, Xg satisfies: 0.6μm≤Xg≤2μm, Yg satisfies: 0.6μm≤Yg≤2μm, α1 is the slope angle of the second functional pattern, and d1 satisfies:

14. The circuit structure according to claim 13, wherein: The distance between adjacent second functional patterns is greater than or equal to Xg+2 μm.

15. The circuit structure according to claim 10, wherein: The width of the third functional pattern in the direction perpendicular to its own extension is greater than or equal to s+Xs+Ys+2*d2 / tan(α2), s satisfies: 4.5μm≤g≤6.5μm, Xs satisfies: 0.6μm≤Xs≤2μm, Ys satisfies: 0.6μm≤Ys≤2μm, α2 is the slope angle of the third functional pattern, and d2 satisfies:

16. The circuit structure according to claim 15, wherein: The distance between adjacent third functional patterns is greater than or equal to Xs+2 μm.

17. The circuit structure according to claim 10, wherein: The third functional pattern is coupled to the first functional pattern through the corresponding via hole, and the third functional pattern is coupled to the second functional pattern through the corresponding via hole; an aperture H of the via hole satisfies: H≥h, and h satisfies: 1μm≤h≤3μm.

18. The circuit structure according to claim 13, wherein: A distance between a boundary of an orthographic projection of the first functional pattern on the substrate and a boundary of an orthographic projection of the via hole on the substrate is greater than or equal to H+Xh+Yh; and / or, A distance between a boundary of an orthographic projection of the second functional pattern on the base substrate and a boundary of an orthographic projection of the via hole on the base substrate is greater than or equal to H+Xh+Yh; and / or, A distance between a boundary of an orthographic projection of the third functional pattern on the base substrate and a boundary of an orthographic projection of the via hole on the base substrate is greater than or equal to H+Xh+Yh; Xh satisfies: 0.1μm≤Xh≤1μm, and Yh satisfies: 0.1μm≤Yh≤1μm.

19. The circuit structure according to any one of claims 1 to 9, wherein: The distance between the orthographic projection of the first electrode on the substrate and / or the orthographic projection of the second electrode on the substrate and the orthographic projection of the adjacent gate pattern on the substrate is greater than or equal to (Xg+Yg+Xs+Ys) / 2, 0.6μm≤Xg≤2μm, Yg satisfies: 0.6μm≤Yg≤2μm, Xs satisfies: 0.6μm≤Xs≤2μm, and Ys satisfies: 0.6μm≤Ys≤2μm.

20. The circuit structure according to any one of claims 1 to 9, wherein: The active pattern includes at least two channel portions, and the orthographic projections of the channel portions on the base substrate overlap with the orthographic projections of the corresponding gate patterns on the base substrate; Along the extending direction of the gate pattern, the width W of the channel portion satisfies: 5 μm≤W≤20 μm, and along the direction perpendicular to the extending direction of the gate pattern, the length L of the channel portion satisfies: 2 μm≤L≤4 μm.

21. The circuit structure according to claim 1, wherein: The circuit structure includes a gate driving circuit, the gate driving circuit includes a gate driving signal output terminal and a pull-down transistor coupled to the gate driving signal output terminal, and the functional transistor includes the pull-down transistor.

22. The circuit structure according to claim 1, wherein: The circuit structure includes a gate driving circuit, the gate driving circuit includes a trigger signal output terminal and an output transistor coupled to the trigger signal output terminal, and the functional transistor includes the output transistor.

23. The circuit structure according to claim 1, wherein: The at least two gate patterns are formed by wet etching.

24. A display substrate comprising the circuit structure according to any one of claims 1 to 23.

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