Chip metallization method and chip
By etching and embedding dielectric and metal materials on the back of the chip substrate, the problems of wafer warping and process difficulty caused by the increase in dielectric layer thickness are solved, and the power supply and heat dissipation performance of the chip are improved.
Patent Information
- Application Number
- PCT/CN2024/077665
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-03-30
- Filing Date
- 2024-02-20
- Publication Date
- 2025-10-23
AI Technical Summary
In existing technologies, increasing the thickness of the chip's metal layer leads to wafer warping and increased difficulty in subsequent processes, thus affecting chip performance.
By etching the back side of the chip substrate, dielectric materials, barrier layers, and metal materials are directly embedded, the thickness of the metal layer is controlled and the thickness of the dielectric layer is reduced, thus avoiding the impact of the dielectric layer on the chip performance.
It improves the chip's power supply performance and heat dissipation capabilities, reduces the impact of dielectric layer thickness on chip performance, facilitates subsequent packaging, and reduces process difficulty.
Smart Images
Figure CN2024077665_23102025_PF_FP_ABST
Abstract
Description
A method of chip metallization and chip
[0001] The present application claims priority to the Chinese patent application No. 202310363203.6, filed on March 30, 2023, and entitled "A method of chip metallization and chip", the whole content of which is incorporated herein by reference. TECHNICAL FIELD
[0002] Embodiments of the present application relate to the field of semiconductor integrated circuit chip technology, and more particularly to a method of chip metallization and chip. BACKGROUND
[0003] Chip metallization refers to the process of depositing a conductive metal film on an insulating medium film during chip manufacturing, forming interconnection metal lines and integrated circuits through photolithography and etching processes, wherein the metal lines conduct signals in the integrated circuit, and the dielectric layer ensures that the signals are not affected by adjacent metal lines. Chip metallization process directly affects the transmission and power supply capability of signals in the chip. In order to improve the performance of the chip, it is desirable to have a thicker metal layer in the chip.
[0004] Typically, the backside of the chip substrate is metallized by etching the deposited dielectric layer and then depositing a metal film. It can also be understood that the thickness of the metal film is positively correlated with the thickness of the dielectric layer, so that the deposited metal can be embedded in the dielectric layer. Therefore, if you want to increase the thickness of the chip metal layer, you must increase the thickness of the dielectric layer. However, if the dielectric layer is too thick, it will generate a large film stress causing the wafer to warp, which will increase the difficulty of subsequent chip processes, and in some cases may damage the entire chip.
[0005] Therefore, there is a need for a method of chip metallization that can increase the thickness of the metal layer on the backside of the chip substrate and reduce the impact of the thickness of the dielectric layer on the performance of the chip.
[0006] SUMMARY
[0007] The present application provides a method of chip metallization that can increase the thickness of the metal layer on the backside of the chip substrate and reduce the impact of the thickness of the dielectric layer on the performance of the chip, thereby improving the power supply performance of the chip.
[0008] The first aspect provides a chip structure, the chip comprising: a back surface of a chip substrate is etched, a thickness of the chip substrate is a first thickness, and a depth of the etching is less than the first thickness; a first thin film is deposited on the back surface of the etched chip substrate, the first thin film being a dielectric material; a second thin film is deposited on the first thin film, the second thin film being a barrier layer material; and a third thin film is deposited on the second thin film, the third thin film being a metal material, wherein the third thin film is embedded in the chip substrate.
[0009] Based on the above technical solution, the chip back surface substrate can be etched directly without depositing a dielectric layer, so that the subsequently deposited first thin film, second thin film and third thin film can be embedded in the chip substrate, and the third thin film is a metal material. In other words, in the present application, the chip substrate is etched, and the thickness of the first thin film and the second thin film can be controlled to flexibly control the thickness of the third thin film. The thickness of the metal layer can be increased, and the thickness of the dielectric layer can be reduced as much as possible. The present application can reduce the influence of a too thick dielectric layer on the performance of the chip, and can improve the power supply performance of the chip, thereby improving the overall performance of the chip.
[0010] In addition, the thermal conductivity of the metal in the chip is generally higher than that of the chip substrate, and the metal electrode itself can be regarded as a heat source. The present application enables the metal electrode to be embedded in the chip substrate, thereby increasing the heat dissipation capacity of the chip. Moreover, the present application avoids the influence of the thickness of the dielectric layer on the performance of the chip, so that the thickness of the entire chip can be reduced, facilitating subsequent packaging of the chip, and reducing the difficulty of subsequent processes of the chip.
[0011] In a possible implementation manner, a fourth thin film is deposited on the back surface of the chip substrate, the fourth thin film being the dielectric material, and a thickness of the fourth thin film being a second thickness; the etching of the back surface of the chip substrate comprises: the chip substrate on which the fourth thin film is deposited is etched; and the deposition of the first thin film on the back surface of the etched chip substrate comprises: the first thin film is deposited on the back surface of the etched chip substrate on which the fourth thin film is deposited, wherein the etching depth is greater than the second thickness and less than a third thickness, and the third thickness is a sum of the first thickness and the second thickness.
[0012] Based on the above technical solution, the etching depth can exceed the thickness of the fourth thin film and reach the chip substrate, so that the metal thin film can be thicker, and the fourth thin film can be thinner, so that the thickness of the entire chip can be reduced, facilitating subsequent packaging of the chip, and reducing the difficulty of subsequent processes of the chip.
[0013] In a possible implementation, the chip substrate is a thinned substrate.
[0014] Based on the technical solution, the chip substrate can be thinned considering the difficulty of packaging process and the requirement on the volume of the chip.
[0015] In a possible implementation, the back surface of the chip substrate is deposited with a fourth thin film with a second thickness, including that the back surface of the chip substrate is deposited with a fifth thin film.
[0016] In a possible implementation, the back surface of the chip substrate is deposited with a fourth thin film with a second thickness, including that the back surface of the chip substrate is deposited with a fifth thin film, and a sixth thin film is deposited on the fifth thin film, wherein the fifth thin film and the sixth thin film are used as a hard mask layer and / or a polishing stop layer.
[0017] For example, the polishing rate of the fifth thin film and / or the sixth thin film can be less than the polishing rate of the metal thin film.
[0018] Based on the technical solution, the application proposes that two layers of dielectric thin films can be deposited, for example, the polishing rate of the fifth thin film and / or the sixth thin film is less than the polishing rate of the metal thin film, which can also be understood as that the entire polishing speed of the chip can be controlled through the fifth thin film and / or the sixth thin film. For another example, in order to prevent the photoresist from evaporating too fast in the etching process, the fifth thin film and / or the sixth thin film can be used as a hard mask layer to ensure the etching depth. It should be understood that the hard mask can transfer the photoresist image to the hard mask, and then transfer the final pattern etching to the substrate through the hard mask.
[0019] In a possible implementation, the chip substrate is a silicon substrate.
[0020] In a possible implementation, the thickness of the third thin film is greater than 9000A.
[0021] In a possible implementation, the back surface of the chip substrate is photoetched with a pattern including a pattern of metal electrodes and an auxiliary pattern, wherein the auxiliary pattern is used to flatten the surface of the third thin film in the polishing process.
[0022] Based on the technical solution, the chip metallization process provided by the application can be used to manufacture thick metal electrodes to improve the power supply capacity of the chip.
[0023] In a second aspect, a chip metallization method is provided, and it should be understood that the beneficial effects of the chip metallization method provided by the application correspond to the various implementations of the chip structure of the first aspect described above, and will not be described again.
[0024] The method comprises: etching a back surface of the chip substrate, wherein a thickness of the chip substrate is a first thickness, and a depth of the etching is less than the first thickness; depositing a first film on the etched chip substrate, the first film being a dielectric material; depositing a second film on the first film, the second film being a barrier layer material; and depositing a third film on the second film, the third film being the metal material, wherein the third film is embedded in the chip substrate.
[0025] In a possible implementation, before the etching the back surface of the chip substrate, the method further comprises:
[0026] depositing a fourth film with a second thickness on the back surface of the chip substrate, wherein the fourth film is the dielectric material; and etching the back surface of the chip substrate after the photolithography, wherein the etching depth is greater than the second thickness and less than a third thickness, and the third thickness is a sum of the first thickness and the second thickness.
[0027] In a possible implementation, the chip substrate is a thinned substrate.
[0028] In a possible implementation, the depositing the fourth film with the second thickness on the back surface of the chip substrate comprises: depositing a fifth film on the back surface of the chip substrate.
[0029] In another possible implementation, the depositing the fourth film with the second thickness on the back surface of the chip substrate comprises: depositing a fifth film on the back surface of the chip substrate; and depositing a sixth film on the fifth film, wherein the fifth film and the sixth film are used as a hard mask layer and / or a polishing stop layer.
[0030] For example, a polishing rate of the fifth film and / or the sixth film can be less than a polishing rate of the metal film.
[0031] In a possible implementation, the chip substrate is a silicon substrate, or the chip substrate is a gallium arsenide substrate, or the chip substrate is an indium phosphide substrate, and the like. The material of the chip substrate is not limited in the present application.
[0032] In a possible implementation, a thickness of the third film is greater than 9000 angstroms.
[0033] In a possible implementation, before etching the back surface of the chip substrate, the method further comprises: performing photoetching on the back surface of the chip substrate, a pattern of the photoetching comprising a pattern of the metal electrode and an auxiliary pattern, wherein the auxiliary pattern is used for flattening the surface of the third thin film in a polishing process.
[0034] In a third aspect, a chip system is provided, comprising a plurality of chips, wherein at least one chip of the plurality of chips is any one of the chips in the possible implementation manners of the first aspect.
[0035] In a fourth aspect, an electronic device is provided, comprising a circuit substrate, and the circuit substrate comprises the chip in any one of the possible implementation manners of the first aspect. BRIEF DESCRIPTION OF DRAWINGS
[0036] FIG. 1 is a schematic diagram of a chip structure formed after a conventional chip metallization process according to the present application.
[0037] FIG. 2 is a schematic flowchart of a chip metallization method 200 according to the present application.
[0038] FIG. 3 is a schematic diagram of a metallization process flow and a chip structure variation according to the present application.
[0039] FIG. 4 is a schematic diagram of a chip integration architecture according to the present application. DETAILED DESCRIPTION
[0040] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.
[0041] For the technical solutions of the present application, the following first introduces some professional terms in the semiconductor process related to the present application.
[0042] 1. Thin film deposition technology
[0043] Thin film deposition is an essential part of semiconductor process, by depositing a thin film on the surface of the semiconductor and then forming a specific circuit pattern through lithography process, so as to accurately control the performance and characteristics of electronic equipment. The traditional thin film deposition process mainly includes chemical vapor deposition (CVD) and physical vapor deposition (PVD). For CVD process, including atomic layer deposition (ALD) and plasma enhanced chemical vapor deposition (PECVD), PVD deposition technology includes magnetron sputtering, electron beam evaporation and thermal evaporation.
[0044] 2、Thinning
[0045] In the back-end-of-line phase, the front side of the wafer has been laid with circuits, and backside thinning is required before subsequent dicing, soldering and packaging to reduce the packaging height, reduce the chip packaging volume, improve the heat diffusion efficiency, electrical performance, mechanical performance of the chip and reduce the processing amount of dicing. Backside grinding has the advantages of high efficiency and low cost, and has replaced the traditional wet etching and ion etching process to become the most important backside thinning technology.
[0046] The grinding processes that have been successfully applied to silicon wafer preparation include rotary table grinding, silicon wafer rotary grinding, double-sided grinding, etc. With the further improvement of the demand for the surface quality of monocrystalline silicon wafers, new grinding technologies are constantly emerging, such as TAIKO grinding, chemical mechanical grinding, polishing grinding and planetary disc grinding, etc.
[0047] 3、Polishing
[0048] After thinning, the wafer surface has many defects, and there are many tiny cracks and stresses inside, so the consistency, uniformity and surface roughness of polishing are very important for the chip. Moreover, a perfect reflecting surface can be achieved through the polishing process. Chemical mechanical polishing (CMP) is one of the key technologies for processing the surface of semiconductor wafers, also known as chemical mechanical planarization (CMP).
[0049] Chemical mechanical polishing uses a process that combines mechanical friction and chemical corrosion: (1) chemical corrosion - polishing liquid: first, the oxidizing agent, catalyst, etc. in the polishing liquid between the workpiece surface and the polishing pad reacts with the workpiece surface material to produce a thin layer of chemical reaction film on the workpiece surface; (2) mechanical friction - polishing pad: then the abrasive particles in the polishing liquid and the polishing pad made of high polymer material remove the thin layer of chemical reaction film by mechanical action, so that the workpiece surface is exposed again, and then chemical reaction is carried out again. The whole process is the alternation of chemical action and mechanical action, and finally the polishing of the workpiece surface is completed, and the polishing rate can be controlled by the thin film with slow polishing rate.
[0050] 4. Cleaning
[0051] Cutting, lapping and polishing are indispensable steps in the production of laser devices. In these three steps, various greases such as lubricating oil and rust-proof oil are used to ensure the normal operation of the machine. Rosin, paraffin or a mixture of the two are usually used as adhesives to fix the single crystal. Various abrasives are used for grinding silicon wafers, often artificial or natural diamond powder such as silicon carbide (SiC) and aluminum oxide (Al2O3). Magnesium oxide (MgO), silicon dioxide (SiO2), and chromium trioxide (Cr2O3) are commonly used polishing powders for polishing. In the cutting, grinding and polishing steps, tap water is usually used for convenience and cost. Ordinary tap water generally contains gold, silver, copper, iron, nickel, potassium, sodium, calcium, magnesium, fluorine, chlorine, oxygen, hydrogen and other elements. In addition, these elements also exist in the air and the environment of production and manufacture. Therefore, after the single crystal is cut, ground and polished, grease, metal elements and dust often adhere to its surface.
[0052] Because almost all working environments and process operations can cause contamination of the single crystal surface, modern semiconductor device production generally uses super-clean workshops or super-clean workbenches. Usually the entire chip process is carried out in a hundred-level super-clean room to minimize dust impurities, and super-pure or high-purity chemicals, high-purity water are used for strict chemical cleaning of silicon wafers, production tools, metal materials, etc. During the cleaning process, impurities will react with chemicals and dissolve, thereby separating from the cleaned epitaxial wafer or device, and cold and hot pure water is used for rinsing to ensure that the surface is completely clean. Contamination of the device surface greatly affects every process in the production process, gradually accumulates, and causes the performance of the produced devices to deteriorate, the reliability to decrease, and finally completely fails.
[0053] 5. Lithography
[0054] In the semiconductor process flow, the determination of discrete devices and the determination of different regions in integrated circuits, such as light-emitting mesa, electrode pattern and current injection region, are realized by photolithography process, so photolithography is an extremely important single process. Photolithography is to transfer the design results on the mask (also known as photomask) to the material layer covering the device, and the pattern transfer can be realized by etching process with non-mask part selective removal. For example, a layer of dielectric film can be grown by PECVD as a preparation for photolithography, and the mask material is usually silicon dioxide (SiO2) or silicon nitride (SiNx). The general process of photolithography is as follows: first, the wafer surface is treated, then the photoresist is spin-coated, then the front oven is performed, then the alignment exposure and development are performed, and the last step is to harden the film.
[0055] 6. Etching
[0056] According to different processes, etching technology can be divided into dry etching and wet etching. In most cases, dry etching is used for preparing mesa in experiments. Compared with wet etching, dry etching has three outstanding advantages: first, the etching depth is easy to control; second, the etching rate can be adjusted independently; and third, the influence of external environment can be avoided. Wet etching is to achieve the required etching by a certain chemical reaction between the solution and the etched part. At present, wet etching is less used and has been gradually replaced by dry etching, but this method has outstanding applications in removing silicon dioxide, removing residues and electrode stripping.
[0057] 7. Chip metallization process
[0058] Metalization process is also known as metal forming process or metal wiring process. The connection between layers is needed for the operation of the circuit of the semiconductor, which requires "metalization process". Usually, the connection line needs to receive power from the outside to prevent the signals between elements from mixing together.
[0059] In the chip manufacturing process, a metal film can be deposited on an insulating dielectric film, and the metal wire is embedded in the insulating dielectric layer to form an electrical connection. Usually, the back metallization process of the chip substrate is to etch the deposited dielectric layer and then deposit a metal film. It can also be understood that the thickness of the metal film is positively correlated with the thickness of the dielectric layer, so that the deposited metal can be embedded in the dielectric layer. Therefore, if you want to increase the thickness of the chip metal layer, you must increase the thickness of the dielectric layer. However, if the dielectric layer is too thick, it will generate a large film stress and cause the wafer to warp, which will increase the difficulty of subsequent chip process and affect the overall performance of the chip.
[0060] Therefore, the application provides a chip metallization method, which can increase the thickness of the metal layer on the back of the chip substrate, reduce the influence of the thickness of the dielectric layer on the performance of the chip, and improve the power supply performance of the chip.
[0061] FIG. 2 is a schematic flow chart of a method 200 for chip metallization, as shown in FIG. 2, the method comprises:
[0062] In step 201, etching the back surface of the chip substrate.
[0063] It should be understood that the back surface and the front surface of the chip substrate can be distinguished by those skilled in the art, for example, the front surface of the chip substrate is used for growing materials of the designed chip structure. It should also be understood that the front surface of the chip substrate is generally used for growing functional materials, and the back surface of the chip substrate generally does not grow functional materials.
[0064] In a possible implementation, before etching the back surface of the chip, the back surface of the chip can also be subjected to photolithography. It should be understood that a pattern of metal electrodes can be made by a photolithography process. It is proposed in the present application that an auxiliary pattern can also be made during photolithography. Considering that the polishing rate of the metal material and the polishing rate of the surrounding dielectric film are different during subsequent polishing of the chip, and the area of the metal electrode is small, the auxiliary pattern can be added during photolithography to increase the area of the metal material, so that the polishing rate of the metal electrode is uniformized, thereby improving the flatness of the metal film surface.
[0065] In the present application, the thickness of the chip substrate is a first thickness. For example, the chip substrate is a silicon (Si) substrate; for another example, the chip substrate is gallium arsenide (GaAs); for yet another example, the chip substrate is indium phosphide (InP), and the like. The chip substrate is not limited in the present application. The etching depth is less than the first thickness.
[0066] In a possible implementation, the chip substrate is a thinned chip substrate.
[0067] Optionally, before step 201, step 202 of depositing a fourth film of a second thickness on the back surface of the chip substrate is further included, and the fourth film is a dielectric material.
[0068] In the present application, the fourth film is a dielectric material. For example, the fourth film can be an oxide film. For another example, the fourth film is a nitride film. The specific material of the dielectric film is not limited in the present application, and those skilled in the art can flexibly determine the material of the dielectric film based on the actual situation.
[0069] In a possible implementation, the fourth film is a layer of dielectric film. For example, it is an oxide film.
[0070] In another possible implementation, the fourth film in step 202 can also be understood as two films. For example, a fifth film can be deposited on the back of the chip substrate first, and then a sixth film can be deposited on the fifth film. The fifth film and the sixth film are hard mask layers and / or polishing stop layers. For example, the polishing rate of the sixth film is less than the polishing rate of the metal film. In view of subsequent polishing of the metal film, in order to control the polishing thickness, a protective film can be deposited in advance to protect the chip, and the protective film has a small polishing rate, and the polishing rate is at least less than the polishing rate of the metal film, so as to control the polishing rate. For another example, since the photoresist evaporates too fast in the etching process, the fifth film and / or the sixth film can also serve as a hard mask layer to ensure the etching depth. It should be understood that the hard mask can transfer the photoresist image to the hard mask, and then transfer the final pattern etching to the substrate through the hard mask.
[0071] In the above implementation, the etching depth is greater than the first thickness and less than the third thickness, and the third thickness is the sum of the first thickness and the second thickness. It can also be understood that the dielectric layer is etched in the etching process, and the chip substrate is further etched. It should be understood that in this implementation, since the fourth film with the first thickness is deposited, the etching depth can be greater than the thickness of the chip substrate.
[0072] It should be noted that according to the method provided by the present application, the present application proposes that the etching depth exceeds the thickness of the deposited fourth film in the etching process, that is, not only the dielectric layer is etched, but also the chip substrate is etched. And the thickness of the deposited fourth film can be less than 9000A, compared with the method of the prior art, the thickness of the dielectric layer can be reduced, the difficulty of subsequent chip process is reduced, and the overall performance of the chip can be improved.
[0073] In step 203, a first film is deposited on the etched chip substrate, and the first film is a dielectric material.
[0074] For example, the first film is an oxide film. For example, a film material with good adhesion to the chip substrate can be used, so as to cover the inside of the etched channel and the surface of the substrate.
[0075] In step 204, a second film is deposited on the first film, and the second film is a barrier layer material.
[0076] In the present application, for example, the second film is used to block the diffusion of the metal material.
[0077] For example, physical vapor deposition or atomic layer deposition can be used to deposit TaN / Ta or TiN / Ti, so as to form a metal barrier layer for blocking the diffusion of the subsequently deposited metal material.
[0078] It should be understood that the thickness of the first film, the sum of the thickness of the second film deposited in the present application is less than the depth of etching. That is, the thickness of the first film and the thickness of the second film sum is not more than the depth of etching. Thus, the third film deposited subsequently can be embedded in the chip substrate.
[0079] Step 205, depositing a third film on the second film, the third film is a metal material, wherein the third film is embedded in the chip substrate.
[0080] For example, copper (Cu), cobalt (Co), tungsten (W) and other metals can be deposited by electron beam evaporation or physical vapor deposition.
[0081] It should be understood that according to the process provided in the present application, the thickness of the metal film can be greater than 9000A.
[0082] Based on the above technical solutions, the present application proposes that without depositing a dielectric layer, the substrate on the back of the chip can be etched directly, so that the first film, the second film and the third film deposited subsequently can be embedded in the chip substrate, wherein the third film is a metal layer. In other words, in the present application, the chip substrate is etched into the chip substrate, and since the chip substrate is generally thick, the thickness of the third film can be flexibly controlled by controlling the thickness of the first film and the second film. Both the thickness of the metal layer and the thickness of the dielectric layer can be increased as much as possible. The scheme of the present application can reduce the influence of the too thick dielectric layer on the performance of the chip, and can improve the power supply performance of the chip, thereby improving the overall performance of the chip.
[0083] In addition, the thermal conductivity of the metal in the chip is generally higher than that of the chip substrate, and the metal electrode itself can be regarded as a heat source. The present application makes the metal electrode embedded in the chip substrate, thereby increasing the heat dissipation capacity of the chip. Moreover, the present application also avoids the influence of the thickness of the dielectric layer on the performance of the chip, so that the thickness of the whole chip can be reduced, facilitating the subsequent packaging of the chip, and reducing the difficulty of the subsequent process of the chip.
[0084] It should be noted that there are many process flows involved in the chip metallization process, and the present application only shows the main process flow or the improved process flow. Other necessary process flows can refer to the existing process, for example, an anti-reflective layer needs to be prepared to reduce the reflection of the bottom of the photoresist, improve the imaging contrast, and thereby improve the line width uniformity, etc. will not be described in detail.
[0085] In order to more clearly understand the technical solutions of the present application, Fig. 3 shows the main process flow involved in the metallization process and the change of the chip structure according to the present application. In the present example, the chip substrate is a silicon substrate for illustration, as shown in Fig. 3, the process flow includes:
[0086] Step 1: Backside thinning and planarization of silicon wafer
[0087] As shown in (a) of FIG. 3, the backside of the silicon wafer can be thinned and planarized by a thinning process and a polishing process.
[0088] Step 2: Deposition of dielectric film #1
[0089] As shown in (b) of FIG. 3, for example, an insulating dielectric film can be deposited on the backside of the thinned chip substrate by a PECVD method. For example, the film can be an oxide film.
[0090] Optionally, the application further proposes that a layer of insulating dielectric film can be re-deposited on the oxide film in step 2. For example, the film can be a nitride film; for another example, the film can still be an oxide film. Among them, the polishing rate of the nitride is less than the polishing rate of the metal film deposited in the subsequent process. Considering the polishing thickness control in the subsequent polishing of the metal film, a protective film can be deposited in advance to protect the chip, and the protective layer has the characteristics of a very small polishing rate, which is at least less than the polishing rate of the metal film. It can also be understood that the deposition of the sixth film controls the polishing rate.
[0091] The deposited dielectric film #1 in the application can be used as a hard mask layer and / or a polishing stop layer.
[0092] Step 3: Photolithography, etching and cleaning
[0093] For example, a pattern is made by a photolithography process, then a trench is etched by a dry etching process, and the chip is cleaned.
[0094] Optionally, the application further proposes that an auxiliary pattern can be made when the pattern of the metal electrode is made by photolithography, which is used to make the polishing rate of the metal electrode relatively more uniform in the subsequent polishing.
[0095] As shown in (c) of FIG. 3, the method in the application not only etches the dielectric film deposited in step 2, but also etches into the silicon substrate, so that the subsequently deposited metal material can be relatively thick, without the need to increase the thickness of the dielectric film.
[0096] Step 4: Deposition of dielectric film #2
[0097] As shown in (d) of FIG. 3, for example, an oxide film can be continuously deposited. A film material with good adhesion to the chip substrate can be used, so as to cover the inside of the etched trench and the surface of the substrate.
[0098] Step 5: Deposition of metal barrier film
[0099] As shown in (e) of FIG. 3, in order to prevent the diffusion of the subsequently deposited metal material, TaN / Ta or TiN / Ti can be deposited to block the diffusion of the metal layer.
[0100] Step 6: Depositing a metal thin film
[0101] As shown in (f) of FIG. 3, a metal such as copper (Cu), cobalt (Co), tungsten (W), etc. can be deposited, for example, by electron beam evaporation or physical vapor deposition.
[0102] Step 7: Polishing
[0103] As shown in (g) of FIG. 3, the trench metal and the metal barrier layer of the back silicon wafer can be polished, for example, by using the CMP method.
[0104] Step 8: Depositing a covering layer
[0105] As shown in (h) of FIG. 3, a nitride or carbonitride covering layer can be deposited, for example, by using the CVD method, to protect the metal electrode.
[0106] For example, (h) of FIG. 3 provides a chip structure obtained by the method of chip metallization according to the present application, as shown in (h) of FIG. 3, the chip includes a silicon wafer substrate, a dielectric thin film #1 (possibly one or two layers, for example, an oxide thin film of the first layer and a nitride thin film of the second layer), a dielectric thin film #2 (for example, an oxide thin film of the third layer), a barrier layer and a metal thin film. As can be seen from (h) of FIG. 3, the etching depth in the present application is greater than the thickness of the dielectric thin film #1, and it can also be understood that the etching in the present application reaches the silicon wafer substrate, so that the metal thin film is embedded in the silicon wafer substrate.
[0107] As can be seen from FIG. 1, the metal electrode is adjacent to the chip substrate on only one side, while as can be seen from (h) of FIG. 3 of the present application, three sides of the metal electrode are tightly adjacent to the chip substrate. Since the metal electrode itself is a heat source, the chip structure provided by the present application can increase the heat dissipation capacity of the chip.
[0108] In a possible implementation, the back of the chip substrate is deposited with a dielectric thin film #1, including: the back of the chip substrate is deposited with an oxide thin film.
[0109] In another possible implementation, the back surface of the chip substrate is deposited with a dielectric film 1, comprising: the back surface of the chip substrate is deposited with a fifth film, and the fifth film is deposited with a sixth film, wherein the polishing rate of the sixth film is less than the polishing rate of the fourth metal film. For example, the fifth film and the sixth film are both oxide films; for another example, the fifth film and the sixth film are both nitride films; for yet another example, the fifth film is an oxide film and the sixth film is a nitride film, and the like. The fifth film and the sixth film are hard mask layers and / or polishing stop layers.
[0110] In a possible implementation, the thickness of the metal film is greater than 9000A.
[0111] In a possible implementation, the pattern of the photolithography includes a pattern of the metal electrode and an auxiliary pattern, wherein the auxiliary pattern is used to homogenize the polishing rate of the metal film in the polishing process, thereby improving the flatness of the surface of the metal film.
[0112] FIG. 4 shows a schematic diagram of a chip integration architecture to which the scheme provided by the present application is applicable. Taking a three-dimensional integrated device as an example, FIG. 4 shows an architecture of three stacked dies. The scheme for manufacturing an ultrathick metal can be implemented on the back surface of the die. Taking die #1 as an example, the metal wiring on the back surface of the die can be implemented after the die is thinned, so that the metal wiring can be connected with the through silicon via, thereby realizing the electrical connection between the front surface and the back surface. Then, the front surface and the back surface of the die can be connected with die #2 through a hybrid bonding process. Similarly, die #3 and more stacked dies can be connected. Finally, the die is singulated and packaged into a chip product.
[0113] In the architecture shown in FIG. 4, based on the scheme provided by the present application, the power supply capability of the chip product can be enhanced, the heat dissipation capability can be increased, and the difficulty of packaging can be reduced.
[0114] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application, but not to limit the same; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalent ones; and such modifications or replacements do not make the essence of the corresponding technical solutions deviate from the protection scope of the technical solutions of the embodiments of the present application.
Claims
1. A chip, characterized by Comprising: a chip substrate, a first film, a second film, a third film, wherein, a back surface of the chip substrate is etched, a thickness of the chip substrate is a first thickness, a depth of the etching is less than the first thickness; a first film is deposited on the back surface of the chip substrate after the etching, the first film is a dielectric material; a second film is deposited on the first film, the second film is a barrier material; a third film is deposited on the second film, the third film is a metal material, wherein the third film is embedded in the chip substrate.
2. The chip according to claim 1, characterized in that, a fourth film is deposited on the back surface of the chip substrate, the fourth film is the dielectric material, a thickness of the fourth film is a second thickness, the etching of the back surface of the chip substrate comprises: the chip substrate on which the fourth film is deposited is etched; the first film is deposited on the back surface of the chip substrate after the etching, comprising: the first film is deposited on the back surface of the chip substrate on which the fourth film is deposited after the etching, wherein the etching depth is greater than the second thickness and less than a third thickness, the third thickness is a sum of the first thickness and the second thickness.
3. The chip of claim 2, wherein, the fourth film of the second thickness is deposited on the back surface of the chip substrate, comprising: a fifth film is deposited on the back surface of the chip substrate, and a sixth film is deposited on the fifth film, wherein the fifth film and the sixth film are used as a hard mask layer and / or a polishing stop layer.
4. The chip according to any one of claims 1 to 3, characterized in that, the chip substrate is a thinned substrate.
5. The chip according to any one of claims 1 to 4, characterized in that, the chip substrate is a silicon substrate.
6. The chip according to any one of claims 1 to 5, characterized in that a thickness of the third film is greater than 9000A.
7. The chip according to any one of claims 1 to 6, wherein a pattern of the back surface of the chip substrate is photoetched, comprising a pattern of a metal electrode and an auxiliary pattern, wherein the auxiliary pattern is used to make a surface of the third film flat in a polishing process.
8. A method of chip metallization, characterized by, Comprising: etching a back surface of the chip substrate, wherein a thickness of the chip substrate is a first thickness, a depth of the etching is less than the first thickness; depositing a first film on the chip substrate after the etching, the first film is a dielectric material; depositing a second film on the first film, the second film is a barrier material; depositing a third film on the second film, the third film is the metal material, wherein the third film is embedded in the chip substrate.
9. The method of claim 8, wherein, the method further comprises, before the etching of the back surface of the chip substrate: depositing a fourth film of a second thickness on the back surface of the chip substrate, wherein the fourth film is the dielectric material; the etching of the chip substrate comprises: etching the back surface of the chip substrate on which the fourth film is deposited, wherein the etching depth is greater than the second thickness and less than a third thickness, the third thickness is a sum of the first thickness and the second thickness.
10. The method of claim 9, wherein, the depositing of the fourth film of the second thickness on the back surface of the chip substrate, comprising: depositing a fifth film on the back surface of the chip substrate; depositing a sixth film on the fifth film; wherein the fifth film and the sixth film are used as a hard mask layer and / or a polishing stop layer.
11. The method according to any one of claims 8 to 10, characterized in that, the chip substrate is a thinned substrate.
12. The method according to any one of claims 8 to 11, characterized in that, the chip substrate is a silicon substrate.
13. The method according to any one of claims 8 to 12, characterized in that, The third thin film has a thickness greater than 9000 A.
14. The method according to any one of claims 8 to 13, characterized in that, Before etching the back surface of the chip substrate, the method further comprises: photolithography on the back surface of the chip substrate, a pattern of the photolithography including a pattern of metal electrodes and an auxiliary pattern, wherein the auxiliary pattern is used to planarize a surface of the third thin film in a polishing process. The electronic device includes a circuit substrate, and the circuit substrate includes the chip according to any one of claims 1 to 7.
15. An electronic device, comprising: