Integrated component package with a laser package arranged on a semiconductor chip

Abstract

The invention relates to an integrated component package, comprising a first semiconductor chip with a first main side and an opposing second main side, wherein a first number of contact areas are formed on the first main side and provided for connecting a laser package, and a second number of contact areas are formed on the second main side and provided for connecting to a carrier, in particular a PCB. The integrated component package also comprises a hermetically encapsulated laser package connected to at least two of the first number of contact areas, and a plurality of first passive electrical components arranged on the first main side and / or on the carrier and each being electrically connected to the first semiconductor chip and / or the carrier. The first semiconductor chip comprises at least one layer with an integrated circuit, which is electrically connected at least to portions of the first number of contact areas and is electrically connected at least to portions of the second number of contact areas for its power supply.

Description

[0001] INTEGRATED COMPONENT PACKAGE WITH A LASER PACKAGE ARRANGED ON A SEMICONDUCTOR CHIP

[0002] This application claims priority from German patent application No. 10 2023 112 751 . 9 of May 15, 2023, the disclosure of which is hereby incorporated by reference into this application.

[0003] The present invention relates to an integrated component package with a laser package arranged on a semiconductor chip and to a method for producing an integrated component package.

[0004] BACKGROUND

[0005] Laser packages play an important role in the development of electronic devices and systems designed to project / emit laser light. In particular, in the field of virtual reality (VR) and augmented reality (AR), laser packages play an important role in things like smart glasses or so-called AR or VR glasses, where they are used to generate holographic images to provide the user with an immersive experience. In the past, laser packages were mainly used in industrial applications where size and weight are not particularly critical. Today, however, they are increasingly being used in consumer devices such as AR and VR glasses. It is therefore crucial that manufacturers develop smaller laser packages and associated driver circuits suitable for these applications.

[0006] However, the size of these components, particularly in combination with a driver circuit for operating the laser package, has so far been a challenge for use in AR and VR glasses. Current laser packages in combination with a driver circuit for operating the laser package are too large to be inconspicuously installed in AR and VR glasses. This presents developers and manufacturers with problems, as they require smaller components to reduce the size and weight of the glasses. There is therefore a need to provide a laser package comprising associated driver electronics that can overcome at least some of the problems mentioned above. There is also a need to provide a method for producing such a laser package with associated driver electronics.

[0007] SUMMARY OF THE INVENTION

[0008] This need is met by the subject matter of the independent patent claims. Further developments and embodiments of the proposed principle are specified in the subclaims.

[0009] To solve the problem mentioned, the inventors propose an integrated component package which comprises a carrier, such as a PCB board, a semiconductor chip arranged on the carrier and comprising an integrated circuit, and a hermetically encapsulated laser package which is in turn arranged on the semiconductor chip. In addition, passive electrical components required for the driver electronics are located on the carrier and / or the semiconductor chip and are thus integrated into the integrated component package. The stacked arrangement on top of one another or on top of one another makes it possible to reduce the overall size of the package because, for example, a space-saving arrangement of the individual components can be selected using direct vias through the semiconductor chip and / or the carrier. In addition, the stacked arrangement makes it possible to reduce the space required in the lateral direction.footprint ) of such an integrated component package can be greatly reduced compared to individual components arranged side by side .

[0010] According to a first aspect, an integrated component package is provided. The integrated component package comprises a first semiconductor chip with a first main side and an opposite second main side. A first number of contact areas is formed on the first main side, which is provided for connecting a laser package, and a second number of contact areas is formed on the first and / or second main side, which is provided for connection to a carrier, in particular a PCB. The first semiconductor chip comprises at least one layer with an integrated circuit, which is electrically connected to at least parts of the first number of contact areas and is electrically connected to at least parts of the second number of contact areas for supplying power to the latter. The integrated component package also comprises a hermetically encapsulated laser package, which is formed on or...is arranged above the first semiconductor chip and is electrically connected to at least two of the first number of contact surfaces. Furthermore, the integrated component package comprises a plurality of first passive electrical components, such as resistors, capacitors and / or inductors, which are arranged on the first main side and / or on the carrier and are each electrically connected to the first semiconductor chip and / or the carrier.

[0011] The laser package can, for example, be a self-contained laser package module that includes one or more light-emitting components, such as laser diodes. The one or more light-emitting components can, for example, be designed to emit light of a specific wavelength or light of different wavelengths. Accordingly, such a laser package can, for example, be designed to emit red, green, blue, and any light that is miscible from these colors, thus providing an RGB laser package. For example, the laser package can include a hermetic encapsulation to increase the service life of the light-emitting components.

[0012] According to some aspects, the contact surfaces of the first and the second number of contact surfaces differ in that the contact surfaces of the second number of contact surfaces are provided for connection to the carrier and optionally for connecting first passive electrical components, and in that the contact surfaces of the first number of contact surfaces are provided for connecting a laser package, first passive electrical components and optionally further semiconductor chips. According to some aspects, the first semiconductor chip has a plurality of first vias, in particular through-silicon vias (TSV), which extend from the first main side to the second main side and optionally electrically connect at least some of the first and second contact surfaces to one another.

[0013] According to some aspects, the first semiconductor chip has at least one redistribution layer (RDL) that is connected to at least some of the first and / or second number of contact pads and is formed above and / or below the one layer with the integrated circuit. In particular, for example, an uppermost and / or a lowermost layer of the first semiconductor chip can be formed by a redistribution layer in order to provide the first and / or second number of contact pads on the first and / or second main side over the entire main side. A redistribution layer can be an additional layer / layer in the first semiconductor chip comprising metallic elements, which makes its contact pads available at other locations on the semiconductor chip in order to enable better access to the contact pads if necessary.In particular, a redistribution layer can be an additional wiring layer on the top and / or bottom of the semiconductor chip, enabling bonding from different locations on the semiconductor chip and thus simplifying chip-to-chip bonding. Another example of the use of RDL is the distribution of contact areas on the semiconductor chip, allowing solder balls to be applied and the thermal load to be distributed during assembly.

[0014] According to some aspects, the plurality of first vias is arranged in a lateral edge region of the first semiconductor chip. In such a case, the at least one rewiring layer can be designed to electrically connect contact surfaces of the first and / or second number, which are arranged in a central region of the first semiconductor chip surrounded by the edge region, to one of the plurality of first vias each. In particular, the at least one rewiring layer can be designed to provide an electrical connection between the first vias arranged in the edge region of the first semiconductor chip and the contact surfaces of the first and / or second number distributed over the entire first and / or second main side.

[0015] According to some aspects, the integrated component package further comprises a plurality of bond wires that electrically connect the carrier to contact surfaces of the second number of contact surfaces. Such bond wires can be provided in addition to or as an alternative to the first vias. Furthermore, for example, parts of the passive electrical components and / or the laser package can also be electrically connected to the first semiconductor chip and / or the carrier by means of additional bond wires or solely by means of bond wires.

[0016] According to some aspects, the first semiconductor chip comprises a substrate layer made of a semiconductor material, in particular Si, which is free of an integrated circuit. Furthermore, the first semiconductor chip may comprise a leveling layer that, for example, level out unevennesses of a rewiring layer or other unevennesses within or on the first and / or second main side.

[0017] According to some aspects, the integrated component package further comprises a second semiconductor chip and / or at least one second passive electrical component, such as a resistor, a capacitor, and / or an inductor, which is integrated into the carrier, in particular on a side opposite the first semiconductor chip. This also allows the lateral space requirement of such an integrated component package to be significantly reduced compared to individual components arranged side by side.

[0018] According to some aspects, the integrated component package further comprises a plurality of second vias, in particular metallic vias, through the carrier, which electrically contact the second semiconductor chip and / or the at least one second passive electrical component. By means of the second vias, the second semiconductor chip and / or the at least one second passive electrical component can be electrically connected to, for example, the first semiconductor chip in a space-saving manner. The second semiconductor chip can be formed according to the aspects of the first semiconductor chip and in particular comprise at least one layer with an integrated circuit which is electrically connected to at least parts of the second vias.

[0019] According to some aspects, the first semiconductor chip comprises at least two layers arranged one above the other, each containing an integrated circuit. The first semiconductor chip can comprise correspondingly stacked layers, each containing an integrated circuit. Between the layers there can be, for example, an intermediate or compensating layer through which third vias run, which electrically couple the layers arranged one above the other, each containing an integrated circuit. In particular, the third vias can therefore also be called IC-IC vias. For example, such an arrangement can also result from two separate integrated circuits being stacked on top of one another with their active area facing one another, and an intermediate or compensating layer being arranged between the two circuits.

[0020] According to some aspects, the first semiconductor chip has fourth vias which extend from the first main side to one of the at least two layers arranged one above the other, each having an integrated circuit, and / or which extend from the second main side to one of the at least two layers arranged one above the other, each having an integrated circuit, and which electrically connect at least some of the first and / or second contact surfaces to one of the at least two layers arranged one above the other, each having an integrated circuit.

[0021] According to some aspects, the second number of contact areas is formed by a ball grid array (BGA) that is connected to contact areas on the carrier. Such a design enables SMD assembly of the first semiconductor chip because the connections are located compactly on the underside of the semiconductor chip. The connections are small solder balls that are arranged next to one another in a grid of columns and rows (array). These balls are melted during reflow soldering in a soldering oven and connect to contact pads on the carrier. This design represents a solution to the problem of accommodating a very large number of connections on a component. In addition, despite surface soldering, e.g. with hot air, the semiconductor chips can be removed (desoldered) from the carrier again without being damaged.The semiconductor chips can then be freed of the old solder balls (deballed), cleaned, and re-beaded with new solder balls (re-beading), before being soldered onto a new carrier. This allows defective semiconductor chips to be replaced, for example, during the repair of an integrated component package.

[0022] According to some aspects, the integrated component package further comprises an optical element, in particular a lens, which is arranged on the first semiconductor chip downstream of the laser package in the light emission direction of the laser package. By arranging the optical element on the first semiconductor chip, on which the laser package is also arranged, thermal stresses within the integrated component package can have no or only a minimal negative effect on the position of the optical element relative to the laser package. This can be due, among other things, to the fact that the optical element is arranged on the same coherent material as the laser package and also to the fact that the first semiconductor chip can have a relatively high rigidity and thus provides an optical bench with high rigidity and low GTE for the arrangement of laser package and optical element.In addition, by placing the optical element and the laser package on the first semiconductor chip, the space requirement in the lateral direction of such an integrated component package can be greatly reduced compared to individual components arranged next to one another.

[0023] According to some aspects, the integrated component package further comprises a submount which is arranged between the laser package and the first semiconductor chip. Such a submount can be advantageous, for example, in combination with an optical element arranged downstream of the laser package in the light emission direction of the laser package, since so-called beam clipping of the light emitted by the laser package can be prevented or at least reduced by raising the height of the laser package. In addition, it also allows greater latitude for the choice of the optical element with regard to, for example, size, optical properties and material, as well as greater latitude with regard to the arrangement of the optical element with regard to the distance between the optical element and the laser package. However, the use of a submount is not restricted to use together with an optical element, but can also be used for other reasons.For example, to provide a heat sink or a heat extraction layer between the laser package and the first semiconductor chip, or to provide a further third semiconductor chip that provides further functionality of the integrated component package. Such a third semiconductor chip can be configured according to the first and / or second semiconductor chip and comprise at least one layer with an integrated circuit.

[0024] According to some aspects, the integrated component package further comprises a heat sink which is arranged on the first semiconductor chip and / or the carrier and / or the laser package and / or the submount. It is also conceivable for the integrated component package additionally or alternatively to comprise a heat extraction layer which is arranged between the first semiconductor chip and the laser package and / or between the first semiconductor chip and the carrier and / or between layers, each containing an integrated circuit of the first semiconductor chip. Such a heat sink and / or such a heat extraction layer can in particular be designed to store and / or dissipate heat generated during operation of the integrated component package in order to prevent overheating and the associated change in the operating conditions of the integrated component package or, in extreme cases, even failure of the integrated component package.

[0025] According to a further aspect, a method for producing an integrated component package, in particular an integrated component package according to at least some of the aspects described above, is provided. The method comprises the steps of: providing a carrier, in particular a PCB board;

[0026] Arranging a first semiconductor chip with a first main side and an opposite second main side on the carrier, o wherein a first number of contact surfaces is formed on the first main side and is provided for connecting a laser package, o wherein a second number of contact surfaces is formed on the first and / or second main side and is provided for connecting to the carrier, and o wherein the first semiconductor chip comprises at least one layer with an integrated circuit which is electrically connected to at least parts of the first number of contact surfaces and is electrically connected to at least parts of the second number of contact surfaces for its power supply;

[0027] Arranging a hermetically encapsulated laser package on the first semiconductor chip such that the laser package is connected to at least two of the first number of contact surfaces; and arranging a plurality of first passive electrical components on the first main side and / or on the carrier such that they are each electrically connected to the first semiconductor chip and / or the carrier.

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Further aspects and embodiments according to the proposed principle will become apparent with reference to the various embodiments and examples which are described in detail in conjunction with the accompanying drawings.

[0030] Figure 1 shows a side view of an integrated component package according to some aspects of the proposed principle; Figures 2A and 2B each show a top view of another integrated component package according to some aspects of the proposed principle;

[0031] Figures 3 and 4 each show a side view of another integrated component package according to some aspects of the proposed principle;

[0032] Figure 5 shows a top view of another integrated

[0033] Component packages according to some aspects of the proposed principle;

[0034] Figures 6 to 8 each show a side view of another integrated component package according to some aspects of the proposed principle;

[0035] Figure 9 shows a top view of another integrated

[0036] Component packages according to some aspects of the proposed principle; and

[0037] Figure 10 shows a side view of another integrated component package according to some aspects of the proposed principle.

[0038] DETAILED DESCRIPTION

[0039] The following embodiments and examples show various aspects and their combinations according to the proposed principle. The embodiments and examples are not always to scale. Likewise, various elements may be shown enlarged or reduced in size to emphasize individual aspects. It goes without saying that the individual aspects and features of the embodiments and examples shown in the figures can be easily combined with one another without thereby impairing the inventive principle. Some aspects have a regular structure or shape. It should be noted that in practice slight deviations from the ideal shape may occur without, however, contradicting the inventive idea.

[0040] Furthermore, the individual figures, features, and aspects are not necessarily shown in the correct size, and the proportions between the individual elements may not always be correct. Some aspects and features are emphasized by being shown at an enlarged size. However, terms such as "top", "above", "below", "larger", "smaller", and the like are correctly represented in relation to the elements in the figures. This makes it possible to infer such relationships between the elements from the illustrations.

[0041] Figure 1 shows a first embodiment of an integrated component package 1 according to some aspects of the proposed principle. The integrated component package 1 comprises a carrier 6 on which a first semiconductor chip 2a is arranged. On the first semiconductor chip 2a there is in turn arranged a laser package 5 which is designed to emit laser light L in a light emission direction along the semiconductor chip. In the case shown and identified by the three arrows, the laser package is in particular designed to emit light in the colors red, green and blue or any color miscible therefrom. The first semiconductor chip 2a has a first main side 3a and an opposite second main side 3b. A first number of contact surfaces 4a (not shown) is formed on the first main side 3a, at least two of which are electrically connected to the laser package 5.Furthermore, a second number of contact surfaces 4b are formed on the second main side 3b, which contact surfaces are designed in the form of a ball grid array and are in electrical contact with contact surfaces on the carrier 6. Furthermore, first passive electrical components 7a are arranged on the first semiconductor chip 2a and (not shown) on the carrier 6, which are each electrically connected to the first semiconductor chip 2a and to the carrier 6 and contribute a partial functionality to the operation of the integrated component package 1. The term "operation of the integrated component package" is to be understood as meaning both an electrical supply and a signal-based control of the integrated component package and, associated with it, the laser package.

[0042] By stacking the carrier 6, the first semiconductor chip 2a, the laser package 5 and the passive electrical components 7a, it is possible to design the integrated component package 1 in the most space-saving way possible compared to a design in which the individual components are arranged next to one another and have to be electrically connected to one another by laterally running contact lines. In addition, such an integrated module can be installed and connected in an intended application simply and without further complex subsequent processes. The laser package 5 is arranged in particular on an edge region of the first semiconductor chip 2a or carrier 6 and is essentially flush with a side surface of the first semiconductor chip 2a and the carrier 6 in order to prevent or at least reduce so-called beam clipping of the light s L emitted by the laser package 6.

[0043] Figures 2A and 2B each show a plan view of an embodiment of an integrated component package 1 according to some aspects of the proposed principle. In particular, Figure 2a shows a plan view of the integrated component package 1 shown in Figure 1. Also shown are the first passive electrical components 7a arranged on the carrier 6. As shown, these are arranged not only on the first semiconductor chip 2a, but also on the carrier 6 next to the first semiconductor chip 2a. Furthermore, contact areas of the first number of contact areas 4a on the first main side 3a are shown, which are electrically connected by means of some of the first passive electrical components 7a. The contact areas of the first number of contact areas 4a that are electrically connected to the first passive electrical components 7a are also redistributed or distributed on the first main side 3a, as shown.to other areas of the first main side in order to electrically contact a correspondingly desired further contact or through-hole connection of the first semiconductor chip 2a. This can be done, for example, in the form of an RDL 10, which forms the first main side 3a. The integrated component package 1 shown in Figure 2B differs from the integrated component package 1 shown in Figure 2A in that the integrated component package 1 further has bonding wires 11, which electrically connect the carrier 6 to contact surfaces of the second number of contact surfaces 4b. At the same time, the contact surfaces of the second number of contact surfaces 4b can serve at least partially to connect at least one terminal of some of the first passive electrical components 7a.The second terminal of these first passive electrical components 7a can, for example, be electrically connected, as shown, to contact surfaces of the first number of contact surfaces 4a. By using bonding wires 11 as an alternative or in addition to vias through the first semiconductor chip 2a, the design and construction of the first semiconductor chip 2a itself can be simplified, since no or at least fewer vias through the first semiconductor chip 2a are necessary.

[0044] Figures 3 and 4 each show a side view of an embodiment of an integrated component package 1 according to some aspects of the proposed principle. In particular, Figure 3 shows an integrated component package 1 comprising first vias 9a, which extend from the first main side 3a to the second main side 3b and electrically connect contact surfaces of the first number of contact surfaces 4a to contact surfaces of the second number of contact surfaces 4b. In addition, Figure 3 shows a possible embodiment of a rewiring layer 10, by means of which contact surfaces of the first number of contact surfaces 4a can be provided over the entire first main top side 3a.First vias 9a can provide an electrical connection between contact surfaces of the second number of contact surfaces 4b and the rewiring layer 10, and the rewiring layer 10 can then lead these first vias 9a, which in particular extend vertically upwards, to other regions on the first main top side 3a.

[0045] Figure 4 additionally shows bonding wires 11, which, in addition to the first vias 9a, provide an electrical connection between the carrier 6 and contact surfaces on the first main side 3a of the first semiconductor chip 2a. Such bonding wires 11 can reduce the number of first vias 9a, which are required, for example, to provide sufficient contact surfaces on the first main side 3a of the first semiconductor chip 2a.

[0046] In addition, Figure 4 shows that the first semiconductor chip 2a comprises a layer with an integrated circuit 8, which is electrically connected to at least parts of the first number of contact surfaces 3a and is electrically connected to at least parts of the second number of contact surfaces 3b for its power supply. In particular, the electrical connection to parts of the second number of contact surfaces 3b can be made directly via the first vias or via the bonding wires 11, contact surfaces of the second number of contact surfaces 4b and a rewiring layer 10. The first semiconductor chip 2a also comprises a substrate layer 12 made of a semiconductor material, in particular Si, which is free of an integrated circuit and on which the layer with the integrated circuit 8 is arranged. This substrate layer 12 can serve, for example, as a carrier for the layer with the integrated circuit 8.The layer with the integrated circuit 8 is indicated by the dashed line. Furthermore, the first semiconductor chip 2a comprises a compensating layer 13, which can either be a component of the rewiring layer 10 and can form an insulating and compensating function between the metallic rewirings of the rewiring layer, or can additionally be arranged as a compensating layer on the rewiring layer 10. In addition to an insulating effect, the compensating layer 13 can serve to provide a flat surface of the first semiconductor chip 2a.

[0047] Figure 5 shows a corresponding top view of an integrated component package 1 according to some aspects of the proposed principle, in particular of the integrated component package 1 shown in Figure 4. In particular, it can be seen that essentially the entire free surfaces of the carrier 6 and the first main side 3a are occupied by first passive electrical components 7a or bonding wires 11, resulting in a highly integrated component package 1. The positioning and number of the first passive electrical components 7a and the bonding wires 11, as well as the contact surfaces of the first and second number of contact surfaces 4a, 4b, are, however, to be understood as examples and can vary depending on the design and application of the integrated component package 1.

[0048] The integrated component package 1, which is shown in Figure 6, additionally has a second semiconductor chip 2b and second passive electrical components 7b, which are integrated into the carrier 6 on a side opposite the first semiconductor chip 2a. For this purpose, the carrier has cutouts in which the components or the semiconductor chip are arranged. In addition, second vias 9b are provided through the carrier, by means of which an electrical contact is led through the carrier 6 in order to be able to electrically contact the second semiconductor chip 2b and the second passive electrical components 7b from the side facing the first semiconductor chip 2a. Such an arrangement makes it possible to further reduce the space required by the integrated component package 1 in the lateral direction.

[0049] The integrated component package 1 shown in Figure 7 has, in addition to the components integrated into the carrier 6, a first semiconductor chip 2a which has two layers stacked one above the other with an integrated circuit 8. In particular, the first semiconductor chip 2a can comprise two separate integrated circuits which are arranged one above the other in a face-to-face arrangement. A compensating or intermediate layer 13 is arranged between the two layers with the integrated circuit 8, and optionally a redistribution layer. The first semiconductor chip 2a also comprises two substrate layers 12 which each form a carrier for the two layers with the integrated circuit 8 and can each form a separate integrated circuit with a layer with the integrated circuit 8.The layers with the integrated circuit 8 are electrically connected to one another by direct third vias 9c, or can be electrically connected to one another by an intermediate redistribution layer, optionally in combination with the third vias 9c. Furthermore, the first semiconductor chip 2a has fourth vias 9d, which extend from the first main side 3a to one of the layers with the integrated circuit 8 or which extend from the second main side 3b to one of the layers with the integrated circuit 8.By combining first vias 9a through the entire first semiconductor chip 2a and / or third vias 9c for connecting the layers to the integrated circuit 8 and / or fourth vias 9d through parts of the first semiconductor chip up to one of the layers with the integrated circuit 8 and / or bond wires 11, the desired and required interconnections and contacts within the integrated component package 1 can be provided in the most space-saving manner possible and at the same time as simply as possible.

[0050] Figures 8 to 10 show embodiments of an integrated component package 1 which additionally comprises an optical element 14. The optical element 14 is arranged downstream of the laser package 5 in the light emission direction on the first semiconductor chip 2a. The optical element 16 can in particular be a passive optical element such as one or more lenses which shape, scatter or deflect / redirect the light emitted by the laser package 5. However, it is also conceivable for the optical element 16 to be formed by an active optical element which actively shapes, scatters or in particular deflects / redirects the light emitted by the laser package 5.

[0051] As shown in Figure 8 in side view and Figure 9 in plan view, two lenses 14 are arranged on the first semiconductor chip 2a in the beam path of the light L emitted by the laser package. The first passive electrical components 7a are arranged correspondingly more behind the laser package 5 on the first semiconductor chip 2a and laterally from the first semiconductor chip 2a on the carrier 6 in order not to produce any shadowing effects in the beam path of the light L emitted by the laser package 5.

[0052] By arranging the optical element 14 on the first semiconductor chip 2a, on which the laser package 5 is also arranged, thermal stresses within the integrated component package 1 can have no or only a minimal negative effect on the position of the optical element 14 relative to the laser package 5. This can be due, among other things, to the fact that the optical element 14 is arranged on the same continuous material as the laser package 5 and also to the fact that the first semiconductor chip 2a can have a relatively high rigidity and thus provides an optical bench with high rigidity and low GTE for the arrangement of the laser package 5 and the optical element 14.In addition, by placing the optical element 14 and the laser package 5 on the first semiconductor chip 2a, the space requirement in the lateral direction of such an integrated component package 1 can be greatly reduced compared to individual components arranged next to one another.

[0053] The integrated component package 1 shown in Figure 10 additionally comprises a submount 15 which is arranged between the laser package 5 and the first semiconductor chip 2a. The submount 15 in combination with the optical element 14 arranged downstream of the laser package 5 in the light emission direction of the laser package 5 is particularly advantageous since, by raising the laser package 5, so-called beam clipping of the light s L emitted by the laser package 5 can be prevented or at least reduced. In addition, it also allows greater latitude for the selection of the optical element 14 with regard to, for example, size, optical properties and material, as well as greater latitude with regard to the arrangement of the optical element with regard to the distance between the optical element 14 and the laser package 5.By using a submount 15, the first passive electrical components 7a can also be arranged in regions "in front" of the laser package 5, as long as they are not arranged in the light cone of the light L emitted by the laser package 5.

[0054] In the case shown, the submount 15 is formed by a third semiconductor chip 2c, which comprises at least one layer with an integrated circuit. The third semiconductor chip 2c can be designed according to the embodiments as described for the first semiconductor chip 2a. In the case shown, the third semiconductor chip is attached to the first semiconductor chip 2a by means of a ball grid array and electrically connected to the latter. The first passive electrical components 7a can be arranged in the integrated component package 1 shown on the first semiconductor chip 2a, the carrier 6 and the third semiconductor chip 2c. The third semiconductor chip 2c can, for example, provide a further functionality or partial functionality of the integrated component package 1, which contributes to the operation of the integrated component package 1.

[0055] LIST OF REFERENCE SYMBOLS

[0056] 1 integrated component package

[0057] 2a, 2b, 2c semiconductor chip

[0058] 3a, 3b Main page

[0059] 4a, 4b contact surface

[0060] 5 laser packages

[0061] 6 carriers

[0062] 7a, 7b passive electrical component

[0063] 8 integrated circuit

[0064] 9a, 9b, 9c, 9d Through-hole plating

[0065] 10 Rewiring layer

[0066] 11 Bonding wire

[0067] 12 substrate layer

[0068] 13 Compensation lay

[0069] 14 optical element

[0070] 15 submounts

[0071] L Light

Claims

PATENT CLAIMS 1. Integrated component package (1) comprising: - a first semiconductor chip (2a) with a first main side (3a) and an opposite second main side (3b), o in which a first number of contact surfaces (4a) is formed on the first main side (3a) and is provided for connecting a laser package (5), and o in which a second number of contact surfaces (4b) is formed on the first and / or second main side (3a, 3b) and is provided for connecting to a carrier (6), in particular a PCB; - a hermetically encapsulated laser package (5) which is electrically connected to at least two of the first number of contact surfaces (4a); and - a plurality of first passive electrical components (7a) which are arranged on the first main side (3a) and / or on the carrier (6) and are each electrically connected to the first semiconductor chip (2a) and / or the carrier (6); wherein the first semiconductor chip (2a) comprises at least one layer with an integrated circuit (8) which is electrically connected to at least parts of the first number of contact surfaces (3a) and is electrically connected to at least parts of the second number of contact surfaces (3b) for supplying power to the first semiconductor chip.

2. Integrated component package according to claim 1, wherein the first semiconductor chip (2a) has a plurality of first vias (9a), in particular silicon vias, which extend from the first main side (3a) to the second main side (3b) and optionally electrically connect at least some of the contact surfaces of the first and second number of contact surfaces (4a, 4b) to one another.

3. Component package according to one of the preceding claims, wherein the first semiconductor chip (2a) has at least one rewiring layer (10) connected to at least some of the contact surfaces of the first and second number of contact surfaces (4a, 4b) and which is formed above and / or below the one layer with the integrated circuit (8).

4. Integrated component package according to one of the preceding claims, wherein the plurality of first vias (9a) are arranged in a lateral edge region of the first semiconductor chip (2a), and wherein the at least one rewiring layer (10) is designed to electrically connect contact surfaces of the first and / or the second number of contact surfaces (4a, 4b), which are arranged in a central region of the first semiconductor chip (2a) surrounded by the edge region, to one of the plurality of first vias (9a).

5. Integrated component package according to one of the preceding claims, further comprising a plurality of bonding wires (11) which electrically connect the carrier (6) to contact surfaces of the second number of contact surfaces (4a).

6. Integrated component package according to one of the preceding claims, wherein the first semiconductor chip (2a) has a substrate layer (12) made of a semiconductor material, in particular Si, which is free of an integrated circuit.

7. Integrated component package according to one of the preceding claims, further comprising a second semiconductor chip (2b) and / or at least one second passive electrical component (7b) which is integrated into the carrier (6), in particular on a side opposite the first semiconductor chip (2a).

8. Integrated component package according to claim 7, further comprising a plurality of second vias (9b) through the carrier (6) which electrically contact the second semiconductor chip (2b) and / or the at least one second passive electrical component (7b).

9. Integrated component package according to one of the preceding claims, wherein the first semiconductor chip (2a) comprises at least two layers arranged one above the other, each having an integrated circuit (8), and wherein the at least two layers arranged one above the other, each having an integrated circuit (8), are electrically coupled to one another, in particular by third vias (9c).

10. Integrated component package according to claim 9, wherein the first semiconductor chip has fourth vias (9d) which extend from the first and / or second main side (3a) to one of the at least two layers arranged one above the other, each having an integrated circuit (8), and optionally electrically connect at least some of the contact surfaces of the first and / or second number of contact surfaces (4a, 4b) to one of the at least two layers arranged one above the other, each having an integrated circuit (8).

11. Integrated component package according to claim 9 or 10, wherein a compensating layer (13) is arranged between the at least two layers arranged one above the other, each having an integrated circuit (8).

12. Integrated component package according to one of the preceding claims, wherein the second number of contact pads (4b) are formed by a ball grid array which are electrically connected to contact pads on the carrier (6).

13. Integrated component package according to one of the preceding claims, further comprising an optical element (14), in particular a lens, which is arranged on the first semiconductor chip (2a) downstream of the laser package (5) in the light emission direction of the laser package (5).

14. Integrated component package according to one of the preceding claims, further comprising a submount (15) arranged between the laser package (5) and the first semiconductor chip (2a).

15. Integrated component package according to claim 14, wherein the submount (15) is formed by a third semiconductor chip (2c) comprising at least one layer with an integrated circuit (8).

16. Integrated component package according to one of the preceding claims, further comprising at least one heat sink arranged on the first semiconductor chip (2a) and / or the carrier (6) and / or the laser package (5) and / or the submount (15).

17. Integrated component package according to one of the preceding claims, further comprising a heat extraction layer which is arranged between the first semiconductor chip (2a) and the laser package (5) and / or between the first semiconductor chip (2a) and the carrier (6) and / or between layers each having an integrated circuit (8) of the first semiconductor chip (2a).

18. A method for producing an integrated component package (1), in particular an integrated component package according to one of the preceding claims, comprising the steps: Providing a carrier (6), in particular PCB boards; Arranging a first semiconductor chip (2a) with a first main side (3a) and an opposite second main side (3b) on the carrier (6), o wherein a first number of contact surfaces (4a) is formed on the first main side (3a) and is provided for connecting a laser package (5), o wherein a second number of contact surfaces (4b) is formed on the first and / or second main side (3b) and is provided for connecting to the carrier (6), and o wherein the first semiconductor chip (2a) comprises at least one layer with an integrated circuit (8) which is electrically connected to at least parts of the first number of contact surfaces (4a) and is electrically connected to at least parts of the second number of contact surfaces (4b) for supplying power to the first semiconductor chip; Arranging a hermetically encapsulated laser package (5) on the first semiconductor chip (2a) such that the laser package (5) is electrically connected to at least two of the first number of contact surfaces (4a); and Arranging a plurality of first passive electrical components (7a) on the first main side (3a) and / or on the carrier (6) such that they are each electrically connected to the first semiconductor chip (2a) and / or the carrier (6).

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