Schottky barrier diode, ldmosfet integrated with schottky barrier diode, and manufacturing method therefor

Abstract

The present application relates to a Schottky barrier diode, comprising: a well region having a first conductivity type; a body region (124) provided at the upper portion of the well region and having a second conductivity type, the body region (124) being penetrated by a trench (131), and the bottom of the trench (131) extending into the well region; and a first cobalt silicide layer (142), which is formed on the bottom surface and the inner wall of the trench (131), the first cobalt silicide layer (142) forming a Schottky contact with the well region. The well region serves as a cathode of the Schottky barrier diode, and the first cobalt silicide layer (142) which is in direct contact with the well region serves as an anode of the Schottky barrier diode, the first conductive type and the second conductive type being opposite conductive types. The present application uses the bottom surface and the inner wall of the trench to form a Schottky contact of a U-shaped structure between the first cobalt silicide layer and the well region, so that a relatively large Schottky contact area can be obtained by means of a relatively small planar area. In addition, since the Schottky contact is formed by the cobalt silicide, the overcurrent capacity thereof is high.

Description

Schottky diode, LDMOSFET integrated with Schottky diode and manufacturing method thereof

[0001] This application claims priority to Chinese patent application number 2023107156486, filed with the Patent Office of China on June 15, 2023, entitled “Schottky diode, LDMOSFET with integrated Schottky diode and manufacturing method thereof,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of semiconductor manufacturing, and in particular to a Schottky barrier diode, an LDMOSFET (lateral double diffused metal oxide semiconductor field effect transistor) with an integrated Schottky diode, and a method for manufacturing an LDMOSFET with an integrated Schottky diode. Background Art

[0003] Figure 1 is a schematic diagram of an exemplary LDMOSFET circuit. A parasitic diode is formed between the source and drain of the LDMOS. An exemplary NLDMOS can form a diode using the drain region, drift region, and P-body region. However, the forward voltage drop of this diode is typically around 0.7V, limiting further reductions in the forward voltage drop and conduction losses.

[0004] As shown in Figure 2, lower conduction losses can be achieved by integrating a Schottky diode within the LDMOS. An exemplary Schottky diode structure utilizes a planar metal-semiconductor interface (MSI). The MSI (the interface between the metal or metal silicide and the N-type semiconductor material) is surrounded by a P-ring, which is extended at an appropriate distance to form the Schottky diode. This occupies a relatively large planar area.

[0005] Summary of the Invention

[0006] Based on this, it is necessary to provide a Schottky diode with a smaller planar area.

[0007] A Schottky diode comprises: a well region having a first conductivity type; a body region disposed above the well region and having a second conductivity type; the body region being penetrated by a trench, the bottom of the trench extending into the well region; a first cobalt silicide layer formed on the bottom surface and inner wall of the trench, the first cobalt silicide layer forming a Schottky contact with the well region; wherein the well region serves as the cathode of the Schottky diode, and the first cobalt silicide layer in direct contact with the well region serves as the anode of the Schottky diode, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0008] The above-mentioned Schottky diode utilizes the bottom surface and inner wall of the trench to form a Schottky contact with the first cobalt silicide layer and the well region with a U-shaped cross-section. A larger Schottky contact area can be obtained with a smaller planar area, and because the Schottky contact is formed by cobalt silicide, it has a stronger overcurrent capability.

[0009] In one embodiment, the Schottky diode further includes a first doped region located in the body region, the first doped region has a first conductivity type, and a portion of the first cobalt silicide layer is located on a surface of the first doped region.

[0010] In one embodiment, a side surface of the first doped region is disposed close to the top of the trench.

[0011] In one embodiment, the Schottky diode further includes: a second doped region directly contacting the well region and having the first conductivity type.

[0012] In one embodiment, the Schottky diode further includes: a field region insulating layer located between the body region and the second doped region.

[0013] In one embodiment, the Schottky diode further includes: a substrate, and the well region is located in the substrate.

[0014] In one embodiment, the Schottky diode further includes: a second cobalt silicide layer located on the surface of the second doped region, and the cathode of the Schottky diode is led out through the second cobalt silicide layer.

[0015] In one embodiment, the Schottky diode further includes a metal titanium bonding layer located on an upper surface of the first cobalt silicide layer, and a titanium nitride layer located on an upper surface of the metal titanium bonding layer.

[0016] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0017] It is also necessary to provide an LDMOSFET with an integrated Schottky diode.

[0018] An LDMOSFET with an integrated Schottky diode comprises: a substrate; a drift region, disposed in the substrate and having a first conductivity type; a body region, disposed in the drift region and having a second conductivity type; the body region being penetrated by a trench, the bottom of the trench extending into the drift region; a first cobalt silicide layer, formed on the bottom surface and inner wall of the trench, the first cobalt silicide layer forming a Schottky contact with the drift region; a source region, disposed in the body region, the source region having the first conductivity type, a portion of the first cobalt silicide layer being disposed on the surface of the source region; and a drain region, directly contacting the drift region and having the first conductivity type; wherein the drift region serves as the cathode of the Schottky diode, the first cobalt silicide layer, which is in direct contact with the drift region, serves as the anode of the Schottky diode, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0019] The LDMOSFET with an integrated Schottky diode utilizes the bottom and inner walls of the trench to form a U-shaped Schottky contact between the first cobalt silicide layer and the drift region. This achieves a large Schottky contact area with a small planar surface. Furthermore, because the Schottky contact is formed from cobalt silicide, it offers strong overcurrent capability. This Schottky diode structure is suitable for low-side, high-side, and fully isolated LDMOSFETs, thus offering broad applicability.

[0020] In one embodiment, a side surface of the first doped region is disposed close to the top of the trench.

[0021] In one embodiment, the LDMOSFET further includes: a field region insulating layer located between the body region and the drain region.

[0022] In one embodiment, the LDMOSFET further includes a gate, one side of which is close to the source region and the other side of which is close to the drain region, and a portion of the gate is located on the field region insulating layer.

[0023] In one embodiment, the LDMOSFET further includes a second cobalt silicide layer located on a surface of the drain region, and the cathode of the Schottky diode is led out through the second cobalt silicide layer.

[0024] In one embodiment, the LDMOSFET with an integrated Schottky diode is an LDMOS with a fully isolated structure, and the LDMOS with a fully isolated structure also includes: a second conductive type well region, the drift region is located in the second conductive type well region; a buried region, located below the second conductive type well region and between the second conductive type well region and the substrate, the buried region has a first conductive type; an isolation region, located outside the second conductive type well region, part of the substrate is located on the side of the isolation region away from the second conductive type well region, and the bottom of the isolation region is in direct contact with the buried region.

[0025] In one embodiment, the LDMOSFET further includes a metal titanium bonding layer located on an upper surface of the first cobalt silicide layer, and a titanium nitride layer located on an upper surface of the metal titanium bonding layer.

[0026] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0027] It is also necessary to provide a method for manufacturing an LDMOSFET with an integrated Schottky diode.

[0028] A method for manufacturing an LDMOSFET with an integrated Schottky diode, comprising: obtaining a substrate; forming a drift region in the substrate, a body region in the drift region, the drift region having a first conductivity type, the body region having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; forming a source region and a drain region; the source region being formed in the body region, the drain region being in direct contact with the drift region, the source region and the drain region having the first conductivity type; forming a trench penetrating the body region, the bottom of the trench extending into the drift region; forming a metal silicide layer by a self-aligned metal silicide process, the metal silicide layer comprising a first cobalt silicide layer formed on the bottom surface and inner wall of the trench, and a second cobalt silicide layer formed on the surface of the drain region, the first cobalt silicide layer forming a Schottky contact with the drift region; wherein the drift region serves as the cathode of the Schottky diode, and the first cobalt silicide layer in direct contact with the drift region serves as the anode of the Schottky diode.

[0029] The above-described method for manufacturing an LDMOSFET with an integrated Schottky diode utilizes the bottom and inner walls of the trench to form a Schottky contact with the drift region, with a U-shaped cross-section. This achieves a large Schottky contact area with a small planar surface. Furthermore, because the Schottky contact is formed using the cobalt silicide layer using a self-aligned metal silicide (salicide) process, it exhibits strong overcurrent capability. This Schottky diode structure is suitable for low-side, high-side, and fully isolated LDMOSFETs, thus possessing broad applicability.

[0030] In one embodiment, before the step of forming the source region and the drain region, the step further includes: forming a field region insulating layer between the body region and the drain region.

[0031] In one embodiment, before the step of forming the source region and the drain region, the step further includes: forming a gate, one side of the gate is close to the source region and the other side is close to the drain region, and a portion of the gate is formed on the field region insulating layer.

[0032] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0033] In one embodiment, after the step of forming the metal silicide layer by the self-aligned metal silicide process, the method further includes the step of forming a metal titanium adhesion layer and a titanium nitride layer on the first cobalt silicide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0035] FIG1 is a schematic circuit diagram of an exemplary LDMOSFET;

[0036] FIG2 is a circuit diagram of an LDMOSFET integrated with a Schottky diode;

[0037] FIG3 is a schematic cross-sectional view of an LDMOSFET with an integrated Schottky diode according to an embodiment of the present application;

[0038] FIG4 is a schematic structural diagram of a fully isolated LDMOSFET with an integrated Schottky diode in one embodiment of the present application;

[0039] FIG5 is a flow chart of a method for manufacturing an LDMOSFET with an integrated Schottky diode according to an embodiment of the present application;

[0040] 6a to 6c are schematic cross-sectional views of a device during the process of manufacturing an LDMOS using the method shown in FIG5 . DETAILED DESCRIPTION

[0041] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0043] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. In this specification, "connection" should be understood as "electrically connected," "communicationally connected," or the like, if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0044] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is turned over, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" can include both the above and below orientations. The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0045] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an" and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" means one or more, and "a plurality" means two or more. "At least a portion of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the present application.

[0047] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0048] FIG3 is a schematic cross-sectional view of an LDMOSFET with an integrated Schottky diode in one embodiment of the present application. Note that the structure shown in FIG3 is bilaterally symmetrical, so only one of the structures is labeled, while the other symmetrical structure is not labeled. The integrated Schottky diode in the embodiment shown in FIG3 includes a well region, a body region 124, and a first cobalt silicide layer 142. The well region is the drift region 122 of the LDMOSFET. The drift region 122 has a first conductivity type. The body region 124 is disposed in the drift region 122 and has a second conductivity type. The body region 124 is penetrated by a trench 131, the bottom of which extends into the drift region 122. The first cobalt silicide layer 142 is formed on the bottom surface and inner wall of the trench 131, forming a Schottky contact with the drift region 122. The drift region 122 serves as the cathode of the Schottky diode, and the first cobalt silicide layer 142, which is in direct contact with the drift region 122, serves as the anode of the Schottky diode. In the embodiment shown in FIG3 , the LDMOSFET is an NLDMOS, wherein the first conductivity type is N-type and the second conductivity type is P-type. Accordingly, the substrate 110 is a P-type substrate (P-Sub), the drift region 122 is an N-type drift region (N-Drift), and the body region 124 is a P-type body region (P-Body).

[0049] The Schottky diode utilizes the bottom surface and inner walls of the trench 131 to form a Schottky contact with the drift region 122, with a U-shaped cross-section. This achieves a large Schottky contact area with a small planar surface, thereby providing a strong current handling capability. Furthermore, since the Schottky contact is formed of cobalt silicide, it also contributes to a strong current handling capability.

[0050] In the embodiment shown in FIG3 , the LDMOSFET further includes a substrate 110, a source region 132 (a first doped region), and a drain region 134 (a second doped region). The drift region 122 is located in the substrate 110. In the embodiment shown in FIG3 , the substrate 110 has the second conductivity type. The source region 132 is located in the body region 124 and has the first conductivity type. A portion of the first cobalt silicide layer 142 is located on the surface of the source region 132. In the embodiment shown in FIG3 , one side of the source region 132 is positioned near the top of the trench 131. The drain region 134 is in direct contact with the drift region 122 and has the first conductivity type. The doping concentration of the drain region 134 is greater than that of the drift region 122. That is, the source region 132 and the drain region 134 are N+ regions. The structure shown in FIG3 is applicable to low-side, high-side, and fully isolated NLDMOSFETs in half-bridge circuits, and therefore has a wide range of applicability. The source, bulk, and substrate of the low-side NLDMOSFET in the half-bridge circuit have the same potential; the bulk and substrate of the high-side NLDMOSFET in the half-bridge circuit have different potentials; and the bulk and substrate of the fully isolated structure also have different potentials.

[0051] In the embodiment shown in FIG3 , the LDMOSFET further includes a field insulating layer 150 and a gate 136. One side of the gate 136 is adjacent to the source region 132, and the other side is adjacent to the drain region 134. A portion of the gate 136 is located on the field insulating layer 150. In one embodiment of the present application, the field insulating layer 150 is a field oxide layer made of silicon oxide, such as silicon dioxide. In one embodiment of the present application, the gate 136 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material for the gate 136.

[0052] In the embodiment shown in FIG3 , the Schottky diode further includes a second cobalt silicide layer 144 located on the surface of the drain region 134. The cathode of the Schottky diode is led out through the second cobalt silicide layer 144. The second cobalt silicide layer 144 can reduce the contact resistance of the drain region 134.

[0053] In one embodiment of the present application, the Schottky diode further includes a metal titanium bonding layer located on the upper surface of the first cobalt silicide layer 142 , and a titanium nitride layer located on the upper surface of the metal titanium bonding layer.

[0054] The U-shaped cross-section allows for a larger Schottky contact area, significantly reducing the conduction voltage drop of the Schottky diode. In one embodiment of the present application, the conduction voltage drop of the Schottky diode can be reduced to approximately 0.3V, thereby reducing the conduction voltage drop and conduction losses of the body diode between the source region 132 and the drain region 134.

[0055] FIG4 is a schematic diagram of the structure of a fully isolated LDMOSFET with an integrated Schottky diode in one embodiment of the present application. Based on the embodiment shown in FIG3 , the LDMOSFET further includes a second conductivity type well region 126, a buried region 128, and an isolation region 129. The drift region 122 is located in the second conductivity type well region 126. The buried region 128 is located below the second conductivity type well region 126 and between the second conductivity type well region 126 and the substrate 110. In the embodiment shown in FIG4 , the buried region 128 is a first conductivity type buried layer. The isolation region 129 is located outside the second conductivity type well region 126, with a portion of the substrate 110 located outside the isolation region 129 (i.e., on the side facing away from the second conductivity type well region 126). The bottom of the isolation region 129 is in direct contact with the buried region 128. In one embodiment of the present application, the isolation region 129 is a doped region of the first conductivity type. The fully isolated LDMOSFET isolates the second conductive type well region 126 from the substrate 110 , so that the second conductive type well region 126 and the substrate 110 have different potentials.

[0056] The present application accordingly provides a method for manufacturing an LDMOSFET with an integrated Schottky diode, which can be used to manufacture an LDMOSFET with an integrated Schottky diode as described in any of the aforementioned embodiments. FIG5 is a flow chart of the method for manufacturing an LDMOSFET with an integrated Schottky diode in one embodiment of the present application, comprising the following steps:

[0057] S210 , obtaining a substrate having a drift region and a body region formed thereon.

[0058] 6a, a drift region 122 is formed in a substrate 110, and a body region 124 is formed in the drift region 122. The drift region 122 has a first conductivity type, and the body region 124 has a second conductivity type. In the embodiment shown in FIG6a, the fabricated LDMOSFET is an NLDMOS, where the first conductivity type is N-type and the second conductivity type is P-type.

[0059] In one embodiment of the present application, substrate 110 is a semiconductor substrate. The substrate 110 may be made of undoped single crystal silicon, doped single crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). It may also be made of at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In the embodiment shown in FIG6 a , substrate 110 is made of single crystal silicon.

[0060] In one embodiment of the present application, a suitable method may be used to form the drift region 122, such as a doping process. Doping is generally achieved by ion implantation. If an N-type drift region 122 is prepared, N-type ion doping is performed on the region of the substrate 110 where the drift region 122 is to be formed, such as ion implantation after photolithography, to form an N-type drift region 122 in the substrate 110. Similarly, a suitable method may be used to form the body region 124, such as a doping process. If a P-type body region 124 is prepared, P-type ion doping is performed on the region of the drift region 122 where the body region 124 is to be formed, such as ion implantation after photolithography, to form a P-type body region 124 in the substrate 110.

[0061] S220 , forming a source region and a drain region.

[0062] The source region 132 is formed in the body region 124, and the drain region 134 is in direct contact with the drift region 122. The source region 132 and the drain region 134 have the first conductivity type.

[0063] In one embodiment of the present application, after step S210 and before step S220, the process further includes forming a field insulating layer 150 and a gate 136, as shown in FIG6b . In one embodiment of the present application, the field insulating layer 150 is a field oxide layer made of silicon oxide, such as silicon dioxide. The field insulating layer 150 can be formed using a process known to those skilled in the art, such as a thermal oxidation process.

[0064] In one embodiment of the present application, the gate 136 is made of polysilicon; in other embodiments, metal, metal nitride, metal silicide, or similar compounds may be used as the gate material. In one embodiment of the present application, the gate 136 may be formed by chemical vapor deposition (CVD), such as low-temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), or by methods such as sputtering and physical vapor deposition (PVD). The thickness of the gate 136 may be an appropriate thickness based on the size of the device, and is not specifically limited here.

[0065] In one embodiment of the present application, a method for forming the source region 132 and the drain region 134 includes performing source-drain ion implantation in regions of the semiconductor substrate where the source and drain regions are to be formed. Specifically, a photolithography process can be used to first form a patterned photoresist layer that exposes the regions where the source and drain regions 132 and 134 are to be formed. The source-drain ion implantation is then performed using the patterned photoresist layer as a mask. Finally, the patterned photoresist layer is removed by, for example, ashing.

[0066] Subsequently, an annealing process may be performed. For example, the annealing process may utilize any annealing method known to those skilled in the art, including but not limited to rapid thermal annealing, furnace annealing, spike annealing, laser annealing, and the like. For example, a rapid temperature ramp annealing process may be performed, utilizing a high temperature of 900 to 1050° C. to activate the dopants in the source region 132 and the drain region 134 and simultaneously repair the lattice structure of the semiconductor substrate surface damaged during the ion implantation process. Furthermore, depending on product requirements and functional considerations, a lightly doped drain (LDD) may be formed between the source region 132, the drain region 134, and the gate 136.

[0067] S230 , forming a trench penetrating the body region.

[0068] Referring to FIG6c, the bottom of the trench 131 extends into the drift region 122. The trench 131 can be formed by photolithography and etching processes. In one embodiment of the present application, in order to maximize the gold semi-interface (the contact surface between the metal or metal silicide and the N-type semiconductor material) of the subsequently formed Schottky diode, the bottom of the trench 131 should be as close as possible to the bottom of the drift region 122, but must be spaced apart from the substrate 110 below the drift region 122. The larger the gold semi-interface area of ​​the Schottky diode, the stronger its ability to reduce the conduction voltage drop and conduction loss of the body diode between the source / drain.

[0069] In the embodiment shown in FIG. 6 c , the top of the trench 131 is located at the edge of the source region 132 .

[0070] S240 , forming a metal silicide layer through a self-aligned metal silicide (salicide) process.

[0071] The device structure after step S240 is completed can be seen in Figure 3. The metal silicide layer includes a first cobalt silicide layer 142 formed on the bottom surface and inner wall of the trench 131, and a second cobalt silicide layer 144 formed on the surface of the drain region 134. The first cobalt silicide layer 142 forms a Schottky contact with the well region. The drift region 122 serves as the cathode of the Schottky diode, and the first cobalt silicide layer 142 in contact with the drift region 122 serves as the anode of the Schottky diode.

[0072] Self-aligned silicide (salicide) is a simple and convenient contact metallization process. During semiconductor device fabrication, some areas require salicide, while others require non-salicide. For devices requiring non-salicide, the properties of salicide are utilized to cover the non-salicide areas with a material that does not react with metal. This material used to cover non-salicide devices is called a self-aligned silicide barrier (SAB).

[0073] Step S240 can form the first cobalt silicide layer 142 using the salicide process of the device's corresponding linewidth, such as the salicide process used in a standard 0.18-micron BCD (Bipolar-CMOS-DMOS) process. The Schottky contact utilizes a standard salicide process to chemically react cobalt with silicon to form cobalt silicide, a simple and easy process with high process compatibility. Referring to Figure 3 , a portion of the first cobalt silicide layer 142 formed in step S240 is formed on the surface of the source region 132.

[0074] The above-described method for manufacturing an LDMOSFET with an integrated Schottky diode utilizes the bottom surface and inner walls of the trench 131 to form a Schottky contact with the first cobalt silicide layer 132 and the drift region 122, with a U-shaped cross-section. This achieves a large Schottky contact area with a small planar surface area. Furthermore, because the Schottky contact is formed using a cobalt silicide layer using a self-aligned metal silicide (salicide) process, it exhibits strong overcurrent capability. This Schottky diode structure is suitable for low-side, high-side, and fully isolated LDMOSFETs, thus possessing broad applicability.

[0075] In one embodiment of the present application, after step S240 , a step of forming a metal titanium adhesion layer and a titanium nitride layer on the first cobalt silicide layer 142 to form an ohmic contact is further included.

[0076] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0077] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0078] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A Schottky diode, comprising: a well region having a first conductivity type; a body region, disposed on an upper portion of the well region and having a second conductivity type; The body region is penetrated by a trench, and the bottom of the trench extends into the well region; A first cobalt silicide layer is formed on the bottom surface and inner wall of the trench, and the first cobalt silicide layer forms a Schottky contact with the well region; The well region serves as the cathode of the Schottky diode, the first cobalt silicide layer directly in contact with the well region serves as the anode of the Schottky diode, and the first conductivity type and the second conductivity type are opposite conductivity types. 2 . The Schottky diode according to claim 1 , further comprising a first doped region located in the body region, the first doped region having a first conductivity type, and a portion of the first cobalt silicide layer is located on a surface of the first doped region.

3. The Schottky diode according to claim 2, wherein: A side surface of the first doping region is disposed close to the top of the trench.

4. The Schottky diode according to claim 1, further comprising: The second doped region is in direct contact with the well region and has a first conductivity type.

5. The Schottky diode according to claim 4, further comprising: The field region insulating layer is located between the body region and the second doped region.

6. The Schottky diode according to claim 3, further comprising: A substrate, wherein the well region is located in the substrate.

7. The Schottky diode according to claim 3, further comprising: A second cobalt silicide layer is located on the surface of the second doped region, and a cathode of the Schottky diode is led out through the second cobalt silicide layer.

8. The Schottky diode according to claim 1, further comprising: A metal titanium bonding layer, located on the upper surface of the first cobalt silicide layer; The titanium nitride layer is located on the upper surface of the metal titanium bonding layer.

9. The Schottky diode according to claim 1, wherein: The first conductivity type is N type, and the second conductivity type is P type.

10. An LDMOSFET with an integrated Schottky diode, comprising: substrate; A drift region, disposed in the substrate and having a first conductivity type; a body region, disposed in the drift region and having a second conductivity type; The body region is penetrated by a trench, and the bottom of the trench extends into the drift region; A first cobalt silicide layer is formed on the bottom surface and inner wall of the trench, wherein the first cobalt silicide layer forms a Schottky contact with the drift region; A source region, located in the body region, the source region has a first conductivity type, and a portion of the first cobalt silicide layer is located on a surface of the source region; a drain region, directly contacting the drift region and having a first conductivity type; The drift region serves as a cathode of the Schottky diode, the first cobalt silicide layer directly in contact with the drift region serves as an anode of the Schottky diode, and the first conductivity type and the second conductivity type are opposite conductivity types.

11. The LDMOSFET with integrated Schottky diode according to claim 10, further comprising: A field region insulating layer, located between the body region and the drain region; A gate has one side close to the source region and the other side close to the drain region, and a portion of the gate is located on the field region insulating layer. 12 . The LDMOSFET with integrated Schottky diode according to claim 10 , further comprising a second cobalt silicide layer located on the surface of the drain region, wherein a cathode of the Schottky diode is led out through the second cobalt silicide layer.

13. The LDMOSFET with integrated Schottky diode according to claim 10, wherein: The LDMOSFET with integrated Schottky diode is a LDMOS with full isolation structure, and the LDMOS with full isolation structure further includes: A second conductive type well region, wherein the drift region is located in the second conductive type well region; a buried region, located below the second conductivity type well region and between the second conductivity type well region and the substrate, the buried region having a first conductivity type; The isolation region is located outside the second conductive type well region, and a portion of the substrate is located away from the isolation region. On one side of the second conductivity type well region, the bottom of the isolation region is in direct contact with the buried region.

14. A method for manufacturing an LDMOSFET with an integrated Schottky diode, comprising: obtaining a substrate; A drift region is formed in the substrate, a body region is formed in the drift region, the drift region has a first conductivity type, the body region has a second conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types; forming a source region and a drain region; the source region is formed in the body region, the drain region is in direct contact with the drift region, and the source region and the drain region have a first conductivity type; forming a trench penetrating the body region, wherein the bottom of the trench extends into the drift region; Forming a metal silicide layer by a self-aligned metal silicide process, the metal silicide layer comprising a first cobalt silicide layer formed on the bottom surface and inner wall of the trench, and a second cobalt silicide layer formed on the surface of the drain region, the first cobalt silicide layer forming a Schottky contact with the drift region; The drift region serves as a cathode of the Schottky diode, and the first cobalt silicide layer directly in contact with the drift region serves as an anode of the Schottky diode.

15. The method for manufacturing the LDMOSFET with integrated Schottky diode according to claim 14, further comprising: Before forming the source region and the drain region, forming a field region insulating layer between the body region and the drain region; A gate is formed, one side of the gate is close to the source region and the other side of the gate is close to the drain region, and a portion of the gate is formed on the field region insulating layer.

Images