Capacitor, isolation transformer, and semiconductor device

Abstract

The present invention relates to a capacitor, an isolation transformer, and a semiconductor device. The isolation transformer comprises: a first dielectric layer of a lower coil, wherein the first dielectric layer covers the lower coil and has a dielectric constant greater than that of silicon dioxide; a main dielectric layer located on the first dielectric layer; a second dielectric layer located on the main dielectric layer, wherein the second dielectric layer has a dielectric constant greater than that of silicon dioxide; an upper coil located on the second dielectric layer; and a third dielectric layer covering the upper coil, wherein the third dielectric layer has a dielectric constant greater than that of silicon dioxide.

Description

Capacitors, isolation transformers and semiconductor devices

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application number 2023107059382, filed on June 14, 2023, entitled “Capacitor Structure, Isolation Transformer and Semiconductor Device,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present invention relates to the field of semiconductor manufacturing, in particular to a capacitor, an isolation transformer, and a semiconductor device. Background Art

[0004] In traditional semiconductor integration processes, isolation transformers typically use silicon dioxide as the insulating dielectric between their upper and lower coils. Increasing the thickness of the silicon dioxide can improve the withstand voltage of the upper and lower coils. However, when etching the metal of the upper coil, numerous defects are created on the surface of the etched material. This can cause dielectric breakdown to occur preferentially in the high-electric-field region of the upper coil, thus compromising the withstand voltage of the entire transformer.

[0005] Summary of the Invention

[0006] According to some embodiments, an isolation transformer having a high voltage withstand capability is provided.

[0007] An isolation transformer includes: a first dielectric layer of a lower coil, covering the lower coil, the dielectric constant of the first dielectric layer being greater than that of silicon dioxide; a main dielectric layer, located on the first dielectric layer; a second dielectric layer, located on the main dielectric layer, the dielectric constant of the second dielectric layer being greater than that of silicon dioxide; an upper coil, located on the second dielectric layer; and a third dielectric layer, covering the upper coil, the dielectric constant of the third dielectric layer being greater than that of silicon dioxide.

[0008] The isolation transformer uses a high-dielectric-constant dielectric (the second and third dielectric layers) to cover the upper coil, optimizing the device's electric field (reducing its strength) and thereby improving its withstand voltage. Furthermore, the first dielectric layer covers the lower coil, similarly reducing the electric field strength there and thus improving the device's withstand voltage.

[0009] In one embodiment, the isolation transformer further includes a fourth dielectric layer, the lower coil is located on the fourth dielectric layer, and the dielectric constant of the fourth dielectric layer is greater than the dielectric constant of silicon dioxide.

[0010] In one embodiment, the isolation transformer further includes a buffer layer, the material of the buffer layer includes silicon oxide; the buffer layer includes: a first buffer layer located between the upper coil and the third dielectric layer, and / or a second buffer layer located between the lower coil and the first dielectric layer.

[0011] In one embodiment, the thickness of the second dielectric layer is greater than 300 nanometers.

[0012] In one embodiment, the thickness of the fourth dielectric layer is greater than 300 nanometers.

[0013] In one embodiment, the thickness of the first dielectric layer is greater than 200 nanometers.

[0014] In one embodiment, the thickness of the third dielectric layer is greater than 200 nanometers.

[0015] In one embodiment, the material of the first dielectric layer includes silicon nitride or silicon oxynitride.

[0016] In one embodiment, the material of the first dielectric layer includes silicon nitride or silicon oxynitride.

[0017] In one embodiment, the material of the second dielectric layer includes silicon nitride or silicon oxynitride.

[0018] In one embodiment, the material of the second dielectric layer includes silicon nitride or silicon oxynitride.

[0019] In one embodiment, the material of the third dielectric layer includes silicon nitride or silicon oxynitride.

[0020] In one embodiment, the material of the third dielectric layer includes silicon nitride or silicon oxynitride.

[0021] In one embodiment, the material of the fourth dielectric layer includes silicon nitride or silicon oxynitride.

[0022] In one embodiment, the material of the fourth dielectric layer includes silicon nitride or silicon oxynitride.

[0023] In one embodiment, the main dielectric layer includes a silicon oxide layer.

[0024] In one embodiment, the thicknesses of the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are all smaller than the thickness of the main dielectric layer.

[0025] In one embodiment, the upper coil and the lower coil are both in the shape of a square spiral.

[0026] In one embodiment, the isolation transformer further includes a passivation layer, and the passivation layer covers at least a portion of the upper coil.

[0027] In one embodiment, the upper coil and the lower coil are metal coils or alloy coils.

[0028] In one embodiment, the upper coil and the lower coil are both made of copper and aluminum.

[0029] According to some embodiments, a semiconductor device is provided.

[0030] A semiconductor device comprises the isolation transformer described in any one of the preceding embodiments.

[0031] According to some embodiments, a capacitor is provided.

[0032] A capacitor includes: a lower plate; a first dielectric layer covering the lower plate, the dielectric constant of the first dielectric layer being greater than the dielectric constant of silicon dioxide; a main dielectric layer located on the first dielectric layer; a second dielectric layer located on the main dielectric layer, the dielectric constant of the second dielectric layer being greater than the dielectric constant of silicon dioxide; an upper plate located on the second dielectric layer; and a third dielectric layer covering the upper plate, the dielectric constant of the third dielectric layer being greater than the dielectric constant of silicon dioxide. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0034] FIG1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present application;

[0035] FIG2A is a schematic diagram of an upper coil in an embodiment of the present application;

[0036] FIG2B is a schematic diagram of a lower coil in one embodiment of the present application;

[0037] FIG3 is a schematic cross-sectional view of a semiconductor device in another embodiment of the present application;

[0038] FIG4 is a cross-sectional schematic diagram of a semiconductor device in another embodiment of the present application;

[0039] FIG5 is a cross-sectional diagram of a capacitor in one embodiment of the present application;

[0040] FIG6 is a cross-sectional schematic diagram of a capacitor in another embodiment of the present application;

[0041] FIG7 is a cross-sectional schematic diagram of a capacitor in yet another embodiment of the present application. DETAILED DESCRIPTION

[0042] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. "Connected" in this specification should be understood as "electrically connected," "communicatively connected," etc., if the connected circuits, modules, units, etc. have electrical signals or data transmission with each other. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0045] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the element or feature described as "under" or "under" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an" and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be understood that "at least one" means one or more, and "a plurality" means two or more. "At least a portion of an element" refers to part or all of an element. It will also be understood that the terms "compose" and / or "comprise", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] FIG1 is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present application. An isolation transformer 100 (i.e., the area within the dashed box in FIG1 ) is integrated into the semiconductor device and includes a lower coil 104, a main dielectric layer 105, a first dielectric layer 122, a second dielectric layer 124, a third dielectric layer 126, a fourth dielectric layer 128, and an upper coil 101. Lower coil 104 is located on fourth dielectric layer 128, with first dielectric layer 122 covering lower coil 104. Main dielectric layer 105 is located on first dielectric layer 122, second dielectric layer 124 is located on main dielectric layer 105, upper coil 101 is located on second dielectric layer 124, and third dielectric layer 126 covers upper coil 101. First dielectric layer 122, second dielectric layer 124, third dielectric layer 126, and fourth dielectric layer 128 are all made of a material with a relatively high dielectric constant, such as a material with a dielectric constant greater than that of silicon dioxide. Since the dielectric constant of silicon dioxide is approximately 3.98 at room temperature, the dielectric constants of the materials of the first dielectric layer 122 , the second dielectric layer 124 , the third dielectric layer 126 , and the fourth dielectric layer 128 are all greater than 3.98.

[0048] In the above-mentioned isolation transformer 100, since the second dielectric layer 124 and the third dielectric layer 126 with high dielectric constants are used to cover the upper coil 101, and the fourth dielectric layer 128 and the first dielectric layer 122 with high dielectric constants are used to cover the lower coil 104, the electric field strength is reduced, thereby achieving the purpose of improving the withstand voltage capability of the device and improving the surge resistance of the semiconductor device.

[0049] In one embodiment of the present application, the materials of the first dielectric layer 122 , the second dielectric layer 124 , the third dielectric layer 126 and the fourth dielectric layer 128 all include silicon nitride (eg, silicon nitride) or silicon oxynitride (eg, silicon oxynitride).

[0050] In one embodiment of the present application, the material of the main dielectric layer 105 includes silicon oxide, such as silicon dioxide. In the embodiment shown in Figure 1 , the semiconductor device further includes a low voltage region 106 for arranging a low voltage device (not shown).

[0051] In one embodiment of the present application, the thickness of the first dielectric layer 122 and the third dielectric layer 126 is greater than 200 nanometers, which is particularly suitable for embodiments in which the first dielectric layer 122 and the third dielectric layer 126 are made of silicon nitride or silicon oxynitride.

[0052] In one embodiment of the present application, the thickness of the second dielectric layer 124 and the fourth dielectric layer 128 is greater than 300 nanometers, which is particularly suitable for embodiments in which the second dielectric layer 124 and the fourth dielectric layer 128 are made of silicon nitride or silicon oxynitride.

[0053] In one embodiment of the present application, the thicknesses of the first dielectric layer 122 , the second dielectric layer 124 , the third dielectric layer 126 , and the fourth dielectric layer 128 are all smaller than the thickness of the main dielectric layer 105 .

[0054] Figures 2A and 2B are schematic diagrams of the upper coil 101 and the lower coil 104 in one embodiment of the present application, respectively. In the embodiment shown in Figures 2A and 2B, the upper coil 101 and the lower coil 104 have the same shape. Specifically, the shape of the lower coil 104 is the same as the shape of the orthographic projection of the upper coil 101 on the surface where the lower coil 104 is located, thereby increasing the mutual coupling coefficient of the inductance. In the embodiment shown in Figures 2A and 2B, the upper coil 101 and the lower coil 104 are both square spirals. In other embodiments, the upper coil 101 and the lower coil 104 can also be other conventional inductor coil shapes in the art, such as a circular spiral. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are alloy coils, generally the main material of which is a mixture of Al and Cu. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are made of the same material.

[0055] In one embodiment of the present application, the isolation transformer 100 further includes a passivation layer 102 . The passivation layer 102 covers at least a portion of the upper coil 101 and the third dielectric layer 126 and is used to protect the dielectric layer of the device and circuit.

[0056] In the embodiment shown in Figures 1 and 2A, the isolation transformer 100 further includes a pad portion 107 located on the second dielectric layer 124. The passivation layer 102 has an opening that exposes the pad portion 107. The pad portion 107 is electrically connected to the upper coil 101 for connecting the upper coil 101 to a peripheral circuit.

[0057] In the embodiment shown in FIG. 1 , the semiconductor device further includes a substrate 112 . In one embodiment of the present application, the upper coil 101 and the lower coil 104 serve as the top metal and the intermetallic layer of the semiconductor device, respectively. Substrate 112 is a semiconductor substrate, and its material can be undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). It can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In one embodiment of the present application, substrate 112 is made of single crystal silicon. Devices, such as NMOS and / or PMOS transistors, can be formed on substrate 112 , though these structures are omitted in FIG. 1 . Similarly, conductive members may be formed in (and on) the substrate 112. The conductive members may be gates, sources, or drains of transistors, or metal interconnect structures electrically connected to the transistors, etc. In the embodiment shown in FIG1 , a shallow trench isolation (STI) structure 114 is also formed in the substrate 112.

[0058] In the embodiment shown in FIG1 , the semiconductor device further includes contact holes 115 and multi-layer metal interconnects 116. The contact holes 115 are filled with a conductive material, such as a tungsten plug, which is electrically connected to the corresponding metal interconnects 116 to lead out device structures such as active areas in the substrate 112.

[0059] In one embodiment of the present application, an interlayer dielectric (ILD) layer (not shown) is further provided between the substrate 112 and the fourth dielectric layer 128. The interlayer dielectric may be a silicon oxide layer, such as a doped or undoped silicon oxide layer formed using a thermal chemical vapor deposition (thermal CVD) process or a high-density plasma chemical vapor deposition (HDPCVD) process, and may specifically be undoped silicate glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric may also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetraethoxysilane (BTEOS).

[0060] Referring to FIG3 , in another embodiment of the present application, the inventors have tested and found that even after removing the fourth dielectric layer 128 from the embodiment shown in FIG1 , the isolation transformer 100 still has a high withstand voltage. Specifically, the first dielectric layer 122 covering the lower coil 104 can also reduce the electric field strength at the lower coil 104, thereby improving the device's withstand voltage.

[0061] Referring to FIG. 4 , in one embodiment of the present application, the isolation transformer 100 further includes a buffer layer. The buffer layer is made of a silicon oxide, such as silicon dioxide. The buffer layer includes a first buffer layer 132 positioned between the upper coil 101 and the third dielectric layer 126, and / or a second buffer layer 134 positioned between the lower coil 104 and the first dielectric layer 122. The first buffer layer 132 serves as a buffer layer between the third dielectric layer 126 and the upper coil 101 during deposition, thereby reducing defects generated during the deposition of the third dielectric layer 126. Similarly, the second buffer layer 134 serves as a buffer layer between the first dielectric layer 122 and the lower coil 104 during deposition, thereby reducing defects generated during the deposition of the first dielectric layer 122.

[0062] The present application accordingly provides a semiconductor device, which includes a transformer area and a low-voltage area 106 . Low-voltage devices are provided in the low-voltage area 106 . The transformer area includes the isolation transformer 100 described in any of the aforementioned embodiments.

[0063] Based on a general inventive concept, the present application also provides a capacitor with a high withstand voltage capability. Figure 5 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present application. The capacitor 200 (i.e., the area framed by the dotted line in Figure 5) is integrated into the semiconductor device and includes a lower plate 204, a main dielectric layer 205, a first dielectric layer 222, a second dielectric layer 224, a third dielectric layer 226, a fourth dielectric layer 228, and an upper plate 201. The lower plate 204 is located on the fourth dielectric layer 228, the first dielectric layer 222 covers the lower plate 204, the main dielectric layer 205 is located on the first dielectric layer 222, the second dielectric layer 224 is located on the main dielectric layer 205, the upper plate 201 is located on the second dielectric layer 224, and the third dielectric layer 226 covers the upper plate 201. The first dielectric layer 222, the second dielectric layer 224, the third dielectric layer 226, and the fourth dielectric layer 228 are all made of a material with a relatively high dielectric constant, such as a material with a dielectric constant greater than that of silicon dioxide. Since the dielectric constant of silicon dioxide is approximately 3.98 at room temperature, the dielectric constants of the materials of the first dielectric layer 222 , the second dielectric layer 224 , the third dielectric layer 226 , and the fourth dielectric layer 228 are all greater than 3.98.

[0064] In the above-mentioned capacitor 200, since the second dielectric layer 224 and the third dielectric layer 226 with high dielectric constants are used to cover the upper plate 201, and the fourth dielectric layer 228 and the first dielectric layer 222 with high dielectric constants are used to cover the lower plate 204, the electric field strength is reduced, thereby achieving the purpose of improving the withstand voltage of the device and improving the surge resistance of the semiconductor device.

[0065] In one embodiment of the present application, the materials of the first dielectric layer 222 , the second dielectric layer 224 , the third dielectric layer 226 and the fourth dielectric layer 228 all include silicon nitride (eg, silicon nitride) or silicon oxynitride (eg, silicon oxynitride).

[0066] In one embodiment of the present application, the main dielectric layer 205 comprises a silicon oxide layer. The material of the main dielectric layer 205 comprises silicon oxide, such as silicon dioxide. In the embodiment shown in FIG5 , the semiconductor device further comprises a low-voltage region 206 for arranging a low-voltage device (not shown).

[0067] In one embodiment of the present application, the thickness of the first dielectric layer 222 and the third dielectric layer 226 is greater than 200 nanometers, which is particularly suitable for embodiments in which the first dielectric layer 222 and the third dielectric layer 226 are made of silicon nitride or silicon oxynitride.

[0068] In one embodiment of the present application, the thickness of the second dielectric layer 224 and the fourth dielectric layer 228 is greater than 300 nanometers, which is particularly suitable for embodiments in which the second dielectric layer 224 and the fourth dielectric layer 228 are made of silicon nitride or silicon oxynitride.

[0069] In one embodiment of the present application, the thicknesses of the first dielectric layer 222 , the second dielectric layer 224 , the third dielectric layer 226 , and the fourth dielectric layer 228 are all smaller than the thickness of the main dielectric layer 205 .

[0070] In one embodiment of the present application, the shape of the upper plate 201 and the lower plate 204 can be a chamfered rectangle, an ellipse, a circle, or other conventional capacitor plate shapes in the art. The shape of the upper plate 201 and the lower plate 204 can be the same. In one embodiment of the present application, the upper plate 201 and the lower plate 204 are alloy plates, generally the main material of which is a mixture of Al and Cu. In one embodiment of the present application, the material of the upper plate 201 and the lower plate 204 is the same.

[0071] In one embodiment of the present application, capacitor 200 further includes a passivation layer 202, which covers at least a portion of top plate 201 and third dielectric layer 226 and is used to protect the dielectric layer of the device and circuit. In the embodiment shown in FIG5 , passivation layer 202 has an opening that partially exposes top plate 201, allowing top plate 201 to be connected to peripheral circuitry through the exposed portion.

[0072] In the embodiment shown in FIG5 , the semiconductor device further includes a substrate 212 . In one embodiment of the present application, the upper plate 201 and the lower plate 204 are the top metal and the intermetallic metal of the device, respectively. The substrate 212 is a semiconductor substrate, and its material can be undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. It can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In one embodiment of the present application, the constituent material of the substrate 212 is single crystal silicon. Devices, such as NMOS and / or PMOS transistors, can be formed on the substrate 212 , but these structures are omitted in FIG5 . Similarly, conductive members may be formed in (and on) the substrate 212 , and the conductive members may be gates, sources, or drains of transistors, or metal interconnect structures electrically connected to the transistors, etc. In the embodiment shown in FIG5 , a shallow trench isolation (STI) structure 214 is also formed in the substrate 212 .

[0073] 5 , the semiconductor device further includes contact holes 215 and multi-layer metal interconnects 216. The contact holes 215 are filled with a conductive material, such as a tungsten plug, which is electrically connected to the corresponding metal interconnects 216 to lead out device structures such as active areas in the substrate 212.

[0074] In one embodiment of the present application, an interlayer dielectric (ILD) layer (not shown) is further provided between the substrate 112 and the fourth dielectric layer 228. The interlayer dielectric may be a silicon oxide layer, for example, a doped or undoped silicon oxide layer formed using a thermal chemical vapor deposition (thermal CVD) process or a high-density plasma chemical vapor deposition (HDPCVD) process, and may specifically be undoped silicate glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric may also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetraethoxysilane (BTEOS).

[0075] Referring to FIG6 , in another embodiment of the present application, the inventors have tested and found that even after removing the fourth dielectric layer 228 in the embodiment shown in FIG5 , the capacitor 200 still has a high withstand voltage. That is, the first dielectric layer 222 covering the lower plate 204 can also reduce the electric field strength at the lower plate 204, thereby improving the device's withstand voltage.

[0076] Referring to FIG. 7 , in one embodiment of the present application, the capacitor 200 further includes a buffer layer, the material of which includes silicon oxide, such as silicon dioxide. The buffer layer includes: a first buffer layer 232 located between the upper plate 201 and the third dielectric layer 226, and / or a second buffer layer 234 located between the lower plate 204 and the first dielectric layer 222. The first buffer layer 232 serves as a buffer layer between the third dielectric layer 226 and the upper plate 201 during deposition, thereby reducing defects generated during deposition of the third dielectric layer 226. Similarly, the second buffer layer 234 serves as a buffer layer between the first dielectric layer 222 and the lower plate 204 during deposition, thereby reducing defects generated during deposition of the first dielectric layer 222.

[0077] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0078] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. An isolation transformer, comprising: Lower coil; A first dielectric layer, covering the lower coil, wherein the dielectric constant of the first dielectric layer is greater than the dielectric constant of silicon dioxide; A main dielectric layer, located on the first dielectric layer; A second dielectric layer, located on the main dielectric layer, wherein the dielectric constant of the second dielectric layer is greater than the dielectric constant of silicon dioxide; an upper coil, located on the second dielectric layer; and A third dielectric layer covers the upper coil, and the dielectric constant of the third dielectric layer is greater than the dielectric constant of silicon dioxide.

2. The isolation transformer according to claim 1, characterized in that: It also includes a fourth dielectric layer, the lower coil is located on the fourth dielectric layer, and the dielectric constant of the fourth dielectric layer is greater than the dielectric constant of silicon dioxide.

3. The isolation transformer according to claim 1, characterized in that: It also includes a first buffer layer located between the upper coil and the third dielectric layer, and / or a second buffer layer located between the lower coil and the first dielectric layer.

4. The isolation transformer according to claim 3, characterized in that: The material of the buffer layer includes silicon oxide.

5. The isolation transformer according to claim 1, characterized in that: The thickness of the second dielectric layer is greater than 300 nanometers.

6. The isolation transformer according to claim 1, characterized in that: The thickness of the first dielectric layer and the third dielectric layer is greater than 200 nanometers.

7. The isolation transformer according to claim 1, characterized in that: The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer all include silicon nitride or silicon nitride oxide.

8. The isolation transformer according to claim 7, characterized in that: The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer all include silicon nitride or silicon nitride oxide.

9. The isolation transformer according to claim 1, characterized in that: The material of the main dielectric layer includes silicon oxide.

10. The isolation transformer according to claim 1, characterized in that: The thickness of the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are all smaller than the thickness of the main dielectric layer.

11. The isolation transformer according to claim 1, characterized in that: The upper coil and the lower coil are both in a square spiral shape.

12. The isolation transformer according to claim 1, characterized in that: A passivation layer is also included, and the passivation layer covers at least a portion of the upper coil.

13. A semiconductor device, comprising the isolation transformer according to any one of claims 1 to 12.

14. A capacitor, comprising: Lower plate; A first dielectric layer, covering the lower electrode plate, wherein the dielectric constant of the first dielectric layer is greater than the dielectric constant of silicon dioxide; A main dielectric layer, located on the first dielectric layer; A second dielectric layer, located on the main dielectric layer, wherein the dielectric constant of the second dielectric layer is greater than the dielectric constant of silicon dioxide; An upper plate, located on the second dielectric layer; and A third dielectric layer covers the upper electrode plate, and the dielectric constant of the third dielectric layer is greater than the dielectric constant of silicon dioxide.

15. A semiconductor device comprising the capacitor according to claim 14.

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