Gallium nitride power device and preparation method therefor

Abstract

The present application relates to a gallium nitride power device and a preparation method therefor. The device comprises a voltage-withstanding region, and the voltage-withstanding region comprises a first conductivity type doped region, a second conductivity type doped region, a plurality of resistor structures, a plurality of conductive structures, a drain doped region and a first drain. The first conductivity type doped region and the second conductivity type doped region are arranged in a substrate, and the resistor structures are arranged on the substrate; two ends of each conductive structure are each connected to one resistor structure, so that the resistor structures are connected in series; and the bottom of one conductive structure is electrically connected to the second conductivity type doped region, and the bottoms of the remaining conductive structures are electrically connected to the first conductivity type doped region. The drain doped region is arranged in the substrate, and the first conductivity type doped region is located between the second conductivity type doped region and the drain doped region, the first drain is arranged on the drain doped region, and the bottom of the first drain is electrically connected to the drain doped region.

Description

Gallium nitride power device and preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 2023107151514, filed on June 15, 2023, entitled “Gallium Nitride Power Device and Preparation Method Thereof,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of semiconductor manufacturing, and in particular to a gallium nitride power device, and also to a method for preparing a gallium nitride power device. Background Art

[0004] The semiconductor industry is increasingly demanding power devices. However, the performance of silicon-based power devices, primarily metal-oxide-semiconductor field-effect transistors and insulated-gate bipolar transistors, has reached the theoretical limits of their materials, failing to meet the higher demands placed on power devices in next-generation power electronics systems. Gallium nitride, a wide-bandgap semiconductor material, offers significant advantages over traditional silicon, including a wide bandgap, high electron saturation drift velocity, and a high critical breakdown electric field. This makes it an ideal semiconductor material for high-power, high-temperature, high-frequency, and radiation-resistant applications.

[0005] Gallium nitride (GaN) high electron mobility transistor (HEMT) power devices offer advantages such as high current density, fast switching speed, and low on-resistance. However, GaN devices have poor avalanche resistance. When the device is in the blocking state, when the drain voltage exceeds the rated withstand voltage, the drain voltage cannot be stabilized and continues to rise with increasing leakage current, causing safety and reliability issues for the device itself and the system. When doping the substrate below the drain with an N-type region to improve avalanche breakdown resistance, applying high voltage to the drain causes a severe substrate bias effect, which increases the dynamic on-resistance of the device and significantly increases its power loss.

[0006] Summary of the Invention

[0007] Based on this, it is necessary to provide a gallium nitride power device with strong avalanche breakdown capability and capable of optimizing the substrate bias effect.

[0008] A gallium nitride power device, comprising: a substrate having a second conductivity type; a buffer layer disposed on the substrate; a barrier layer disposed on the buffer layer; a source electrode disposed on the barrier layer; a second drain electrode disposed on the barrier layer; a first conductivity type doped region disposed in the substrate; the first conductivity type and the second conductivity type being opposite conductivity types; a second conductivity type doped region disposed in the substrate; a plurality of resistor structures disposed on the substrate; a plurality of conductive structures, each of the conductive structures having two ends connected to a resistor structure, thereby connecting the resistor structures in series; a bottom of one conductive structure being electrically connected to the second conductivity type doped region, and the bottoms of the remaining conductive structures being electrically connected to the first conductivity type doped region. doped regions are electrically connected; a drain doped region having a first conductivity type is provided in the substrate, the first conductivity type doped region is located between the second conductivity type doped region and the drain doped region; a first drain electrode is provided on the drain doped region, the bottom of the first drain electrode is electrically connected to the drain doped region; wherein the gallium nitride power device has a device region and a voltage-withstand region, the buffer layer, the barrier layer, the source electrode and the second drain electrode are located in the device region, the first conductivity type doped region, the second conductivity type doped region, each resistance structure, each conductive structure, the drain doped region and the first drain electrode are located in the voltage-withstand region; the second conductivity type doped region is closer to the device region than each of the first conductivity type doped regions.

[0009] In the aforementioned GaN power device, when the drain voltage is excessive, the PN junction formed by the drain doped region and the substrate undergoes avalanche breakdown, preventing the drain voltage from further increasing and significantly enhancing the avalanche breakdown capability of the GaN power device. Furthermore, in the withstand voltage region, a resistor structure divides the voltage input to the first drain electrode, causing each first-conductivity-type doped region and each second-conductivity-type doped region to follow the voltage of the conductive structure above it. Consequently, the voltage gradually decreases from the drain doped region to the second-conductivity-type doped region, thereby controlling the substrate potential of the device region and optimizing the substrate bias effect. When the conductive structure above the second-conductivity-type doped region is grounded, the potential of the second-conductivity-type doped region is also zero. Since the second-conductivity-type doped region is located close to the device region, the substrate potential of the device region is also zero. Compared to devices that enhance avalanche capability and reduce substrate bias effects through external integrated structures, the aforementioned GaN power device can reduce external metal interconnects and suppress device parasitic characteristics.

[0010] In one embodiment, when the gallium nitride power device is in operation, the first drain electrode is connected to the potential of the second drain electrode.

[0011] In one embodiment, the doping concentration of the second conductive type doping region is greater than the doping concentration of the substrate.

[0012] In one embodiment, when the gallium nitride power device is in operation, the conductive structure electrically connected to the second conductive type doping region is grounded.

[0013] In one embodiment, a portion of the bottom of the resistor structure is in direct contact with the first conductive type doping region.

[0014] In one embodiment, the resistance values ​​of the resistance structures are equal.

[0015] In one embodiment, the resistor structure is a two-dimensional electron gas resistor.

[0016] In one embodiment, the resistance of the two-dimensional electron gas resistor is greater than one million ohms and less than one hundred million ohms.

[0017] In one embodiment, the gallium nitride power device includes a high electron mobility transistor located in the device region.

[0018] In one embodiment, the buffer layer comprises gallium nitride, and the barrier layer comprises aluminum gallium nitride.

[0019] In one embodiment, the two-dimensional electron gas resistor includes a gallium nitride layer and an aluminum gallium nitride layer on the gallium nitride layer.

[0020] In one embodiment, the gallium nitride power device also includes an isolation structure located in the voltage-resistant region, and the isolation structure is formed between adjacent resistance structures and between adjacent conductive structures; the isolation structure includes a gallium nitride layer and an aluminum gallium nitride layer treated by high-energy particle injection, the injection energy of the high-energy particle injection is not less than 20 keV, the aluminum gallium nitride layer treated by high-energy particle injection is located on the gallium nitride layer treated by high-energy particle injection, and the resistivity of the isolation structure is greater than the resistivity of the two-dimensional electron gas resistor.

[0021] In one embodiment, the gallium nitride power device further includes a gate disposed on the barrier layer, wherein the gate includes a P-type gallium nitride region disposed on the barrier layer and a gate electrode disposed on the P-type gallium nitride region.

[0022] In one embodiment, the gallium nitride power device further includes a passivation layer located on the barrier layer and the isolation structure, and the passivation layer does not cover the gate, the source electrode, the first drain electrode, the second drain electrode, and the conductive structures.

[0023] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0024] In one embodiment, the voltage-sustaining region is located on one side of the device region.

[0025] In one embodiment, the voltage-sustaining region is located on both sides of the device region.

[0026] In one embodiment, the voltage-sustaining region is located around the device region.

[0027] It is also necessary to provide a method for preparing a gallium nitride power device.

[0028] A method for preparing a gallium nitride power device, comprising: providing a substrate having a first conductivity type doped region, a second conductivity type doped region, and a drain doped region; the substrate having the second conductivity type, the drain doped region having the first conductivity type, the first conductivity type doped region, the second conductivity type doped region, and the drain doped region being located in a voltage-sustaining region of the gallium nitride power device, and the first conductivity type doped region being formed between the second conductivity type doped region and the first drain doped region; the first conductivity type and the second conductivity type being opposite conductivity types; forming a buffer layer on the substrate; forming a barrier layer on the buffer layer; and performing high-energy particle injection into the buffer layer and the barrier layer in a portion of the voltage-sustaining region through photolithography and doping to destroy a two-dimensional electron gas so that the high-energy injection region is electrically conductive. The resistivity of the buffer layer and the barrier layer is greater than that of the buffer layer and the barrier layer without high-energy particle injection, thereby forming an isolation structure, and the injection energy of the high-energy particle injection is not less than 20 keV; a portion of the buffer layer and the barrier layer in the voltage-sustaining region that are not doped with the first impurity is removed to form a trench that exposes at least a portion of the first conductive type doped region, at least a portion of the second conductive type doped region, and at least a portion of the drain doped region, wherein the trench divides the buffer layer and the barrier layer in the voltage-sustaining region that are not doped with the first impurity into multiple two-dimensional electron gas resistors; a conductive material is filled in the trench to connect the two-dimensional electron gas resistors in series, the conductive material on the drain doped region serves as a first drain electrode, and a source electrode and a second drain electrode are formed on the barrier layer in the device region of the gallium nitride power device.

[0029] The fabrication method for the gallium nitride power device utilizes the same buffer and barrier layers as the device region to form a two-dimensional electron gas resistor in the voltage-stable region. High-energy particle implantation is then used to destroy the two-dimensional electron gas formed by the buffer and barrier layers in the non-two-dimensional electron gas resistor region, thereby forming an isolation structure. This requires fewer additional steps to establish the resistor. When the drain voltage is excessive, the PN junction formed between the drain doped region and the substrate undergoes avalanche breakdown, preventing the drain voltage from further increasing and significantly enhancing the avalanche breakdown capability of the gallium nitride power device. Furthermore, the resistor structure divides the voltage input to the first drain electrode, causing each first-conductivity-type doped region and each second-conductivity-type doped region to follow the voltage of the conductive structure above it. Consequently, the voltage gradually decreases from the drain doped region to the second-conductivity-type doped region, thereby controlling the substrate potential of the device region and optimizing the substrate bias effect. When the conductive structure above the second-conductivity-type doped region is grounded, the potential of the second-conductivity-type doped region is also zero. Since the second-conductivity-type doped region is located close to the device region, the substrate potential of the device region is also zero. Compared with devices that enhance avalanche capability and reduce the bias effect through external integrated structures, the device manufactured by the above-mentioned method for manufacturing gallium nitride power devices can reduce external metal interconnections and suppress the parasitic characteristics of the device.

[0030] In one embodiment, when the gallium nitride power device is in operation, the first drain electrode is connected to the potential of the second drain electrode.

[0031] In one embodiment, after the step of forming a barrier layer on the buffer layer, the method further includes: forming a P-type gallium nitride region on the barrier layer in the device region; and forming a gate electrode on the P-type gallium nitride region.

[0032] In one embodiment, after the lithography and doping steps and before the step of removing the portion of the buffer layer and barrier layer in the voltage-resistant region that is not doped with the first impurity, the step also includes forming a passivation layer on the barrier layer; the passivation layer exposes the positions where the grooves, source electrodes, second drain electrodes and gate electrodes need to be formed.

[0033] In one embodiment, the buffer layer comprises gallium nitride, and the barrier layer comprises aluminum gallium nitride.

[0034] In one embodiment, the high-energy particle implantation is performed by implanting at least one of nitrogen ions, boron ions, magnesium ions, and helium ions using ion implantation equipment.

[0035] In one embodiment, the injection dose of the high energy particle injection is not less than 1E14cm -2 .

[0036] In one embodiment, the doping concentration of the second conductive type doping region is greater than the doping concentration of the substrate.

[0037] In one embodiment, the resistance value of each of the two-dimensional electron gas resistors is greater than one million ohms and less than one hundred million ohms.

[0038] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0040] FIG1 is a cross-sectional view of a gallium nitride power device according to an embodiment;

[0041] FIG2 is a front view of a gallium nitride power device according to an embodiment;

[0042] FIG3a is a cross-sectional view along line AA' in FIG2;

[0043] FIG3 b is a cross-sectional view along line BB′ in FIG2 ;

[0044] FIG3c is a cross-sectional view along line CC' in FIG2;

[0045] FIG4 is a cross-sectional view of a two-dimensional electron gas resistor according to one embodiment;

[0046] FIG5 is a front view of a gallium nitride power device in yet another embodiment;

[0047] FIG6 is a front view of a gallium nitride power device according to another embodiment;

[0048] FIG7 is a cross-sectional view taken along line DD' in FIG6;

[0049] FIG8 is a cross-sectional view taken along line EE' in FIG6;

[0050] FIG9 is a cross-sectional view taken along line FF' in FIG6;

[0051] FIG10 is a cross-sectional view taken along line GG' in FIG6;

[0052] FIG11 is a cross-sectional view taken along line HH' in FIG6;

[0053] FIG12 is a cross-sectional view taken along line II' in FIG6;

[0054] FIG13 is a flow chart of a method for preparing a gallium nitride power device in one embodiment. DETAILED DESCRIPTION

[0055] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0057] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. "Connected" in this specification should be understood to mean "electrically connected," "communicatively connected," etc., if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0058] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0059] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an" and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be understood that "at least one" means one or more, and "a plurality" means two or more. "At least a portion of an element" refers to part or all of an element. It will also be understood that the terms "compose" and / or "comprise", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0060] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0061] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0062] This application addresses the issues of poor avalanche resistance and substrate bias effects in gallium nitride power devices by proposing a novel gallium nitride power device structure. Referring to FIG1 , a gallium nitride power device according to one embodiment can be divided into a device region 10, which houses the main body of the device, and a voltage-sustaining region 20, which serves as a voltage-sustaining structure. The gallium nitride power device includes a substrate 110, a buffer layer 132, a barrier layer 134, a source electrode 144, a first drain electrode 162, a second drain electrode 146, a first conductivity-type doped region 124, a second conductivity-type doped region 126, a drain doped region 122, multiple resistor structures 150, and multiple conductive structures 164. The buffer layer 132, barrier layer 134, source electrode 144, and second drain electrode 146 are located in the device region 10; the first conductivity-type doped region 124, the second conductivity-type doped region 126, the resistor structures 150, the conductive structures 164, the drain doped region 122, and the first drain electrode 162 are located in the voltage-sustaining region 20. The substrate 110 extends over the device region 10 and the voltage-sustaining region 20 .

[0063] The substrate 110 has a second conductivity type. A buffer layer 132 is disposed on the substrate 110. A barrier layer 134 is disposed on the buffer layer 132. A source electrode 144 and a second drain electrode 146 are disposed on the barrier layer 134. The buffer layer 132 and the barrier layer 134 can be made of materials known to those skilled in the art for buffer and barrier layers of gallium nitride power devices. In one embodiment of the present application, the gallium nitride power device includes a high electron mobility transistor (HEMT). The buffer layer 132, the barrier layer 134, the source electrode 144, and the second drain electrode 146 are respectively the buffer layer, barrier layer, source electrode, and drain electrode of the HEMT; accordingly, the buffer layer 132 is made of GaN, the barrier layer is made of AlGaN, and the source electrode 144 and the second drain electrode 146 are made of metal and / or alloy. A first conductivity type doping region 124 and a second conductivity type doping region 126 are disposed in the substrate 110, with the second conductivity type doping region 126 being closer to the device region 10 than the first conductivity type doping region 124. A drain doping region 122 has a first conductivity type and is disposed in the substrate 122. The first conductivity type doping region 124 is located between the second conductivity type doping region 126 and the drain doping region 122. The second conductivity type doping region 126 is disposed near the device region 10, i.e., at the edge of the voltage-withstand region 20. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may also be P-type, in which case the second conductivity type is N-type.

[0064] Each resistor structure 150 is provided on the substrate 110. One end of the conductive structure 164 is connected to a resistor structure 150, and the other end is connected to another resistor structure 150, thereby connecting each resistor structure 150 in series. The bottom of one of the conductive structures 164 (hereinafter referred to as the conductive structure A) is electrically connected to the second conductive type doping region 126, and the bottoms of the remaining conductive structures 164 are electrically connected to the first conductive type doping region 124. The first drain electrode 162 is provided on the drain doping region 122, and the bottom of the first drain electrode 162 is electrically connected to the drain doping region 122. When the device is working, the first drain electrode 162 is connected to the potential of the second drain electrode 146, for example, the first drain electrode 162 and the second drain electrode 146 can be short-circuited. In one embodiment of the present application, the material of the conductive structure 164 can be metal and / or alloy. The ellipsis in Figure 1 indicates that repeated structures are omitted.

[0065] Conventional gallium nitride power devices have poor avalanche resistance. When the device is in the blocking state, if the drain voltage exceeds the rated withstand voltage of the device, the drain voltage will continue to rise as the leakage current increases, causing safety and reliability issues for the device and system. However, in the gallium nitride power device provided in the above embodiment, when the HEMT is in operation, the second drain electrode 146, and therefore the first drain electrode 162, is connected to a high voltage; the conductive structure A is connected to a low voltage. For example, the conductive structure A can be connected to the potential of the source electrode 144 and grounded together with the source electrode 144. When the drain voltage is excessive, the PN junction formed by the drain doped region 122 and the substrate 110 undergoes avalanche breakdown (the PN junction formed by other first conductivity type doped regions 124 and the substrate 110 may also undergo avalanche breakdown), preventing the drain voltage from continuing to increase and significantly enhancing the avalanche breakdown capability of the gallium nitride power device.

[0066] Each resistance structure 150 divides the voltage input to the first drain electrode 162, so that each first conductive type doping region 124 and second conductive type doping region 126 follows the voltage of the conductive structure 164 above it. Therefore, the voltage gradually decreases from the drain doping region 122 to the second conductive type doping region 126, thereby achieving the purpose of controlling the potential of the substrate 110 of the device area 10 and optimizing the substrate bias effect.

[0067] Specifically, assuming that the first drain electrode 162 is connected to a high voltage of 600V, the conductive structure A is connected to the source electrode 144 and grounded, with a potential of 0V, shielding the high voltage. In Figure 1, there are a total of 10 resistor structures 150 connected in series. Assuming that the resistance values ​​of each resistor structure 150 are the same, the voltage divided by each resistor is 60V. Then, the potential of the conductive structure 164 closest to the first drain electrode 162 is 540V, and the potential of the first conductive type doped region 124 electrically connected thereto is also 540V accordingly. The first conductive type doped region 124 forms a reverse-biased PN junction with the nearby substrate 110, and the depletion layer is widened on the substrate 110 to withstand the voltage. Similarly, from the conductive structure 164 closest to the first drain electrode 162 to the conductive structure A, the potentials are 540V, 480V, ..., 0V, respectively. The potential of the first conductivity-type doped region 124 beneath each conductive structure 164 is also correspondingly pulled to 540V, 480V, ..., and forms a reverse-biased PN junction with the nearby substrate 110, widening the depletion layer on the substrate 110 to withstand the voltage. The potential of the conductive structure A is 0V, and the second conductivity-type doped region 126 connected to the conductive structure A is also 0V, thereby making the potential of the substrate 110 in the device region 10 all 0V. In other words, the substrate potential drops uniformly from the side of the first drain electrode 162 inward, reaching 0 in the device region 10, thereby achieving the purpose of controlling the substrate potential. When the second drain electrode 146 and the first drain electrode 162 are connected to a high voltage, the substrate potential of the device region 10 can also be maintained at 0V, thereby eliminating the bias effect and preventing an increase in dynamic on-resistance.

[0068] In the embodiment shown in FIG1 , the GaN power device further includes a gate 140 disposed on the barrier layer 134. The gate 140 is located in the device region 10 and includes a P-type GaN region 141 disposed on the barrier layer 134 and a gate electrode 142 disposed on the P-type GaN region 141. The gate electrode 142 can be made of a metal and / or an alloy.

[0069] In one embodiment of the present application, resistor structure 150 is a two-dimensional electron gas resistor. In one embodiment of the present application, resistor structure 150 employs the same structure as buffer layer 132 and barrier layer 134. Specifically, resistor structure 150 includes a buffer layer and a barrier layer on the buffer layer, with the two-dimensional electron gas formed by a heterojunction at the junction of the buffer and barrier layers. In one embodiment of the present application, resistor structure 150 includes a gallium nitride layer and an aluminum gallium nitride layer on the gallium nitride layer.

[0070] In the embodiment shown in FIG1 , the gallium nitride power device further includes an isolation structure 136 located in the voltage-resistant region 20. An isolation structure 136 is formed between adjacent resistance structures 150 and between adjacent conductive structures 164. In one embodiment of the present application, the isolation structure 136 includes a gallium nitride layer treated by high-energy particle injection, and an aluminum gallium nitride layer treated by high-energy particle injection. The aluminum gallium nitride layer treated by high-energy particle injection is located on the gallium nitride layer treated by high-energy particle injection. In the present application, high energy refers to an injection energy of not less than 20 kiloelectron volts (keV). That is, the isolation structure 136 can be a two-dimensional electron gas resistance structure that undergoes high-energy particle injection to destroy the two-dimensional electron gas, thereby increasing the resistivity and obtaining a resistivity close to that of an insulating material. In one embodiment, the high-energy particle injection is performed by using an ion injection device to inject nitrogen ions, or one of boron ions, magnesium ions, and helium ions. In one embodiment of the present application, the injection dose of the high-energy particle injection is not less than 1E14 cm -2 .

[0071] In the embodiment shown in FIG1 , the gallium nitride power device further includes a passivation layer 160 located on the barrier layer 134 and the isolation structure 136. The passivation layer 160 does not cover the gate electrode 142, the source electrode 144, the first drain electrode 162, the second drain electrode 146, and the conductive structures 164. In one embodiment of the present application, the passivation layer 160 is made of silicon nitride.

[0072] In one embodiment of the present application, the doping concentration of the second conductive type doping region 126 is greater than the doping concentration of the substrate 110. In the embodiment shown in FIG1 , the first conductive type doping region 124 is an N+ region, and the second conductive type doping region 126 is a P+ region.

[0073] From the perspective of eliminating substrate bias effects, a uniform change in the potential line from the drain doped region 122 to the second conductivity type doped region 126 can achieve better results. To this end, the resistance value, shape, structure, and arrangement of each resistor structure 150 can be reasonably designed. In one embodiment of the present application, the resistance value of each resistor structure 150 is equal. The following illustrates the planar structure of the resistor structure through different embodiments.

[0074] Figure 2 is a front view of a gallium nitride power device according to one embodiment of the present application. In this embodiment, the voltage-sustaining region 20 is located on one side of the device region 10. Figure 3a is a cross-sectional view along line AA' in Figure 2, Figure 3b is a cross-sectional view along line BB' in Figure 2, and Figure 3c is a cross-sectional view along line CC' in Figure 2. The gallium nitride power device includes a substrate 210, a buffer layer 232, a barrier layer 234, a source electrode 244, a gate 240, a first drain electrode 262, a second drain electrode 246, a first conductivity type doped region 224, a second conductivity type doped region 226, a drain doped region 222, a passivation layer 260, an isolation structure 236, a plurality of two-dimensional electron gas resistors 250, and a plurality of conductive structures 264. The two-dimensional electron gas resistors 250 include a gallium nitride layer 251 and an aluminum gallium nitride layer 252 on the gallium nitride layer 251.

[0075] Figure 4 is a cross-sectional view of a two-dimensional electron gas resistor 250 in one embodiment of the present application. A row of dots in Figure 4 represents a two-dimensional electron gas. In one embodiment of the present application, a portion of the bottom of the two-dimensional electron gas resistor 250 is in direct contact with the first conductivity type doped region 224.

[0076] In one embodiment of the present application, the resistance of each 2DEG resistor 250 is greater than one million ohms and less than one hundred million ohms. Furthermore, the resistance of each 2DEG resistor 250 is in the tens of millions ohms range, thereby limiting leakage current to less than 1 microampere.

[0077] In FIG2 , the voltage-sustaining region 20 is located on one side of the device region 10. In other embodiments, a voltage-sustaining region 20 may be provided on each side of the device region 10, as shown in FIG5 . The structure of the voltage-sustaining region 20 in the embodiment shown in FIG5 is similar to that in the embodiment shown in FIG2 , and the two voltage-sustaining regions 20 are symmetrically arranged, and their structure will not be described in detail here.

[0078] Figure 6 is a front view of a gallium nitride power device according to another embodiment of the present application. In this embodiment, a voltage-sustaining region 20 (not labeled in Figure 6 ) is located around the device region 10 (not labeled in Figure 6 ). Figure 7 is a cross-sectional view taken along line DD' in Figure 6 , Figure 8 is a cross-sectional view taken along line EE' in Figure 6 , Figure 9 is a cross-sectional view taken along line FF' in Figure 6 , Figure 10 is a cross-sectional view taken along line GG' in Figure 6 , Figure 11 is a cross-sectional view taken along line HH' in Figure 6 , and Figure 12 is a cross-sectional view taken along line II' in Figure 6 .

[0079] Referring to the figure, the present application provides a method for preparing a gallium nitride power device, which can be used to prepare the gallium nitride power device described in any of the above embodiments. The method includes the following steps:

[0080] S310 , providing a substrate.

[0081] Specifically, a substrate is provided, having a first conductivity type doped region, a second conductivity type doped region, and a drain doped region. The substrate has the second conductivity type, the drain doped region has the first conductivity type, the first conductivity type doped region, the second conductivity type doped region, and the drain doped region are located in a voltage-sustaining region, and the first conductivity type doped region is formed between the second conductivity type doped region and the first drain doped region. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0082] In one embodiment of the present application, the doping concentration of the second conductive type doping region is greater than the doping concentration of the substrate.

[0083] S320 , forming a buffer layer on the substrate.

[0084] In one embodiment of the present application, the buffer layer is a gallium nitride layer.

[0085] S330 , forming a barrier layer on the buffer layer.

[0086] In one embodiment of the present application, the barrier layer is an aluminum gallium nitride layer.

[0087] S340 , high-energy ion implantation is performed into the buffer layer and the barrier layer in a portion of the voltage-sustaining region through photolithography and doping.

[0088] High-energy particles are injected into the buffer layer and the barrier layer in part of the voltage-sustaining region to destroy the two-dimensional electron gas so that the resistivity of the high-energy injected region is greater than that of the buffer layer and the barrier layer without high-energy particle injection, thereby forming an isolation structure.

[0089] In one embodiment of the present application, a photoresist having a corresponding pattern is used. After exposure and development, a photoresist layer covering the device area and the two-dimensional electron gas resistance area is formed, and the area where the isolation structure needs to be formed is exposed, and high-energy particle injection is performed. The two-dimensional electron gas at the junction of the buffer layer and the barrier layer in the exposed area of ​​the photoresist layer is destroyed by the high-energy particle injection, so that the resistivity of the injection area is greater than the resistivity of the buffer layer and the barrier layer injected with high-energy particles (the buffer layer and the barrier layer in the voltage-resistant area that have not been injected with high-energy particles subsequently serve as the two-dimensional electron gas resistance), thereby forming an isolation structure.

[0090] In one embodiment of the present application, the high energy particle implantation is performed by using an ion implantation device to implant nitrogen ions, or one of boron ions, magnesium ions, and helium ions. In one embodiment of the present application, the implantation dose of the high energy particle implantation is not less than 1E14 cm -2 .

[0091] S350 , forming a trench for dividing the structure of the voltage-sustaining region not doped with the first impurity into a plurality of two-dimensional electron gas resistors.

[0092] In one embodiment of the present application, a portion of the buffer layer and barrier layer in the voltage-sustaining region that are not doped with the first impurity are removed by photolithography and etching, thereby forming a trench that exposes at least a portion of the first conductivity type doped region, at least a portion of the second conductivity type doped region, and at least a portion of the drain doped region. The trench divides the buffer layer and barrier layer in the voltage-sustaining region that are not doped with the first impurity into multiple two-dimensional electron gas resistors.

[0093] S360 , filling the trench with a conductive material to connect the two-dimensional electron gas resistors in series, and forming a source electrode and first and second drain electrodes.

[0094] In one embodiment of the present application, a conductive material (e.g., a metal and / or alloy) is deposited. The conductive material filled in the trench above the drain doped region serves as the first drain electrode. The conductive material filled in the trenches above the first conductivity type doped region and the second conductivity type doped region serves as a conductive structure that connects the two-dimensional electron gas resistors in series. Metal deposited on the barrier layer in the device region forms the source electrode and the second drain electrode.

[0095] The fabrication method for the gallium nitride power device utilizes the same buffer and barrier layers as the device region to form a two-dimensional electron gas resistor in the voltage-stable region. High-energy particle implantation is then used to destroy the two-dimensional electron gas formed by the buffer and barrier layers in the non-two-dimensional electron gas resistor region, thereby forming an isolation structure. This requires fewer additional steps to establish the resistor. When the drain voltage is excessive, the PN junction formed between the drain doped region and the substrate undergoes avalanche breakdown, preventing the drain voltage from further increasing and significantly enhancing the avalanche breakdown capability of the gallium nitride power device. Furthermore, the resistor structure divides the voltage input to the first drain electrode, causing each first-conductivity-type doped region and each second-conductivity-type doped region to follow the voltage of the conductive structure above it. Consequently, the voltage gradually decreases from the drain doped region to the second-conductivity-type doped region, thereby controlling the substrate potential of the device region and optimizing the substrate bias effect. When the conductive structure above the second-conductivity-type doped region is grounded, the potential of the second-conductivity-type doped region is also zero. Since the second-conductivity-type doped region is located close to the device region, the substrate potential of the device region is also zero. Compared with devices that enhance avalanche capability and reduce the bias effect through external integrated structures, the device manufactured by the above-mentioned method for manufacturing gallium nitride power devices can reduce external metal interconnections and suppress the parasitic characteristics of the device.

[0096] In one embodiment of the present application, after step S330, the process further includes forming a P-type GaN region on the barrier layer in the device region. After forming the P-type GaN region, thermal annealing may be performed. The P-type GaN region serves as a component of the P-type GaN gate of the HEMT. The formed P-type GaN can be etched away in areas where it is not needed, specifically, the P-type GaN in the withstand voltage region and the P-type GaN outside the gate region of the device region are etched away.

[0097] Accordingly, the metal deposited in step S360 forms a gate electrode on the P-type gallium nitride region.

[0098] In one embodiment of the present application, after step S340 and before step S350, a passivation layer is further formed on the barrier layer. The passivation layer exposes the locations where the trench, source electrode, second drain electrode, and gate electrode need to be formed. In one embodiment of the present application, the passivation layer can be formed after the P-type gallium nitride region is formed, and the passivation layer is removed from the locations where the passivation layer is not needed by photolithography and etching. In one embodiment of the present application, the passivation layer is made of silicon nitride.

[0099] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0100] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0101] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A gallium nitride power device, comprising: a substrate having a second conductivity type; A buffer layer is disposed on the substrate; A barrier layer, disposed on the buffer layer; A source electrode, disposed on the barrier layer; A second drain electrode is disposed on the barrier layer; A first conductivity type doped region is provided in the substrate; the first conductivity type is opposite to the second conductivity type; A second conductive type doped region is provided in the substrate; A plurality of resistor structures are disposed on the substrate; A plurality of conductive structures, each conductive structure having two ends connected to a resistor structure, so that the resistor structures are connected in series; The bottom of one of the conductive structures is electrically connected to the second conductive type doped region, and the bottoms of the remaining conductive structures are electrically connected to the first conductive type doped region; a drain doped region, having the first conductivity type, disposed in the substrate, wherein the first conductivity type doped region is located between the second conductivity type doped region and the drain doped region; and A first drain electrode is disposed on the drain doping region, and a bottom of the first drain electrode is electrically connected to the drain doping region; The gallium nitride power device has a device region and a voltage-resistant region, the buffer layer, the barrier layer, the source electrode and the second drain electrode are located in the device region, the first conductive type doped region, the second conductive type doped region, the multiple resistor structures, the multiple conductive structures, the drain doped region and the first drain electrode are located in the voltage-resistant region; the second conductive type doped region is closer to the device region than the first conductive type doped region.

2. The gallium nitride power device according to claim 1, characterized in that: The resistance values ​​of the resistance structures are equal.

3. The gallium nitride power device according to claim 1, characterized in that: The resistor structure is a two-dimensional electron gas resistor.

4. The gallium nitride power device according to claim 3, characterized in that: The two-dimensional electron gas resistor includes a gallium nitride layer and an aluminum gallium nitride layer on the gallium nitride layer.

5. The gallium nitride power device according to claim 4, characterized in that: It also includes an isolation structure located in the voltage-resistant area, wherein the isolation structure is formed between adjacent resistance structures and between adjacent conductive structures; the isolation structure includes a gallium nitride layer treated by high-energy particle injection and an aluminum gallium nitride layer treated by high-energy particle injection, the injection energy of the high-energy particle injection is not less than 20keV, the aluminum gallium nitride layer treated by high-energy particle injection is located on the gallium nitride layer treated by high-energy particle injection, and the resistivity of the isolation structure is greater than the resistivity of the two-dimensional electron gas resistor.

6. The gallium nitride power device according to claim 1, characterized in that: It also includes a gate disposed on the barrier layer, wherein the gate includes a P-type gallium nitride region disposed on the barrier layer and a gate electrode disposed on the P-type gallium nitride region.

7. The gallium nitride power device according to claim 1, characterized in that: The voltage-resistant region is located at one side of the device region, or the voltage-resistant region is located at both sides of the device region, or the voltage-resistant region is located around the device region.

8. The gallium nitride power device according to claim 1, characterized in that: When the gallium nitride power device is working, the first drain electrode is connected to the potential of the second drain electrode.

9. The gallium nitride power device according to claim 1, characterized in that: The buffer layer includes gallium nitride, and the barrier layer includes aluminum gallium nitride.

10. The gallium nitride power device according to claim 1, characterized in that: The doping concentration of the second conductive type doping region is greater than the doping concentration of the substrate.

11. The gallium nitride power device according to claim 1, characterized in that: When the gallium nitride power device is working, the conductive structure electrically connected to the second conductive type doping region is grounded.

12. The gallium nitride power device according to claim 1, characterized in that: A portion of the bottom of the resistor structure is in direct contact with the first conductive type doping region.

13. The gallium nitride power device according to claim 3, characterized in that: The resistance value of the two-dimensional electron gas resistor is greater than one million ohms and less than one hundred million ohms.

14. The gallium nitride power device according to claim 1, characterized in that: The gallium nitride power device includes a high electron mobility transistor located in the device region.

15. The gallium nitride power device according to claim 1, characterized in that: It also includes a passivation layer located on the barrier layer and the isolation structure, and the passivation layer does not cover the gate, the source electrode, the first drain electrode, the second drain electrode and each conductive structure.

16. A method for preparing a gallium nitride power device, comprising: Providing a substrate having a first conductivity type doping region, a second conductivity type doping region and a drain doping region formed thereon; The substrate has a second conductivity type, the drain doping region has a first conductivity type, the first conductivity type doping region, the second conductivity type doping region and the drain doping region are located in a voltage-withstand region of the gallium nitride power device, and the first conductivity type doping region is formed between the second conductivity type doping region and the first drain doping region; the first conductivity type is opposite to the second conductivity type; forming a buffer layer on the substrate; forming a barrier layer on the buffer layer; By photolithography and doping, high-energy particles are injected into the buffer layer and the barrier layer in a part of the voltage-sustaining region to destroy the two-dimensional electron gas so that the resistivity of the high-energy injected region is greater than the resistivity of the buffer layer and the barrier layer without high-energy particle injection, thereby forming an isolation structure, wherein the injection energy of the high-energy particle injection is not less than 20 keV; removing part of the buffer layer and barrier layer in the voltage-sustaining region that are not doped with the first impurity, forming a groove that exposes at least part of the first conductive type doped region, at least part of the second conductive type doped region, and at least part of the drain doped region, wherein the groove cuts the buffer layer and barrier layer in the voltage-sustaining region that are not doped with the first impurity into a plurality of two-dimensional electron gas resistors; and A conductive material is filled in the trench to connect the two-dimensional electron gas resistors in series, the conductive material on the drain doping region serves as a first drain electrode, and a source electrode and a second drain electrode are formed on the barrier layer in the device region of the gallium nitride power device.

17. The method according to claim 16, characterized in that After the step of forming a barrier layer on the buffer layer, the method further comprises: forming a P-type gallium nitride region on the barrier layer in the device region; A gate electrode is formed on the P-type gallium nitride region.

18. The method according to claim 17, characterized in that After the photolithography and doping steps and before the step of removing the buffer layer and barrier layer that are partially undoped with the first impurity in the voltage-resistant region, the method further includes: forming a passivation layer on the barrier layer; the passivation layer exposes the positions where the grooves, source electrodes, second drain electrodes and gate electrodes need to be formed.

19. The method according to claim 16, characterized in that The high-energy particle implantation is to use ion implantation equipment to implant at least one of nitrogen ions, boron ions, magnesium ions, and helium ions.

20. The method according to claim 16, characterized in that The injection dose of the high energy particle injection is not less than 1E14cm -2 .

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