Array substrate and preparation method therefor, display panel, and display apparatus

Abstract

An array substrate and a preparation method therefor, a display panel, and a display apparatus. The array substrate comprises a base substrate (1), a planarization layer (2) and a common electrode layer (3), wherein the planarization layer (2) is arranged on one side of the base substrate (1), and the planarization layer (2) is provided with a plurality of first via holes (201) extending through the planarization layer (2) in a thickness direction of the planarization layer (2); the common electrode layer (3) is arranged on the side of the planarization layer (2) away from the base substrate (1), and the common electrode layer (3) is provided with a plurality of second via holes (301) extending through the common electrode layer (3) in a thickness direction of the common electrode layer (3); and the orthographic projection of the second via hole (301) on the base substrate (1) completely covers the orthographic projection of the first via hole (201) on the base substrate (1). The array substrate is beneficial to the formation of the common electrode layer, and also enables any other structural layer that is subsequently formed above the common electrode layer to have good coverage, which helps to improve the yield rate.

Description

Array substrate and manufacturing method thereof, display panel and display device

[0001] This disclosure claims priority to Chinese patent application No. 202310709047.4 filed on June 14, 2023, entitled “Array substrate, preparation method thereof, display panel and display device”, the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel, and a display device. Background Art

[0003] With the widespread use of liquid crystal displays (LCDs), the demand for broadband technology is increasing. Broadband technology refers to the ability of a display panel to operate normally at both low refresh rates (e.g., 2 Hz) and high refresh rates (e.g., 240 Hz). This places higher demands on the uniformity of the common voltage (or COM voltage) within the LCD.

[0004] Summary of the Invention

[0005] The present application provides an array substrate and a manufacturing method thereof, a display panel, and a display device.

[0006] In a first aspect, the present application provides an array substrate, comprising a base substrate, a flat layer, and a common electrode layer, wherein the flat layer is arranged on one side of the base substrate, and the flat layer has a plurality of first via holes penetrating the flat layer along the thickness direction of the flat layer; the common electrode layer is arranged on a side of the flat layer away from the base substrate, and the common electrode layer has a plurality of second via holes penetrating the common electrode layer along the thickness direction of the common electrode layer, wherein the orthographic projections of the second via holes on the base substrate completely cover the orthographic projections of the first via holes on the base substrate.

[0007] In some possible implementations, the array substrate further includes a common electrode line, a plurality of gate lines, and a plurality of data lines, wherein the common electrode line, the plurality of gate lines, and the plurality of data lines are all arranged between the planar layer and the base substrate, the common electrode line is connected to the common electrode layer, the plurality of gate lines are arranged along a first direction, the plurality of data lines are arranged along a second direction, the first direction intersects the second direction, and the common electrode layer and the plurality of gate lines are arranged on the same layer;

[0008] The array substrate also includes a common electrode compensation line, which is arranged on a side of the common electrode layer away from the base substrate. The orthographic projection of the common electrode compensation line on the base substrate at least partially overlaps with the orthographic projection of the multiple gate lines or the multiple data lines on the base substrate, and the common electrode compensation line is connected to the common electrode layer.

[0009] In some possible implementations, the array substrate further includes a plurality of spacers, and the plurality of spacers are arranged on a side of the common electrode compensation line away from the base substrate;

[0010] The common electrode compensation line includes an island structure, the width of the island structure is greater than the width of the common electrode compensation line at other parts, the island structure has a bearing plane on the side facing the spacer, and the orthographic projection of the spacer on the base substrate is located within the orthographic projection of the bearing plane on the base substrate.

[0011] In some possible implementations, the array substrate includes a display area and a non-display area disposed on at least one side of the display area; the plurality of gate lines and the plurality of data lines are disposed in the display area, and the common electrode lines are disposed in the non-display area;

[0012] The common electrode layer in the overlapping area between the first projection and the second projection is connected to the common electrode line, the first projection is the orthographic projection of the common electrode compensation line on the common electrode layer, and the second projection is the orthographic projection of the common electrode line on the common electrode layer.

[0013] In some possible implementations, the non-display area of ​​the array substrate is arranged around the display area, and the common electrode line is a ring line surrounding the display area;

[0014] The orthographic projections of the plurality of gate lines or the plurality of data lines on the base substrate are within the orthographic projections of the common electrode compensation line on the base substrate; each of the first projections has an overlapping area at both ends in its length direction.

[0015] In some possible implementations, the first via hole is a tapered hole, and the slope angle of the hole wall of the first via hole is 50° to 60°; wherein the slope angle of the hole wall is the angle between the hole wall and the plane of the substrate.

[0016] In some possible implementations, the first via hole includes a first opening facing the common electrode layer and a second opening away from the common electrode layer; a diameter of the first opening is greater than a diameter of the second opening;

[0017] A minimum distance between an edge of the second via hole and an edge of the first orifice is 1.7 micrometers to 3.2 micrometers.

[0018] A second aspect of the present application provides a display panel, comprising any array substrate as described in the first aspect.

[0019] In some possible implementations, the display panel further includes a color filter substrate, the color filter substrate includes a black matrix; the array substrate includes a plurality of pixel areas, each of the pixel areas includes at least two domain display areas;

[0020] The array substrate also includes a common electrode compensation line, the orthographic projection of the common electrode compensation line on the base substrate is located within the total dark area, the total dark area includes a first sub-dark area and a second sub-dark area intersecting the first sub-dark area, the first sub-dark area is the orthographic projection of the black matrix on the base substrate, the second sub-dark area is the set of orthographic projections of all intersection domain areas on the base substrate, and each intersection domain area is a transition area between two adjacent domain display areas within the pixel area.

[0021] In some possible implementations, all orthographic projections of the common electrode compensation lines on the base substrate are located within the first sub-dark area.

[0022] A third aspect of the present application provides a method for preparing the array substrate according to the first aspect, comprising:

[0023] Providing a stacked planar layer, a first electrode layer, a first conductive layer, and a photoresist layer, wherein the planar layer has the first via hole, the first conductive layer is provided with a first through hole corresponding to the first via hole, the photoresist layer includes a second through hole corresponding to the first via hole, a first portion corresponding to the common electrode compensation line, and a second portion excluding the second through hole and the first portion, wherein the thickness of the first portion is greater than the thickness of the second portion;

[0024] removing the second portion of the photoresist layer;

[0025] A portion of the first electrode layer not covered by the first conductive layer is removed to form the common electrode layer having the second via hole.

[0026] In some possible implementations, removing the portion of the first electrode layer not covered by the first conductive layer to form the common electrode layer having the second via hole includes:

[0027] The portion of the first electrode layer not covered by the first conductive layer is removed by a first etching solution; wherein the etching rate of the first etching solution on the first electrode layer is greater than the etching rate on the first conductive layer.

[0028] In some possible implementations, before providing the stacked planar layer, the first electrode layer, the first conductive layer, and the photoresist layer, the method further includes:

[0029] Providing the planar layer, the first electrode layer, the first conductive layer to be formed, and the photoresist layer to be formed, which are stacked, wherein the planar layer has the first via hole, and the thickness of the photoresist layer to be formed is not less than the thickness of the first portion of the photoresist layer;

[0030] exposing and developing the photoresist layer to be formed through a semi-transparent mask to form the photoresist layer;

[0031] The portion of the first conductive layer to be formed that is not covered by the photoresist layer is removed to form the first conductive layer having the first through hole.

[0032] In some possible implementations, the semi-transparent mask includes a first light-transmitting pattern, a second light-transmitting pattern, and a third light-transmitting pattern with different light transmittances, so that the photoresist layer to be formed forms the second through hole, the first portion, and the second portion with different thicknesses.

[0033] In some possible implementations, the light transmittance of the first light-transmitting pattern is 100%, the light transmittance of the second light-transmitting pattern is 0%, and the light transmittance of the third light-transmitting pattern is no more than 20% and greater than 0%.

[0034] In some possible implementations, the display substrate further includes a common electrode compensation line, and the method further includes: removing a portion of the first conductive layer not covered by the first portion of the photoresist layer to form the common electrode compensation line.

[0035] A fourth aspect of the present application provides a display device, comprising: the array substrate as described in the first aspect, or the display panel as described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in this application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] FIG1 is a schematic top view of a first structure of an array substrate in the related art;

[0038] FIG2 is a top view schematic diagram of a second structure of an array substrate in the related art;

[0039] FIG3 is a schematic cross-sectional view of an array substrate in the related art;

[0040] FIG4 is a schematic cross-sectional view of an array substrate according to an embodiment of the present application;

[0041] FIG5 is a schematic top view of an array substrate according to an embodiment of the present application;

[0042] FIG6 is a partially enlarged top view of the array substrate at the first position according to an embodiment of the present application;

[0043] FIG7 is a partially enlarged top view of the second position of the array substrate according to an embodiment of the present application;

[0044] FIG8 is a flow chart of a method for preparing an array substrate according to an embodiment of the present application;

[0045] 9 to 14 are schematic diagrams of a first method for preparing an array substrate according to an embodiment of the present application;

[0046] 15 to 17 are schematic diagrams of a second method for preparing an array substrate according to an embodiment of the present application;

[0047] FIG18 is a flow chart of the pre-stage of the method for preparing an array substrate according to an embodiment of the present application;

[0048] FIG19 is a schematic diagram of forming a photoresist layer by using a semi-transparent mask in a method for preparing an array substrate according to an embodiment of the present application;

[0049] 20 to 22 are schematic diagrams showing experimental results of determining the light transmittance of a semi-transparent mask in a method for manufacturing an array substrate according to an embodiment of the present application;

[0050] 23 and 24 are schematic diagrams of the microstructure of a common electrode layer formed in a method for preparing an array substrate according to an embodiment of the present application;

[0051] 25 and 26 are schematic diagrams of the microstructure of forming a common electrode compensation line in the array substrate preparation method according to an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of this application more clear, this application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0053] It should be noted that the relative arrangement of the components, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise.

[0054] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0055] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0056] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the usual meanings understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in the embodiments of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0057] The structure shown in FIG1 is used as an example for illustration. FIG1 is a schematic top view of an array substrate in a display panel. The array substrate includes a display area 15 and a non-display area 16 surrounding the display area 15. The display area 15 is surrounded by gate lines 4 and data lines (not shown in FIG1 ) that cross each other to form a plurality of pixel areas 17 distributed in an array. Common electrode lines 6 connected to the common electrode layer 3 are provided in the non-display area 16. The common electrode lines 6 and the gate lines 4 are provided in the same layer (the common electrode layer 3 in FIG1 is located on the top layer, and the common electrode lines 6 and the gate lines 4 are located on the bottom layer relative to the common electrode layer 3. Therefore, the common electrode lines 6 and the gate lines 4 are represented by dotted lines). A common electrode voltage input interface is provided on the common electrode line 6 for providing a common electrode voltage to the common electrode layer 3.

[0058] As the size of liquid crystal displays becomes larger and larger, the actual common electrode voltage of the pixel area 17 close to the peripheral common electrode line 6 is significantly different from the actual common electrode voltage of the pixel area 17 far from the peripheral common electrode line 6, resulting in uneven distribution of the common electrode voltage on the array substrate.

[0059] To solve the above problem, a first solution is to provide a common electrode branch line 601 parallel to the gate line 4 in the display area 15. The two ends of the common electrode branch line 601 are respectively connected to the peripheral common electrode line 6, and the portion of the common electrode layer 3 corresponding to each pixel area 17 is connected to the common electrode branch line 601 through a first connection via 602. However, since a first connection via 602 needs to be provided in each pixel area 17, the aperture ratio of the pixel area 17 is adversely affected.

[0060] In addition to the above solution, as shown in Figure 2, there is also a second solution, which uses a metal wire 7 provided on the common electrode layer 3 to replace the common electrode branch line 601 in the first solution. The portion of the metal wire 7 in the display area 15 is directly connected to the common electrode layer 3. Since the line resistance of the metal wire 7 is relatively small, its direct contact with the common electrode layer 3 can form a parallel resistance effect, thereby achieving the function of balancing the common electrode voltage in the display panel. In the non-display area 16, the common electrode layer 3 or the metal wire 7 is connected to the common electrode line 6 through the second connecting via 701. In this solution, since there is no need to provide a via in the display area 15, it helps to increase the aperture ratio of the pixel area 17.

[0061] In the manufacturing process of the second solution, it is necessary to first form a stacked thin-film transistor 8, a flat layer 2, and a common electrode layer 3. In order to enable the pixel electrode layer 11 subsequently arranged on the side of the common electrode layer 3 away from the flat layer 2 to be connected to the source and drain of the thin-film transistor 8, the flat layer 2 and the common electrode layer 3 are both provided with vias corresponding to the source and drain. However, the applicant's research found that after the metal wire 7 is formed on the common electrode layer 3, the aperture of the via of the flat layer 2 will expand, and even exceed the aperture of the via of the common electrode layer 3, as shown in Figure 3. This causes the edge of the via of the common electrode layer 3 to be suspended due to lack of support from the flat layer 2, which in turn causes the second passivation layer 13 (or PVX2, which can be made of SiNx) and the pixel electrode layer 11 (which can be made of ITO) subsequently formed on the common electrode layer 3 to have poor coverage, resulting in defects.

[0062] In view of this, as shown in Figure 4, an embodiment of the present application provides an array substrate, including a base substrate 1, a flat layer 2 is provided on one side of the base substrate 1, and a first through-hole 201 is provided on the flat layer 2 along the thickness direction; a common electrode layer 3 is provided on the side of the flat layer 2 away from the base substrate 1, and a second through-hole 301 is provided on the common electrode layer 3 along the thickness direction, and the orthographic projection of the second through-hole 301 on the flat layer 2 completely covers the first through-hole 201.

[0063] FIG4 is an exemplary structure illustrating an array substrate. FIG4 shows a cross-sectional schematic diagram of a pixel region 17 in the array substrate, including a base substrate 1. A gate line 4 and a gate insulating layer 5 (GI) covering the gate line 4 are provided on one side of the base substrate 1. A thin film transistor 8 (IGZO transistor), a data line 9 connected to the drain 801 of the thin film transistor 8, and a first passivation layer 12 (PVX1) covering the thin film transistor 8 and the data line 9 are provided on the side of the gate insulating layer 5 away from the base substrate 1. The gate of the thin film transistor 8 is connected to the gate line 4. A planarization layer 2 (ORG), a common electrode layer 3 (COM ITO, also referred to as 1ITO in this embodiment), and a second passivation layer 13 (PVX2) covering the common electrode layer 3 are stacked on the side of the first passivation layer 12 away from the base substrate 1 in a direction away from the first passivation layer 12 (the Z direction in FIG4 ). A pixel electrode layer 11 (PXL ITO, which may also be referred to as 2ITO in this embodiment) is further provided on the side of the second passivation layer 13 away from the base substrate 1. The pixel electrode layer 11 is connected to the source 802 of the thin film transistor 8 through a via hole that penetrates the second passivation layer 13, the common electrode layer 3, the planar layer 2 and the first passivation layer 12.

[0064] Exemplarily, the second via hole 301 provided in the common electrode layer 3 is coaxially arranged with the first via hole 201 provided in the planar layer 2 .

[0065] It should be noted that in this embodiment, the orthographic projection of the second via 301 on the planar layer 2 completely covers the first via 201 (the projection of the second via 301 on the base substrate 1 completely covers the projection of the first via 201 on the base substrate 1), that is, the second via 301 can completely expose the first via 201. Taking the direction shown in Figure 4 as an example, since the planar layer 2 surrounding the first via 201 is a solid structure, and the second via 301 completely exposes the first via 201, this means that the edge of the second via 301 is located beyond the range of the first via 201 and is located on the solid structure of the planar layer 2. Therefore, the portion of the common electrode layer 3 outside the edge of the second via 301 also has the solid structure of the planar layer 2 underneath, which ensures that this portion can be reliably supported by the planar layer 2.

[0066] The array substrate provided in this embodiment enables the second via hole 301 of the common electrode layer 3 to completely cover the first via hole 201 of the flat layer 2 in the orthographic projection of the flat layer 2, so that the portion of the common electrode layer 3 close to the second via hole 301 can be reliably supported by the flat layer 2. This is not only beneficial to the formation of the common electrode layer 3, but also enables other structural layers subsequently formed above the common electrode layer 3 to have better coverage, which helps to improve the yield rate.

[0067] As shown in FIG4 , in some embodiments, the first via hole 201 is a tapered hole, and the hole wall slope angle α of the first via hole 201 is 50° to 60°; wherein the hole wall slope angle α is the angle between the hole wall and the plane where the base substrate 1 is located.

[0068] The hole wall slope angle α is set to 50° to 60°, which can expose as much of the source of the thin film transistor 8 as possible through the first via hole 201 when the molding process permits, ensuring that the source can provide a larger connection area, thereby ensuring that the pixel electrode layer 11 can be reliably connected to the source of the thin film transistor 8.

[0069] As shown in Figure 4, in some embodiments, the first via 201 includes a first opening facing the common electrode layer 3, and a second opening away from the common electrode layer 3; the diameter b of the first opening is greater than the diameter c of the second opening; the minimum distance a between the edge of the second via 301 and the edge of the first opening is 1.7 microns to 3.2 microns.

[0070] Setting the minimum distance a between the edge of the second via hole 301 and the edge of the first opening to 1.7 microns to 3.2 microns can, on the one hand, further ensure that the orthographic projection of the second via hole 301 on the planar layer 2 can completely cover the first via hole 201. On the other hand, it can also prevent the excessively large aperture of the second via hole 301 from adversely affecting the coverage of the common electrode layer 3, thereby affecting the aperture ratio of the pixel area 17 in the display panel.

[0071] As shown in Figures 4 and 5, in some embodiments, a common electrode line 6 connected to the common electrode layer 3, a plurality of gate lines 4 spaced apart along a first direction (such as the Y direction in Figure 5), and a plurality of data lines 9 spaced apart along a second direction (such as the X direction in Figure 5) are provided on the side of the flat layer 2 close to the base substrate 1. The gate lines 4 and the data lines 9 are insulated and overlapped, and the gate lines 4 and the common electrode lines 6 are separated and arranged in the same layer; a common electrode compensation line 10 is provided on the side of the common electrode layer 3 away from the base substrate 1, and the common electrode compensation line 10 at least partially corresponds to the gate line 4 or the data line 9, and the common electrode compensation line 10 is connected to the common electrode layer 3.

[0072] Exemplarily, the common electrode compensation line 10 is in contact with and connected to the common electrode layer 3 .

[0073] Since the common electrode compensation line 10 is arranged on the side of the common electrode layer 3 away from the base substrate 1, the common electrode compensation line 10 and the gate line 4 or the data line 9 are not in the same structural layer. In other words, the setting position of the common electrode compensation line 10 does not need to avoid the gate line 4 or the data line 9. When selecting the setting position of the common electrode compensation line 10, not affecting the aperture ratio of the pixel area 17 can be taken as the main consideration.

[0074] Taking the direction shown in FIG. 5 as an example, multiple gate lines 4 are spaced apart in the longitudinal direction, each extending in the transverse direction; multiple data lines 9 are spaced apart in the transverse direction, each extending in the longitudinal direction. The gate lines 4 and data lines 9 are located between two adjacent pixel regions 17. When the common electrode compensation line 10 is positioned to correspond to the position of the gate line 4 or the position of the data line 9 (the common electrode compensation line 10 corresponds to the position of the gate line 4 in FIG. 5 ), the adverse effect of the common electrode compensation line 10 on the aperture ratio of the pixel region 17 can be effectively reduced.

[0075] The common electrode compensation line 10 is connected to the common electrode layer 3 to form a parallel resistor effect, so as to achieve the function of balancing the common electrode voltage in the display panel.

[0076] As shown in Figure 5, in some embodiments, the array substrate includes a display area 15 and a non-display area 16 arranged at least on one side of the display area 15; a plurality of the gate lines 4 and the data lines 9 are overlapped and arranged in the display area 15, the common electrode line 6 is arranged in the non-display area 16, the orthographic projection of the common electrode compensation line 10 on the common electrode layer 3 is a first projection, the orthographic projection of the common electrode line 6 on the common electrode layer 3 is a second projection, there is an overlapping area 302 between the first projection and the second projection, and the common electrode layer 3 in the overlapping area 302 is connected to the common electrode line 6.

[0077] Exemplarily, the common electrode layer 3 and the common electrode line 6 are connected through a via structure.

[0078] Taking the direction shown in FIG. 5 as an example, the non-display area 16 can be provided on at least one of the upper, lower, left, and right sides of the display area 15. The common electrode line 6 is provided within the non-display area 16. The common electrode line 6 transmits the common electrode voltage to the common electrode layer 3 from the position where it connects to the common electrode layer 3. In this embodiment, the common electrode compensation line 10 extends to the connection position between the common electrode layer 3 and the common electrode line 6, which enables the parallel resistance effect it generates on the common electrode layer 3 to be more uniform, further improving the balancing effect of the common electrode compensation line 10 on the common electrode voltage.

[0079] As shown in Figure 5, in some embodiments, the non-display area 16 of the array substrate is arranged around the display area 15, and the common electrode line 6 is a ring line surrounding the display area 15; the common electrode compensation line 10 corresponds one-to-one with the gate line 4, or corresponds one-to-one with the data line 9; there is an overlapping area 302 between the two ends of the first projection of each common electrode compensation line 10 and the second projection of the common electrode line 6.

[0080] To improve the uniformity of the common electrode voltage, the common electrode line 6 is configured as a ring line, and the common electrode layer 3 is connected to opposite sides of the ring line through via structures. Accordingly, both ends of the common electrode compensation line 10 also extend to the via structures on both sides, further improving the balancing effect of the common electrode compensation line 10 on the common electrode voltage.

[0081] As shown in Figure 6, in some embodiments, the common electrode compensation line 10 is further provided with a spacer 18 on the side away from the base substrate 1; the common electrode compensation line 10 is provided with an island structure 1001, the width of the island structure 1001 is greater than the width of other common electrode compensation lines 10 except the island structure 1001, and the island structure 1001 is provided with a supporting plane 1002 on the side facing the spacer 18, and the positive projection of the spacer 18 on the common electrode compensation line 10 is at least partially located within the supporting plane 1002.

[0082] Exemplarily, the location of the island structure 1001 also corresponds to the location of the thin film transistor 8 , that is, the island structure 1001 is located directly above the thin film transistor 8 .

[0083] Exemplarily, the thickness of the island structure 1001 is the same as the thickness of other common electrode compensation lines 10 except the island structure 1001 .

[0084] The setting position of the island structure 1001 corresponds to the setting position of the spacer 18, and can provide a relatively flat setting base for the spacer 18 through the supporting plane 1002, thereby preventing the spacer 18 from sliding due to the uneven setting base, thereby causing defects in the display panel.

[0085] The orthographic projection of the spacer 18 on the common electrode compensation line 10 is at least partially located within the supporting plane 1002, that is, the projection may be located within the supporting plane 1002; or, the projection completely covers the supporting plane 1002 and is still partially located outside the supporting plane 1002; or, only a portion of the projection is located within the supporting plane 1002 and does not completely cover the supporting plane 1002, and the other portion is located outside the supporting plane 1002.

[0086] In order to provide a larger carrying plane 1002 , the width of the island structure 1001 is greater than the width of other common electrode compensation lines 10 except the island structure 1001 .

[0087] Based on the same inventive concept and in combination with the description of the array substrates of the above embodiments, this embodiment provides a display panel having the corresponding technical effects of the array substrates of the above embodiments, which will not be described in detail here.

[0088] As shown in FIG7 , a display panel includes a color filter substrate and an array substrate as described in the above embodiments; the color filter substrate is provided with a black matrix, and the orthographic projection of the black matrix on the base substrate 1 forms a first sub-dark area 1401;

[0089] The array substrate includes a plurality of overlapping gate lines 4 and data lines 9 to form a plurality of pixel areas 17, each of the pixel areas 17 is provided with at least two domain display areas 1701, each of the domain display areas 1701 includes a slit 1702 provided in the common electrode layer 3 or the pixel electrode layer 11, and the directions of the slits 1702 in adjacent domain display areas 1701 are different, so that an intersection domain area is formed between two adjacent domain display areas 1701; the orthographic projection of each intersection domain area on the base substrate 1 forms a second sub-dark area 1402 that intersects with the first sub-dark area 1401, and all the second sub-dark areas 1402 and the first sub-dark areas 1401 form a total dark area 14;

[0090] The array substrate further includes a common electrode compensation line 10 , and an orthographic projection of the common electrode compensation line 10 on the base substrate 1 is located within the total dark area 14 .

[0091] Exemplarily, the black matrix has a grid-like structure, one of its functions being to cover the gate lines 4 and the data lines 9. The location of the first sub-dark area 1401 formed by the orthographic projection of the black matrix on the base substrate 1 is shown in FIG7 . Typically, the width of the portion of the first sub-dark area 1401 corresponding to the gate line 4 is greater than the width of the gate line 4, and the width of the portion of the first sub-dark area 1401 corresponding to the data line 9 is also greater than the width of the data line 9.

[0092] Exemplarily, the common electrode layer 3 has a full-plate structure, with at least one pixel electrode disposed within each pixel region 17, and all pixel electrodes forming the pixel electrode layer 11. Slits 1702 are disposed in the pixel electrodes 11. The location of the second sub-dark area 1402 formed by the orthographic projection of the intersection region on the substrate 1 is shown in FIG7 . It can be seen that the second sub-dark area 1402 formed by the intersection region of each row of pixel regions 17 intersects with the first sub-dark area 1401, and all second sub-dark areas 1402 and first sub-dark areas 1401 form a grid-like total dark area 14.

[0093] The orthographic projection of the common electrode compensation line 10 on the base substrate 1 is located in the total dark area 14, that is, the common electrode compensation line 10 can be arranged only in the first sub-dark area 1401, or in the second sub-dark area 1402, or part of it can be arranged in the second sub-dark area 1402 and the other part can be arranged in the first sub-dark area 1401.

[0094] When the common electrode compensation line 10 is disposed only within the first sub-dark area 1401, the common electrode compensation line 10 may be located directly above the gate line 4 or directly above the data line 9 (as shown in FIG4 ). The width of the common electrode compensation line 10 located directly above the gate line 4 may be less than, equal to, or greater than the width of the gate line 4, but the width of the common electrode compensation line 10 must be less than the width of the first sub-dark area 1401 covering the gate line 4. Similarly, the width of the common electrode compensation line 10 located directly above the data line 9 may be less than, equal to, or greater than the width of the data line 9, but the width of the common electrode compensation line 10 must be less than the width of the first sub-dark area 1401 covering the data line 9.

[0095] When a portion of the common electrode compensation line 10 is located in the second sub-dark area 1402 , it is necessary to ensure that the width of this portion is smaller than the width of the second sub-dark area 1402 .

[0096] The above situation is the disposition method of the common electrode compensation line 10 when the pixel region 17 has a 1P2D (1 pixel 2 domain) structure.

[0097] In some embodiments, there is no intersection region in the pixel area 17 , and accordingly, there is no second sub-dark area 1402 . In this case, the orthographic projection of the common electrode compensation line 10 on the base substrate 1 is within the first sub-dark area 1401 .

[0098] Based on the same inventive concept and in combination with the description of the array substrates of the above embodiments, this embodiment provides a method for preparing the array substrates of the above embodiments. This method has the corresponding technical effects of the array substrates of the above embodiments, which will not be repeated here.

[0099] The common electrode compensation lines 10 are typically fabricated after the common electrode layer 3 is formed, using patterning processes such as film formation, exposure, and etching to form the common electrode compensation lines 10 on the already formed common electrode layer 3. This approach increases the complexity of the array substrate manufacturing process, increases process costs, and limits production capacity.

[0100] In view of this, as shown in FIG8 , an embodiment of the present application provides a method for preparing the array substrate according to each of the above embodiments, comprising:

[0101] Step S100, providing a stacked flat layer, a first electrode layer, a first conductive layer and a photoresist layer, wherein the flat layer is provided with the first via hole, the first conductive layer is provided with a first through hole corresponding to the first via hole, the photoresist layer includes a second through hole corresponding to the first through hole, a first portion excluding the second through hole, and a second portion, and the thickness of the first portion is greater than the thickness of the second portion.

[0102] As shown in Figures 10 and 11, after forming the planar layer 2, this embodiment first stacks and lays the first electrode layer 19 for forming the common electrode layer 3 and the first conductive layer 20 for forming the common electrode compensation line 10. Different from the layer-by-layer forming method in the related art, this embodiment first performs regional forming after laying the first electrode layer 19 and the first conductive layer 20. That is, each structural layer is formed in the area corresponding to the first via hole 201. For example, the second through hole 2101 is formed at the position of the photoresist layer 21 corresponding to the first via hole 201, and the first through hole 2001 is formed at the position of the first conductive layer 20 corresponding to the first via hole 201.

[0103] At the same time, the portion of the photoresist layer 21 excluding the second through-hole 2101 is configured as a first portion 2102 and a second portion 2103 of different thicknesses, thereby enabling the patterning of both the common electrode layer 3 and the common electrode compensation line 10 to be completed using the same photoresist layer 21. The thicker first portion 2102 can serve as a shielding layer when etching the first conductive layer 20 to form the common electrode compensation line 10, thereby protecting the patterned area of ​​the common electrode compensation line 10, as shown in FIG14. The thinner second portion 2103 can serve as a shielding layer when etching the first conductive layer 20 to form the first through-hole 2001, thereby protecting the area of ​​the first conductive layer 20 excluding the pattern of the first through-hole 2001, as shown in FIG11. The second portion 2103 can also serve as a shielding layer when etching the first electrode layer 19 to form the common electrode layer 3, thereby protecting the area of ​​the common electrode layer 3 excluding the pattern of the second via 301, as shown in FIG12.

[0104] As shown in FIG. 18 , in some embodiments, a method for forming the first conductive layer 20 including the first through hole 2001 and forming the photoresist layer 21 may include the following steps:

[0105] Step S010, providing the stacked flat layer, the first electrode layer, the first conductive layer to be formed, and the photoresist layer to be formed, wherein the flat layer is provided with the first via hole, and the thickness of the photoresist layer to be formed is not less than the thickness of the first part of the photoresist layer.

[0106] As shown in FIG9 , the first electrode layer 19 covers the planar layer 2 and the first via hole 201 , the first conductive layer 23 to be formed covers the first electrode layer 19 , and the photoresist 24 to be formed covers the first conductive layer 23 to be formed.

[0107] Step S020 , exposing and developing the photoresist layer to be formed through a semi-transparent mask to form the photoresist layer.

[0108] The formed photoresist layer 21 is shown in FIG. 10 .

[0109] In order to achieve different thicknesses in different regions of the photoresist layer 24 with originally uniform thickness after one exposure and development using the half tone mask 22 (HT mask), the half tone mask 22 needs to be divided into regions and the light transmittance of each region needs to be set.

[0110] The area division of the semi-transparent mask 22 may be performed with reference to the area design of the photoresist layer 21 .

[0111] As shown in Figure 19, in some embodiments, the semi-transparent mask 22 includes a first light-transmitting pattern 2201, a second light-transmitting pattern 2202 and a third light-transmitting pattern 2203 with different light transmittances, so that the photoresist layer 24 to be formed forms the second through hole 2101, the first part 2102 and the second part 2103 with different thicknesses.

[0112] Since the photoresist layer 21 to be formed includes three areas: the second through hole 2101, the first part 2102 and the second part 2103, the semi-transparent mask 22 is also correspondingly configured to include a first light-transmitting pattern 2201 corresponding to the position and pattern (including shape and size) of the second through hole 2101, a second light-transmitting pattern 2202 corresponding to the position and pattern of the first part 2102, and a third light-transmitting pattern 2203 corresponding to the position and pattern of the second part 2103.

[0113] After the semi-transparent mask 22 is divided into regions, the light transmittance of each region needs to be designed.

[0114] As shown in FIG19 , in some embodiments, the light transmittance of the first light-transmitting pattern 2201 is 100%, the light transmittance of the second light-transmitting pattern 2202 is 0%, and the light transmittance of the third light-transmitting pattern 2203 is less than or equal to 20% and greater than 0%.

[0115] For the first light-transmitting pattern 2201, since the corresponding area needs to form the second through hole 2101 of the photoresist layer 21 after exposure and development, that is, the photoresist layer material (such as PR glue, or photoresist) in this area needs to be completely removed, the light transmittance of the first light-transmitting pattern 2201 can be designed to be 100% (the arrows in Figure 19 represent the light during exposure).

[0116] Regarding the second light-transmitting pattern 2202, since the area corresponding thereto needs to form the first portion 2102 of the photoresist layer 21 after exposure and development, and the first portion 2102 has the greatest thickness among the second through-hole 2101, the first portion 2102, and the second portion 2103 of the photoresist layer 21, the photoresist material in this area does not need to be removed (it is sufficient to ensure that the thickness of the photoresist layer 24 to be formed is the same as the thickness of the first portion 2102 of the photoresist layer 21). Therefore, the light transmittance of the second light-transmitting pattern 2202 can be designed to be 0%.

[0117] Regarding the third light-transmitting pattern 2203, since the area corresponding thereto needs to form the second portion 2103 of the photoresist layer 21 after exposure and development, and the thickness of the second portion 2103 is intermediate among the second through-hole 2101, the first portion 2102, and the second portion 2103 of the photoresist layer 21, that is, the photoresist material in this area needs to be removed but cannot be completely removed, the light transmittance of the third light-transmitting pattern 2203 can be designed to be between 0% and 100%.

[0118] Specifically, the light transmittance of the third light-transmitting pattern 2203 can be selected based on the designed thickness of the second portion 2103 and the light intensity during exposure. In other words, to meet process requirements, the photoresist layer 21 formed after exposure and development must not only have no material residue in the area corresponding to the first via 201, but also have a thickness of the second portion 2103 that is no less than the designed thickness.

[0119] In order to achieve the above effects, the applicant conducted multiple experiments.

[0120] First, the light transmittance of the third light-transmitting pattern 2203 is set to 30%. The light intensity during exposure is set to such an intensity that, after light passes through the third light-transmitting pattern 2203, the thickness of the corresponding photoresist layer 24 to be formed reaches the designed thickness. After exposure and development, residual material of the photoresist layer to be formed exists at the position corresponding to the first via 201. As shown in Figure 20, the darker areas within the elongated circle within the dashed box indicate areas of residual material.

[0121] Next, the light intensity during exposure was increased while the light transmittance of the third light-transmitting pattern 2203 was reduced. The light transmittance of the third light-transmitting pattern 2203 was set to 25%, and the light intensity during exposure was still set at this intensity. After light passed through the third light-transmitting pattern 2203, the thickness of the corresponding photoresist layer 21 to be formed reached the designed thickness. After exposure and development, residual material from the photoresist layer 21 to be formed still remained at the location corresponding to the first via 201. As shown in Figure 21, the darker areas within the dotted circle still exist, but the extent of these darker areas has been reduced.

[0122] Next, the light intensity during exposure is increased, while the light transmittance of the third light-transmitting pattern 2203 is decreased. The light transmittance of the third light-transmitting pattern 2203 is set to 20%, and the light intensity during exposure is still set to this intensity. After light passes through the third light-transmitting pattern 2203, the thickness of the corresponding photoresist layer 21 to be formed reaches the designed thickness. After exposure and development, the location corresponding to the first via 201 is free of material from the photoresist layer 21 to be formed. As shown in Figure 22, the darker areas within the elongated circle within the dashed box are no longer visible.

[0123] Through comparative analysis of the above experimental results, it can be determined that the light intensity required for forming the photoresist layer 21 through the exposure and development process is the required light intensity. Furthermore, under this light intensity, the light transmittance of the third light-transmitting pattern 2203 of the semi-transparent mask 22 must be set to be less than or equal to 20% to ensure that the thickness of the second portion 2103 of the formed photoresist layer 21 is not less than the designed thickness.

[0124] In step S030 , the photoresist layer is used as a shielding layer to remove a portion of the first conductive layer to be formed corresponding to the first via hole, so that the portion forms the first through hole, and the first conductive layer to be formed forms a first conductive layer.

[0125] As shown in Figures 10 and 11, after the photoresist layer 21 is formed, the first conductive layer 23 to be formed can be etched with the aid of the photoresist layer 21 to form first through-holes 2001 at the etched locations, thereby forming the first conductive layer 23 to be formed into the first conductive layer 20. It should be noted that after the formation of the first through-holes 2001, the first conductive layer 20 has not yet formed the final design pattern, namely, the common electrode compensation line 10. One purpose of this step is to expose the portion of the first electrode layer 19 corresponding to the first through-hole 201, so as to facilitate the subsequent removal of this portion of the first electrode layer 19 to form the second through-hole 301 in the first electrode layer 19.

[0126] After forming the first conductive layer 20, the exposed first electrode layer 19 can be etched to form second vias 301 in the first electrode layer 19, as shown in Figure 12. At this point, the first electrode layer 19 has reached the final design pattern, forming the common electrode layer 3. Subsequently, the second portion 2103 of the photoresist layer 21 is removed by ashing. However, since the first portion 2102 of the photoresist layer 21 is thicker than the second portion 2103, some thickness remains after ashing, as shown in Figure 13. At this point, the portion of the first conductive layer 20 that needs to be etched is exposed, while the portion of the first conductive layer 20 that needs to be retained can be protected by the remaining first portion 2102 of the photoresist layer 21.

[0127] [Corrected 08.08.2024 according to Rule 91] However, the applicant has discovered that if this method is used, after forming the second via hole 301, the hole wall of the first via hole 201 in the planar layer 2 will be exposed, as shown in Figure 12. When the second portion 2103 of the photoresist layer 21 is subsequently ashed, the hole wall of the first via hole 201 will be etched by the ashing atmosphere, causing the hole wall to shrink inward, that is, the aperture of the first via hole 201 will increase, thereby causing the aforementioned portion of the common electrode layer 3 near the second via hole 301 to be suspended, as shown in Figure 13.

[0128] In view of this, in this embodiment, after forming the first conductive layer 20, the following steps are performed:

[0129] Step S200: removing the second portion of the photoresist layer.

[0130] First, the second portion 2103 of the photoresist layer 21 is removed. At this time, the hole wall of the first via hole 201 of the flat layer 2 is still covered by the first electrode layer 19, as shown in Figure 15. Therefore, the ashing atmosphere will not have an adverse effect on the hole wall, thereby preventing the first via hole 201 from expanding uncontrollably after the flat layer 2 is formed, and preventing the common electrode layer 3 from being suspended near the second via hole 301.

[0131] In step S300 , the first conductive layer is used as a shielding layer, and a portion of the first electrode layer corresponding to the first via hole is removed to form the second via hole, and the first electrode layer forms the common electrode layer.

[0132] Since the second portion 2103 of the photoresist layer 21 has been removed, when etching the first electrode layer 19 , the second portion 2103 can no longer be relied upon to protect the portion of the first electrode layer 19 that does not need to be etched.

[0133] However, at this time, the first conductive layer 20 still covers the portion of the first electrode layer 19 that does not need to be etched, as shown in FIG15 . Therefore, the portion of the first electrode layer 19 that does not need to be etched can be protected by the first conductive layer 20. Furthermore, the portion of the first conductive layer 20 that needs to be retained is covered and protected by the first portion 2102 of the photoresist layer 21, while the portion not covered by the first portion 2102 is the portion that needs to be etched when the common electrode compensation line 10 is formed in the first conductive layer 20. Therefore, even if this portion is partially etched when the first electrode layer 19 is etched, it will not adversely affect the formation of the common electrode compensation line 10.

[0134] In order for the first conductive layer 20 to serve as a shielding layer when etching the first electrode layer 19 , it is necessary that after the first electrode layer 19 is etched, the first conductive layer 20 can still cover the portion of the first electrode layer 19 that does not need to be etched.

[0135] In view of this, step S300 includes: removing the portion of the first electrode layer 19 corresponding to the first via 201 by a first etching solution to form the second via 301; wherein the etching rate of the first etching solution on the first electrode layer 19 is greater than the etching rate on the first conductive layer 20; the orthographic projection of the second via 301 on the first conductive layer 20 completely covers the first through hole 2001.

[0136] Typically, the material of the first electrode layer 19 is indium tin oxide (ITO), and the material of the first conductive layer 20 can be a metal such as copper (Cu) or aluminum (Al). The first etchant used to etch the first electrode layer 19 does not have strong etching ability for these metals, that is, the etching rate of the first etchant on the first electrode layer 19 is greater than the etching rate on the first conductive layer 20. The microstructure of the first electrode layer 19 after etching is shown in Figures 23 and 24.

[0137] When etching the first electrode layer 19, due to over-etching, the walls of the formed second via hole 301 are not aligned with the walls of the first through hole 2001, but are somewhat indented compared to the walls of the first through hole 2001, as shown in the dotted box in FIG16 . Therefore, the orthographic projection of the formed second via hole 301 on the first conductive layer 20 completely covers the first through hole 2001, that is, the aperture of the second via hole 301 is larger than that of the first through hole 2001. This further ensures that the common electrode layer 3 adjacent to the second via hole 301 is reliably supported by the planar layer 2.

[0138] In step S400 , the first portion of the photoresist layer is used as a shielding layer, and a portion of the first conductive layer corresponding to the second portion of the photoresist layer is removed, so that the first conductive layer forms the common electrode compensation line.

[0139] Finally, the first conductive layer 20 is etched to remove the portion of the first conductive layer 20 not covered by the first portion 2102 of the photoresist layer 21, as shown in Figure 17. The microstructure of the first electrode layer 19 after etching is complete is shown in Figures 25 and 26. At this point, the first conductive layer 20 has become the final design pattern, forming the common electrode compensation line 10.

[0140] Based on the same inventive concept and in combination with the description of the array substrate and display panel of the above embodiments, this embodiment provides a display device. The method has the corresponding technical effects of the array substrate of the above embodiments, which will not be repeated here.

[0141] A display device includes the array substrate or the display panel according to the above embodiments.

[0142] It should be noted that the above description is limited to some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in an order different from that described in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0143] The various embodiments in this application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0144] The description of this application is provided for purposes of illustration and description and is not intended to be exhaustive or to limit the application to the disclosed form. Many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the application and to enable those skilled in the art to understand the application and design various embodiments with various modifications suitable for specific applications.

[0145] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. Within the scope of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0146] While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0147] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of this application.

Claims

1. An array substrate, characterized in that: The invention comprises a base substrate, a flat layer and a common electrode layer, wherein the flat layer is arranged on one side of the base substrate, and the flat layer has a plurality of first via holes penetrating the flat layer along the thickness direction of the flat layer; the common electrode layer is arranged on a side of the flat layer away from the base substrate, and the common electrode layer has a plurality of second via holes penetrating the common electrode layer along the thickness direction of the common electrode layer, and the orthographic projections of the second via holes on the base substrate completely cover the orthographic projections of the first via holes on the base substrate.

2. The array substrate according to claim 1, characterized in that: The array substrate further comprises a common electrode line, a plurality of gate lines and a plurality of data lines, wherein the common electrode line, the plurality of gate lines and the plurality of data lines are all arranged between the planar layer and the base substrate, the common electrode line is connected to the common electrode layer, the plurality of gate lines are arranged along a first direction, the plurality of data lines are arranged along a second direction, the first direction intersects the second direction, and the common electrode layer and the plurality of gate lines are arranged in the same layer; The array substrate also includes a common electrode compensation line, which is arranged on a side of the common electrode layer away from the base substrate, and the orthographic projection of the common electrode compensation line on the base substrate at least partially overlaps with the orthographic projection of the multiple gate lines or the multiple data lines on the base substrate, and the common electrode compensation line is connected to the common electrode layer.

3. The array substrate according to claim 2, characterized in that: The array substrate further comprises a plurality of spacers, and the plurality of spacers are arranged on a side of the common electrode compensation line away from the base substrate; The common electrode compensation line includes an island structure, the width of the island structure is greater than the width of the common electrode compensation line at other parts, the island structure has a bearing plane on the side facing the spacer, and the orthographic projection of the spacer on the base substrate is located within the orthographic projection of the bearing plane on the base substrate.

4. The array substrate according to claim 2, characterized in that: The array substrate comprises a display area and a non-display area arranged at least on one side of the display area; the plurality of gate lines and the plurality of data lines are arranged in the display area, and the common electrode line is arranged in the non-display area; The common electrode layer in the overlapping area between the first projection and the second projection is connected to the common electrode line, the first projection is the orthographic projection of the common electrode compensation line on the common electrode layer, and the second projection is the orthographic projection of the common electrode line on the common electrode layer.

5. The array substrate according to claim 4, characterized in that: The non-display area of ​​the array substrate is arranged around the display area, and the common electrode line is a ring line surrounding the display area; The orthographic projections of the plurality of gate lines or the plurality of data lines on the base substrate are within the orthographic projections of the common electrode compensation line on the base substrate; each of the first projections has an overlap region at both ends in its length direction.

6. The array substrate according to claim 1, characterized in that: The first via hole is a tapered hole, and the slope angle of the hole wall of the first via hole is 50° to 60°; wherein the slope angle of the hole wall is the angle between the hole wall and the plane where the substrate is located.

7. The array substrate according to claim 1, characterized in that: The first via hole comprises a first opening facing the common electrode layer and a second opening away from the common electrode layer; a diameter of the first opening is greater than a diameter of the second opening; A minimum distance between an edge of the second via and an edge of the first opening is 1.7 micrometers to 3.2 micrometers.

8. A display panel, characterized in that: It comprises the array substrate as described in claims 1 to 7.

9. The display panel according to claim 8, characterized in that: The display panel further comprises a color filter substrate, wherein the color filter substrate comprises a black matrix; the array substrate comprises a plurality of pixel regions, each of which comprises at least two domain display regions; The array substrate also includes a common electrode compensation line, the orthographic projection of the common electrode compensation line on the base substrate is located within the total dark area, the total dark area includes a first sub-dark area and a second sub-dark area intersecting the first sub-dark area, the first sub-dark area is the orthographic projection of the black matrix on the base substrate, the second sub-dark area is the set of orthographic projections of all intersection domain areas on the base substrate, and each intersection domain area is a transition area between two adjacent domain display areas in the pixel area.

10. The display panel according to claim 9, characterized in that: The orthographic projections of the common electrode compensation lines on the base substrate are all located within the first sub-dark area.

11. A method for preparing the array substrate according to any one of claims 1 to 7, characterized in that: include: Providing a planar layer, a first electrode layer, a first conductive layer and a photoresist layer which are stacked, wherein the planar layer has the first via hole, the first conductive layer is provided with a first through hole corresponding to the first via hole, the photoresist layer includes a second through hole corresponding to the first via hole, a first portion corresponding to the common electrode compensation line, and a second portion other than the second through hole and the first portion, and the thickness of the first portion is greater than the thickness of the second portion; removing the second portion of the photoresist layer; The portion of the first electrode layer not covered by the first conductive layer is removed to form the common electrode layer having the second via hole.

12. The method according to claim 11, characterized in that The removing the portion of the first electrode layer not covered by the first conductive layer to form the common electrode layer having the second via hole comprises: The portion of the first electrode layer not covered by the first conductive layer is removed by a first etching solution; wherein the etching rate of the first etching solution on the first electrode layer is greater than the etching rate on the first conductive layer.

13. The method according to claim 11, characterized in that Before providing the planar layer, the first electrode layer, the first conductive layer and the photoresist layer in a stacked arrangement, the method further comprises: Providing the flat layer, the first electrode layer, the first conductive layer to be formed, and the photoresist layer to be formed, which are stacked, wherein the flat layer has the first via hole, and the thickness of the photoresist layer to be formed is not less than the thickness of the first part of the photoresist layer; Exposing and developing the photoresist layer to be formed through a semi-transparent mask to form the photoresist layer; The portion of the first conductive layer to be formed that is not covered by the photoresist layer is removed to form the first conductive layer having the first through hole.

14. The method according to claim 13, characterized in that The semi-transparent mask includes a first light-transmitting pattern, a second light-transmitting pattern and a third light-transmitting pattern with different light transmittances, so that the photoresist layer to be formed forms the second through hole, the first part and the second part with different thicknesses.

15. The method according to claim 14, characterized in that The light transmittance of the first light-transmitting pattern is 100%, the light transmittance of the second light-transmitting pattern is 0%, and the light transmittance of the third light-transmitting pattern is not more than 20% and more than 0%.

16. The method according to claim 11, characterized in that The display substrate further includes a common electrode compensation line, and the method further includes: The portion of the first conductive layer not covered by the first portion of the photoresist layer is removed to form the common electrode compensation line.

17. A display device, characterized in that: It comprises the array substrate as described in any one of claims 1 to 7, or the display panel as described in any one of claims 8 to 10.

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