Silicon carbide device and manufacturing method therefor

Abstract

A silicon carbide device, comprising: an n-type silicon carbide substrate (21), wherein an n-type silicon carbide layer (22) is formed on the n-type silicon carbide substrate (21); a plurality of gate trenches (31) are formed in the n-type silicon carbide layer (22); p-type body regions (23) are respectively formed at two sides of each gate trench (31), and the p-type body region (23) at each side comprises a first p-type body region (23a) and a second p-type body region (23b) which is located between the first p-type body region (23a) and an adjacent gate trench (31); an n-type source region (25) and a current channel region (10) are formed in each p-type body region (23); the current channel region (10) comprises a horizontal channel region (10a) and a vertical channel region (10b); two gate electrodes (27) are formed in each gate trench (31), and the two gate electrodes (27) are respectively located at two side walls of the gate trench (31) and respectively extend to positions above horizontal channel regions (10a) at respective corresponding sides; each gate electrode (27) is insulated and isolated from the n-type silicon carbide layer (22) by means of a gate insulating layer (26) between the gate electrode (27) and the n-type silicon carbide layer (22); and each gate electrode (27) is configured to control the turning-on and turning-off of a current channel region (10) by means of a gate voltage.

Description

Silicon carbide device and manufacturing method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 16, 2023, with application number 202310715907.5. The entire contents of the above application are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the technical field of silicon carbide devices, and for example relates to a silicon carbide device and a method for manufacturing the same. Background Art

[0003] As a representative of the third generation of wide-bandgap semiconductor materials, silicon carbide (SiC) boasts a wide bandgap, high critical breakdown electric field, high thermal conductivity, and high electron saturation drift velocity. It holds broad application prospects in high-power, high-temperature, and high-frequency power electronics. Planar SiC devices have low mobility, and the parasitic junction field-effect transistor (JFET) resistance increases their on-resistance, resulting in a larger chip area. Trench SiC devices eliminate the parasitic JFET resistance found in planar SiC devices, reducing cell size and significantly increasing current density. Consequently, trench SiC devices have gradually replaced planar SiC devices and become the mainstream. SiC devices typically use silicon dioxide as the gate dielectric material. Because SiC has a dielectric constant approximately 2.5 times that of SiO2, the gate dielectric experiences approximately 2.5 times the drift layer electric field when the SiC device is in the blocking state. In trench-type silicon carbide devices, the electric field distribution at the bottom corner of the gate trench is concentrated, making the gate dielectric layer at the bottom corner of the gate trench more likely to be broken down before the silicon carbide device undergoes avalanche breakdown, thereby affecting the withstand voltage of the silicon carbide device and thus affecting the reliability and stability of the device.

[0004] Summary of the Invention

[0005] The present application provides a silicon carbide device and a manufacturing method thereof, so as to improve the voltage resistance of the silicon carbide device and reduce the on-resistance of the silicon carbide device.

[0006] An embodiment of the present application provides a silicon carbide device, comprising:

[0007] n-type silicon carbide substrate;

[0008] An n-type silicon carbide layer is formed on the n-type silicon carbide substrate;

[0009] A plurality of gate trenches are formed in the n-type silicon carbide layer;

[0010] A p-type body region is formed on both sides of each gate trench, the p-type body region on each side including a first p-type body region and a second p-type body region located between the first p-type body region and an adjacent gate trench, the depth of the second p-type body region being less than the depth of the first p-type body region, and the depth of the gate trench being less than the depth of the first p-type body region and greater than the depth of the second p-type body region;

[0011] An n-type source region and a current channel region are formed in each p-type body region, wherein the current channel region includes a horizontal channel region and a vertical channel region;

[0012] Two gates are formed in each gate trench, and the two gates are respectively located at the two side walls of each gate trench and extend respectively to the horizontal channel region on each corresponding side. The gates are insulated and isolated from the n-type silicon carbide layer by a gate insulation layer between the gates and the n-type silicon carbide layer. The gates are configured to control the opening and closing of the current channel region by a gate voltage.

[0013] Optionally, the thickness of the gate insulation layer at the bottom of the gate trench is greater than the thickness of the gate insulation layer at the sidewall of the gate trench.

[0014] Optionally, the n-type source region is located in a first p-type body region among the p-type body regions, and the horizontal channel region is located in a second p-type body region among the p-type body regions.

[0015] Optionally, the n-type source region is located in a first p-type body region of the p-type body regions, and the horizontal channel region is located in a second p-type body region of the p-type body regions and extends to the first p-type body region of the p-type body regions.

[0016] Optionally, the n-type source region is located in a first p-type body region of the p-type body region and extends to a second p-type body region of the p-type body region, and the horizontal channel region is located in the second p-type body region of the p-type body region.

[0017] Optionally, the silicon carbide device further includes a p-type body region contact region located in each of the first p-type body regions.

[0018] Optionally, the silicon carbide device further includes an n-type doped region located in the n-type silicon carbide layer and below each gate trench, and each n-type doped region overlaps with a gap between two gates in its corresponding gate trench.

[0019] The present application also provides a method for manufacturing a silicon carbide device, comprising:

[0020] forming an n-type silicon carbide layer on an n-type silicon carbide substrate;

[0021] forming a first insulating layer on the n-type silicon carbide layer;

[0022] etching the first insulating layer to form a mask pattern;

[0023] Performing vertical p-type ion implantation using the first insulating layer as a mask to form a plurality of first p-type body regions in the n-type silicon carbide layer;

[0024] Using the first insulating layer as a mask, perform p-type ion implantation tilted toward one side of each first p-type body region to form a second p-type body region located on one side of each first p-type body region in the n-type silicon carbide layer;

[0025] Using the first insulating layer as a mask, perform p-type ion implantation obliquely toward the other side of each first p-type body region to form a second p-type body region located on the other side of each first p-type body region in the n-type silicon carbide layer. The plurality of first p-type body regions and the plurality of second p-type body regions form a plurality of p-type body regions of the silicon carbide device.

[0026] Etching away the first insulating layer and performing n-type ion implantation to form an n-type source region in each p-type body region;

[0027] Etching the n-type silicon carbide layer to form a plurality of gate trenches in the n-type silicon carbide layer;

[0028] forming a gate insulating layer on the bottom and sidewall surfaces of each gate trench and the surface of the n-type silicon carbide layer;

[0029] A first conductive layer is formed on the surface of the gate insulating layer, and the first conductive layer is etched to form two gates in each gate trench. The two gates are respectively located at two side walls of each gate trench and extend to the horizontal channel region on each corresponding side.

[0030] Optionally, the method for manufacturing a silicon carbide device further includes: performing n-type ion implantation into the n-type silicon carbide layer through a gap between two gates in each gate trench, thereby forming an n-type doped region in the n-type silicon carbide layer located below each gate trench.

[0031] Optionally, the method for manufacturing a silicon carbide device further includes, before forming an n-type source region in each p-type body region: performing p-type ion implantation to form a p-type body region contact region in each p-type body region. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The following is a brief introduction to the drawings needed to describe the embodiments. In the drawings, the thickness of the layers and regions are exaggerated for ease of explanation, and the sizes shown do not represent actual sizes. The drawings are schematic diagrams of idealized embodiments of the present application, and the embodiments shown in the present application should not be considered to be limited to the specific shapes of the regions shown in the drawings, but include the resulting shapes, such as deviations caused by manufacturing. For example, the curves obtained by etching usually have curved or rounded characteristics, but in the embodiments of the present application, they are all represented by rectangles. The representations in the figures are schematic, but this should not be considered to limit the scope of the present application.

[0033] FIG1 is a schematic diagram of the cross-sectional structure of a silicon carbide device provided in an embodiment of the present application;

[0034] FIG2 is a schematic cross-sectional view of a structure in which an n-type silicon carbide layer is formed in a method for manufacturing a silicon carbide device according to an embodiment of the present application;

[0035] 3 is a schematic cross-sectional view of a structure in which a first p-type body region is formed in a method for manufacturing a silicon carbide device according to an embodiment of the present application;

[0036] 4 is a schematic cross-sectional view of a second p-type body region formed on one side of a first p-type body region in a method for manufacturing a silicon carbide device according to an embodiment of the present application;

[0037] 5 is a schematic cross-sectional view of a second p-type body region formed on the other side of the first p-type body region in a method for manufacturing a silicon carbide device according to an embodiment of the present application;

[0038] 6 is a schematic cross-sectional view of a p-type body contact region formed in a method for manufacturing a silicon carbide device according to an embodiment of the present application;

[0039] 7 is a schematic cross-sectional view of a first p-type body region and a second p-type body region formed in a method for manufacturing a silicon carbide device according to an embodiment of the present application;

[0040] 8 is a schematic cross-sectional view of the structure of an n-type source region formed in a method for manufacturing a silicon carbide device according to an embodiment of the present application;

[0041] 9 is a schematic cross-sectional view of a gate trench formed in a method for manufacturing a silicon carbide device according to an embodiment of the present application;

[0042] 10 is a schematic cross-sectional view of a structure in which a gate insulating layer and a gate are formed in a method for manufacturing a silicon carbide device according to an embodiment of the present application;

[0043] FIG11 is a schematic cross-sectional view of the structure of an n-type doped region formed in a method for manufacturing a silicon carbide device according to an embodiment of the present application;

[0044] FIG12 is a flow chart of a method for manufacturing a silicon carbide device according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] Figure 1 is a schematic diagram of the cross-sectional structure of a silicon carbide device provided in an embodiment of the present application. As shown in Figure 1, the silicon carbide device includes an n-type silicon carbide substrate 21, an n-type silicon carbide layer 22 located on the n-type silicon carbide substrate 21, and a plurality of gate trenches 31 located in the n-type silicon carbide layer 22. For ease of display, only two gate trenches 31 are shown as an example in the embodiment of the present application.

[0046] The p-type body region 23 is located in the n-type silicon carbide layer 22 and on both sides of the gate trench 31. The p-type body region 23 includes a first p-type body region 23a and a second p-type body region 23b located between the first p-type body region 23a and the gate trench 31. The depth of the second p-type body region 23b is less than the depth of the first p-type body region 23a. At the same time, the depth of the gate trench 31 is less than the depth of the first p-type body region 23a and greater than the depth of the second p-type body region 23b.

[0047] An n-type source region 25 and a current channel region 10 are located within the p-type body region 23. The current channel region 10 includes a horizontal channel region 10a and a vertical channel region 10b. The vertical channel region 10b is located within the second p-type body region 23b. Alternatively, the n-type source region 25 is located within the first p-type body region 23a, and the horizontal channel region 10a is located within the second p-type body region 23b. Alternatively, the n-type source region 25 is located within the first p-type body region 23a, and the horizontal channel region 10a is located within the second p-type body region 23b and extends into the first p-type body region 23a. Alternatively, the n-type source region 25 is located within the first p-type body region 23a and extends into the second p-type body region 23b, and the horizontal channel region 10a is located within the second p-type body region 23b. In the embodiment of the present application, it is taken as an example that the n-type source region 25 is located in the first p-type body region 23 a , and the horizontal channel region 10 a is located in the second p-type body region 23 b and extends into the first p-type body region 23 a .

[0048] The p-type body region contact region 24 is located in the first p-type body region 23 a . The p-type body region contact region 24 can reduce the contact resistance when the p-type body region 23 is connected to an external electrode.

[0049] Two gates 27 are located within the gate trench 31. The two gates 27 are located on the two sidewalls of the gate trench 31 and extend above the horizontal channel region 10a on each corresponding side. The silicon carbide device includes a horizontal channel region 10a and a vertical channel region 10b corresponding to each gate 27. The gates 27 are insulated and isolated from the n-type silicon carbide layer 22 by a gate insulating layer 26. The material of the gate insulating layer 26 is typically silicon oxide. Optionally, the thickness of the gate insulating layer 26 at the bottom of the gate trench 31 is greater than the thickness of the gate insulating layer 26 at the sidewalls of the gate trench 31, which can improve the withstand voltage of the silicon carbide device.

[0050] The gate 27 controls the opening and closing of the current channel region 10 located in the p-type body region 23 through a gate voltage. The current channel region is an inversion layer formed in the body region when the semiconductor device is turned on.

[0051] The silicon carbide device in the embodiment of the present application may further include an n-type doped region disposed within the n-type silicon carbide layer below the gate trench, thereby reducing parasitic JFET resistance.

[0052] The current channel region of the silicon carbide device in the embodiment of the present application includes a horizontal channel region at the top and a vertical channel region on the sidewalls, overcoming the low mobility problem of planar silicon carbide devices. The embodiment of the present application also adopts a shallow gate trench structure, which not only alleviates the parasitic JFET effect but also reduces the on-resistance. At the same time, the shallow depth of the gate trench can reduce the electric field at the bottom oxide layer of the gate trench, making it less prone to breakdown, thereby improving the reliability and stability of the silicon carbide device.

[0053] Figures 2 to 11 are schematic cross-sectional views of the structures formed during the steps of the method for manufacturing a silicon carbide device according to an embodiment of the present application. A method for manufacturing a silicon carbide device according to an embodiment of the present application includes:

[0054] Step 1: As shown in Figure 2, an n-type silicon carbide layer 22 is formed on a provided n-type silicon carbide substrate 21. A first insulating layer 30 is formed on the n-type silicon carbide layer 22. The material of the first insulating layer 30 is typically silicon oxide or a stack of silicon oxide and silicon nitride. The position of the first p-type body region 23a is defined by photolithography, and then the first insulating layer 30 is etched to expose the n-type silicon carbide layer 22.

[0055] Step 2, as shown in FIG. 3 , vertical p-type ion implantation is performed using the first insulating layer 30 as a mask to form a first p-type body region 23 a in the n-type silicon carbide layer 22 .

[0056] Step 3, as shown in FIG4 , uses the first insulating layer 30 as a mask to perform p-type ion implantation tilted toward one side of each first p-type body region to form a second p-type body region 23 b located on one side of the first p-type body region 23 a in the n-type silicon carbide layer 22 .

[0057] Step 4, as shown in FIG5 , uses the first insulating layer 30 as a mask to perform p-type ion implantation at an angle toward the other side of each first p-type body region, thereby forming a second p-type body region 23b located on the other side of the first p-type body region 23a within the n-type silicon carbide layer 22. The first p-type body region 23a and the second p-type body region 23b together form the p-type body region of the silicon carbide device.

[0058] Step 5, as shown in FIG6 , the first insulating layer 30 is etched away, and then the position of the p-type body contact region 24 is defined by a photolithography process, and then p-type ion implantation is performed to form the p-type body contact region 24 in the p-type body region 23 .

[0059] In the embodiments of the present application, the structural regions of the silicon carbide device are shown as rectangles. However, in actual manufacturing processes, the edges of the structural regions of the silicon carbide device are typically curved or rounded. For example, the step-like shape between the first p-type body region 23a and the second p-type body region 23b in the embodiments of the present application will typically assume an arc shape after annealing in actual manufacturing processes. In fact, the shape between the first p-type body region 23a and the second p-type body region 23b is not a step-like shape, but an arc shape 40, as shown in Figure 7. However, for ease of illustration, the embodiment of the present application still shows the step-like shape. When the shape between the first p-type body region 23a and the second p-type body region 23b is an arc shape, the depth of the second p-type body region 23b is less than the depth of the first p-type body region 23a. This can be understood as the depth of the second p-type body region 23b on the side closest to the gate trench 31 being less than the depth of the first p-type body region 23a, or the minimum depth of the second p-type body region 23b being less than the depth of the first p-type body region 23a.

[0060] Step 6, as shown in FIG8 , defines the location of the n-type source region 25 by photolithography, and then performs n-type ion implantation to form the n-type source region 25 within the p-type body region 23 . The n-type source region 25 formed within a p-type body region 23 is located on both sides of the p-type body contact region 24 .

[0061] Step 7, as shown in FIG9 , defines the position of the gate trench 31 by a photolithography process, and then etches the n-type silicon carbide layer 22 to form a plurality of gate trenches 31 in the n-type silicon carbide layer 22 . In the embodiment of the present application, only two gate trenches 31 are shown as an example.

[0062] Step 8: As shown in FIG10 , a gate insulating layer 26 is formed on the surface of the gate trench 31 and the surface of the n-type silicon carbide layer 22. A first conductive layer is then formed on the surface of the gate insulating layer 26 and etched to form two gates 27 within the gate trench 31. The two gates 27 are located on two sidewalls of the gate trench 31 and extend onto the horizontal channel region 10 a on their respective sides.

[0063] Step 9, as shown in FIG11 , n-type ions are implanted into the n-type silicon carbide layer 22 through the gap between the two gates 27 in the same gate trench 31 to form an n-type doped region 28 below the gate trench in the n-type silicon carbide layer 22. The n-type doped region can reduce the parasitic JFET resistance.

[0064] Step 10: forming a passivation layer on the surface of the formed structure, and etching the formed passivation layer to form contact holes, and then forming a metal layer to form a silicon carbide device. This step is not shown in the figure.

[0065] As shown in FIG12 , the method for manufacturing a silicon carbide device according to an embodiment of the present application includes:

[0066] S1. forming an n-type silicon carbide layer on an n-type silicon carbide substrate;

[0067] S2. forming a first insulating layer on the n-type silicon carbide layer;

[0068] S3, etching the first insulating layer to form a mask pattern;

[0069] S4, performing vertical p-type ion implantation using the first insulating layer as a mask to form a plurality of first p-type body regions in the n-type silicon carbide layer;

[0070] S5, using the first insulating layer as a mask to perform p-type ion implantation inclined toward one side of each first p-type body region, to form a second p-type body region located on one side of each first p-type body region in the n-type silicon carbide layer;

[0071] S6. Using the first insulating layer as a mask, perform p-type ion implantation in an inclined manner toward the other side of each first p-type body region to form a second p-type body region located on the other side of each first p-type body region in the n-type silicon carbide layer. The plurality of first p-type body regions and the plurality of second p-type body regions form a plurality of p-type body regions of the silicon carbide device.

[0072] S7, etching away the first insulating layer, and performing n-type ion implantation to form an n-type source region in each p-type body region;

[0073] S8, etching the n-type silicon carbide layer to form a plurality of gate trenches in the n-type silicon carbide layer;

[0074] S9, forming a gate insulating layer on the bottom and sidewall surfaces of each gate trench and the surface of the n-type silicon carbide layer;

[0075] S10. Form a first conductive layer on the surface of the gate insulating layer, and etch the first conductive layer to form two gates in each gate trench. The two gates are respectively located at two sidewalls of each gate trench and extend to the horizontal channel region on each corresponding side.

Claims

1. A silicon carbide device, comprising: n-type silicon carbide substrate; An n-type silicon carbide layer is formed on the n-type silicon carbide substrate; A plurality of gate trenches are formed in the n-type silicon carbide layer; A p-type body region is formed on both sides of each gate trench, the p-type body region on each side includes a first p-type body region and a second p-type body region located between the first p-type body region and an adjacent gate trench, the depth of the second p-type body region is less than the depth of the first p-type body region, the depth of the gate trench is less than the depth of the first p-type body region and greater than the depth of the second p-type body region; An n-type source region and a current channel region are formed in each p-type body region, wherein the current channel region includes a horizontal channel region and a vertical channel region; Two gates are formed in each gate trench, and the two gates are respectively located at the two side walls of each gate trench and respectively extend to the horizontal channel region on each corresponding side. The gate is insulated and isolated from the n-type silicon carbide layer by a gate insulating layer between the gate and the n-type silicon carbide layer, and the gate is configured to control the opening and closing of the current channel region by a gate voltage.

2. The silicon carbide device according to claim 1, wherein: The thickness of the gate insulating layer at the bottom of the gate trench is greater than the thickness of the gate insulating layer at the sidewall of the gate trench.

3. The silicon carbide device according to claim 1, wherein: The n-type source region is located in a first p-type body region among the p-type body regions, and the horizontal channel region is located in a second p-type body region among the p-type body regions.

4. The silicon carbide device according to claim 1, wherein: The n-type source region is located in a first p-type body region of the p-type body regions, and the horizontal channel region is located in a second p-type body region of the p-type body regions and extends to a first p-type body region of the p-type body regions.

5. The silicon carbide device according to claim 1, wherein: The n-type source region is located in a first p-type body region of the p-type body regions and extends to a second p-type body region of the p-type body regions, and the horizontal channel region is located in the second p-type body region of the p-type body regions. 6 . The silicon carbide device of claim 1 , further comprising a p-type body region contact region located within each of the first p-type body regions.

7. The silicon carbide device according to claim 1, further comprising an n-type doped region located in the n-type silicon carbide layer and below each of the gate trenches, each n-type doped region overlapping a gap between two gates in a respective corresponding gate trench.

8. A method for manufacturing a silicon carbide device, comprising: forming an n-type silicon carbide layer on an n-type silicon carbide substrate; forming a first insulating layer on the n-type silicon carbide layer; Etching the first insulating layer to form a mask pattern; Performing vertical p-type ion implantation using the first insulating layer as a mask to form a plurality of first p-type body regions in the n-type silicon carbide layer; Using the first insulating layer as a mask, perform p-type ion implantation tilted toward one side of each first p-type body region to form a second p-type body region located on one side of each first p-type body region in the n-type silicon carbide layer; Using the first insulating layer as a mask, perform p-type ion implantation tilted toward the other side of each first p-type body region to form a second p-type body region located on the other side of each first p-type body region in the n-type silicon carbide layer, wherein the plurality of first p-type body regions and the plurality of second p-type body regions form a plurality of p-type body regions of the silicon carbide device; Etching away the first insulating layer, and performing n-type ion implantation to form an n-type source region in each p-type body region; Etching the n-type silicon carbide layer to form a plurality of gate trenches in the n-type silicon carbide layer; forming a gate insulating layer on the bottom and sidewall surfaces of each gate trench and the surface of the n-type silicon carbide layer; A first conductive layer is formed on the surface of the gate insulating layer, and the first conductive layer is etched to form two gates in each gate trench, wherein the two gates are respectively located at two side walls of each gate trench and respectively extend to the horizontal channel region on each corresponding side.

9. The method for manufacturing a silicon carbide device according to claim 8, further comprising: N-type ions are implanted into the n-type silicon carbide layer through a gap between two gates in each gate trench, so as to form an n-type doped region located below each gate trench in the n-type silicon carbide layer.

10. The method for manufacturing a silicon carbide device according to claim 8, before forming an n-type source region in each p-type body region, further comprising: P-type ion implantation is performed to form a p-type body region contact region in each of the p-type body regions.

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