Interdigitated diamond junction field-effect transistor (interjfet) and method for manufacturing same

Abstract

The present invention relates to a junction field-effect transistor (JFET) for high-power electronics using diamond lateral / selective growth, based on an interdigitated geometry, InterJFET. It is a novel approach consisting of a depleted FET (field-effect transistor) that is vertically oriented and interdigitated, InterJFET. The manufacturing method includes novel diamond growth solutions, such as selective and lateral growth. This device allows high drain currents (from 16-32A to 10V polarisation in 4x4 mm2 substrates) due to its interdigitated architecture which maximises the "density of channels per substrate surface area". This architecture can further work at voltages of up to 3 kV and at temperatures greater than 250 °C.

Description

[0001] DESCRIPTION

[0002] INTERDIGITATED DIAMOND JUNCTION FIELD EFFECT TRANSISTOR (INTERJFET) AND MANUFACTURING PROCEDURE

[0003] TECHNICAL SECTOR

[0004] Industrial sector: Energy.

[0005] BACKGROUND OF THE INVENTION

[0006] In a context of widespread concern about the conflict between energy and the environment, an extraordinary increase in the use of electricity in energy production, transportation, and consumption is expected. New power electronics (PE) energy conversion systems will enable enormous energy savings and major improvements in quality of life. All energy-consuming devices, from pacemakers and household appliances to electric vehicles and industrial waste processing plants, will be affected. All alternative, sustainable, and distributed energy sources, as well as energy storage systems, will be linked to a smart grid through fast and efficient PE converters.

[0007] In applications where society demands increasingly optimized electrical energy conversion (low-carbon renewable energy, transportation energy, and smart grids), the impact of power electronics is striking. Approximately 30% of all generated electrical energy uses PE at some point between the point of generation and its end use. PE is used for more efficient renewable energy transportation, production, and distribution, including long-distance electricity distribution via high-voltage direct current (HVDC) power lines, as well as for improved control of loads in switching power supplies and variable-speed drives in fan, pump, and compressor motors. By 2030, up to 80% of all electrical energy is expected to use power electronics at some point between its generation and consumption.However, with the current state of electrical equipment, the transformation of electrical energy entails significant losses (for example, 9% in Spain from source to point of use). This is because the available semiconductors are not ideal for these high powers. Silicon is a well-established semiconductor material that has addressed power conversion requirements for over 50 years. However, it is widely known (as can be seen in Research Roadmaps on Power Semiconductor Devices [1]) that the use of devices based on wide bandgap (WBG) semiconductor materials would result in a real improvement in power electronics. These materials have electrical characteristics far superior to those of silicon for applications in power devices.Many grid applications, for example for the 320 kV HVDC grid, use multilevel converters, with 3.3 kV (and 6.5 kV) silicon power semiconductors in series for each required voltage level. To achieve high current levels, parallel connection of the devices is required. WBG-based power electronics devices will lead to substantial improvements in the performance of power electronic systems by offering higher blocking voltages, improved efficiency and reliability (higher performance-to-cost ratios), easier paralleling, and lower thermal requirements, enabling more efficient and greener electronic systems. For a decade now, companies such as ABB, Mitsubishi, and Toshiba have been using Si IGBTs or SiC MOSFETs (e.g., Infineon, MOS: metal-oxide-semiconductor FET).These systems currently reach 6.5 kV, and the next step is to reach 13 kV for HVDC converters. At this point, diamond may be the only material capable of achieving such a voltage resistance, as shown in Table 1. In addition to its high voltage resistance, diamond is also highly tolerant of "high power density," which is highly desirable for ultra-high-power devices.

[0008] Table 1: Diamond properties are surprisingly superior to other semiconductors when considering its use in power electronic devices. Johnson Figure of Merit (FoM) is a measure of the ultimate performance of a transistor’s high power, high frequency electronic device, Keyes FoM measures the performance limited by heat generation and removal, and Baliga FoM measures the loss-limited performance in high power, high frequency operation. Properties / figures where diamond excels for the present invention are highlighted in red.

[0009] Due to its exceptional properties [2], diamond is considered the ultimate WBG semiconductor for high-power electronics applications among all WBG semiconductors. Its dielectric breakdown strength is 3 times higher than that of silicon carbide (SiC) and more than 30 times higher than that of silicon (Si). Furthermore, unlike most other WBG semiconductors, the mobility of both carrier types is very high and its thermal conductivity is unsurpassed (see Table 1). This is driving its use in industry where, in 1995, a diamond FET using a mesa-like architecture was patented [3]. The transistor makes use of a substrate on which diamond is heteroepitaxially grown. Although it is claimed that the device can be made with either mono or polycrystalline diamond, at present it is not possible to grow monocrystalline diamond on substrates other than monocrystalline diamond.This is because small differences in lattice parameters between the substrate and the diamond layer result in extremely high defect densities. Furthermore, the grain boundaries of polycrystalline diamond have a high graphite content and act as electrical paths, short-circuiting the device.

[0010] Three decades later, a three-dimensional structure MOSFET was patented whose manufacturing process allows it to be made entirely of monocrystalline diamond [4]. This design takes into account the possible existence of crystalline defects, thus solving one of the main problems faced by these devices. However, it does not take into account other equally important technological problems. In diamond MOSFETs, to date, inversion has only been demonstrated very recently on the surface of (111) oriented diamond [4], while accumulation has been obtained with the oxygen-terminated diamond surface when S¡O2 is deposited. The main problem is the oxide / diamond configuration where interface states can fix the Fermi level and prevent the formation of a 2D carrier gas (2DG) due to an inappropriate band gap configuration at the interface.This problem is not straightforward. The type of growth (3D or 2D), poor substrate cleavage orientation (miscuous orientation), and many other factors can alter the "free" bonds at the interface and modify Fermi level pinning. Therefore, controlling diamond / oxide structures capable of generating 2D is not currently feasible, and therefore, a diamond MOSFET cannot currently meet the demands of society.

[0011] Consequently, this invention presents an alternative, much more decisive approach. Figure 1 describes the structure of the invention, which is based on different technological steps for its manufacture: (i) growth of p-type diamonds [6], (ii) growth of n-type diamonds [7], (iii) lateral growth or selective growth [8], (iv) contact manufacturing [9] and ICP etching of the diamond

[0010] , (v) electrical characterization

[0011] , (vi) structural characterization

[0012] , (vii) doping evaluation

[0013] , forbidden band

[0014] and band adjustment

[0015] In addition, control of growth parameters such as doping level, mis-cutting, etc. is required to achieve good quality homoepitaxial diamond layers.

[0016] ,

[0012] DESCRIPTION OF THE INVENTION

[0013] In this context, the present invention consists of a diamond-based transistor device and its manufacturing method. This is an original approach, a vertically oriented and interdigitated depletion FET (field effect transistor), InterJFET. The manufacturing method includes original diamond growth solutions, such as selective and lateral growth. This device allows high drain currents (16-32A at 10V bias on 4x4 mm substrates) 2) thanks to its interdigitated architecture that maximizes the “channel density per substrate surface area.” This architecture can also operate at voltages up to 3 kV and temperatures exceeding 250°C.

[0014] The invention utilizes a vertical architecture that allows for increased drain current density and dielectric breakdown voltage compared to lateral devices.

[0017] This is a novel device, being a vertical diamond transistor with bulk conduction. For surface conduction and vertical architecture (which allows increasing the total current), only one example of a diamond MOSFET is known.

[0018]

[0019] , in this case it works in inversion mode, 2DG. Furthermore, the pn junction of the invention makes the “Normally OFF' state of the J FET possible, while the latter reported in the literature are “Normally ON" which makes them unstable due to the H termination concept (current fluctuations in ON mode). As stated, to obtain a “Normally OFF' state, a pn junction is used to close the vertical channel. It would not be technically possible to use a Schottky junction since metal depositions on vertical surfaces are not technically possible. The problem of vertical deposition between the digits is solved by MPCVD (microwave plasma assisted chemical vapor deposition) growth of an n-doped layer that generates a depleted zone. Indeed, MPCVD diamond growth of an n-type layer can be easily done in two ways: (i) by a selective growth step or (ii) by lateral growth.This layer allows, on the one hand, to increase the ON-state current and, on the other, to increase the voltage resistance (a pN junction is more resistant than a Schottky contact), allowing operation at higher powers. Adjusting the doping levels is essential to correctly size the depleted and drift zones, avoiding punch-through if possible. The proposed design (Figures 1 and 2) allows for voltages greater than 1 kV.

[0015] Moreover, to achieve a very high density of vertical interfaces, i.e., to maximize the total current per substrate surface, the proposal presents an interdigitated concept, only possible thanks to its vertical architecture. In this way, it allows reaching currents of 30-100 A per 4 mm x 4 mm substrate. The normalized resistance for each device is 3 thousand cm 2 This value is similar to the best values ​​obtained for vertical H-terminated FETs.

[0016] BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1: Schematic description in cross-sectional view of the InterJFET of the invention. A p-doped layer is grown on the substrate (4). +(5) in which the ohmic drain contact (6) will be manufactured. The MPCVD growth, being selective, will allow the growth of the p-doped regions of the device (3), as well as the n-doped regions (1). On these, the source (8) and gate (7) contacts will be manufactured respectively. Alternatives to selective growth are considered (see section “Embodiment of the invention”). The Normally OFF state is achieved thanks to the depleted zone of the pn junction. It can be seen that critical dimensions such as the depth and width of the interdigits make laser photolithography difficult. Therefore, electrolithography and / or FIB nanomachining must be used. Figure 2: Schematic description from above (top view) of the entire substrate revealing the interdigitated structure. The drain (6), source (8) and gate (7) contacts have been marked. The latter laterally closes the channel on both sides (1) with a p-doped vertical channel (2).Relative dimensions and sizes are not respected (see for example the sizes between digits).

[0018] Figure 3: First device manufacturing process. Growth on the substrate (4) of the bilayer formed by a highly doped p-type layer, p + (5), followed by a layer with low p-type doping, p' (3).

[0019] Figure 4: Manufacturing process of the interdigitated structure (2) formed by a first layer with low p, p type doping; (3) followed by a highly doped p, p type layer. + (9). The fabrication of this structure can be carried out by two alternative processes: Selective growth using a Ti mask, of a p- / p+ structure

[0020] (2 and 9) over the first p+ / p- bilayer (5 and 3).

[0021] Growth of a p+ layer (9) on the previously grown p+ / p- bilayer (5 and 3) and subsequent nanomachining with a focused ion beam (FIB) microscope, or by inductively coupled plasma (ICP) etching and electrolithography, on the p- / p+ layers to generate the “columns” (2 and 9, the interdigits).

[0022] Figure 5: Manufacturing process of the n-type layer (1). A layer of n-type diamond is grown by selective growth (with Ti mask and electrolithography before growth).

[0023] Figure 6: Contact manufacturing. The drain (6), source (8) and gate (7) contacts are manufactured on the structure. The gate contact is manufactured directly on the n-type doped layer (1). The source contact must be manufactured on the interdigits (2). Finally, to manufacture the drain contact, the structure must be etched at one end until it contacts the first of the p-type doped layers. + growth (5). The contact manufacturing process can be carried out by electrolithography and PVD, ICP or FIB. PREFERRED EMBODIMENT OF THE INVENTION

[0024] The invention consists of a junction field effect transistor (JFET) for high power electronics obtained by lateral / selective diamond growth, based on an interdigitated geometry.

[0025] The JFET object of the invention comprises: a) An electronic quality diamond substrate that is suitably polished (surface roughness <1 nm). b) A first layer of highly doped p+ type semiconductor diamond material. c) A second layer of low doped p- type diamond material. d) A third layer of low doped p- type diamond consisting of a digitized structure. e) A fourth layer of highly doped p+ type diamond that vertically continues the previous digitized structure. f) A fifth layer of n-type doped semiconductor diamond material grown on the slopes of each digitized structure of the previous layer. g) Etchings at their ends, of sufficient depth to reach the first layer of p+ type semiconductor diamond.

[0026] Some features of the JFET are as follows:

[0027] - It uses monocrystalline diamond as a substrate and active material.

[0028] - The second layer of p- diamond has an engraving on its surface in such a way that it exhibits an interdigitated structure.

[0029] - The first layer, of semiconductor diamond p + , has a boron concentration in the range 10 17 <[B]<10 24 cm -3

[0030] - Its second and third layers, made of p-diamond, have a boron concentration in the range 10 15 <[B]<10 17 cm -3 .

[0031] - Its fourth layer, of semiconductor diamond p + , has a boron concentration in the range 10 17 <[B]<10 24 cm -3

[0032] - Its fifth layer, of n-type doped diamond, is deposited in the spacing between the digits of p7p+ diamond material.

[0033] Its drain contacts are manufactured on the first layer of p-type diamond. +, the source contacts are manufactured on the digits of the last p-type diamond layer + and the gate contacts are manufactured on the n-type diamond layer, but in neither case are they limited to occupying those layers. A preferred embodiment of the developed invention is described below.

[0034] A high p-doped layer (p-layer) will be grown on a high quality, low roughness commercial diamond substrate (electronic grade and finely polished). + ). This is achieved by doping the diamond with boron. On top of this highly doped layer, which acts as a drain contact, another low-doped layer (p' layer) is grown, which acts as a drift layer. The drain contact requires a B doping level of 10 19 - 10 20 cm -3, to have an ohmic character with a low contact resistance, while the drift layer grown on it needs doping levels of around 1-3 x 10 16 cm -3 . Therefore, growth must be carried out in separate reactors or by changing the quartz tube of the MPCVD chamber between the growth of both layers.

[0035] For the fabrication of the interdigits, two equally valid options are proposed: Option A: Selective growth, using a Ti mask, of a p7p structure + over the first bilayer p + / p _ .

[0036] Option B: Growth of a p layer + over the p bilayer + / p _ pre-grown and subsequent nanomachining with a focused ion beam (FIB) microscope, or by inductively coupled plasma (ICP) etching and electrolithography, on the p7p layers +for the generation of the “columns” (the interdigits).

[0037] Once the interdigits of any of the proposed options have been manufactured, an n-type doped layer is selectively grown, which can be doped with nitrogen or phosphorus (using a Ti mask and electrolithography before growth). This layer generates an SCR that will close the channel to the Normally-OFF state. Because the doping must be n-type, this growth must be carried out in a different reactor than the one used for boron doping, to ensure no cross-contamination.

[0038] The drain, source, and gate contacts are fabricated on this structure. The gate contact is fabricated directly on the n-doped layer. The source contact must be fabricated on the interdigits. Finally, to fabricate the drain contact, the structure must be etched at one end until it contacts the first of the p-doped layers.+ growth. The contact manufacturing process can be carried out using electrolithography and PVD, ICP or FIB.

[0039] It should be noted that due to the requirement of having very close spacings (to reach the Normally OFF state with p-doping of 2 x 10 16 cm -3 (a 2-3 pm space between digits is required) the use of electrolithography is necessary to provide accuracy in the nm range.

[0040] References

[0041] [1] H. Ohashi, Proceedings of the 24th ISPSD 3-7 June 2012, Bruges, Belgium.

[0042] [2] D. Araujo, M. Suzuki, F. Lloret, G. Alba and P. Villar, Diamond for Electronics:

[0043] Materials, Processing and Devices, Materials 14, 7081 (2021). https: / / doi.org / 10.3390 / ma14227081.

[0044] [3] DL Dreifus, patent J PH06177400A, Kobe Steel LTD, 1994

[0045] [4] F. Lloret, D. Araujo, P. Godignon, D. Eon, J. Pernot, E. Bustarret, Patente ES2763702A1 , Universidad de Cádiz, CSIC, 2020.

[0046] [5] T. Matsumoto, H. Kato, T. Makino, M. Ogura, D. Takeuchi, S. Yamasaki, T. Inokuma and N. Tokuda, Inversion channel mobility and interface state density of diamond MOSFET using N-type body with various phosphorus concentrations, Appl. Phys. Lett. 114, 242101 (2019).

[0047] [6] F. Lloret, A. Fiori, D. Araujo, D. Eon, M. P. Villar, and E. Bustarret, Stratigraphy of a diamond epitaxial three-dimensional overgrowth using doping superlattices, Appl. Phys. Lett. 108, 181901 (2016) 11 R. Rouzbahani, Sh. S. Nicley, D. E.P. Vanpoucke, F. Lloret, P. Pobedinskas, D. Araujo, K. Haenen, Impact of methane concentration on surface morphology and boron incorporation of heavily boron-doped single crystal diamond layers, Carbon 172, 463 (2021)

[0048] [7] S. Koizumi, M. Suzuki, n-type doping of diamond, Phys. Stat. Sol. A 203, 3358 (2006) / / F. Lloret, B. Soto, R. Rouzbahani, M. Gutierrez, K. Haenen, D. Araujo, “High phosphorous incorporation in (100)-oriented MP CVD diamond growth”, Diamond & Related Materials 133, 109746 (2023)

[0049] [8] F. Lloret, D. Eon, E. Bustarret, F. Donatini, and D. Araujo, Selectively boron doped homoepitaxial diamond growth for power device applications, Appl. Phys. Lett. 118, 023504 (2021); https: / / doi.Org / 10.1063 / 5.0031478 .

[0050] [9] G. Alba, D. Leinen, M.P. Villar, R. Alcántara, J.C. Piñero, A. Fiori, T. Teraji, D. Araujo, Comprehensive nanoscopic analysis of tungsten carbide / Oxygenated-diamond contacts for Schottky barrier diodes, Appl. Surf. Sci. 537, 147874 (2021), https: / / doi.Org / 10.1016 / j.apsusc.2020.147874 .

[0051]

[0010] B. Soto, J. Canes, MP Villar, D. Araujo and J. Pernot. Transport mechanism in O- terminated diamond / ZrO2 based MOSCAPs, Diam. Rel. Mater 121 , 108745 (2021), https: / / doi.org / 10.1016 / j.diamond.2021.108745 / /

[0052]

[0011] TT Pham, JC Piñero, A. Maréchal, M. Gutierrez, F. Lloret, D. Eon, E. Gheeraert, N. Rouger, D. Araújo and J. Pernot, Impact of Nonhomoepitaxial Defects in Depleted Diamond MOS Capacitors, IEEE Trans. On Electr. Dev. 65, 1830 (2018) / / M. Suzuki, T. Sakai, T. Makino, H. Kato. D. Takeuchi, M. Ogura, H. Okushi and S. Yamasaki, "Electrical characteristics of 5 kV PiN diodes", Proceedings of Hasselt Diamond Workshop 2014, p.71. See also: M. Suzuki, "High voltage diamond pin diodes". Obesity 85, 218 (2016).

[0053]

[0012] MP Alegre, D. Araújo, A. Fiori, JC Pinero, F. Lloret, MP Villar, P. Achatz, G. Chicot, E. Bustarret, and F. Jomard, Critical boron-doping levels for generation of dislocations in synthetic diamond, Appl. Phys. Lett. 105, 173103 (2014); doi: 10.1063 / 1.4900741

[0054]

[0013] D. Araujo, MP Alegre, A. García, P. Villar, E. Bustarret, Ph. Buy, PN Volpe,

[0055] F. Omnes, Phys. Stat. Alone. (c) 8, 1366 (2011) I DOI 10.1002 / pssc.201083991 / / D. Araujo, MP Alegre, A. García, P. Villar, E. Bustarret, Ph. Achatz, PN Volpe, F. Omnés, Phys. Stat. Alone. (c) 8, 1366 (2011) I DOI 10.1002 / pssc.201083991

[0056]

[0014] J. Cañas, JC Piñero, F. Lloret, M. Gutierrez, T. Pham, J. Pernot, D. Araujo, Determination of alumina bandgap and dielectric functions of diamond MOS by STEM- VEELS, Appl. Surf. Sci. 461 , 93 (2018)

[0057]

[0015] J. Cañas, G. Alba, D. Leinen, F. Lloret, M. Gutierrez, D. Eon, J. Pernot, E. Gheeraert, D. Araujo, Diamond / y-alumina band offset determination byXPS, Appl. South. Sci. 535, 146301 (2021), https: / / doi.Org / 10.1016 / j.apsusc.2020.146301

[0058]

[0016] F. Lloret, D. Eon, E. Bustarret, A. Fiori and D. Araujo, Boron-Doping Proximity Effects on Dislocation Generation during Non-Planar MPCVD Homoepitaxial Diamond Growth, Nanomaterials 8, 480 (2018); doi:10.3390 / nano8070480 / / D. Araujo, F. Lloret,

[0059] G. Alba, MP Alegre, and MP Villar, Dislocation generation mechanisms in heavily boron-doped diamond epilayers, Appl. Phys. Lett. 118, 052108 (2021); https: / / doi.Org / 10.1063 / 5.0031476

[0060]

[0017] J. Cañas et al, MRS Fall Meeting in Boston (November 30, 2021): “1kV Normally OFF Diamond lateral reverse blocking MESFET”

[0061]

[0018] M. Iwataki et al., "Over 12000 A / cm2 and 3.2 mD cm2 Miniaturized Vertical-Type Two-Dimensional Hole Gas Diamond MOSFET," in IEEE Electron Device Letters, vol. 41 , no. 1 , pp. 111-114, Jan. 2020, doi: 10.1109 / LED.2019.2953693

[0019] H. Kawarada et al., "Diamond MOSFETs using 2D hole gas with 1700V breakdown voltage," 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2016, pp. 483-486, doi: 10.1109 / ISPSD.2016.7520883.

Claims

CLAIMS 1.- Junction field effect transistor (JFET) for high power electronics using lateral / selective diamond growth, based on an interdigitated geometry. 2.- Junction field effect transistor (JFET) for high power electronics by lateral / selective diamond growth, according to claim 1 , comprising: a) An electronic quality diamond substrate that is conveniently polished (surface roughness <1 nm). b) A first layer of highly doped p+ type semiconductor diamond material. c) A second layer of low doped p- type diamond material, d) A third layer of low doped p- type diamond consisting of a digitized structure. e) A fourth layer of highly doped p+ type diamond that vertically continues the previous digitized structure. f) A fifth layer of n-type doped semiconductor diamond material grown on the slopes of each digitized structure of the previous layer. g) Etchings at their ends, of sufficient depth to reach the first layer of p+ type semiconductor diamond. 3.- Junction field effect transistor (JFET) for high power by lateral / selective diamond growth, according to claims 1 and 2, which uses monocrystalline diamond as a substrate and active material. 4.- Diamond junction field effect transistor (JFET) for high power by lateral / selective growth, according to claims 1, 2 and 3, characterized in that the second layer of p-diamond has an engraving on its surface such that it exhibits an interdigitated structure. 5.- Diamond junction field effect transistor (JFET) for high power by lateral / selective growth, according to claims 1, 2, 3 and 4, whose first layer, of semiconductor diamond p + , has a boron concentration in the range 10 17 <[B]<10 24 cm -3 6.- Diamond junction field effect transistor (JFET) for high power by lateral / selective growth, according to claims 1, 2, 3, 4 and 5, whose second and third layer, of p diamond; has a boron concentration in the range 10 15 <[B]<10 17 cm -3 . 7.- Diamond junction field effect transistor (JFET) for high power by lateral / selective growth, according to claims 1, 2, 3, 4, 5 and 6, whose fourth layer, of semiconductor diamond p + , has a boron concentration in the range 10 17 <[B]<10 24 cm -3 8.- Diamond junction field effect transistor (JFET) for high power by lateral / selective growth, according to claims 1, 2, 3, 4, 5, 6 and 7, whose fifth layer, of n-type doped diamond, is deposited in the spacing between the digits of p7p+ diamond material. 9.- Diamond junction field effect transistor (JFET) for high power by lateral / selective growth, according to claims 1, 2, 3, 4, 5, 6, 7 and 8, whose drain contacts are manufactured on the first p-type diamond layer + , the source contacts are manufactured on the digits of the last p-type diamond layer + and the gate contacts are manufactured on the n-type diamond layer, but in neither case do they have to be limited to occupying those layers. 10.- Manufacturing process of a diamond junction field effect transistor (JFET), according to claims 1 to 9, which is carried out on a suitably polished electronic quality diamond substrate, comprising the following steps: a) Growth of a first layer of p-type doped diamond, p + . b) Growth of a second layer of undoped p, p-type diamond. c) Growth of a third layer of p, p-doped diamond+ . d) Etching of the second and third diamond layers with fingered structures. e) Selective growth of a layer of n-type doped diamond between the walls of the fingered structures. f) Etching in regions outside the three-dimensional structure that reach the first grown layer. + . 11.- Manufacturing process of a diamond junction field effect transistor (JFET), according to claims 1 to 9, which is carried out on a suitably polished electronic quality diamond substrate, comprising the following steps: a) Growth of a first layer of p-type doped diamond, p + . b) Growth of a second layer of undoped p, p-type diamond. c) Selective mask growth of a third layer of p, p'-doped diamond, forming a digitated structure. d) Selective mask growth of a fourth layer of p, p-doped diamond +, on top of the previous layer, vertically continuing the fingered structure. e) Selective growth of a layer of n-type doped diamond between the walls of the fingered structures. f) Etching in regions outside the three-dimensional structure that reach the first grown layer p + . 12.- Manufacturing process of a junction field effect transistor (JFET), according to claim 10, in which the growth of the third layer, corresponding to n-type doped diamond, is carried out laterally. 13.- Manufacturing process of a junction field effect transistor (JFET), according to claim 11, in which the growth of the third layer, corresponding to n-type doped diamond, is carried out laterally. 14.- Manufacturing process of a junction field effect transistor (JFET), according to claim 10, in which the growth of the third layer, corresponding to n-type doped diamond, is carried out selectively by means of a mask. 15.- Manufacturing process of a junction field effect transistor (JFET), according to claim 11, in which the growth of the third layer, corresponding to n-type doped diamond, is carried out selectively by means of a mask.

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