Shield gate trench device and manufacturing method therefor

Abstract

Provided in the present application are a shield gate trench device and a manufacturing method therefor. The manufacturing method for a shield gate trench device comprises the following steps: providing a semiconductor layer comprising a substrate and an epitaxial layer, and forming a patterned mask layer on the upper surface of the semiconductor layer; on the basis of the patterned mask layer, successively forming trenches, a first dielectric layer located in the trenches and a shield gate layer filling the bottom portions of the trenches; thinning the first dielectric layer on the inner walls of the trenches above the shield gate layer, so as to simultaneously obtain a mesa, and etching back the shield gate layer until the upper surface of the shield gate layer is flush with the mesa; forming a second dielectric layer covering the surface of the first dielectric layer above the mesa, the first dielectric layer and the second dielectric layer being made of different materials; and using the second dielectric layer and the mask layer as a mask to form an isolation layer, and removing the second dielectric layer and the first dielectric layer covering the inner walls of the trenches above the isolation layer.

Description

Shielded gate trench device and preparation method thereof

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 2023108127885, filed on June 30, 2023, entitled “A Shielded Gate Trench Device and Its Preparation Method,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of semiconductor integrated circuit manufacturing, and in particular to a shielded gate trench device and a method for preparing the same. Background Art

[0004] Shielded gate trench devices have a wide range of applications due to their advantages, including high power density, low conduction losses, fast switching speeds, and low switching losses. In shielded gate trench devices, an isolation oxide layer is formed on the shielding gate layer. The quality of this isolation oxide layer directly affects device performance, making it crucial to develop a high-quality isolation oxide layer.

[0005] Summary of the Invention

[0006] The present application provides a method for preparing a shielded gate trench device, comprising the following steps:

[0007] Providing a semiconductor layer including a substrate and an epitaxial layer stacked in sequence, forming a mask layer on an upper surface of the epitaxial layer and patterning the mask layer;

[0008] Based on the patterned mask layer, a plurality of trenches are formed on the upper surface of the epitaxial layer and are spaced apart from each other, and a first dielectric layer covering the inner walls and bottom surfaces of the trenches and a shielding gate layer filling the trenches are sequentially formed, wherein the upper surface of the shielding gate layer is lower than the upper surface of the epitaxial layer by a preset distance;

[0009] Thinning the first dielectric layer covering the inner wall of the trench above the shielding gate layer, so that after thinning, a mesa is formed at the contact point between the first dielectric layer and the top of the shielding gate layer, which is lower than the upper surface of the shielding gate layer, and etching back the shielding gate layer so that the upper surface of the shielding gate layer is flush with the mesa;

[0010] forming a second dielectric layer covering the first dielectric layer and the exposed surface of the shielding grid layer, wherein the second dielectric layer is made of a different material from the first dielectric layer, and removing the second dielectric layer covering the mesa and the upper surface of the shielding grid layer;

[0011] An isolation layer is formed using the second dielectric layer and the mask layer as masks, and the second dielectric layer and the first dielectric layer covering the inner wall of the trench above the isolation layer are removed.

[0012] In some embodiments, the mask layer is made of silicon nitride.

[0013] In some embodiments, the method of forming the first dielectric layer includes a thermal oxidation method.

[0014] In some embodiments, the method of thinning the first dielectric layer includes wet etching.

[0015] In some embodiments, the method of removing the second dielectric layer covering the mesa and the upper surface of the shield gate layer comprises dry etching.

[0016] In some embodiments, a method of forming the isolation layer includes a thermal oxidation method.

[0017] In some embodiments, the second dielectric layer is made of silicon nitride.

[0018] In some embodiments, after removing the first dielectric layer covering the inner wall of the trench above the isolation layer, the method further includes forming a gate dielectric layer, a gate conductive layer, a second conductive type body region, a first conductive type source region, a gate, a source electrode, and a drain electrode.

[0019] In some embodiments, after removing the first dielectric layer covering the inner wall of the trench above the isolation layer, the method also includes forming a gate dielectric layer, a polysilicon gate layer, a second conductive type base region, a first conductive type emitter region, a second conductive type emitter contact region, a gate, an emitter, a second conductive type collector region and a collector.

[0020] In some embodiments, the method further includes: forming a mask buffer layer between the mask layer and the semiconductor layer.

[0021] In some embodiments, patterning the mask layer includes: forming a patterned photoresist layer on the upper surface of the mask layer; and etching the mask layer and the mask buffer layer in sequence based on the patterned photoresist layer to obtain the patterned mask layer.

[0022] In some embodiments, a method of forming the second dielectric layer includes chemical vapor deposition or physical vapor deposition.

[0023] In some embodiments, forming the shielding gate layer includes: forming a shielding gate layer that fills the groove and covers the upper surface of the mask layer; and removing the shielding gate layer located on the upper surface of the mask layer and the shielding gate layer located in the groove and within a preset height range from the upper surface of the mask layer to obtain the shielding gate layer filling the bottom of the groove.

[0024] The present application also provides a shielded gate trench device, which is manufactured using the above-mentioned method for manufacturing the shielded gate trench device.

[0025] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0027] FIG1 is a schematic diagram showing a cross-sectional structure of a method for preparing a shielded gate trench device in the related art after forming a polysilicon shielding gate layer.

[0028] FIG2 is a schematic diagram showing a cross-sectional structure of a shielded gate trench device after etching the field oxide layer in a method for preparing the shielded gate trench device in the related art.

[0029] FIG3 is a schematic diagram showing a cross-sectional structure of a shielded gate trench device fabrication method in the related art after forming an isolation oxide material layer.

[0030] FIG4 is a schematic diagram showing a cross-sectional structure of a shielded gate trench device fabrication method in the related art after etching the isolation oxide material layer to obtain the isolation oxide layer.

[0031] FIG5 is a schematic diagram showing a cross-sectional structure of a shielded gate trench device fabrication method in the related art after directly forming an isolation oxide layer by a thermal oxidation process.

[0032] FIG. 6 is a process flow chart showing a method for fabricating a shielded gate trench device according to an embodiment of the present application.

[0033] FIG. 7 is a schematic diagram showing a cross-sectional structure of a shielded gate trench device after trench formation in a method for manufacturing the shielded gate trench device according to an embodiment of the present application.

[0034] FIG8 is a schematic diagram showing a cross-sectional structure of a shield gate trench device after forming a shield gate layer in a method for manufacturing the shield gate trench device according to an embodiment of the present application.

[0035] FIG. 9 is a schematic diagram showing a cross-sectional structure of a shielded gate trench device fabrication method after thinning the first dielectric layer in an embodiment of the present application.

[0036] FIG. 10 is a schematic diagram showing a cross-sectional structure of a shield gate trench device fabrication method after etching back the shield gate layer in one embodiment of the present application.

[0037] FIG. 11 is a schematic diagram showing a cross-sectional structure of a shielded gate trench device fabrication method after forming a second dielectric layer in an embodiment of the present application.

[0038] FIG12 is a schematic cross-sectional view showing a method for fabricating a shielded gate trench device in an embodiment of the present application after removing the second dielectric layer covering the mesa and the exposed surface of the shielding gate layer.

[0039] FIG. 13 is a schematic diagram showing a cross-sectional structure of a shielded gate trench device after forming an isolation layer in a method for preparing the shielded gate trench device according to an embodiment of the present application.

[0040] FIG14 is a schematic diagram showing a cross-sectional structure of a shielded gate trench device fabrication method according to an embodiment of the present application after removing the first dielectric layer covering the inner wall of the trench above the isolation layer.

[0041] FIG. 15 is a schematic diagram showing a cross-sectional structure of a shielded gate trench device after forming a source contact hole in a method for manufacturing the shielded gate trench device according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following describes the embodiments of the present application through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present application from the disclosure herein. The present application may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present application.

[0043] To the applicant's knowledge, the fabrication of the isolation oxide layer (IPO) in shielded gate trench devices often utilizes high-density plasma (HDP) deposition processes, thermal oxidation isolation processes, and the like. In the fabrication of the isolation oxide layer in shielded gate trench devices, a wet etching process is typically employed to etch the field oxide layer on the inner wall of the trench after forming a polysilicon shielding gate layer (Source poly), thereby forming the isolation oxide layer.

[0044] During their research, the applicant discovered that the isotropic corrosion characteristics of wet etching lead to the formation of a groove between the top of the polysilicon shielding gate layer and the inner wall of the trench. Figures 1 and 2 are schematic cross-sectional views of the structure after the polysilicon shielding gate layer is formed and after the field oxide layer is wet-etched, respectively, showing semiconductor layer 01, substrate 011, epitaxial layer 012, trench 013, field oxide layer 014, polysilicon shielding gate layer 015, and groove 016. When using a high-density plasma deposition process to form an isolation oxide layer, it is necessary to first use a high-density plasma deposition process to form an oxide layer that fills the trench, then perform a back-etch of the oxide layer, and control the back-etching time to obtain an isolation oxide layer with the required thickness. Figures 3 and 4 are schematic cross-sectional views of the structure after forming an isolation oxide material layer to fill the trench and after etching the isolation oxide material layer to obtain the isolation oxide layer, respectively. These views illustrate semiconductor layer 01, substrate 011, epitaxial layer 012, trench 013, field oxide layer 014, polysilicon shielding gate layer 015, groove 016, isolation oxide layer 02, and isolation oxide material layer 03. Etching back the oxide layer to fill the trench requires a photomask, and the opening size of the groove between the polysilicon shielding gate layer and the inner wall of the trench is relatively small, which easily results in voids when filling the groove. Furthermore, in a lower-voltage shielding gate structure, due to the small trench width, the high-density plasma deposition process cannot effectively fill the groove, resulting in poor quality of the isolation oxide layer, thereby affecting the gate-source breakdown resistance of the device.

[0045] When the isolation oxide layer is formed using a thermal oxidation process, the formation of the isolation oxide layer is not affected by the critical dimension (CD) of the trench. After the field oxide layer is etched, the exposed polysilicon shielding gate layer is directly oxidized to obtain the isolation oxide layer. FIG5 shows a schematic cross-sectional structure diagram after the isolation oxide layer is formed using a thermal oxidation process, including a semiconductor layer 01, a substrate 011, an epitaxial layer 012, a trench 013, a field oxide layer 014, a polysilicon shielding gate layer 015, a groove 016, and an isolation oxide layer 02. The applicant also found in the study that, due to the groove formed between the polysilicon shielding gate layer and the inner wall of the trench, directly oxidizing the exposed polysilicon shielding gate layer will result in the formation of a sharp corner at the groove, and the isolation oxide layer at the sharp corner is relatively thin, which can easily cause gate-source breakdown instability. In addition, after filling the polysilicon gate, the contact area between the gate and the source will also increase, which in turn will increase the Miller capacitance Crss of the device, affecting the switching time of the device.

[0046] Therefore, a method for preparing a shielded gate trench device is needed that has a simple process, improves the breakdown resistance of the isolation layer, and does not affect the Miller capacitance of the device.

[0047] Referring to Figures 6 to 15 , the present application provides a shielded gate trench device and a method for fabricating the same. It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present application. Therefore, the diagrams only show components relevant to the present application and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be varied arbitrarily, and the component layout may also be more complex.

[0048] Example 1

[0049] This embodiment provides a method for preparing a shielded gate trench device. FIG6 is a process flow chart of the method for preparing the shielded gate trench device, which includes the following steps:

[0050] S1: providing a semiconductor layer including a substrate and an epitaxial layer stacked in sequence, forming a mask layer on an upper surface of the epitaxial layer and patterning the mask layer;

[0051] S2: forming a plurality of trenches on the upper surface of the epitaxial layer and spaced apart based on the patterned mask layer, and sequentially forming a first dielectric layer covering the inner walls and bottom surfaces of the trenches and a shielding gate layer filling the trenches, wherein the upper surface of the shielding gate layer is lower than the upper surface of the epitaxial layer by a preset distance;

[0052] S3: thinning the first dielectric layer covering the inner wall of the trench above the shielding gate layer, so that after thinning, a mesa is formed at the contact point between the first dielectric layer and the top of the shielding gate layer, which is lower than the upper surface of the shielding gate layer, and etching back the shielding gate layer so that the upper surface of the shielding gate layer is flush with the mesa;

[0053] S4: forming a second dielectric layer covering the first dielectric layer and the exposed surface of the shielding grid layer, wherein the second dielectric layer is made of a different material from the first dielectric layer, and removing the second dielectric layer covering the mesa and the upper surface of the shielding grid layer;

[0054] S5: using the second dielectric layer and the mask layer as masks to form an isolation layer, and removing the second dielectric layer and the first dielectric layer covering the inner wall of the trench above the isolation layer.

[0055] Referring to FIG. 7 to FIG. 10 , the steps S1, S2, and S3 are performed as follows: providing a semiconductor layer 1 including a substrate 11 and an epitaxial layer 12 stacked in sequence, forming a mask layer 2 on the upper surface of the epitaxial layer 12 and patterning the mask layer 2; forming a plurality of trenches 13 located on the upper surface of the epitaxial layer 12 and spaced apart based on the patterned mask layer 2, and sequentially forming a first dielectric layer 14 covering the inner wall and bottom surface of the trenches 13 and a dielectric layer filling the trenches 13; 3, and the upper surface of the shielding gate layer 15 is lower than the upper surface of the epitaxial layer 12 by a preset distance; the first dielectric layer 14 covering the inner wall of the trench 13 above the shielding gate layer 15 is thinned, and after thinning, the contact between the first dielectric layer 14 and the top of the shielding gate layer 15 forms a table 141 lower than the upper surface of the shielding gate layer 15, and the shielding gate layer 15 is etched back to make the upper surface of the shielding gate layer 15 flush with the table 141.

[0056] The first conductivity type described in each embodiment of the present application includes one of N-type or P-type, the second conductivity type includes one of N-type or P-type, and the first conductivity type and the second conductivity type are different. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0057] In each embodiment of the present application, while ensuring device performance, the size, thickness and shape of the substrate 11 can be selected according to actual conditions and are not limited here.

[0058] In this embodiment, the conductivity type of the substrate 11 is the first conductivity type, the conductivity type of the epitaxial layer 12 is the first conductivity type, and the doping concentration of the epitaxial layer 12 is lower than the doping concentration of the substrate 1. While ensuring device performance and the doping concentration of the epitaxial layer 12 is lower than the doping concentration of the substrate 11, the doping concentration of the substrate 11 can be selected based on actual conditions and is not limited here. The doping concentration of the epitaxial layer 12 can be selected based on actual conditions and is not limited here.

[0059] While ensuring device performance, the size, thickness and shape of the epitaxial layer 12 can be selected according to actual conditions and are not limited here.

[0060] As an example, the mask layer 2 is made of silicon nitride or other suitable dielectric materials.

[0061] Methods for forming the mask layer 2 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0062] In this embodiment, a mask buffer layer 20 is further provided between the mask layer 2 and the semiconductor layer 1 to facilitate the formation of the mask layer 2 .

[0063] Methods for forming the mask buffer layer 20 include thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0064] Under the condition of ensuring the quality of the formed mask layer 2, the thickness of the mask buffer layer 20 can be selected according to actual conditions and is not limited here.

[0065] Under the condition of ensuring the shielding performance of the mask layer 2 in subsequent processes, the thickness of the mask layer 2 can be selected according to actual conditions and is not limited here.

[0066] In this embodiment, patterning the mask layer 2 includes the following steps: forming a patterned photoresist layer (not shown) on the upper surface of the mask layer 2; and etching the mask layer 2 and the mask buffer layer 20 in sequence based on the patterned photoresist layer to obtain the patterned mask layer 2.

[0067] The method for forming the photoresist layer and the patterned photoresist layer is a commonly used photoresist coating, exposure, and development method, which will not be described in detail here.

[0068] The method of etching the mask layer 2 includes dry etching, wet etching or other suitable methods; the method of etching the mask buffer layer 20 includes dry etching, wet etching or other suitable methods.

[0069] FIG7 is a schematic diagram of the cross-sectional structure after the trenches 13 are formed. The method of forming the plurality of trenches 13 on the upper surface layer of the epitaxial layer 12 includes dry etching, wet etching or other suitable methods.

[0070] In this embodiment, after forming the plurality of trenches 13 and before forming the first dielectric layer 14, the method further includes a step of removing the photoresist layer. The method for removing the photoresist layer is a conventional photoresist stripping method, which will not be described in detail here.

[0071] As an example, the method of forming the first dielectric layer 14 includes thermal oxidation or other suitable methods. In this embodiment, the first dielectric layer 14 is a thick silicon oxide layer formed on the inner wall and bottom surface of the trench 11 by thermal oxidation.

[0072] Due to the shielding of the mask layer 2, during the process of forming the first dielectric layer 14 using the thermal oxidation process, the first dielectric layer 14 is only formed on the inner wall and bottom surface of the groove 13, thereby avoiding the formation of the first dielectric layer 14 on the upper surface of the semiconductor layer 1, thereby eliminating the step of removing the first dielectric layer 14 located on the upper surface of the semiconductor layer 1.

[0073] While ensuring device performance, the thickness of the first dielectric layer 14 can be selected according to actual conditions and is not limited here.

[0074] FIG8 is a schematic diagram of the cross-sectional structure after forming the shield gate layer 15. Forming the shield gate layer 15 includes the following steps: forming the shield gate layer 15 to fill the trench 13 and cover the upper surface of the mask layer 2; removing the shield gate layer 15 located on the upper surface of the mask layer 2 and the shield gate layer 15 located in the trench 13 and within a predetermined height range from the upper surface of the mask layer 2, so as to obtain the shield gate layer 15 filling the bottom of the trench 13, that is, the upper surface of the shield gate layer 15 is lower than the upper surface of the semiconductor layer 1 by a predetermined distance.

[0075] The shielding gate layer 15 may be formed by chemical vapor deposition, physical vapor deposition or other suitable methods.

[0076] Methods for removing the shield gate layer 15 on the upper surface of the mask layer 2 and in the trench 13 include chemical mechanical polishing, dry etching, wet etching or other suitable methods.

[0077] Under the condition of ensuring the performance of the device, the distance between the upper surface of the shielding gate layer 15 and the upper surface of the semiconductor layer 1 can be selected according to actual conditions and is not limited here.

[0078] As an example, FIG9 shows a schematic cross-sectional structure diagram after the first dielectric layer 14 above the shielding gate layer 15 is thinned. The method of thinning the first dielectric layer 14 includes wet etching or other suitable methods.

[0079] Since wet etching has the characteristics of isotropy and high etching selectivity, when the first dielectric layer 14 is etched by wet etching, the etchant will produce an etching effect on the part in contact with the first dielectric layer 14, resulting in the contact between the first dielectric layer 14 and the top of the shielding gate layer 15 to produce the mesa 141 which is lower than the upper surface of the shielding gate layer 15.

[0080] After thinning the first dielectric layer 14 , the first dielectric layer 14 with a preset thickness is adhered to the inner wall of the trench 13 above the mesa 141 , so as to facilitate the subsequent formation of the second dielectric layer on the inner wall of the trench 13 (see subsequent FIG. 11 ).

[0081] Under the condition of ensuring device performance and facilitating the formation of the second dielectric layer, the thickness of the thinned first dielectric layer 14 can be selected according to actual conditions and is not limited here.

[0082] FIG10 is a schematic diagram of the cross-sectional structure of the shielding gate layer 15 after etching back. The method of etching back the shielding gate layer 15 includes dry etching, wet etching or other suitable methods.

[0083] Please refer to Figures 11 to 15, and perform steps S4 and S5: forming a second dielectric layer 3 covering the exposed surface of the first dielectric layer 14 and the shield gate layer 15, wherein the second dielectric layer 3 is made of a different material from the first dielectric layer 14, and removing the second dielectric layer 3 covering the mesa 141 and the upper surface of the shield gate layer 15; forming an isolation layer 4 using the second dielectric layer 3 and the mask layer 2 as a mask, and removing the second dielectric layer 3 and the first dielectric layer 14 covering the inner wall of the trench 13 above the isolation layer 4.

[0084] As an example, the material of the second dielectric layer 3 includes silicon nitride or other suitable dielectric materials.

[0085] FIG11 is a schematic diagram of the cross-sectional structure after the second dielectric layer 3 is formed. The method of forming the second dielectric layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0086] As an example, FIG12 is a schematic cross-sectional view of the structure after removing the second dielectric layer 3 covering the mesa 141 and the exposed surface of the shield gate layer 15. The method for removing the second dielectric layer 3 covering the mesa 141 and the upper surface of the shield gate layer 15 includes dry etching or other suitable methods. In this embodiment, dry etching is used to remove the second dielectric layer 3 covering the mesa 141 and the upper surface of the shield gate layer 15. Because dry etching has anisotropic etching characteristics, the ratio of the various components in the etchant can be adjusted so that the etchant only etches the second dielectric layer 3 covering the mesa 141 and the upper surface of the shield gate layer 15, while retaining the second dielectric layer 3 located on the inner wall of the trench 13.

[0087] As an example, FIG13 is a schematic diagram of a cross-sectional structure after the isolation layer 4 is formed. The method of forming the isolation layer 4 includes a thermal oxidation method or other suitable methods.

[0088] In the process of forming the isolation layer 4 by the thermal oxidation method, due to the shielding effect of the second dielectric layer 3 and the mask layer 2, the isolation layer 4 is formed only at the exposed mesa 141 and the shielding gate layer 15, thereby avoiding the problem of sharp corners generated during the etching of the first dielectric layer 14, resulting in a local thinness between the isolation layer 4 and the inner wall of the trench 13, which makes the device prone to gate-source breakdown. At the same time, it avoids increasing the facing area between the gate and the source (emitter) of the device, thereby increasing the Miller capacitance Crss of the device and affecting the switching time of the device.

[0089] Figure 14 is a schematic cross-sectional view of the structure after removing the first dielectric layer 14 covering the inner wall of the trench 13 above the isolation layer 4. The removal of the second dielectric layer 3 located on the inner wall of the trench 13 is accompanied by the removal of the mask layer 2 located above the semiconductor layer 1. The removal of the first dielectric layer 14 located on the inner wall of the trench 13 above the isolation layer 4 is accompanied by the removal of the mask buffer layer 20 located on the upper surface of the semiconductor layer 1.

[0090] Methods for removing the second dielectric layer 3 on the inner wall of the trench 13 include dry etching, wet etching or other suitable methods. Methods for removing the first dielectric layer 14 on the inner wall of the trench 13 above the isolation layer 4 include dry etching, wet etching or other suitable methods.

[0091] As an example, Figure 15 is a schematic cross-sectional view of the structure after forming the source contact hole 52. In this embodiment, after removing the first dielectric layer 14 covering the inner wall of the trench 13 above the isolation layer 4, the method further includes the steps of forming a gate dielectric layer 16, a gate conductive layer 17, a second conductivity type body region 5, a first conductivity type source region 51, a gate (not shown), a source (not shown), and a drain (not shown) to obtain a shielded gate trench MOS device.

[0092] The gate dielectric layer 16 covers the exposed inner wall of the trench 13 and the exposed surface of the isolation layer 4 .

[0093] The gate dielectric layer 16 may be formed by thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods. In this embodiment, the gate dielectric layer 16 is formed by thermal oxidation.

[0094] Under the premise of ensuring device performance, the thickness of the gate dielectric layer 16 can be selected according to actual conditions and is not limited here.

[0095] The gate conductive layer 17 may be formed by chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0096] The gate conductive layer 17 fills the portion of the trench 13 above the isolation layer 4 , and the gate dielectric layer 16 wraps the sidewalls and bottom surface of the gate conductive layer 17 .

[0097] The body region 5 is located on the upper surface of the epitaxial layer 12 and has a bottom surface no lower than the bottom surface of the gate conductive layer 17 . The source region 51 is located on the upper surface of the body region 5 .

[0098] The method of forming the body region 5 includes ion implantation or other suitable methods; the method of forming the source region 51 includes ion implantation or other suitable methods.

[0099] The device is further provided with a source contact hole 52 that penetrates the source region 51 and exposes the body region 5 at the bottom. The source electrode fills the source contact hole 52 , and the gate is electrically connected to the gate conductive layer 17 .

[0100] Methods for forming the source contact hole 52 include dry etching, wet etching or other suitable methods.

[0101] While ensuring device performance and the source contact hole 52 passing through the source region 51, the opening size and depth of the source contact hole 52 can be selected based on actual conditions and are not limited here. The depth here refers to the distance between the bottom surface and the top opening of the source contact hole 52.

[0102] A second conductive type source contact region (not shown) is provided in the body region 5 at the bottom of the source contact hole 52. The source contact region forms an ohmic contact with the source. While ensuring the performance of the device, the doping concentration, thickness and size of the source contact region can be selected according to actual conditions and are no longer restricted here.

[0103] Methods for forming the source contact region include ion implantation or other suitable methods.

[0104] The drain electrode is electrically connected to the substrate 11 , and the contact type between the drain electrode and the substrate 11 is ohmic contact.

[0105] The method for forming the gate includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods. The method for forming the source includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods. The method for forming the drain includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0106] As an example, after removing the first dielectric layer 14 covering the inner wall of the trench 13 above the isolation layer 4, the method also includes the steps of forming a gate dielectric layer (not shown), a polysilicon gate layer (not shown), a second conductive type base region (not shown), a first conductive type emitter region (not shown), a second conductive type emitter contact region (not shown), a gate (not shown), an emitter (not shown), a second conductive type collector region (not shown) and a collector (not shown) to obtain a shielded gate trench insulated gate bipolar transistor (IGBT) device.

[0107] Since the gate dielectric layer and the polysilicon gate layer in the IGBT device have the same structure, material and formation method as the gate dielectric layer 16 and the gate conductive layer 17 in the MOS device, they are not described in detail here.

[0108] The base region is located on the upper surface of the epitaxial layer 12 , and the bottom surface of the base region is not lower than the bottom surface of the polysilicon gate layer. The emitter region is located on the upper surface of the base region, and the collector region is located at the bottom of the substrate 11 .

[0109] The IGBT device is further provided with an emitter contact hole (not shown) penetrating the emitter region and exposing the base region at the bottom. The emitter contact region is located in the base region at the bottom of the emitter contact hole.

[0110] Methods for forming the emitter contact hole include dry etching, wet etching or other suitable methods.

[0111] The base region may be formed by ion implantation or other suitable methods. The emitter region may be formed by ion implantation or other suitable methods. The emitter contact region may be formed by ion implantation or other suitable methods. The collector region may be formed by ion implantation or other suitable methods.

[0112] The emitter fills the emitter contact hole and forms ohmic contacts with the emitter contact region and the emitter region respectively. The collector is electrically connected to the collector region and forms an ohmic contact. The gate is electrically connected to the polysilicon gate layer.

[0113] The emitter may be formed by magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. The collector may be formed by magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0114] Since the gate of the IGBT device is formed using the same method and material as the gate of the MOS device, no further restrictions are imposed here.

[0115] Because the patterned mask layer 2 is formed on the upper surface of the semiconductor layer 1 before the first dielectric layer 14 is formed by the thermal oxidation process, the first dielectric layer 14 is avoided from being formed on the upper surface of the semiconductor layer 1 at the same time as the first dielectric layer 14 is formed, thereby avoiding the step of removing the first dielectric layer 14 covering the upper surface of the semiconductor layer 1, thereby simplifying the process steps.

[0116] By thinning the first dielectric layer 14 attached to the inner wall of the trench 13 and etching back the shielding gate layer 15, and then forming the second dielectric layer 3 located only on the inner wall of the trench 13, and forming the isolation layer 4 based on the second dielectric layer 3, it is avoided that the portion of the isolation layer 4 formed close to the inner wall of the trench 13 forms a sharp corner, which leads to an increase in the facing area between the source (emitter) and the gate of the device, and thus leads to an increase in the Miller capacitance of the device. It also avoids the problem that the isolation layer 4 is difficult to fill the gap between the shielding gate layer 15 and the trench 13, improves the quality of the isolation layer 4, effectively improves the breakdown stability of the gate and source (emitter) of the device, improves the switching performance of the device, and then improves the performance of the device, and the thickness of the isolation layer 4 can also be freely adjusted as needed.

[0117] The preparation method of the shielded gate trench device of this embodiment improves the process of manufacturing the device. After forming the patterned mask layer 2 on the upper surface of the semiconductor layer 1, the trench 13, the first dielectric layer 14 located on the inner wall and bottom surface of the trench 13, and the shielding gate layer 15 filling the bottom of the trench 13 are sequentially formed based on the patterned mask layer 2, the first dielectric layer 14 on the inner wall of the trench 13 above the shielding gate layer 15 is thinned to form the table 141 lower than the upper surface of the shielding gate layer 15, and then the shielding gate layer 15 is etched back so that the upper surface of the shielding gate layer 15 is flush with the table 141, and then the surface of the first dielectric layer 14 covering the table 141 is formed. The second dielectric layer 3 is formed based on the isolation layer 4 formed by the second dielectric layer 3 and the mask layer 2, so that the thickness of the isolation layer 4 can be freely adjusted as needed. At the same time, the formation of a sharp corner of the portion of the isolation layer 4 close to the inner wall of the groove 13 is avoided, which leads to an increase in the facing area of ​​the gate and the source (emitter) in the device. The problem of the isolation layer 4 being difficult to fill the gap between the shielding layer 15 and the groove 13, which affects the breakdown resistance of the gate and the source (emitter) of the device, is also avoided. The quality of the isolation layer 4 is improved, the breakdown stability of the gate and the source (emitter) of the device is effectively improved, the increase of the Miller capacitance of the device is avoided, the switching performance of the device is improved, and the performance of the device is thereby improved.

[0118] Example 2

[0119] This embodiment provides a shielded gate trench device. FIG15 is a schematic diagram of a partial cross-sectional structure of the shielded gate trench device. The shielded gate trench device is manufactured using the shielded gate trench device manufacturing method described in the first embodiment.

[0120] In one embodiment, when the shielded gate trench device is a MOS device, the shielded gate trench device includes a semiconductor layer 1, a trench 13, a first dielectric layer 14, a shielding gate layer 15, an isolation layer 4, a gate dielectric layer 16, a gate conductive layer 17, a second conductivity type body region 5, a first conductivity type source region 51, a source contact hole 52, a second conductivity type source contact region, a gate, a source, and a drain. The semiconductor layer 1 includes a substrate 11 and an epitaxial layer 12 stacked in sequence. A plurality of trenches 13 spaced apart are embedded in the upper surface layer of the epitaxial layer 12. The first dielectric layer 14 covers the bottom surface and bottom inner wall of the trench 13. The shielding gate layer 15 fills the bottom of the trench 13. The first dielectric layer 14 wraps the sidewalls and bottom surface of the shielding gate layer 15. The isolation layer 4 covers the exposed surfaces of the first dielectric layer 14 and the shielding gate layer 15. The gate dielectric layer 16 covers the isolation layer 4 and the exposed surface of the inner wall of the trench 13 above the isolation layer 4. The gate conductive layer 17 fills the upper portion of the trench 13. The gate dielectric layer 16 wraps the sidewalls and bottom surface of the gate conductive layer 17. The body region 5 is located on the upper surface of the epitaxial layer 12 and its bottom surface is not lower than the bottom surface of the gate conductive layer 17. The source region 51 is located on the upper surface of the body region 5. The source contact hole 52 passes through the source region 51 and its bottom surface exposes the body region 5. The source contact region is located in the body region 5 at the bottom of the source contact hole 52. The gate is electrically connected to the gate conductive layer 17. The source electrode fills the source contact hole 52. The drain electrode covers the bottom surface of the substrate 11 and is electrically connected to the substrate 11.

[0121] In one embodiment, when the shielded gate trench device is an IGBT device, the shielded gate trench device includes a semiconductor layer 1, a trench 13, a first dielectric layer 14, a shielding gate layer 15, an isolation layer 4, a gate dielectric layer, a polysilicon gate layer, a second conductivity type base region, a first conductivity type emitter region, an emitter contact hole, a second conductivity type emitter contact region, a gate, an emitter, a second conductivity type collector region, and a collector. The semiconductor layer 1 includes a substrate 11 and an epitaxial layer 12 stacked in sequence. A plurality of trenches 13 spaced apart are embedded in the upper surface of the epitaxial layer 12. The first dielectric layer 14 covers the bottom surface and bottom inner wall of the trenches 13. The shielding gate layer 15 fills the bottom of the trenches 13. The first dielectric layer 14 wraps around the sidewalls and bottom surface of the shielding gate layer 15. The isolation layer 4 covers the exposed surfaces of the first dielectric layer 14 and the shielding gate layer 15. The gate dielectric layer covers the isolation layer 4 and the exposed surface of the inner wall of the trench 13 above the isolation layer 4. The polysilicon gate layer fills the upper part of the trench 13, and the gate dielectric layer wraps the sidewalls and bottom surface of the polysilicon gate layer. The base region is located on the upper surface of the epitaxial layer 12 and the bottom surface is not lower than the bottom surface of the polysilicon gate layer. The emitter region is located on the upper surface of the base region. The emitter contact hole passes through the emitter region and the bottom surface exposes the base region. The emitter contact region is located in the base region at the bottom of the emitter contact hole. The gate is electrically connected to the polysilicon gate layer. The emitter fills the emitter contact hole. The collector region is located on the lower surface of the substrate 11; the collector electrode covers the collector region and is electrically connected to the collector region.

[0122] The substrate 1 is made of silicon, silicon carbide, silicon germanium or other suitable semiconductor materials.

[0123] A mask buffer layer 20 is further provided between the mask layer 2 and the semiconductor layer 1 to facilitate forming the mask layer 2 with better quality.

[0124] The mask buffer layer 20 is made of silicon oxide or other dielectric films that enhance the bonding strength between the mask layer 2 and the semiconductor layer 1 .

[0125] The mask layer 2 is made of silicon nitride or other suitable materials.

[0126] Under the premise of ensuring the performance of the device, the depth and opening size of the trench 13 can be selected according to actual conditions and are not limited here.

[0127] The first dielectric layer 14 is made of silicon oxide or other suitable dielectric materials.

[0128] The shielding gate layer 15 is made of polysilicon or other suitable conductive materials.

[0129] The isolation layer 4 is made of silicon oxide or other suitable dielectric materials.

[0130] The gate dielectric layer 16 may be made of silicon oxide or other suitable dielectric materials. The gate dielectric layer 16 may be made of silicon oxide or other suitable dielectric materials.

[0131] The gate conductive layer 17 is made of polysilicon or other suitable conductive materials.

[0132] The gate may be made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten or other suitable conductive materials.

[0133] Under the condition that the device performance is guaranteed and the source electrode forms an ohmic contact with the source region 51, the doping concentration, thickness and size of the body region 5 can be selected according to actual conditions and are not limited here. The doping concentration, thickness and size of the source region 51 can be selected according to actual conditions and are not limited here.

[0134] The source electrode may be made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, or other suitable conductive materials. The drain electrode may be made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, or other suitable conductive materials.

[0135] Under the premise of ensuring the performance of the device, the doping concentration, thickness and size of the base region can be selected according to the actual situation and are not limited here. The doping concentration, thickness and size of the emitter region can be selected according to the actual situation and are not limited here. The doping concentration, thickness and size of the emitter contact region can be selected according to the actual situation and are not limited here. The opening size and depth of the emitter contact hole can be selected according to the actual situation and are not limited here. The doping concentration and thickness of the collector region can be selected according to the actual situation and are not limited here. The depth here refers to the distance between the bottom surface of the emitter contact hole and the opening of the emitter contact hole.

[0136] The emitter electrode may be made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, or other suitable conductive materials. The collector electrode may be made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, or other suitable conductive materials.

[0137] Since the shielded gate trench device is manufactured by adopting the shielded gate trench device described in the first embodiment, the quality of the isolation layer 4 is improved, thereby improving the breakdown resistance of the device.

[0138] The shielded gate trench device of this embodiment is manufactured by adopting the method for manufacturing the shielded gate trench device described in the first embodiment, thereby improving the quality of the isolation layer 4 in the device and further improving the breakdown resistance performance of the device.

[0139] In summary, the shielded gate trench device and its preparation method of the present application optimize the process of manufacturing the device, form a patterned mask layer on the upper surface of the semiconductor layer, and form a trench, a first dielectric layer and a shielding gate layer in sequence based on the patterned mask layer, then thin the first dielectric layer covering the inner wall of the trench above the shielding gate layer, and form a mesa while thinning the first dielectric layer, etch back the shielding gate layer so that the upper surface of the shielding gate layer is flush with the mesa, and then form a second dielectric layer covering the surface of the first dielectric layer above the mesa, and use the second dielectric layer and the mask layer as a mask to form an isolation layer. The thickness of the obtained isolation layer can be freely adjusted as needed, avoiding the formation of sharp corners in the portion of the isolation layer close to the inner wall of the trench, which leads to an increase in the facing area between the gate and the source (emitter) of the device, thereby avoiding the problem of an increase in the Miller capacitance of the device due to the formation in the isolation layer, and also avoiding the problem that the isolation layer is difficult to fill the gap between the shielding gate layer and the trench, thereby improving the switching performance of the device, improving the quality of the isolation layer, and effectively improving the breakdown stability between the gate and the source (emitter), thereby improving the performance of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0140] It is understood that the manufacturing method of the shielded gate trench device in this embodiment is not limited to the manufacturing method described in the first embodiment.

[0141] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A method for preparing a shielded gate trench device, comprising the following steps: Providing a semiconductor layer including a substrate and an epitaxial layer stacked in sequence, forming a mask layer on the upper surface of the epitaxial layer and patterning the mask layer; Based on the patterned mask layer, a plurality of grooves are formed on the upper surface of the epitaxial layer and are spaced apart from each other, and a first dielectric layer covering the inner wall and bottom of the groove and a shielding gate layer filling the groove are sequentially formed, wherein the upper surface of the shielding gate layer is lower than the upper surface of the epitaxial layer by a preset distance; The first dielectric layer covering the inner wall of the trench above the shielding gate layer is thinned, and after the thinning, a table lower than the upper surface of the shielding gate layer is formed at the contact point between the first dielectric layer and the top of the shielding gate layer, and the shielding gate layer is back-etched to make the upper surface of the shielding gate layer flush with the table; forming a second dielectric layer covering the first dielectric layer and the exposed surface of the shielding grid layer, wherein the second dielectric layer is made of a different material from the first dielectric layer, and removing the second dielectric layer covering the mesa and the upper surface of the shielding grid layer; and An isolation layer is formed by using the second dielectric layer and the mask layer as masks, and the second dielectric layer and the first dielectric layer covering the inner wall of the trench above the isolation layer are removed.

2. The method for preparing a shielded gate trench device according to claim 1, wherein: The material of the mask layer includes silicon nitride.

3. The method for preparing a shielded gate trench device according to claim 1 or 2, wherein: The method of forming the first dielectric layer includes a thermal oxidation method.

4. The method for preparing a shielded gate trench device according to any one of claims 1 to 3, wherein: The method of thinning the first dielectric layer includes wet etching.

5. The method for preparing a shielded gate trench device according to any one of claims 1 to 4, wherein: The method of removing the second dielectric layer covering the mesa and the upper surface of the shielding gate layer comprises dry etching.

6. The method for preparing a shielded gate trench device according to any one of claims 1 to 5, wherein: The method of forming the isolation layer includes a thermal oxidation method.

7. The method for preparing a shielded gate trench device according to any one of claims 1 to 6, wherein: The material of the second dielectric layer includes silicon nitride.

8. The method for preparing a shielded gate trench device according to any one of claims 1 to 7, wherein: After removing the first dielectric layer covering the inner wall of the trench above the isolation layer, the method further includes forming a gate dielectric layer, a gate conductive layer, a second conductive type body region, a first conductive type source region, a gate, a source electrode and a drain electrode.

9. The method for preparing a shielded gate trench device according to any one of claims 1 to 7, wherein: After removing the first dielectric layer covering the inner wall of the trench above the isolation layer, the method also includes the steps of forming a gate dielectric layer, a polysilicon gate layer, a second conductive type base region, a first conductive type emitter region, a second conductive type emitter contact region, a gate, an emitter, a second conductive type collector region and a collector.

10. The method for preparing a shield trench device according to claim 1, wherein: The method further includes forming a mask buffer layer between the mask layer and the semiconductor layer.

11. The method for preparing a shield trench device according to claim 10, wherein: The patterning of the mask layer comprises: forming a patterned photoresist layer on the upper surface of the mask layer; and The mask layer and the mask buffer layer are sequentially etched based on the patterned photoresist layer to obtain the patterned mask layer.

12. The method for preparing a shield trench device according to any one of claims 1 to 11, wherein: The method of forming the second dielectric layer includes chemical vapor deposition or physical vapor deposition.

13. The method for preparing a shield trench device according to any one of claims 1 to 12, wherein: Forming the shielding grid layer includes: forming a shielding gate layer filling the trench and covering the upper surface of the mask layer; and The shielding gate layer located on the upper surface of the mask layer and the shielding gate layer located in the trench and within a preset height range from the upper surface of the mask layer are removed to obtain the shielding gate layer filling the bottom of the trench.

14. A shielded gate trench device, wherein the shielded gate trench device is manufactured by the method for manufacturing a shielded gate trench device according to any one of claims 1 to 13.

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