Chip and electronic device

Abstract

Provided in the embodiments of the present disclosure are a chip and an electronic device. The chip comprises: a plurality of chip ports, a port multiplexing logic module and a scanning test logic module, wherein the port multiplexing logic module is provided with a plurality of groups of first ports and a plurality of groups of second ports, and the plurality of chip ports are divided into a plurality of groups according to a preset granularity; each group of chip ports is connected to at least one of the plurality of groups of first ports and the plurality of groups of second ports of the port multiplexing logic module, and the plurality of groups of first ports or the plurality of groups of second ports of the port multiplexing logic module are connected to the scanning test logic module; and the port multiplexing logic module is configured to control the gating of a path between each of the chip ports and the scanning test logic module according to a control instruction and in the unit of the preset granularity.

Description

Chips and electronic devices

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on Chinese patent application CN202310804578.1 filed on June 30, 2023, with the invention name “Chips and Electronic Devices”, and claims the priority of the patent application, and all the contents disclosed therein are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of chip design, and in particular, to a chip and an electronic device. Background Art

[0004] As integrated circuits (ICs) continue to grow in complexity, scan chain testing technology plays a crucial role in effectively screening out chip faults and reducing testing time. To address the challenges of excessively long scan chains, which hinder testing, embedded deterministic testing (EDT) compression technology is being introduced to increase the number of scan chains and reduce their length. While the number of scan chains continues to increase, the chip's input / output (I / O) resources are relatively limited, necessitating time-sharing multiplexing of these I / O resources.

[0005] The current industry-wide commonly used pin multiplexing (PinMux) method groups different modules and allocates fixed I / O resources to them. However, in the early stages of chip design, it's impossible to accurately determine the complexity of each module and its power consumption distribution. The optimal grouping strategy can only be determined after signoff or even tape-out. Traditional grouping methods have fixed I / O allocations, making it impossible to adjust the design based on the optimal grouping. This can easily lead to irrational I / O allocations, resulting in complex modules not receiving sufficient I / O resources, long testing times, uneven power distribution, and device voltage drops.

[0006] In summary, there is no good solution to the problems of unreasonable I / O allocation and long testing time for large-scale complex chips in related technologies.

[0007] Summary of the Invention

[0008] The embodiments of the present disclosure provide a chip and an electronic device to at least solve the problems of unreasonable I / O allocation and long testing time in large-scale complex chips in the related art.

[0009] According to one embodiment of the present disclosure, a chip is provided, which includes multiple chip ports, a port multiplexing logic module and a scan test logic module, wherein: the port multiplexing logic module has multiple groups of first ports and multiple groups of second ports, and the multiple chip ports are divided into multiple groups according to a preset granularity; each group of chip ports is connected to at least one of the multiple groups of first ports and multiple groups of second ports of the port multiplexing logic module, and the multiple groups of first ports or the multiple groups of second ports of the port multiplexing logic module are connected to the scan test logic module; the port multiplexing logic module is configured to control the selection of the path between the chip port and the scan test logic module in units of preset granularity according to a control instruction.

[0010] According to yet another embodiment of the present disclosure, an electronic device is provided, comprising the chip in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a block diagram of a chip according to an embodiment of the present disclosure;

[0012] FIG2 is a block diagram of another chip according to an embodiment of the present disclosure;

[0013] FIG3 is a schematic diagram of the circuit structure of a chip according to an embodiment of the present disclosure;

[0014] FIG4 is a schematic diagram of a circuit structure of a port multiplexing logic module according to an embodiment of the present disclosure (I);

[0015] FIG5 is a schematic diagram (II) of the circuit structure of a port multiplexing logic module according to an embodiment of the present disclosure;

[0016] FIG6 is a schematic diagram (III) of a circuit structure of a port multiplexing logic module according to an embodiment of the present disclosure;

[0017] FIG7 is a circuit structure diagram (four) of a port multiplexing logic module according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0019] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0020] The present disclosure provides a chip for embedded deterministic testing. As chip size continues to grow, the number of scan chains to be tested also increases. However, a chip's I / O resources are relatively limited. The chip to be tested, designed according to the following embodiments, can readjust the connection between chip ports and the scan chains to be tested within the chip during the chip testing phase, enabling dynamic adjustment and flexible allocation of I / O resources.

[0021] FIG1 is a block diagram of a chip according to an embodiment of the present disclosure. As shown in FIG1 , the chip includes the following structures:

[0022] A plurality of chip ports 12 , a port multiplexing logic module 14 and a scan test logic module 16 .

[0023] In this embodiment, the port multiplexing logic module has multiple groups of first ports and multiple groups of second ports, and the multiple chip ports are divided into multiple groups according to a preset granularity.

[0024] In this embodiment, each group of chip ports is connected to at least one of the multiple groups of first ports and the multiple groups of second ports of the port multiplexing logic module, and the multiple groups of first ports or the multiple groups of second ports of the port multiplexing logic module are connected to the scan test logic module.

[0025] In this embodiment, the port multiplexing logic module is configured to control the gating of the path between the chip port and the scan test logic module in units of the preset granularity according to a control instruction.

[0026] Through the embodiments of the present disclosure, port grouping can be achieved through preset granularity, which improves the freedom of I / O allocation. The conduction relationship between input ports and output ports is controlled in units of granularity, which can solve the problems of unreasonable I / O allocation and long testing time for large-scale complex chips in related technologies. I / O resources can also be dynamically adjusted during the testing phase, effectively reducing chip testing time.

[0027] In some embodiments, the plurality of chip ports are divided into i+1 groups, and the number of port groups of the scan test logic module is j+1, where i is less than j, and i and j are positive integers. When the chip ports are chip input ports, the plurality of groups of first ports of the port multiplexing logic module are groups of input ports, and the plurality of groups of second ports of the port multiplexing logic module are groups of output ports, each group of chip ports is connected to at least one group of the plurality of groups of first ports of the port multiplexing logic module, and the plurality of groups of second ports of the port multiplexing logic module are connected to the scan test logic module. The number of input port groups of the port multiplexing logic module is i+1, and the number of output port groups of the port multiplexing logic module is j+1.

[0028] In some embodiments, the port multiplexing logic module includes j+1 first multiplexer groups, wherein each of the first multiplexer groups is connected to i+1 input port groups of the port multiplexing logic module, and each of the first multiplexer groups is connected to one output port group of the port multiplexing logic module; the first multiplexer group is configured to select a target input port group and a corresponding target output port group among the i+1 input port groups according to the control instruction.

[0029] In some embodiments, when the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the first multiplexer groups includes N first multiplexers.

[0030] In some embodiments, the port multiplexing logic module further includes: i+1 input register groups and j+1 input channel register groups; the i+1 input port groups are connected to each of the first multiplexer groups through the i+1 input register groups; and each of the first multiplexer groups is connected to one output port group through one of the input channel register groups.

[0031] In some embodiments, the port multiplexing logic module includes i+1 first demultiplexer groups and j+1 OR operation modules, wherein each of the first demultiplexer groups is connected to one input port group of the port multiplexing logic module, each of the first demultiplexer groups is connected to the j+1 OR operation modules, and each of the OR operation modules is connected to one of the output port groups of the port multiplexing logic module; the first demultiplexer group is configured to select one target output port group among the j+1 output port groups and the corresponding target input port group according to the control instruction.

[0032] In some embodiments, when the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the first demultiplexer groups includes N first demultiplexers.

[0033] In some embodiments, the port multiplexing logic module further includes: i+1 input register groups and j+1 input channel register groups; each input port group is connected to a first demultiplexer group through an input register group; and each OR operation module is connected to an output port group through an input channel register group.

[0034] In some embodiments, the plurality of chip ports are divided into i+1 groups, and the number of port groups of the scan test logic module is j+1, where i is less than j, and i and j are positive integers. When the chip ports are chip output ports, the plurality of groups of second ports of the port multiplexing logic module are groups of output ports, and the plurality of groups of first ports of the port multiplexing logic module are groups of input ports, each group of chip ports is connected to at least one group of the plurality of groups of second ports of the port multiplexing logic module, the plurality of groups of first ports of the port multiplexing logic module are connected to the scan test logic module, the number of input port groups of the port multiplexing logic module is j+1, and the number of output port groups of the port multiplexing logic module is i+1.

[0035] In some embodiments, the port multiplexing logic module includes i+1 second multiplexer groups, wherein each second multiplexer group is connected to j+1 input port groups of the port multiplexing logic module, and each second multiplexer group is connected to one output port group of the port multiplexing logic module; the second multiplexer group is configured to select a target input port group and a corresponding target output port group among the j+1 input port groups according to the control instruction.

[0036] In some embodiments, when the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the second multiplexer groups includes N second multiplexers.

[0037] In some embodiments, the port multiplexing logic module further includes: j+1 output channel register groups and i+1 output register groups; each input port group is connected to each second multiplexer group through one output channel register group, and each second multiplexer group is connected to one output port group through one output register group.

[0038] In some embodiments, the port multiplexing logic module includes j+1 second demultiplexer groups and i+1 OR operation modules, wherein each of the second demultiplexer groups is connected to one input port group of the port multiplexing logic module, each of the second demultiplexer groups is connected to the i+1 OR operation modules, and each of the OR operation modules is connected to one of the output port groups of the port multiplexing logic module; the second demultiplexer group is configured to select one target output port group among the i+1 output port groups and the corresponding target input port group according to the control instruction.

[0039] In some embodiments, when the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the second demultiplexer groups includes N second demultiplexers.

[0040] In some embodiments, the port multiplexing logic module further includes: j+1 output channel register groups and i+1 output register groups; each input port group is connected to a second demultiplexer group through an output channel register group; and each OR operation module is connected to an output port group through an output register group.

[0041] A test chip is also provided in an embodiment of the present disclosure.

[0042] FIG2 is a block diagram of another chip according to an embodiment of the present disclosure. As shown in FIG2 , the chip includes:

[0043] Chip port 22 , controller 24 , port multiplexing logic module 26 and scan test logic module 28 .

[0044] In this embodiment, the chip ports are connected to the ports of the scan test logic module through the port multiplexing logic module, wherein the number of the chip ports is less than the number of the ports of the scan test logic module.

[0045] In this embodiment, the controller is configured to send a control instruction to the port multiplexing logic module.

[0046] In this embodiment, the port multiplexing logic module is the port multiplexing logic module in any of the above embodiments, and may be a port multiplexing logic module and / or a port multiplexing logic module.

[0047] In this embodiment, the scan test logic module includes: a plurality of embedded deterministic test EDT channel chains, wherein the ports of the scan test logic module are ports of the EDT channel chains.

[0048] Furthermore, the scan test logic module is configured to test the EDT channel chain connected to the chip port.

[0049] In some embodiments, the scan test logic module may include multiple scan test modules, wherein each of the scan test modules contains at least one EDT channel chain; the scan test logic module is configured to test each of the multiple test groups at different times, wherein each of the test groups contains at least one EDT channel chain group, wherein the multiple EDT channel chains are divided into multiple EDT channel chain groups according to the preset granularity, and the multiple test groups are allocated according to the attribute parameters of the multiple scan test modules.

[0050] Through the embodiments of the present disclosure, the test grouping can be dynamically adjusted according to the attribute parameters of the test module during the chip testing phase, effectively reducing the test time, thereby solving the problems of unreasonable IO allocation and long test time in large-scale complex chips in related technologies.

[0051] FIG3 is a schematic diagram of the circuit structure of a chip according to an embodiment of the present disclosure. As shown in FIG3 , the chip includes the following structures:

[0052] A plurality of general input ports 100 , a port multiplexing logic module 200 , a scan test logic module 300 , a port multiplexing logic module 400 , a plurality of general output ports 500 and a controller 600 .

[0053] In this embodiment, the plurality of universal input ports 100 are equivalent to the chip input ports in the above embodiment, and the plurality of universal output ports 500 are equivalent to the chip output ports in the above embodiment.

[0054] In this embodiment, the plurality of general input ports and the plurality of general output ports are divided into a plurality of I / O groups according to a preset granularity.

[0055] Furthermore, data is input from a general-purpose input port in a general-purpose input / output (GPIO) to the port multiplexing logic module, and after the logic module is scanned and tested, the test data result is output from a general-purpose output port.

[0056] In this embodiment, multiple universal input ports are connected to multiple input ends of the port multiplexing logic module, multiple output ends of the port multiplexing logic module are connected to multiple input ends of the scan test logic module, multiple output ends of the scan test logic module are connected to multiple input ends of the port multiplexing logic module, multiple output ends of the port multiplexing logic module are connected to the multiple universal output ports, and the controller is connected to the port multiplexing logic module and the port multiplexing logic module respectively.

[0057] In this embodiment, granularity is used to describe I / O grouping, specifically the number of I / Os contained in each group. The granularity directly impacts the degree of freedom in I / O allocation during scan testing and the logic increment within the I / O multiplexing logic module. The minimum granularity setting is 1.

[0058] Furthermore, smaller granularity increases I / O allocation freedom, but also requires the introduction of more scan I / O reuse logic. Larger granularity effectively simplifies scan I / O reuse logic, but limits the freedom of I / O allocation during scan testing. Therefore, granularity should be appropriately configured during chip design to achieve a balance between I / O allocation freedom and the amount of I / O reuse logic.

[0059] In this embodiment, the grouping of logic units in each port or module in the chip is based on granularity.

[0060] In this embodiment, the scan test logic module is configured to test the embedded deterministic test EDT channel chain connected to the universal input port and the universal output port.

[0061] Specifically, the EDT channel chain is obtained by compressing the scan chain and is the basic unit of Embedded Deterministic Testing (EDT).

[0062] In this embodiment, the controller is configured to send control instructions to the port multiplexing logic module and the port multiplexing logic module respectively.

[0063] In this embodiment, the port multiplexing logic module is configured to connect the multiple general input ports and part of the input ends of the scan test logic module in units of the I / O group according to the control instruction, wherein the number of the multiple general input ports is less than the number of the multiple input ends of the scan test logic module.

[0064] In this embodiment, the port multiplexing logic module is configured to connect part of the output ends of the scan test logic module to the multiple general output ports in units of the I / O group according to the control instruction, wherein the number of the multiple general output ports is less than the number of the multiple output ends of the scan test logic module.

[0065] Furthermore, the port multiplexing logic module is configured to implement time-division multiplexing of the universal input port, and the port multiplexing logic module is configured to implement time-division multiplexing of the universal output port.

[0066] Specifically, the number of general-purpose input / output ports is less than the number of input / output terminals of the scan test logic module. By instructing the port multiplexing logic module and the port multiplexing logic module through the controller, the general-purpose output / output ports can be turned on with different input / output terminals in the scan test logic module at different times, that is, time-sharing multiplexing of the general-purpose output / output ports is realized, thereby ensuring the test effect of the scan test logic module when I / O resources are limited.

[0067] In some embodiments, the controller 600 may be a test access port controller (TAP) or other device that can output a control signal and control a multiplexer / demultiplexer, which is not limited in the present disclosure.

[0068] Through the embodiments of the present disclosure, dynamic adjustment of I / O resources is achieved during the testing phase, so that I / O allocation is not restricted by the chip design phase. It is even possible to dynamically adjust the grouping of test modules under different test modes according to the actual conditions of the modules to be tested, thereby effectively reducing the chip testing time and solving the problems of unreasonable I / O allocation and long testing time for large-scale complex chips in related technologies.

[0069] In some embodiments, the preset granularity is N, each I / O group includes N general input ports and N general output ports, where N is a positive integer.

[0070] In some embodiments, the scan test logic module includes multiple scan test modules, wherein each of the scan test modules includes at least one EDT channel chain, the input end of each of the EDT channel chains is an input end of the scan test logic module, and the output end of each of the EDT channel chains is an output end of the scan test logic module.

[0071] In some embodiments, the scan test logic module is configured to test each test group in a plurality of test groups at different times, wherein each of the test groups includes at least one EDT channel chain group, and each of the EDT channel chain group includes N EDT channel chains, and the plurality of test groups are allocated according to the attribute parameters of the plurality of scan test modules.

[0072] Furthermore, the number of ports in each I / O group and the number of EDT channel chains in each EDT channel chain group are the same as the preset granularity. When a port in an I / O group is connected to an EDT channel chain in an EDT channel chain group, the other ports in the I / O group are connected to the other EDT channel chains in the EDT channel chain group.

[0073] In this embodiment, the number of general input / output ports is less than the number of EDT channel chains to be tested. By configuring the controller, the conduction status of the general input / output ports and the EDT channel chains can be dynamically adjusted to achieve data transmission between the I / O and EDT channel chains.

[0074] In some embodiments, the attribute parameters of the scan test module may include, but are not limited to, any one or combination of the following parameters: number of EDT channels, cross-talk paths between scan test modules, test mode, number of test vector patterns, and power consumption. The attribute parameters may also include any other parameters that may affect the test process or test results.

[0075] In some embodiments, the port multiplexing logic module and the port multiplexing logic module can be implemented by a multiplexer or a demultiplexer. Technicians can also implement time-sharing multiplexing of I / O input / output ports by using a selector or other logic operation modules, and this disclosure does not limit this.

[0076] FIG4 is a schematic diagram (I) of a circuit structure of a port multiplexing logic module according to an embodiment of the present disclosure. As shown in FIG4 , the port multiplexing logic module may include the following structures:

[0077] A plurality of first multiplexer groups 240 .

[0078] In this embodiment, the number of the plurality of first multiplexer groups is the same as the number of the plurality of EDT channel chain groups.

[0079] In this embodiment, each first multiplexer group includes multiple groups of input terminals and one group of output terminals, and one group of input terminals and one group of output terminals can be selected under the control of a control instruction.

[0080] In some embodiments, based on a preset granularity, the input ports of the port multiplexing logic module are divided into i+1 groups, including dft_edt_in_0 through dft_edt_in_i. Each group of input ports is connected to a group of general input ports. The output ports of the port multiplexing logic module are divided into j+1 groups, including dft_edt_in_channel_0 through dft_edt_in_channel_j. Each group of output ports is connected to an EDT channel chain group. Accordingly, the number of first multiplexer groups is j+1, where i is less than j.

[0081] In some embodiments, the port multiplexing logic module may further include a plurality of input registers 220 and a plurality of input channel registers 260 .

[0082] In some embodiments, the preset granularity is N, the input / output port group (I / O group) includes N input / output ports, each first multiplexer group includes N first multiplexers, and each EDT channel chain group includes N EDT channel chains.

[0083] Furthermore, the circuit connections in Figure 4 are implemented in a bus manner, with each bus comprising a group of N lines. The number of input registers 220 and input channel registers 260 in Figure 4 is omitted, as each line can actually be connected to a register.

[0084] In this embodiment, the input (dft_edt_in) register is located on the input port side of the port multiplexing logic module, and the input channel (dft_edt_in_channel) register is located on the output port side of the port multiplexing logic module. The logic between the input register and the input channel register is the I / O multiplexing (scan io reuse) logic in the port multiplexing logic module.

[0085] In this embodiment, each group universal input port is respectively connected to the multiple first multiplexer groups through the input register, and each first multiplexer group is connected to one EDT channel chain group through the input channel register, wherein each first multiplexer in the first multiplexer group corresponds to one EDT channel chain in one EDT channel chain group.

[0086] In this embodiment, the first multiplexer group is configured to select a target I / O group among the multiple I / O groups and the corresponding target EDT channel chain group according to the control instruction, wherein the N general input ports in the target I / O group are connected to the input ends of the N EDT channel chains in the target EDT channel chain group.

[0087] In some embodiments, when the granularity is N, each first multiplexer group includes N first multiplexers. Each first multiplexer has i+1 inputs and one output. The i+1 inputs are each connected to a universal input port in the i+1 I / O groups, and the output is connected to an input of an EDT channel chain. The first multiplexer can select one of the i+1 universal input ports as a target universal input port and connect it to the corresponding uniquely connected EDT channel chain, thereby implementing testing of the EDT channel chain.

[0088] In some embodiments, each group of N first multiplexers can be controlled by a single control signal to enable selection of N paths. For example, the input of the first first multiplexer in the first multiplexer group can be connected to the first port in each bus (or each group of universal input ports), and one of the multiple first ports is selected to be connected to the first output port in the output port group of the first multiplexer group. Correspondingly, the other first multiplexers in the first multiplexer group are sequentially connected to the corresponding ports in each bus (or each group of universal input ports).

[0089] Furthermore, the first multiplexer in each first multiplexer group in FIG4 can be connected to ports such as dft_edt_in_0[0], dft_edt_in_1[N], and dft_edt_in_i[N·i], and one port can be selected to be connected to the first port in the corresponding output port group. The second first multiplexer can be connected to ports such as dft_edt_in_0[1], dft_edt_in_1[N+1], and dft_edt_in_i[N·i+1], and the same applies to the other first multiplexers.

[0090] In some embodiments, the logic of the I / O reuse logic module (scan io reuse) is controlled by a configuration chain in the tap controller. The configuration chain can control the conduction logic of the first multiplexer or the first multiplexer group, thereby realizing dynamic I / O reuse allocation.

[0091] In this embodiment, the configure chain in the tap controller is connected to the select terminal dft_edt_in_sel of each multiplexer, so that only one path from dft_edt_in to dft_edt_in_channel in the multiplexer is selected, thereby realizing dynamic allocation and time-division multiplexing of the scan io input terminal. The bit width of the dft_edt_in_sel signal is related to the I / O granularity N.

[0092] In some embodiments, the control instructions include a first serial instruction and a second serial instruction.

[0093] In some embodiments, the controller is configured to control the plurality of first multiplexer groups or the plurality of first demultiplexer groups in the port multiplexing logic module to select the plurality of general input ports and part of the input terminals of the scan test logic module through the first serial instruction.

[0094] In some embodiments, the controller is further configured to control multiple second multiplexer groups or multiple second demultiplexer groups in the port multiplexing logic module through the second serial instruction to select part of the output ends of the scan test logic module and the multiple general output ports.

[0095] In the disclosed embodiment, by controlling the I / O multiplexing logic through the controller, time-sharing multiplexing of the chip's general input and output ports can be achieved, and adjustment of the I / O grouping can be achieved during the test process, thereby effectively reducing the EDT test time.

[0096] FIG5 is a schematic diagram (II) of a circuit structure of a port multiplexing logic module according to an embodiment of the present disclosure. As shown in FIG5 , the port multiplexing logic module may include the following structures:

[0097] A plurality of first demultiplexer groups 230 and a plurality of OR operation modules 250 .

[0098] In this embodiment, the number of the plurality of first demultiplexer groups is the same as the number of the plurality of I / O groups.

[0099] In this embodiment, each first demultiplexer group includes a group of input terminals and multiple groups of output terminals. Under the control of a control instruction, one group of input terminals and one group of output terminals can be selected.

[0100] In some embodiments, based on a preset granularity, the input ports of the port multiplexing logic module are divided into i+1 groups, including dft_edt_in_0 through dft_edt_in_i. Each group of input ports is connected to a group of universal input ports. The output ports of the port multiplexing logic module are divided into j+1 groups, including dft_edt_in_channel_0 through dft_edt_in_channel_j. Each group of output ports is connected to an EDT channel chain group. The multiple EDT channel chains are divided into j+1 EDT channel chain groups. Correspondingly, the number of first demultiplexer groups is i+1, where i is less than j.

[0101] In some embodiments, the port multiplexing logic module may further include a plurality of input registers 220 and a plurality of input channel registers 260 .

[0102] In some embodiments, the preset granularity is N, the input / output port group (I / O group) includes N input / output ports, each first demultiplexer group includes N first demultiplexers, and each EDT channel chain group includes N EDT channel chains.

[0103] Furthermore, the circuit connections in Figure 5 are implemented in a bus manner, with each bus comprising a group of N lines. The number of input registers 220 and input channel registers 260 in Figure 5 is omitted, as each line can actually be connected to a register.

[0104] In this embodiment, each group universal input port is connected to one of the first demultiplexer groups through the input register, each of the first demultiplexer groups is respectively connected to the multiple OR operation modules, and each of the OR operation modules is connected to one of the EDT channel chain groups through the input channel register.

[0105] In this embodiment, the first demultiplexer group is configured to select a target EDT channel chain group among the multiple EDT channel chain groups and the corresponding target I / O group according to the control instruction, wherein the N general input ports in the target I / O group are connected to the input ends of the N EDT channel chains in the target EDT channel chain group.

[0106] In some embodiments, when the granularity is N, each first demultiplexer group includes N first demultiplexers. Each first demultiplexer has one input terminal and j+1 output terminals, one input terminal is connected to a universal input port in one I / O group, and each output terminal is connected to multiple OR operation modules.

[0107] Furthermore, each first demultiplexer selects a target output end from j+1 output ends under the control of the control instruction, connects the input end with the target output end, and then transmits it to a target EDT channel chain in the corresponding EDT channel chain group through the OR operation module, thereby realizing the test of the target EDT channel chain.

[0108] In some embodiments, each group of N first demultiplexers can be controlled by a single control signal to enable selection of N paths. For example, the input of the first first demultiplexer in the first demultiplexer group can be connected to the first port in each bus (or each group of universal input ports), and one of the multiple first ports is selected to be connected to the first output port in the output port group of the first demultiplexer group. Correspondingly, the other first demultiplexers in the first demultiplexer group are sequentially connected to the corresponding ports in each bus (or each group of universal input ports).

[0109] Furthermore, the input terminal of the first first demultiplexer in the first first demultiplexer group in FIG5 is connected to dft_edt_in_0[0], and the output terminal can be connected to ports such as dft_edt_in_channel_0[0], dft_edt_in_channel_1[N], and dft_edt_in_channel_j[N·j], and one of them is selected to be turned on. The same applies to the other first demultiplexers.

[0110] In some embodiments, each OR operation module comprises multiple OR gates. Each OR operation module may have i+1 sets of input ports and one set of output ports, respectively connected to i+1 first demultiplexer groups and one EDT channel chain group. In conjunction with the controller's control of the i+1 first demultiplexer groups, the OR operation module may transmit any input signal from the i+1 sets of input ports to the corresponding EDT channel chain group. Each OR operation module may only receive one set of conduction signals at a time.

[0111] In this embodiment, the configure chain in the tap controller is connected to the select terminal dft_edt_in_sel of each demultiplexer, so that only one path from dft_edt_in to dft_edt_in_channel in the demultiplexer is selected, thereby realizing dynamic allocation and time-division multiplexing of the scan io input terminal. The bit width of the dft_edt_in_sel signal is related to the I / O granularity N.

[0112] In some embodiments, using the structures of the port multiplexing logic modules in Figures 4 and 5 as examples, the first multiplexer group in Figure 4 is located near the scan test logic module and its number is equal to the number of EDT channel chain groups, while the first demultiplexer group in Figure 5 is located near the general input port side and its number is consistent with the number of general input port groups. Due to the small number of general input ports and the large number of EDT channel chains within the module, the number of the first demultiplexer group in Figure 5 is smaller than that of the first multiplexer group in Figure 4, and the internal gating logic of the first demultiplexer group is more complex, provided all other conditions are the same.

[0113] Furthermore, since the bit width of the strobe port of a multiplexer / demultiplexer group and the number of internal channels thereof have an exponential relationship, selecting a multiplexer / demultiplexer group with more complex internal logic is beneficial to compressing the bit width of the strobe port.

[0114] In some embodiments, the total bit width (bit) required for the selection end of the multiplexer group / demultiplexer group in Figures 4 and 5 is N bit1 、N bit2 They are: N bit1=(j + 1)log2(i + 1); N bit2 =(i + 1)log2(j + 1);

[0115] Since typically i << j, thus N bit1 >> N bit2 , that is, the chain length of the configure chain in Figure 5 will be shorter.

[0116] Figure 6 is a schematic diagram (III) of the circuit structure of a port multiplexing logic module according to an embodiment of the present disclosure. As shown in Figure 6, the port multiplexing logic module may include the following structures:

[0117] Multiple second multiplexer groups 440.

[0118] In this embodiment, the number of multiple second multiplexer groups is the same as the number of the multiple EDT channel chain groups.

[0119] In this embodiment, each second multiplexer group includes multiple groups of input terminals and a group of output terminals, and can gate a group of input terminals and a group of output terminals under the control of a control instruction.

[0120] In some embodiments, when the granularity is N, the input ports of the port multiplexing logic module are divided into j + 1 groups, including dft_edt_out_channel_0 to dft_edt_out_channel_j. Each group of input ports is connected to a group of EDT channel chains. The multiple EDT channel chains are divided into j + 1 EDT channel chain groups. Each EDT channel chain group contains N EDT channel chains. The output ports of the port multiplexing logic module are divided into i + 1 groups, including dft_edt_out_0 to dft_edt_out_i. Each group of output ports is connected to a group of general output ports. The multiple general output ports are divided into i + 1 I / O groups. Each I / O group contains N general output ports. Correspondingly, the number of second multiplexer groups is i + 1, and i is less than j.

[0121] In some embodiments, the port multiplexing logic module may further include multiple output channel registers 420 and multiple output registers 460.

[0122] In some embodiments, the preset granularity is N. The input / output port group (I / O group) contains N input / output ports. Each second demultiplexer group contains N second demultiplexers. Each EDT channel chain group contains N EDT channel chains.

[0123] Furthermore, the circuit connections in Figure 7 are made in a bus manner, and each bus contains a group of N lines.

[0124] In this embodiment, each of the EDT channel chain groups is connected to the plurality of second multiplexer groups respectively through the output channel registers, and each of the second multiplexer groups is connected to a group universal output port through the output registers.

[0125] In this embodiment, the second multiplexer group is configured to select a target EDT channel chain group among the multiple EDT channel chain groups and the corresponding target I / O group according to the control instruction, wherein the output ends of the N EDT channel chains in the target EDT channel chain group are connected to the N general output ports in the target I / O group.

[0126] In some embodiments, each second multiplexer group includes N second multiplexers. Each second multiplexer has j+1 inputs and one output. The j+1 inputs are respectively connected to one EDT channel chain in the j+1 EDT channel chain group, and the output is connected to one universal output port. The second multiplexer can select one of the j+1 EDT channel chains as a target EDT channel chain and connect it to the corresponding uniquely connected universal output port, thereby obtaining a test result for the target EDT channel chain.

[0127] In some embodiments, the logic of the I / O reuse logic module (scan io reuse) is controlled by a configuration chain in the tap controller. The configuration chain can be used to control the conduction logic of the second multiplexer or the second multiplexer group, thereby achieving dynamic I / O reuse allocation.

[0128] In this embodiment, the configure chain in the tap controller is connected to the select terminal dft_edt_out_sel of each multiplexer, so that only one path from dft_edt_out_channel to dft_edt_out in the multiplexer is selected, thereby realizing dynamic allocation and time-division multiplexing of the scan io input terminal. The bit width of the dft_edt_out_sel signal is related to the I / O granularity N.

[0129] FIG7 is a schematic diagram (four) of a circuit structure of a port multiplexing logic module according to an embodiment of the present disclosure. As shown in FIG7 , the port multiplexing logic module may include the following structures:

[0130] a plurality of second demultiplexer groups 430 and a plurality of OR operation modules 450 .

[0131] In this embodiment, the number of the plurality of second demultiplexer groups is the same as the number of the plurality of EDT channel chain groups.

[0132] In this embodiment, each second demultiplexer group includes a group of input terminals and multiple groups of output terminals. Under the control of a control instruction, one group of input terminals and one group of output terminals can be selected.

[0133] In some embodiments, based on a preset granularity, the input ports of the port multiplexing logic module are divided into j+1 groups, including dft_edt_out_channel_0 through dft_edt_out_channel_j. Each group of input ports is connected to a group of EDT channel chains, and the multiple EDT channel chains are divided into j+1 EDT channel chain groups. The output ports of the port multiplexing logic module are divided into i+1 groups, including dft_edt_out_0 through dft_edt_out_i. Each group of output ports is connected to a group of general-purpose output ports, and the multiple general-purpose output ports are divided into i+1 I / O groups. Correspondingly, the number of second demultiplexer groups is j+1, where i is less than j.

[0134] In some embodiments, the port multiplexing logic module may further include a plurality of output channel registers 420 and a plurality of output registers 460 .

[0135] In this embodiment, each of the EDT channel chain groups is connected to one of the second demultiplexer groups through the output channel register, each of the multiple second demultiplexer groups is respectively connected to the multiple OR operation modules, and each of the OR operation modules is connected to a group of general output ports through the output register.

[0136] In this embodiment, the second demultiplexer group is configured to select a target I / O group among the multiple I / O groups and the corresponding target EDT channel chain group according to the control instruction, wherein the output ends of the N EDT channel chains in the target EDT channel chain group are connected to the N general output ports in the target I / O group.

[0137] In some embodiments, when the granularity is N, each second demultiplexer group includes N second demultiplexers. Each second demultiplexer has one input terminal and i+1 output terminals, one input terminal is connected to one EDT channel chain, and each output terminal is connected to multiple OR operation modules.

[0138] Furthermore, each second demultiplexer selects a target output end from the i+1 output ends under the control of the control instruction, connects the input end with the target output end, and then transmits the signal of the target output end to the only connected universal output port through the OR operation module, thereby obtaining the test result of the EDT channel chain.

[0139] In some embodiments, the logic of the I / O reuse logic (scan io reuse) module is controlled by a configuration chain in the tap controller, and the configuration chain can be used to control the conduction logic of the second demultiplexer or the second demultiplexer group, thereby achieving dynamic I / O multiplexing allocation.

[0140] In this embodiment, the configure chain in the tap controller is connected to the select terminal dft_edt_out_sel of each demultiplexer, so that only one path from dft_edt_out_channel to dft_edt_out in the demultiplexer is selected, thereby realizing dynamic allocation and time-division multiplexing of the scan io input terminal. The bit width of the dft_edt_out_sel signal is related to the I / O granularity N.

[0141] In some embodiments, when the granularity is 1, the number of general input ports is i+1, the number of EDT channel chains is j+1, and without considering the selection end, the number of standard cells required for the I / O multiplexing logic is N. cell It can be expressed as: N cell =(2(i+1)-1)(j+1).

[0142] In some embodiments, when the granularity is N, assuming that the number of general input ports is N(i+1), the number of EDT channel chains is N(j+1), the number of I / O groups and the number of EDT channel chain groups remain unchanged, and correspondingly, the number of standard units N cell Under the condition that the internal logic complexity is the same, more I / O resources can be allocated through the embodiments of the present disclosure.

[0143] In some embodiments, when the granularity is N, assuming that the number of general input ports is i+1 and the number of EDT channel chains is j+1, the corresponding number of I / O groups is (i+1) / N, and the number of EDT channel chain groups is (j+1) / N. At this time, the number of standard cells required for the I / O multiplexing logic module is N. cell for:

[0144] That is, the number of standard cells in the I / O multiplexing logic module will be approximately equal to the square of the granularity N. 2 relationship decreased.

[0145] In some embodiments, the number of standard cells N required for the I / O multiplexing logic module in FIG5 can be obtained by deduction. cell for:

[0146] Figures 6 and 7 further illustrate the transmission process from the output of the EDT channel chain to the universal output port. Similar to the input transmission logic, the output signal is connected to the universal output port through the output channel register, the I / O multiplexing logic module, and the output register. By configuring the configuration chain (dft_edt_out_select) in the tap controller, which controls the I / O multiplexing logic module, you can dynamically select a specific I / O multiplexing logic, thereby achieving dynamic allocation and time-sharing multiplexing of the universal output port.

[0147] In an exemplary embodiment, the I / O multiplexing logic modules in the above embodiments can be combined arbitrarily to obtain a complete port multiplexing logic module.

[0148] The port reuse logic module in the disclosed embodiment is a dynamic scan io reallocation technology proposed for the scan test (scan) mode. It has a high degree of freedom in grouping and can effectively solve the key problem of fixed I / O allocation and inability to reallocate in related technologies. Through the disclosed embodiment, using the scan io reuse logic, I / O resources can be reallocated according to the optimal module grouping at any stage of chip design, even after chip tape-out. The entire scan io reallocation process reflects a high degree of flexibility and configurability, playing an important role in both chip design and testing.

[0149] In some embodiments, the scan test logic module includes multiple scan test modules, which can be divided into multiple test groups based on attribute parameters of the multiple scan test modules. The scan test logic module can test different test groups at different times.

[0150] Furthermore, attribute parameters include, but are not limited to, any of the following parameters or combinations thereof: number of EDT channels, crosstalk paths between scan test modules, test mode, number of test vector patterns, and power consumption. Attribute parameters can be expanded and selected based on the test module grouping strategy. For example, the number of test vector patterns can be used as the grouping criterion for the shortest test time grouping strategy, while power consumption can be used as the grouping criterion for the optimal power consumption grouping strategy.

[0151] In an exemplary embodiment, a high degree of freedom grouping can be achieved through the port multiplexing logic module, achieving a grouping strategy with the shortest test time and saving test costs.

[0152] In this embodiment, all modules are grouped for testing during the chip scan test. The optimal grouping strategy is to make the number of test vectors (patterns) of the test modules in each test group close, that is, the test time of each test module is close, to avoid only one test module being tested in a period of time, which wastes test time.

[0153] In this embodiment, assuming that there are 8 test modules that need to be tested, the number of EDT channels of each test module is 4, the chip I / O resources are 16, and 4 test modules can be tested simultaneously. Therefore, the test needs to be divided into two groups.

[0154] Furthermore, Table 1 shows an example of the number of patterns for eight test modules in different test modes. As shown in Table 1, the optimal grouping strategy can be determined for each test mode. For example, in stuck-at mode, modules 0, 1, 2, and 3 are grouped together, while modules 4, 5, 6, and 7 are grouped together. In transition mode, modules 0, 2, 3, and 4 are grouped together, while modules 1, 5, 6, and 7 are grouped together.

[0155] Table 1:

[0156] In the disclosed embodiment, the port multiplexing logic module can realize dynamic I / O resource reallocation, thereby realizing different groupings of test modules under different test modes. Through the disclosed embodiment, the actual test time can also be effectively reduced, and the test efficiency can be improved.

[0157] In another exemplary embodiment, a high degree of freedom grouping can be achieved through a port multiplexing logic module, thereby realizing a power consumption-optimal grouping strategy.

[0158] In this embodiment, the power consumption-optimized grouping strategy during the test process is to avoid clustering of test modules, which would cause chip heating and IR drop, thereby leading to overkill during the test.

[0159] In this embodiment, when grouping, it is necessary to ensure that the power consumption of each test group is evenly distributed as much as possible to avoid excessive power consumption of a certain group.

[0160] In this embodiment, assuming that there are 8 test modules that need to be tested, the number of EDT channels of each test module is 4, the chip I / O resources are 16, and 4 test modules can be tested simultaneously. Therefore, the test needs to be divided into two groups.

[0161] Furthermore, Table 2 is an example of the power consumption and physical location distribution of 8 test modules. As shown in Table 2, according to the optimal power consumption grouping strategy, the test grouping should be adjusted to modules 0, 2, 5, and 7 as one group, and modules 1, 3, 4, and 6 as another group.

[0162] Table 2:

[0163] In the disclosed embodiments, the port multiplexing logic module enables dynamic I / O resource reallocation, thereby dynamically readjusting the test module grouping strategy based on power consumption. This disclosed embodiment allows for dynamic adjustment of the grouping strategy based on actual power consumption distribution, enabling true chip quality testing and improved yield rates.

[0164] In another exemplary embodiment, high-degree-of-freedom grouping can be achieved through the port multiplexing logic module, thereby achieving full coverage testing of cross-talk paths between test modules.

[0165] In this embodiment, in scan extest mode, the cross-talk relationships between test modules are assumed to be as follows: modules 0, 1, 2, and 3 all have cross-talk with each other; modules 4, 5, 6, and 7 all have cross-talk with each other; there is cross-talk between modules 0 and 4; there is cross-talk between modules 1 and 5; there is cross-talk between modules 2 and 6; and there is cross-talk between modules 3 and 7. To fully cover all cross-talk paths, the scan extest test grouping should test the following four groups: modules 0, 1, 2, and 3 as the first group; modules 4, 5, 6, and 7 as the second group; modules 0, 4, 1, and 5 as the third group; and modules 2, 6, 3, and 7 as the fourth group.

[0166] In the disclosed embodiments, the port multiplexing logic module enables dynamic I / O resource reallocation, meeting the needs of multiple module groupings and enabling full coverage testing of cross-talk paths between test modules. This allows all test paths to be covered, improving test accuracy and facilitating chip screening.

[0167] An embodiment of the present disclosure further provides an electronic device, which includes the chip in any one of the above embodiments.

[0168] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0169] The foregoing is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that the present disclosure is susceptible to various modifications and variations. Any modifications, equivalent substitutions, improvements, and the like made within the principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A chip comprising a plurality of chip ports, a port multiplexing logic module and a scan test logic module, wherein: The port multiplexing logic module has multiple groups of first ports and multiple groups of second ports, and the multiple chip ports are divided into multiple groups according to a preset granularity; Each group of chip ports is connected to at least one of the multiple groups of first ports and the multiple groups of second ports of the port multiplexing logic module, and the multiple groups of first ports or the multiple groups of second ports of the port multiplexing logic module are connected to the scan test logic module; The port multiplexing logic module is configured to control the gating of the path between the chip port and the scan test logic module in units of the preset granularity according to a control instruction.

2. The chip according to claim 1, wherein: The plurality of chip ports are divided into i+1 groups, and the number of port groups of the scan test logic module is j+1, wherein i is less than j, and i and j are positive integers; In the case where the chip port is a chip input port, the multiple groups of first ports of the port multiplexing logic module are multiple groups of input ports, and the multiple groups of second ports of the port multiplexing logic module are multiple groups of output ports, each group of chip ports is connected to at least one group of the multiple groups of first ports of the port multiplexing logic module, the multiple groups of second ports of the port multiplexing logic module are connected to the scan test logic module, the number of input port groups of the port multiplexing logic module is i+1, and the number of output port groups of the port multiplexing logic module is j+1.

3. The chip according to claim 2, wherein: The port multiplexing logic module comprises j+1 first multiplexer groups, wherein each of the first multiplexer groups is connected to i+1 input port groups of the port multiplexing logic module, and each of the first multiplexer groups is connected to one output port group of the port multiplexing logic module; The first multiplexer group is configured to select a target input port group and a corresponding target output port group among the i+1 input port groups according to the control instruction.

4. The chip according to claim 3, wherein: When the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the first multiplexer groups includes N first multiplexers.

5. The chip according to claim 2, wherein: The port multiplexing logic module comprises i+1 first demultiplexer groups and j+1 OR operation modules, wherein each of the first demultiplexer groups is connected to one input port group of the port multiplexing logic module, each of the first demultiplexer groups is connected to the j+1 OR operation modules, and each of the OR operation modules is connected to one of the output port groups of the port multiplexing logic module; The first demultiplexer group is configured to select a target output port group among the j+1 output port groups and a corresponding target input port group according to the control instruction.

6. The chip according to claim 5, wherein: When the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the first demultiplexer groups includes N first demultiplexers.

7. The chip according to claim 1, wherein: The plurality of chip ports are divided into i+1 groups, and the number of port groups of the scan test logic module is j+1, wherein i is less than j, and i and j are positive integers; In the case where the chip port is a chip output port, the multiple groups of second ports of the port multiplexing logic module are multiple groups of output ports, and the multiple groups of first ports of the port multiplexing logic module are multiple groups of input ports, each group of chip ports is connected to at least one group of the multiple groups of second ports of the port multiplexing logic module, the multiple groups of first ports of the port multiplexing logic module are connected to the scan test logic module, the number of input port groups of the port multiplexing logic module is j+1, and the number of output port groups of the port multiplexing logic module is i+1.

8. The chip according to claim 7, wherein: The port multiplexing logic module includes i+1 second multiplexer groups, wherein each of the second multiplexer groups is connected to j+1 input port groups of the port multiplexing logic module, and each of the second multiplexer groups is connected to one output port group of the port multiplexing logic module; The second multiplexer group is configured to select a target input port group and a corresponding target output port group among the j+1 input port groups according to the control instruction.

9. The chip according to claim 8, wherein: When the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the second multiplexer groups includes N second multiplexers.

10. The chip according to claim 7, wherein: The port multiplexing logic module comprises j+1 second demultiplexer groups and i+1 OR operation modules, wherein each of the second demultiplexer groups is connected to one input port group of the port multiplexing logic module, each of the second demultiplexer groups is connected to i+1 OR operation modules, and each of the OR operation modules is connected to one of the output port groups of the port multiplexing logic module; The second demultiplexer group is configured to select a target output port group and a corresponding target input port group among the i+1 output port groups according to the control instruction.

11. The chip according to claim 10, wherein: When the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the second demultiplexer groups includes N second demultiplexers.

12. The chip according to any one of claims 1 to 11, wherein: The scan test logic module includes: a plurality of embedded deterministic test EDT channel chains, wherein the plurality of EDT channel chains are divided into a plurality of groups according to the preset granularity; The scan test logic module is configured to test a plurality of EDT channel chains connected to the chip ports.

13. The chip according to claim 12, wherein: The scan test logic module includes a plurality of scan test modules, wherein each of the scan test modules includes at least one EDT channel chain; The scan test logic module is configured to test each test group in a plurality of test groups at different times, wherein each of the test groups includes at least one EDT channel chain group, and wherein the plurality of test groups are allocated according to attribute parameters of the plurality of scan test modules.

14. The chip according to claim 13, wherein: The chip further comprises: The controller is configured to send the control instruction to the port multiplexing logic module.

15. An electronic device, comprising the chip according to any one of claims 1 to 14.

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