Wiring substrate and preparation method therefor, and display apparatus

Abstract

Disclosed in the present disclosure are a wiring substrate and a preparation method therefor, and a display apparatus, which are configured to prevent electrode corrosion in a fan-out area. A wiring substrate provided in the embodiments of the present disclosure, the wiring substrate comprising: a base substrate, which comprises a fan-out area; a plurality of first electrodes, which are located on one side of the base substrate; and a first protective layer, which is located on the side of the plurality of first electrodes away from the base substrate and comprises a plurality of first openings penetrating the thickness of the first protective layer, wherein each first opening among the plurality of first openings corresponds to one first electrode, the orthographic projection of said first opening on the base substrate overlaps the orthographic projection of the first electrode on the base substrate; the first protective layer covers at least the side surfaces of the first electrodes.

Description

Wiring substrate, manufacturing method thereof, and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on June 29, 2023, with application number 202310787059.9 and invention name "Wiring substrate, preparation method thereof, and display device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a wiring substrate and a manufacturing method thereof, and a display device. Background Art

[0004] Micro light-emitting diodes have a significant increase in usage in the display field due to their smaller size, ultra-high brightness, and long life.

[0005] Summary of the Invention

[0006] The embodiments of the present disclosure provide a wiring substrate and a manufacturing method thereof, and a display device, so as to prevent the electrodes in the fan-out area from being corroded.

[0007] An embodiment of the present disclosure provides a wiring substrate, the wiring substrate comprising:

[0008] a substrate base plate including a fan-out region;

[0009] A plurality of first electrodes are located on one side of the substrate;

[0010] The first protective layer is located on the side of the multiple first electrodes facing away from the base substrate, and includes multiple first openings running through its thickness; each of the multiple first openings corresponds to a first electrode, and the orthographic projection of the first opening on the base substrate overlaps with the orthographic projection of the first electrode on the base substrate; the first protective layer at least covers the side surfaces of the first electrode.

[0011] In some embodiments, an orthographic projection of the first opening on the substrate falls within an orthographic projection of the first electrode on the substrate.

[0012] In some embodiments, the wiring substrate further comprises:

[0013] A plurality of anti-oxidation layers are located on a side of the plurality of first electrodes away from the base substrate; each of the plurality of anti-oxidation layers is electrically connected to one of the plurality of first electrodes; and the orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the first opening on the base substrate.

[0014] In some embodiments, an orthographic projection of the first opening on the base substrate falls within an orthographic projection of the anti-oxidation layer on the base substrate;

[0015] The orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the edge of the first protection layer at the first opening on the base substrate.

[0016] In some embodiments, the wiring substrate further comprises:

[0017] The second protective layer is located on a side of the first protective layer away from the base substrate and includes a second opening; the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the second opening on the base substrate.

[0018] In some embodiments, an orthographic projection of the oxidation protection layer on the base substrate falls within an orthographic projection of the second opening on the base substrate.

[0019] In some embodiments, the wiring substrate further comprises:

[0020] The second protective layer is located on the side of the first protective layer away from the first conductive layer, and includes a plurality of second openings running through the thickness thereof; the orthographic projections of the second openings on the substrate fall within the orthographic projections of the first electrode on the substrate.

[0021] In some embodiments, the second opening and the first opening are formed in the same patterning process.

[0022] In some embodiments, at the first opening and the second opening, the anti-oxidation layer covers the side surfaces of the first protection layer and the side surfaces of the second protection layer.

[0023] In some embodiments, at the contact portion between the anti-oxidation layer and the second protective layer, a surface of the anti-oxidation layer away from the substrate and a surface of the second protective layer away from the substrate are located in the same plane.

[0024] In some embodiments, the first electrode has a first surface facing away from the substrate; and a distance between an edge of the first opening and an edge of the first surface is greater than or equal to 8 micrometers and less than or equal to 9 micrometers.

[0025] In some embodiments, the wiring substrate further comprises:

[0026] A plurality of second electrodes are located between the base substrate and the plurality of first electrodes in the fan-out region; each of the plurality of second electrodes is electrically connected to the first electrode, and an orthographic projection of the second electrode on the base substrate overlaps an orthographic projection of the first electrode on the base substrate;

[0027] a first insulating layer located between the base substrate and the plurality of second electrodes; the first insulating layer comprising a plurality of third openings extending through the thickness thereof; an orthographic projection of the third openings on the base substrate falling within an orthographic projection of the first electrode on the base substrate, and an orthographic projection of the third openings on the base substrate falling within an orthographic projection of the second electrode on the base substrate;

[0028] The second insulating layer is located on the side of the first insulating layer away from the base substrate; the first insulating layer includes a plurality of fourth openings extending through its thickness; the orthographic projection of the third opening on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, and the orthographic projection of the second electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate; the first electrode is electrically connected to the second electrode at the fourth opening and the third opening.

[0029] An embodiment of the present disclosure provides a method for preparing a wiring substrate, the method comprising:

[0030] Providing a substrate substrate; the substrate substrate includes a fan-out region;

[0031] forming a plurality of first electrodes in a fan-out region of the base substrate;

[0032] A first protective layer is formed on a side of the plurality of first electrodes facing away from the base substrate, and the first protective layer is patterned to form a plurality of first openings extending through the thickness thereof; each of the plurality of first openings corresponds to a first electrode, and the orthographic projection of the first opening on the base substrate overlaps with the orthographic projection of the first electrode on the base substrate, and the first protective layer at least covers the side surfaces of the first electrode.

[0033] In some embodiments, after patterning the first protective layer to form a plurality of first openings extending through the thickness of the first protective layer, the method further includes:

[0034] An anti-oxidation layer is formed on the side of each first electrode facing away from the base substrate by adopting a chemical plating process; the orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the first opening on the base substrate.

[0035] In some embodiments, after patterning the first protective layer to form a plurality of first openings extending through the thickness thereof and before forming the anti-oxidation layer, the method further includes:

[0036] forming a second protective layer on a side of the first protective layer away from the base substrate;

[0037] The second protection layer is patterned to form a plurality of second openings penetrating the thickness thereof; the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the second openings on the base substrate.

[0038] In some embodiments, before patterning the first protective layer to form a plurality of first openings extending through the thickness of the first protective layer, the method further includes:

[0039] forming a second protective layer on a side of the first protective layer away from the base substrate;

[0040] Performing a patterning process on the first protective layer to form a plurality of first openings penetrating the thickness of the first protective layer specifically includes:

[0041] The second protection layer and the first protection layer are patterned to form a plurality of second openings penetrating the second protection layer and a plurality of first openings penetrating the first protection layer.

[0042] In some embodiments, before forming a plurality of first electrodes in the fan-out region of the substrate, the method further includes:

[0043] forming a plurality of second electrodes in the fan-out region of the base substrate;

[0044] A first insulating layer pattern is formed on a side of the plurality of second electrodes facing away from the base substrate; the first insulating layer includes a plurality of third openings extending through the thickness thereof; the orthographic projections of the third openings on the base substrate fall within the orthographic projections of the first electrodes on the base substrate, and the orthographic projections of the third openings on the base substrate fall within the orthographic projections of the second electrodes on the base substrate;

[0045] A pattern of a second insulating layer is formed on the side of the first insulating layer facing away from the base substrate; the orthographic projection of the third opening on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, and the orthographic projection of the second electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate.

[0046] An embodiment of the present disclosure provides a light-emitting substrate, which includes the wiring substrate provided by the embodiment of the present disclosure and a light-emitting device bound to the wiring substrate.

[0047] In some embodiments, the light emitting device is a micro-sized inorganic electroluminescent device.

[0048] An embodiment of the present disclosure provides a display device, which includes the light-emitting substrate provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] FIG1 is a schematic structural diagram of a wiring substrate provided by the related art;

[0051] FIG2 is a schematic structural diagram of a wiring substrate provided in an embodiment of the present disclosure;

[0052] FIG3 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0053] FIG4 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0054] FIG5 is a schematic diagram of an enlarged structure of the D area in FIG4 according to an embodiment of the present disclosure;

[0055] FIG6 is a schematic diagram of an enlarged structure of the E region in FIG4 according to an embodiment of the present disclosure;

[0056] FIG7 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0057] FIG8 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0058] FIG9 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0059] FIG10 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0060] FIG11 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0061] FIG12 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0062] FIG13 is a cross-sectional view of GG′ in FIG5 provided by an embodiment of the present disclosure;

[0063] FIG14 is another cross-sectional view of GG′ in FIG5 provided by an embodiment of the present disclosure;

[0064] FIG15 is a cross-sectional view of JJ′ in FIG5 provided by an embodiment of the present disclosure;

[0065] FIG16 is another cross-sectional view of JJ′ in FIG5 provided by an embodiment of the present disclosure;

[0066] FIG17 is a schematic flow chart of a method for preparing a wiring substrate according to an embodiment of the present disclosure;

[0067] FIG18 is a schematic structural diagram of a light-emitting substrate provided in an embodiment of the present disclosure;

[0068] FIG19 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0070] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0071] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0072] In the related art, as shown in FIG1 , a wiring substrate includes: an electrode structure 01 disposed on one side of a substrate 06 and bonded to a circuit board, and a protective layer 02 covering the electrode structure 01; the electrode structure 01 includes a lower electrode 011 and an upper electrode 012 connected to the lower electrode 011; the protective layer 02 has a relatively large opening to expose the surface of the upper electrode 012; and the wiring substrate further includes a first insulating film layer 03, a second insulating film layer 04, and a third insulating film layer 05 located between the upper electrode 012 and the lower electrode 011. To ensure electrical connection between the circuit board and the electrode structure 01, the openings in the protective layer 02 typically completely expose the surface of the upper electrode 012, meaning that the protective layer 02 does not cover the upper electrode 012. The upper electrode 012 typically has a laminated structure, for example, including a copper layer in direct contact with the lower electrode 011, and a molybdenum-niobium alloy layer located on the side of the copper layer away from the lower electrode 011. In addition, the wiring substrate also includes a plurality of solder pads arranged on the same layer as the upper electrode 012, that is, the solder pads also include a copper layer and a molybdenum-niobium alloy layer, and the surfaces of the plurality of solder pads also need to be exposed by the openings of the protective layer 02 so that the solder pads can be connected to the pins of other components through solder. Therefore, the surfaces of the solder pads exposed by the openings of the protective layer 02 need to be solderable, while the molybdenum-niobium alloy layer only has an anti-oxidation function and has poor solderability. Before welding, the molybdenum-niobium alloy layer needs to be removed to ensure that the solder pads can be reliably connected to the components through solder. Therefore, in the process of manufacturing the wiring substrate, in the process of making the opening of the protective layer 02, in some cases, in order to take into account the reliability of other areas of the wiring substrate, it is necessary to perform an over-etching process on the protective layer 02; in this process, not only the molybdenum-niobium alloy layer in the area where the upper electrode 012 is exposed by the opening is removed, but also a portion of the first insulating film layer 03 and the second insulating film layer 04 under the protective layer 02 are also etched away, that is, in area A in Figure 1, the protective layer 02 is completely removed and a portion of the first insulating film layer 03 and the second insulating film layer 04 are both etched away. Since this area lacks the protection of the protective layer 02, water vapor can easily invade along the interface between the upper electrode 012 and the first insulating film layer 03, and can also easily invade along the second insulating film layer 04 to corrode the lower electrode 011.

[0073] The present disclosure provides a wiring substrate, as shown in FIG2 and FIG3 , which includes:

[0074] The substrate 1 includes a fan-out region 101;

[0075] A plurality of first electrodes 2 are located on one side of the base substrate 1;

[0076] The first protective layer 3 is located on the side of the multiple first electrodes 2 facing away from the base substrate 1, and includes multiple first openings 301 running through its thickness; each first opening 301 in the multiple first openings 301 corresponds to a first electrode 2, and the orthographic projection of the first opening 301 on the base substrate 1 overlaps with the orthographic projection of the first electrode 2 on the base substrate 1; the first protective layer 3 at least covers the side surface 201 of the first electrode 2.

[0077] In the wiring substrate provided by the embodiment of the present disclosure, the first protective layer at least covers the side surfaces of the first electrode, that is, the first opening does not expose the entire area of ​​the first electrode. By setting a smaller first opening so that the first protective layer can protect the side surfaces of the first electrode, corrosion caused by water vapor invading from the side surfaces of the first electrode can be avoided, thereby avoiding affecting the yield of the wiring substrate.

[0078] It should be noted that, as shown in Figures 2 and 3, the first electrode 201 also has a second surface 202 facing the base substrate 1 and a first surface 203 facing away from the base substrate 1. The side surface 201 of the first electrode 2 connects the second surface 202 and the first surface 203.

[0079] In some embodiments, as shown in FIG. 4 , in the fan-out region 10 , multiple first electrodes 2 are arranged along the first direction X; the number of first openings 301 is equal to the number of first electrodes 2 , and one first opening 301 corresponds to one first electrode 2 ; that is, multiple first openings 301 are also arranged along the first direction X.

[0080] It should be noted that FIG. 2 is, for example, a cross-sectional view along line BB′ in FIG. 4 , and FIG. 3 is, for example, a cross-sectional view along line CC′ in FIG. 4 .

[0081] In a specific implementation, the plurality of first electrodes are used to be bound to a circuit board, that is, the plurality of first electrodes serve as signal input terminals of the wiring substrate. The circuit board is, for example, a flexible circuit board or a printed circuit board.

[0082] In some embodiments, as shown in FIG4 , the substrate 1 further includes: a pad area 102, and a first peripheral area 103 and a second peripheral area 104 located on both sides of the pad area 102 in a first direction X; in a second direction Y, the fan-out area 10 is located on one side of the pad area 102; the second direction Y intersects the first direction X; FIG4 is illustrated by taking the second direction Y as perpendicular to the first direction X as an example; the pad area 102 includes a plurality of pad group units 1021.

[0083] In some embodiments, as shown in FIG. 4 , the wiring substrate further includes a plurality of signal lines 9 , and the signal lines 9 are electrically connected to the pad group unit 1021 and the first electrode 2 .

[0084] In specific implementations, the wiring substrate provided by the embodiments of the present disclosure can be applied to a light-emitting substrate, with the first pad group used to bond with the light-emitting device, and the second pad group used to bond with the driver chip. Thus, signals provided by the circuit board can be transmitted via the first electrodes to the corresponding signal lines, and then transmitted to the pad group unit to drive the light-emitting device to emit light.

[0085] In some embodiments, as shown in Figures 2 to 4 , the orthographic projection of the first opening 301 on the base substrate 1 falls within the orthographic projection of the first electrode 2 on the base substrate 1. That is, as shown in Figures 2 and 3 , the first protective layer 3 not only covers the side surfaces of the first electrode 2 but also covers a portion of the surface of the first electrode 2 facing away from the base substrate 1. This prevents the opening from exposing the side surfaces of the first electrode due to process errors, improves the protective effect of the first protective layer on the side surfaces of the first electrode, and prevents corrosion caused by moisture intrusion from the side surfaces of the first electrode, thereby preventing the yield of the wiring substrate from being affected.

[0086] In some embodiments, as shown in FIG. 2 and FIG. 3 , in any direction parallel to the plane where the substrate 1 is located, the first width L1 of the first opening 301 is smaller than the width L2 of the first surface 203 of the first electrode 2 .

[0087] It should be noted that, in Figures 2 and 3, at the first opening 301, the side surface of the first protective layer 3 is an inclined surface that is not perpendicular to the plane where the base substrate 1 is located, and the first width L1 of the first opening 301 is the minimum width of the first opening 301 in a direction parallel to the plane where the base substrate is located.

[0088] In some embodiments, L2 - L1 is the distance between the edge of the first opening and the edge of the first surface, and L2 - L1 is greater than or equal to 8 micrometers and less than or equal to 9 micrometers.

[0089] In some embodiments, in the first direction X, L1 is greater than or equal to 190 micrometers and less than or equal to 194 micrometers, L2 is greater than or equal to 198 micrometers and less than or equal to 202 micrometers, and in the second direction Y, L1 is greater than or equal to 790 micrometers and less than or equal to 794 micrometers, L2 is greater than or equal to 798 micrometers and less than or equal to 802 micrometers.

[0090] In some embodiments, as shown in FIG7 and FIG8 , the wiring substrate further includes:

[0091] Multiple anti-oxidation layers 4 are located on the side of the multiple first electrodes 2 away from the base substrate 1; each of the multiple anti-oxidation layers 4 is electrically connected to one of the multiple first electrodes 2; the orthographic projection of the anti-oxidation layer 4 on the base substrate 1 covers the orthographic projection of the first opening 301 on the base substrate 1.

[0092] It should be noted that FIG. 7 is, for example, a cross-sectional view along line BB′ in FIG. 4 , and FIG. 8 is, for example, a cross-sectional view along line CC′ in FIG. 4 .

[0093] The wiring substrate provided by the embodiment of the present disclosure has an anti-oxidation layer provided on the side of the first electrode facing away from the base substrate, which can protect the surface of the first electrode facing away from the base substrate and improve the electrical connection performance of the wiring substrate and the circuit board.

[0094] In a specific implementation, the anti-oxidation layer on the side of the first electrode facing away from the substrate is bonded to the circuit board, for example, the anti-oxidation layer and the circuit board are electrically connected via conductive adhesive to achieve bonding between the anti-oxidation layer and the circuit board. The conductive adhesive can be, for example, anisotropic conductive adhesive.

[0095] In some embodiments, as shown in FIG. 7 and FIG. 8 , the orthographic projection of the first opening 301 on the base substrate 1 falls within the orthographic projection of the anti-oxidation layer 4 on the base substrate 1 ;

[0096] Furthermore, the orthographic projection of the anti-oxidation layer 4 on the base substrate 1 covers the orthographic projection of the edge of the first protection layer 3 at the first opening 301 on the base substrate 1 .

[0097] In some embodiments, as shown in FIG. 7 and FIG. 8 , the anti-oxidation layer 4 includes a first sublayer 14 and a second sublayer 15 stacked on a side of the first electrode 2 facing away from the substrate 1 .

[0098] In a specific implementation, the anti-oxidation layer is formed by, for example, adopting a chemical plating process, that is, first growing a first sub-layer and then growing a second sub-layer on the side of the first electrode facing away from the substrate.

[0099] In some embodiments, the material of the first electrode includes copper, the material of the first sublayer included in the oxidation protection layer includes nickel, and the material of the second sublayer included in the oxidation protection layer includes gold.

[0100] In a specific implementation, the anti-oxidation layer is formed in a chemical gold (chemical nickel gold) process, where a first sub-layer, namely a nickel layer, is grown first, and then a second sub-layer, namely a gold layer, is grown.

[0101] In some embodiments, the thickness of the first sub-layer is greater than the thickness of the second sub-layer. The thickness of the first sub-layer is greater than the thickness of the first opening.

[0102] In some embodiments, the thickness of the first sub-layer is greater than or equal to 4 microns and less than or equal to 5 microns, and the thickness of the second sub-layer is greater than or equal to 0.01 microns and less than or equal to 1 micron. That is, the thickness of nickel is greater than or equal to 4 microns and less than or equal to 5 microns, and the thickness of gold is greater than or equal to 0.01 microns and less than or equal to 1 micron.

[0103] In a specific implementation, the total thickness of the anti-oxidation layer is greater than or equal to 4.01 micrometers and less than or equal to 6 micrometers. For example, the total thickness of the anti-oxidation layer is 5 micrometers.

[0104] In a specific implementation, when the anti-oxidation layer is formed using a gold deposition process, since the gold deposition process sequentially grows a nickel layer and a gold layer on a metal layer using the displacement principle, the size of the anti-oxidation layer formed by the gold deposition process is limited by the size of the corresponding first electrode. In a specific implementation, the orthographic projection of the anti-oxidation layer on the substrate coincides with the orthographic projection of the first electrode on the substrate, or the orthographic projection of the anti-oxidation layer on the substrate falls within the orthographic projection of the first electrode on the substrate. In any direction parallel to the plane of the substrate, the width of the anti-oxidation layer is less than or equal to the width of the corresponding first electrode.

[0105] On this basis, when the first protective layer covers the edge of the first electrode, the orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the edge of the first protective layer at the first opening on the base substrate, and makes the width of the anti-oxidation layer equal to the width of the corresponding first electrode in any direction parallel to the plane of the base substrate, so that the anti-oxidation layer can be maximized under process limitations, thereby maximizing the area of ​​the binding area between the anti-oxidation layer and the circuit board, which is conducive to improving the binding yield.

[0106] It should be noted that FIG7 and FIG8 illustrate an example in which the first electrode 2 includes only one first protective layer 3 on the side facing away from the base substrate 1. Of course, in some embodiments, as shown in FIG9 to FIG11 , the wiring substrate further includes:

[0107] The second protection layer 5 is located on a side of the first protection layer 3 facing away from the base substrate 1 and includes a second opening 501 .

[0108] It should be noted that the first protective layer is relatively thin, typically about 2400 angstroms, and the structure covered by the first protective layer is not flat. Therefore, the thin first protective layer covering the non-flat area is prone to cracking, affecting the first protective layer's protective effect on the underlying film layer. The wiring substrate provided in the disclosed embodiments also includes a second protective layer on the side of the first protective layer facing away from the base substrate. Even if cracks appear in the first protective layer, the second protective layer can cover the cracks to prevent moisture and other substances from invading through the cracks, thereby improving the protective effect and, in turn, the wiring substrate yield.

[0109] It should be noted that the thickness of the second protective layer is greater than that of the first protective layer. The thickness of the first protective layer is approximately 2400 angstroms, and the thickness of the second protective layer is approximately 3 microns. In the related art, when the wiring substrate includes a second protective layer, the opening of the second protective layer also needs to expose the first electrode, that is, the openings of the second protective layer and the first protective layer are both large openings. In addition, in the wiring substrate of the related art, the side of the first electrode facing away from the base substrate does not include an anti-oxidation layer. If the opening of the first protective layer is set to a small opening, it will result in a large step difference between the film layers at the opening. When the first electrode is bonded to the circuit board via conductive adhesive, a large step difference in the film layer affects the filling of the conductive adhesive, that is, the fluidity of the conductive adhesive is poor, which may result in areas where the conductive adhesive and the first electrode do not contact each other, thereby affecting the bonding reliability. The wiring substrate provided in the embodiment of the present disclosure is provided with an anti-oxidation layer on the side of the first electrode facing away from the base substrate. The anti-oxidation layer is relatively thick. Even if the opening of the first protective layer is set to a small opening, the presence of the anti-oxidation layer can eliminate the problem of poor fluidity of the conductive adhesive caused by the large step difference, avoid affecting the bonding effect, and improve the bonding yield.

[0110] In some embodiments, as shown in FIG. 9 , the orthographic projection of the first electrode 2 on the base substrate 1 falls within the orthographic projection of the second opening 501 on the base substrate 1 .

[0111] In some embodiments, as shown in FIG. 9 , the orthographic projection of the anti-oxidation layer 4 on the base substrate 1 falls within the orthographic projection of the second opening 501 on the base substrate 1 .

[0112] That is, in FIG9 , the second opening included in the second protective layer is a large opening that exposes the first electrode and the area where the anti-oxidation layer is located.

[0113] In the wiring substrate provided by the embodiment of the present disclosure, the second opening included in the second protective layer is a large opening that exposes the area where the first electrode and the anti-oxidation layer are located, which can reduce the step difference in the area, improve the fluidity of the conductive adhesive, and help improve the binding yield.

[0114] In some embodiments, as shown in Figure 12, the second protective layer 5 includes a second opening 501, and the second opening 501 corresponds to multiple first electrodes 2 and multiple anti-oxidation layers 4, that is, the orthographic projections of the multiple first electrodes 2 on the base substrate 1 fall within the orthographic projection of the second opening 501 on the base substrate 1, and the orthographic projections of the multiple anti-oxidation layers 4 on the base substrate 1 fall within the orthographic projection of the second opening 501 on the base substrate 1.

[0115] It should be noted that FIG9 is a cross-sectional view taken along line FF′ in FIG12 , and the cross-sectional view taken along line GG′ in FIG12 is the same as that in FIG8 , ie, the second protective layer is not provided in the region between two adjacent electrodes in the first direction X.

[0116] In some embodiments, as shown in FIG. 9 , in the region corresponding to the second opening 501 , a distance L3 between the second protection layer 5 and the first electrode 2 is greater than or equal to 498 micrometers and less than or equal to 502 micrometers.

[0117] In a specific implementation, in the first direction, the distance between two adjacent first electrodes is greater than or equal to 58 microns and less than or equal to 62 microns, that is, the distance between the two adjacent first electrodes is relatively small. When the opening in the second protective layer needs to expose the first electrode, the second protective layer corresponding to the area between the two adjacent first electrodes is removed, which helps to reduce the difficulty of patterning the second protective layer.

[0118] Alternatively, in some embodiments, as shown in Figures 10 and 11, the orthographic projection of the second opening 501 on the base substrate 1 falls within the orthographic projection of the first electrode 2 on the base substrate 1; and the second protective layer 5 covers the surface of the first protective layer 3 facing away from the base substrate 1.

[0119] That is, in the wiring substrate provided in the embodiment of the present disclosure, the second opening included in the second protective layer is also a small opening that only exposes a portion of the first electrode. Since the first protective layer covers the side of the first electrode, that is, the first protective layer needs to climb where it covers the first electrode, and since the first protective layer is relatively thin, it is still prone to cracking in the first protective layer where it covers the first electrode. In the wiring substrate provided in the embodiment of the present disclosure, the second opening is also a small opening that only exposes a portion of the first electrode, and the second protective layer covers the first protective layer. This can enhance the protection of the first electrode, and even if the first protective layer cracks where it covers the first electrode, it can prevent water vapor from invading along the crack and corroding the first electrode.

[0120] In some embodiments, the number of the second openings is equal to the number of the first electrodes, that is, one second opening corresponds to one first electrode.

[0121] In some embodiments, as shown in Figures 10 and 11, the second opening 501 and the first opening 301 are formed in the same patterning process. In a specific implementation, after forming the first protective layer, a patterning process is not performed to form the first opening. Instead, after forming the second protective layer, the second and first protective layers are patterned to form an opening 14 that penetrates the thickness of the second protective layer 5 and the first protective layer 3, as shown in Figures 10 and 11. That is, the opening 14 includes the second opening 501 and the first opening 301.

[0122] In the wiring substrate provided by the embodiment of the present disclosure, the second opening and the first opening are manufactured in the same patterning process, which can simplify the wiring substrate preparation process, and the patterning process of the second opening and the first opening only uses one mask plate, which can save costs.

[0123] In some embodiments, as shown in FIG. 10 and FIG. 11 , at the first opening 301 and the second opening 501 , the anti-oxidation layer 4 covers the side surfaces of the first protective layer 3 and the side surfaces of the second protective layer 5 .

[0124] In some embodiments, as shown in FIG10 and FIG11 , at the contact point between the anti-oxidation layer 4 and the second protective layer 5 , the surface of the anti-oxidation layer 4 away from the base substrate 1 and the surface of the second protective layer 5 away from the base substrate 1 are located in the same plane.

[0125] In the wiring substrate provided by the disclosed embodiments, the anti-oxidation layer covers the sides of the first protective layer and the sides of the second protective layer, thereby improving the protection of the first electrode. Furthermore, at the point of contact between the anti-oxidation layer and the second protective layer, the surface of the anti-oxidation layer facing away from the substrate and the surface of the second protective layer facing away from the substrate are coplanar, reducing the step difference in this area, improving the fluidity of the conductive adhesive, and facilitating improved bonding yield.

[0126] In some embodiments, as shown in FIG. 2 , FIG. 7 , FIG. 9 , and FIG. 10 , the wiring substrate further includes:

[0127] A plurality of second electrodes 6 are located between the base substrate 1 and the plurality of first electrodes 2 in the fan-out region; each second electrode 6 of the plurality of second electrodes 6 is electrically connected to the first electrode 2, and an orthographic projection of the second electrode 6 on the base substrate 1 overlaps with an orthographic projection of the first electrode 2 on the base substrate 1;

[0128] a first insulating layer 7 located between the base substrate 1 and the plurality of second electrodes 6; the first insulating layer 7 includes a plurality of third openings 701 extending through the thickness thereof; the orthographic projections of the third openings 701 on the base substrate 1 fall within the orthographic projections of the first electrodes 2 on the base substrate 1, and the orthographic projections of the third openings 701 on the base substrate 1 fall within the orthographic projections of the second electrodes 6 on the base substrate 1;

[0129] The second insulating layer 8 is located on the side of the first insulating layer 7 away from the base substrate 1; the first insulating layer 7 includes a plurality of fourth openings 801 extending through its thickness; the orthographic projection of the third opening 701 on the base substrate 1 falls within the orthographic projection of the fourth opening 801 on the base substrate 1, the orthographic projection of the first electrode 2 on the base substrate 1 falls within the orthographic projection of the fourth opening 801 on the base substrate 1, and the orthographic projection of the second electrode 6 on the base substrate 1 falls within the orthographic projection of the fourth opening 801 on the base substrate 1; the first electrode 2 is electrically connected to the second electrode 6 at the fourth opening 801 and the third opening 701.

[0130] The wiring substrate provided in the embodiment of the present disclosure further includes a second electrode electrically connected to the first electrode in the fan-out region, that is, the electrically connected first electrode and the second electrode jointly serve as a signal input terminal of the wiring substrate. The double-layer wiring of the signal input terminal is beneficial for increasing the resistance of the signal input terminal, thereby reducing the impedance. Furthermore, the orthographic projections of the first electrode and the second electrode on the base substrate both fall within the orthographic projection of the fourth opening on the base substrate, that is, the orthographic projection of the first electrode on the base substrate and the orthographic projection of the second insulating layer on the base substrate do not overlap, that is, there is no second insulating layer directly below the first electrode. This reduces the number of film layers at the connection between the first electrode and the second electrode, thereby reducing the thickness of the film layers, avoiding a large step difference in the electrical connection area between the first electrode and the second electrode that affects the overlap between the first electrode and the second electrode, and is beneficial for improving the yield of the wiring substrate.

[0131] In a specific implementation, as shown in Figures 2, 7, 9, and 10, the wiring substrate further includes: a buffer layer 11 located between the second electrode 6 and the base substrate 1, a third insulating layer 12 located between the second electrode 6 and the first insulating layer 7, and a fourth insulating layer 13 located between the first insulating layer 7 and the second insulating layer 8. The third insulating layer 12 and the fourth insulating layer 13 also have openings, and the orthographic projections of the openings of the third insulating layer 12 and the fourth insulating layer 13 on the base substrate 1 both fall within the orthographic projection of the first electrode 2 on the base substrate 1, that is, the first electrode 2 is electrically connected to the second electrode 6 via the opening that passes through the fourth insulating layer 13, the first insulating layer 7, and the third insulating layer 12.

[0132] In a specific implementation, the buffer layer can prevent the second electrode from being directly disposed on the substrate from falling off. The first insulating layer and the second insulating layer not only play an insulating role, but also play a flattening role.

[0133] In a specific implementation, the thickness of the first insulating layer is about 3.5 microns, the thickness of the second insulating layer is about 4 microns, the thickness of the third insulating layer is about 2400 angstroms, and the thickness of the fourth insulating layer is about 1200 angstroms.

[0134] In a specific implementation, the first protective layer, the third insulating layer, and the fourth insulating layer are, for example, inorganic layers, that is, the first protective layer, the third insulating layer, and the fourth insulating layer include inorganic insulating materials, and the inorganic insulating materials are, for example, at least one of silicon nitride, silicon oxide, silicon oxynitride, and amorphous silicon; the second protective layer, the first insulating layer, and the second insulating layer are organic layers, that is, the second protective layer, the first insulating layer, and the second insulating layer include organic insulating materials, and the organic insulating materials include, for example: dipentaerythritol pentaacrylate, dipentaerythritol hexaacrylate mixture, acrylic acid and acrylate copolymer, photoinitiator, etc.

[0135] In some embodiments, as shown in Figures 2, 7, 9, and 10, at least in the fan-out region, signal line 9 includes a first sub-signal line 9-1 and a second sub-signal line 9-2 located on different layers. That is, double-layer routing of signal line 9, at least in the fan-out region, helps increase the resistance of the signal line, thereby reducing the impedance of the signal line and preventing excessive voltage drop during signal transmission due to excessive impedance.

[0136] In a specific implementation, in an area outside the fan-out area, the signal line includes at least one of a first sub-signal line and a second sub-signal line.

[0137] In some embodiments, as shown in Figures 2, 7, 9, and 10, the first sub-signal line 9-1 is provided in the same layer as the second electrode 6, and the second sub-signal line 9-2 is provided in the same layer as the first electrode 2. The second sub-signal line 9-2 is electrically connected to the first sub-signal line 9-1 through a via hole that penetrates the fourth insulating layer 13, the second insulating layer 8, the first insulating layer 7, and the third insulating layer 12.

[0138] The film layer where the second sub-signal line and the first electrode are located is called a first conductive layer, and the film layer where the first sub-signal line and the second electrode are located is called a second conductive layer.

[0139] In some embodiments, as shown in Figures 2, 7, 9, and 10, the first sub-signal line 9-1 is connected to the second electrode 6. This enables the signal line to be electrically connected to the second electrode, the first electrode, and further to the circuit board.

[0140] In a specific implementation, for example, the first sub-signal line 9 - 1 is formed integrally with the second electrode 6 .

[0141] In a specific implementation, as shown in FIG. 2 , FIG. 7 , FIG. 9 , and FIG. 10 , the second sub-signal line 9 - 2 and the first electrode 2 are disconnected from each other.

[0142] In a specific implementation, the second sub-signal line may be connected to the first electrode, while the first sub-signal line and the second electrode may be disconnected from each other.

[0143] In a specific implementation, the first conductive layer and the second conductive layer include a third sublayer, and the material of the third sublayer includes copper. The first conductive layer and the second conductive layer may also include a fourth sublayer on the side of the third sublayer facing away from the base substrate. Specifically, the material of the third sublayer includes copper, and the fourth sublayer is a molybdenum-niobium layer formed on the surface of the copper facing away from the base substrate using a magnetron sputtering process. Forming a molybdenum-niobium layer on the surface of the copper facing away from the base substrate can protect the copper from corrosion of the conductive layer, and can also increase the surface adhesion of the first conductive layer and the second conductive layer to avoid problems of film detachment and peeling. It should be noted that the first electrode exposed in the first opening does not include the fourth sublayer, i.e., the molybdenum-niobium layer, and the first opening is formed using an over-etching process so that the molybdenum-niobium layer on the surface of the first electrode in this area is removed during the graphical process of forming the first opening.

[0144] In some embodiments, as shown in Figures 5 and 6, each pad group unit 1021 includes: at least one first pad group H1 and a second pad group H2 electrically connected to the at least one first pad group H1, the first pad group H1 includes a first pad H11 and a second pad H12, and the second pad group H2 includes: a ground pad H21, an output pad H23, an address pad H24 and a power supply pad H22.

[0145] It should be noted that FIG5 is a schematic structural diagram of the D region in FIG4 , and FIG6 is a schematic structural diagram of the E region in FIG4 .

[0146] In some embodiments, the cross-sectional view of GG′ in FIG5 is shown in FIG13 and FIG14 , and the first pad H11 and the second pad H12 are disposed in the same layer as the first electrode.

[0147] In a specific implementation, if the side of the first electrode facing away from the base substrate includes a first protective layer but does not include a second protective layer, as shown in Figure 13, the wiring substrate also includes a plurality of fourth openings 302 and a plurality of fifth openings 303 that penetrate the first protective layer 3 and expose the first conductive layer 18; the orthographic projections of the fourth openings 302 and the fifth openings 303 on the base substrate 1 fall within the orthographic projection of the first conductive layer 18 on the base substrate 1, and the portion of the first conductive layer 18 exposed by the fourth opening 302 is the first pad H11, and the portion of the first conductive layer 18 exposed by the fifth opening 303 is the second pad H12.

[0148] In a specific implementation, if the side of the first electrode facing away from the base substrate includes a first protective layer and a second protective layer, as shown in Figure 14, the wiring substrate also includes a plurality of sixth openings 16 and a plurality of seventh openings 17 that penetrate the first protective layer 3 and the second protective layer 4 and expose the first conductive layer 18; the orthographic projections of the sixth openings 16 and the seventh openings 17 on the base substrate 1 fall within the orthographic projection of the first conductive layer 18 on the base substrate 1, and the portion of the first conductive layer 18 exposed by the sixth opening 16 is the first pad H11, and the portion of the first conductive layer 18 exposed by the seventh opening 17 is the second pad H12.

[0149] In some embodiments, the cross-sectional view of JJ' in FIG5 is shown in FIG15 and FIG16 , and the ground pad H21, output pad H23, address pad (not shown), and power pad (not shown) included in the second pad group H2 are arranged in the same layer as the first electrode. The ground pad H21, output pad H23, address pad (not shown), and power pad (not shown) included in the second pad group H2 are all located in the first conductive layer 18.

[0150] It should be noted that FIG5 is an example in which the second pad group includes four pads and the second pad group includes one output pad. Of course, the second pad group may also include multiple output pads.

[0151] In a specific implementation, if the side of the first electrode facing away from the base substrate includes the first protective layer but does not include the second protective layer, as shown in Figure 15, the wiring substrate also includes a plurality of eighth openings 304, a plurality of ninth openings 305, a plurality of tenth openings (not shown) and a plurality of eleventh openings (not shown) that penetrate the first protective layer 3 and expose the first conductive layer 18; the orthographic projections of the eighth opening 304, the ninth opening 305, the tenth opening (not shown) and the eleventh opening (not shown) on the base substrate 1 fall within the orthographic projection of the first conductive layer 18 on the base substrate 1, the portion of the first conductive layer 18 exposed by the eighth opening 304 is the ground pad H21, the portion of the first conductive layer 18 exposed by the ninth opening 305 is the output pad H23, the portion of the first conductive layer exposed by the tenth opening is the address pad, and the portion of the first conductive layer exposed by the eleventh opening is the power supply pad.

[0152] In a specific implementation, if the side of the first electrode facing away from the base substrate includes a first protective layer and a second protective layer, as shown in Figure 16, the wiring substrate also includes a plurality of twelfth openings 19, a plurality of thirteenth openings 20, a plurality of fourteenth openings (not shown) and a plurality of fifteenth openings (not shown) that penetrate the first protective layer 3 and the second protective layer 4 and expose the first conductive layer 18; the orthographic projections of the twelfth opening 19, the thirteenth opening 20, the fourteenth opening and the fifteenth opening on the base substrate 1 fall within the orthographic projection of the first conductive layer 18 on the base substrate 1, the portion of the first conductive layer 18 exposed by the twelfth opening 19 is the ground pad H21, the portion of the first conductive layer 18 exposed by the thirteenth opening 20 is the output pad H23, the portion of the first conductive layer exposed by the tenth opening is the address pad, and the portion of the first conductive layer exposed by the eleventh opening is the power supply pad.

[0153] In a specific implementation, as shown in FIG5 , the plurality of signal lines 9 include, for example, a plurality of constant voltage signal lines VLED, a plurality of common voltage signal lines GND, a plurality of power signal lines 901, a plurality of address signal lines (not shown), and a plurality of cascade lines 903. In a specific implementation, the address signal lines 902, the cascade lines 903, and the power signal lines 901 all include portions located in the pad area 102.

[0154] In a specific implementation, the address signal line includes a first address signal line and a second address signal line.

[0155] It should be noted that in Figures 5 and 6, the pad group unit 1021 includes four first pad groups H1 connected in sequence as an example for illustration. Here, each pad group H1 is regarded as a whole, and the four first pad groups H1 are connected in series. The four first pad groups H1 are respectively H1-1, H1-2, H1-3, and H1-4. The constant voltage signal line VLED is electrically connected to the first pad H11 of the first pad group H1-1. Of course, each pad group unit can also include other numbers of first pad groups. When each pad group unit includes multiple first pad groups, the multiple first pad groups can be connected in series or in parallel.

[0156] In a specific implementation, multiple second pad groups in a column of pad group units can be cascaded, and the address pads of the first-level second pad group in the same column are connected to the first address signal line. As shown in Figures 5 and 6, the output pad H23 of the k-th (k is a positive integer)-level second pad group H2 and the address pad H24 of the (k+1)-th-level second pad group H2 are connected via a cascade line 903, and the output pad H23 of the last-level second pad group H2 is connected to the feedback signal line 905; the second address signal line (not shown) is located at the common line between two adjacent pad group columns. The first pad 9021 is electrically connected to the first address signal line 9021 on the side of the pad area away from the fan-out area; the cascade line 903 is also electrically connected to a second pad H22 in the first pad group H1 (the second pad H22 of H1-4 in Figures 2 and 3); each power supply pad H22 in a column of pad group 5-1 is electrically connected to the same power supply signal line 901; and each grounding pad H21 in a column of pad group 5-1 is electrically connected to the same common voltage signal line GND.

[0157] In a specific implementation, as shown in Figures 5 and 6, among the various signal lines 9 electrically connected to a column pad group unit 1021, the cascade line 903 and the power signal line 901 are located between the first pad group H1 and the common voltage signal line GND, the cascade line 903 is located in the area between the power signal line 901 and the first pad group H1, and the address signal line 902 is located on the side of the power signal line 901 away from the common voltage signal line GND adjacent to it.

[0158] In some embodiments, as shown in Figures 5 and 6, the electrostatic shielding line 904 passes through the first peripheral area 103 and the second peripheral area 104. The first border area 103 includes the electrostatic shielding line 904, the power signal line 901, the feedback signal line 905, and the fixed voltage signal line GND, and the second border area 104 includes the electrostatic shielding line 904 and the constant voltage signal line VLED.

[0159] In some embodiments, as shown in Figures 5 and 6, the power signal line 901 is integrally connected to the power supply pad H22; the power signal line 901 passes through the area between the ground pad H21 and the output pad H23 and is electrically connected to the power supply pad H22, and the ground pad H21 is electrically connected to the common voltage signal line GND.

[0160] In a specific implementation, as shown in Figures 5 and 6, the pad group unit 1021 also includes three first connecting leads 15, two longitudinal first connecting leads 15 extending along the first direction Y, and one transverse first connecting lead 15 extending along the second direction X. The first pad group H1-1 is electrically connected to the first pad group H1-2 through the longitudinal first connecting leads 15, the first pad group H1-3 is electrically connected to the first pad group H1-4 through the longitudinal first connecting leads 15, and the first pad group H1-2 is electrically connected to the first pad group H1-3 through the transverse first connecting leads 15.

[0161] In a specific implementation, if the signal line is wired in a single layer in an area outside the fan-out area, in order to reduce the process steps and save production costs, the constant voltage signal line, the cascade line, the address signal line, the feedback signal line, the power signal line, the first connection lead, and the common voltage signal line can be arranged in the same layer, that is, the above structure is located in the same conductive layer. For example, in the area of ​​single-layer wiring, the above structure is arranged in the same layer as the first electrode. It should be noted that in the present disclosure, "arranged in the same layer" refers to the use of the same film-forming process to form a film layer for making a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to one mask. Depending on the specific pattern, a single patterning process may include exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or may be at different heights or have different thicknesses.

[0162] Based on the same inventive concept, the present disclosure also provides a method for preparing a wiring substrate, as shown in FIG17 , comprising:

[0163] S101, providing a substrate; the substrate includes a fan-out region;

[0164] S102, forming a plurality of first electrodes in a fan-out region of the substrate;

[0165] S103. Form a first protective layer on the side of the multiple first electrodes facing away from the base substrate, and perform a patterning process on the first protective layer to form a plurality of first openings penetrating the thickness thereof; each of the multiple first openings corresponds to a first electrode, and the orthographic projection of the first opening on the base substrate overlaps with the orthographic projection of the first electrode on the base substrate, and the first protective layer at least covers the side surfaces of the first electrode.

[0166] In the method for preparing a wiring substrate provided by an embodiment of the present disclosure, after the first protective layer is subjected to a patterning process to form a first opening exposing the first electrode, the first protective layer at least covers the side surface of the first electrode, that is, the first opening does not expose the entire area of ​​the first electrode. By setting a smaller first opening so that the first protective layer can protect the side surface of the first electrode, corrosion caused by water vapor invading from the side surface of the first electrode can be avoided, thereby avoiding affecting the yield of the wiring substrate.

[0167] In some embodiments, after patterning the first protective layer to form a plurality of first openings extending through the thickness of the first protective layer, the method further includes:

[0168] An anti-oxidation layer is formed on the side of each first electrode facing away from the base substrate by adopting a chemical plating process; the orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the first opening on the base substrate.

[0169] In some embodiments, forming an anti-oxidation layer on a side of each first electrode facing away from the substrate by a chemical plating process specifically includes:

[0170] The anti-oxidation layer is formed using a chemical gold (electroless nickel gold) process.

[0171] Specifically, a first sub-layer, ie, a nickel layer, is first grown on a side of the first electrode facing away from the substrate, and then a second sub-layer, ie, a gold layer, is grown.

[0172] In some embodiments, after patterning the first protective layer to form a plurality of first openings extending through the thickness thereof and before forming the anti-oxidation layer, the method further includes:

[0173] forming a second protective layer on a side of the first protective layer away from the base substrate;

[0174] The second protection layer is patterned to form a plurality of second openings penetrating the thickness thereof; the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the second openings on the base substrate.

[0175] In a specific implementation, the mask plate used in the patterning process of the second protection layer to form the second opening is different from the mask plate used in the patterning process of the first protection layer to form the first opening.

[0176] In some embodiments, before patterning the first protective layer to form a plurality of first openings extending through the thickness of the first protective layer, the method further includes:

[0177] forming a second protective layer on a side of the first protective layer away from the base substrate;

[0178] Performing a patterning process on the first protective layer to form a plurality of first openings penetrating the thickness of the first protective layer specifically includes:

[0179] The second protection layer and the first protection layer are patterned to form a plurality of second openings penetrating the second protection layer and a plurality of first openings penetrating the first protection layer.

[0180] That is, after the first protective layer is formed, the first opening is not formed first. After the second protective layer is formed, an opening is formed through the second protective layer and the first protective layer in a single patterning process. This opening includes the first opening and the second opening. This allows the first opening and the second opening to be formed using a single mask, saving costs.

[0181] In some embodiments, forming a plurality of first electrodes in a fan-out region of a substrate specifically includes:

[0182] forming a third sub-layer of a plurality of first electrodes in the fan-out region of the base substrate;

[0183] forming a fourth sub-layer on a side of the third sub-layer facing away from the substrate by using a magnetron sputtering process;

[0184] The method includes performing a patterning process on the first protection layer to form a plurality of first openings penetrating the thickness of the first protection layer, and also removing the fourth sub-layer at the first openings.

[0185] In some embodiments, before forming a plurality of first electrodes in the fan-out region of the substrate, the method further includes:

[0186] forming a plurality of second electrodes in the fan-out region of the base substrate;

[0187] A first insulating layer pattern is formed on a side of the plurality of second electrodes facing away from the base substrate; the first insulating layer includes a plurality of third openings extending through the thickness thereof; the orthographic projections of the third openings on the base substrate fall within the orthographic projections of the first electrodes on the base substrate, and the orthographic projections of the third openings on the base substrate fall within the orthographic projections of the second electrodes on the base substrate;

[0188] A pattern of a second insulating layer is formed on the side of the first insulating layer facing away from the base substrate; the orthographic projection of the third opening on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, and the orthographic projection of the second electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate.

[0189] In some embodiments, before forming a plurality of second electrodes in the fan-out region of the substrate, the method further includes:

[0190] A buffer layer is formed.

[0191] In some embodiments, before forming a pattern of the first insulating layer on a side of the plurality of second electrodes facing away from the substrate, the method further includes:

[0192] forming a third insulating layer on a side of the plurality of second electrodes facing away from the substrate;

[0193] During specific implementation, the first insulating layer and the third insulating layer may be subjected to a patterning process to form the third opening of the first insulating layer and the opening of the third insulating layer.

[0194] In some embodiments, after forming a pattern of the second insulating layer on a side of the first insulating layer facing away from the substrate and before forming a plurality of first electrodes, the method further includes:

[0195] A pattern of a fourth insulating layer is formed on a side of the second insulating layer facing away from the base substrate.

[0196] In some embodiments, forming a plurality of second electrodes further includes:

[0197] forming a pattern of a first sub-signal line;

[0198] While forming the plurality of first electrodes, the method further includes:

[0199] A pattern of a second sub-signal line, a first pad group, and a second pad group is formed.

[0200] An embodiment of the present disclosure provides a light-emitting substrate, as shown in FIG18 , which includes a wiring substrate 24 provided in an embodiment of the present disclosure, and a light-emitting device bound to the wiring substrate 24 .

[0201] In some embodiments, as shown in FIG18 , the light-emitting substrate further includes: a plurality of driving chips ICs.

[0202] In some embodiments, when the wiring substrate includes a plurality of first pad groups and a plurality of second pad groups, the light emitting device is electrically connected to the first pad group, and the driving chip is electrically connected to the second pad group.

[0203] In a specific implementation, the light emitting device has two pins, which are electrically connected to the first pad and the second pad of the first pad group, respectively. The driver chip has the same number of pins as the pads in the second pad group, for example, the driver chip has four pins, which are electrically connected to the ground pad, the output pad, the address pad, and the power pad, respectively.

[0204] In some embodiments, the light emitting device is a micro-sized inorganic electroluminescent device.

[0205] In a specific implementation, the micro-sized inorganic electroluminescent device is, for example, a mini light emitting diode (Mini Light Emitting Diode, Mini-LED) or a micro light emitting diode (Micro Light Emitting Diode, Micro-LED). Mini-LED and Micro-LED are small in size and high in brightness, and can be widely used in display devices or their backlight modules. For example, the typical size (such as length) of Micro-LED is less than 100 microns, such as 10 microns to 80 microns; the typical size (such as length) of Mini-LED is 80 microns to 350 microns, such as 80 microns to 120 microns. The light-emitting element can be at least one of Micro-LED or Mini-LED.

[0206] The light-emitting substrate provided in the embodiment of the present disclosure includes the wiring substrate provided in the embodiment of the present disclosure. Therefore, the implementation of the light-emitting substrate can refer to the embodiment of the wiring substrate mentioned above, and the repeated parts will not be repeated.

[0207] An embodiment of the present disclosure provides a display device, as shown in FIG19 , which includes a light-emitting substrate 22 provided in an embodiment of the present disclosure.

[0208] In specific implementations, the light-emitting substrate can be used in the display field. For example, the light-emitting substrate can serve as a backlight source for a display panel. As shown in Figure 19 , the display device also includes a display panel 23 located on the light-emitting side of the light-emitting substrate 22. The display panel 23 is, for example, a liquid crystal display panel, comprising an array substrate 2301 and an opposing substrate 2302 disposed opposite each other, and a liquid crystal layer 2303 located between the array substrate 2301 and the opposing substrate 2302.

[0209] The display device provided by the embodiment of the present disclosure includes the wiring substrate provided by the embodiment of the present disclosure. Therefore, the implementation of the display device can refer to the embodiment of the wiring substrate mentioned above, and the repeated parts will not be repeated.

[0210] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the above-described display panel embodiments, and any repetitive details will not be repeated.

[0211] To sum up, in the wiring substrate, light-emitting substrate and display device provided by the embodiments of the present disclosure, the first protective layer at least covers the side of the first electrode, that is, the first opening does not expose the entire area of ​​the first electrode. By setting a smaller first opening so that the first protective layer can protect the side of the first electrode, corrosion caused by water vapor invading from the side of the first electrode can be avoided, thereby avoiding affecting the yield of the wiring substrate.

[0212] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0213] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A wiring substrate, wherein: The wiring substrate comprises: A substrate base plate, including a fan-out region; A plurality of first electrodes are located on one side of the substrate; A first protective layer is located on a side of the multiple first electrodes away from the base substrate, and includes multiple first openings that penetrate its thickness; each of the multiple first openings corresponds to a first electrode, and the orthographic projection of the first opening on the base substrate overlaps with the orthographic projection of the first electrode on the base substrate; the first protective layer at least covers the side surfaces of the first electrode.

2. The wiring substrate according to claim 1, wherein: The orthographic projection of the first opening on the base substrate falls within the orthographic projection of the first electrode on the base substrate.

3. The wiring substrate according to claim 2, wherein: The wiring substrate further includes: A plurality of anti-oxidation layers are located on a side of a plurality of first electrodes away from the base substrate; each of the plurality of anti-oxidation layers is electrically connected to one of the plurality of first electrodes; and the orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the first opening on the base substrate.

4. The wiring substrate according to claim 3, wherein: The orthographic projection of the first opening on the base substrate falls within the orthographic projection of the anti-oxidation layer on the base substrate; The orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the edge of the first protection layer at the first opening on the base substrate.

5. The wiring substrate according to claim 4, wherein: The wiring substrate further includes: The second protection layer is located on a side of the first protection layer away from the base substrate, and comprises a second opening; the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the second opening on the base substrate.

6. The wiring substrate according to claim 5, wherein: The orthographic projection of the anti-oxidation layer on the base substrate falls within the orthographic projection of the second opening on the base substrate.

7. The wiring substrate according to claim 3, wherein: The wiring substrate further includes: The second protective layer is located on a side of the first protective layer away from the first conductive layer, and includes a plurality of second openings penetrating through the thickness thereof; the orthographic projection of the second openings on the base substrate falls within the orthographic projection of the first electrode on the base substrate.

8. The wiring substrate according to claim 7, wherein: The second opening and the first opening are made in the same patterning process.

9. The wiring substrate according to claim 8, wherein: At the first opening and the second opening, the anti-oxidation layer covers the side surfaces of the first protection layer and the side surfaces of the second protection layer.

10. The wiring substrate according to claim 9, wherein: At the contact point between the anti-oxidation layer and the second protective layer, a surface of the anti-oxidation layer away from the base substrate and a surface of the second protective layer away from the base substrate are located in the same plane.

11. The wiring substrate according to any one of claims 1 to 10, wherein: The first electrode has a first surface facing away from the substrate; a distance between an edge of the first opening and an edge of the first surface is greater than or equal to 8 micrometers and less than or equal to 9 micrometers.

12. The wiring substrate according to any one of claims 1 to 10, wherein: The wiring substrate further includes: A plurality of second electrodes are located between the base substrate and the plurality of first electrodes in the fan-out region; each of the plurality of second electrodes is electrically connected to the first electrode, and an orthographic projection of the second electrode on the base substrate overlaps an orthographic projection of the first electrode on the base substrate; A first insulating layer is located between the base substrate and the plurality of second electrodes; the first insulating layer comprises a plurality of third openings penetrating the thickness thereof; the orthographic projection of the third openings on the base substrate falls within the orthographic projection of the first electrode on the base substrate, and the orthographic projection of the third openings on the base substrate falls within the orthographic projection of the second electrode on the base substrate; The second insulating layer is located on the side of the first insulating layer away from the substrate; the first insulating layer includes a plurality of fourth openings penetrating the thickness thereof; the third opening is projected on the substrate The fourth opening falls within the orthographic projection of the substrate, the orthographic projection of the first electrode on the substrate falls within the orthographic projection of the fourth opening on the substrate, and the orthographic projection of the second electrode on the substrate falls within the orthographic projection of the fourth opening on the substrate; the first electrode is electrically connected to the second electrode at the fourth opening and the third opening.

13. A method for preparing a wiring substrate, wherein: The method comprises: Providing a substrate substrate; the substrate substrate includes a fan-out region; forming a plurality of first electrodes in the fan-out region of the base substrate; A first protective layer is formed on a side of the multiple first electrodes away from the base substrate, and the first protective layer is patterned to form a plurality of first openings extending through the thickness thereof; each of the multiple first openings corresponds to one first electrode, an orthographic projection of the first opening on the base substrate overlaps with an orthographic projection of the first electrode on the base substrate, and the first protective layer at least covers a side surface of the first electrode.

14. The method according to claim 13, wherein: After the first protective layer is patterned to form a plurality of first openings penetrating the first protective layer, the method further comprises: An anti-oxidation layer is formed on a side of each first electrode away from the base substrate by chemical plating; the orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the first opening on the base substrate.

15. The method according to claim 14, wherein: After the first protective layer is patterned to form a plurality of first openings penetrating the thickness thereof and before the anti-oxidation layer is formed, the method further comprises: forming a second protective layer on a side of the first protective layer away from the base substrate; The second protective layer is subjected to a patterning process to form a plurality of second openings penetrating the thickness thereof; the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the second opening on the base substrate.

16. The method according to claim 14, wherein: Before patterning the first protective layer to form a plurality of first openings penetrating the first protective layer, the method further includes: forming a second protective layer on a side of the first protective layer away from the base substrate; The step of patterning the first protective layer to form a plurality of first openings penetrating the thickness of the first protective layer specifically includes: The second protection layer and the first protection layer are subjected to a patterning process to form a plurality of second openings penetrating the second protection layer and a plurality of first openings penetrating the first protection layer.

17. The method according to any one of claims 13 to 16, wherein: Before forming a plurality of first electrodes in the fan-out region of the substrate, the method further comprises: forming a plurality of second electrodes in the fan-out region of the base substrate; A pattern of a first insulating layer is formed on a side of the plurality of second electrodes away from the base substrate; the first insulating layer includes a plurality of third openings penetrating the thickness thereof; the orthographic projection of the third openings on the base substrate falls within the orthographic projection of the first electrode on the base substrate, and the orthographic projection of the third openings on the base substrate falls within the orthographic projection of the second electrode on the base substrate; A pattern of a second insulating layer is formed on the side of the first insulating layer facing away from the base substrate; the orthographic projection of the third opening on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, and the orthographic projection of the second electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate.

18. A light-emitting substrate, wherein: The light emitting substrate comprises the wiring substrate according to any one of claims 1 to 12, and a light emitting device bound to the wiring substrate.

19. The light emitting substrate according to claim 18, wherein: The light emitting device is a micro-sized inorganic electroluminescent device.

20. A display device, wherein: The display device comprises the light emitting substrate according to claim 18 or 19.

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