Display substrate, manufacturing method therefor, and display apparatus

Abstract

A display substrate, a manufacturing method therefor, and a display apparatus. The display substrate comprises a base substrate, a driving circuit layer and a plurality of light-emitting devices. The base substrate comprises a light-emitting area and a non-light-emitting area except for the light-emitting area. The driving circuit layer is located on a side of the base substrate, and the driving circuit layer comprises a plurality of data signal lines, the plurality of data signal lines being located in the non-light-emitting area. The plurality of light-emitting devices are located on the side of the driving circuit layer away from the base substrate, and the plurality of light-emitting devices comprise a first light-emitting device. An anode of the first light-emitting device comprises a plurality of sub-anodes and a connection part, there being a gap between adjacent sub-anodes, and the plurality of sub-anodes in the first light-emitting device all being connected to the connection part. The orthographic projections of the data signal lines on the base substrate do not overlap the orthographic projections of the sub-anodes on the base substrate.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to Chinese patent application No. 202310805257.3, filed on June 30, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0004] At present, with the continuous advancement of display technology, large-size OLED display devices or QLED display devices are being used more and more widely in public places such as schools, companies, stations and airports.

[0005] Summary of the Invention

[0006] On the one hand, a display substrate is provided. The display substrate includes a base substrate, a driving circuit layer, and a plurality of light-emitting devices. The base substrate includes a light-emitting area and a non-light-emitting area other than the light-emitting area. The driving circuit layer is located on one side of the base substrate, and the driving circuit layer includes a plurality of data signal lines. The plurality of data signal lines are located in the non-light-emitting area. The plurality of light-emitting devices are located on a side of the driving circuit layer away from the base substrate. The plurality of light-emitting devices include a first light-emitting device. The anode of the first light-emitting device includes a plurality of sub-anodes and a connecting portion. There is a gap between adjacent sub-anodes, and the plurality of sub-anodes are respectively connected to the connecting portions. The orthographic projection of the data signal line on the base substrate does not overlap with the orthographic projection of the sub-anode on the base substrate.

[0007] In some embodiments, the plurality of light-emitting devices further include a second light-emitting device and a third light-emitting device. The light-emitting area of ​​the first light-emitting device is larger than the light-emitting area of ​​the second light-emitting device, and the light-emitting area of ​​the first light-emitting device is larger than the light-emitting area of ​​the third light-emitting device. A portion of the sub-anodes in the first light-emitting device is located on one side of the data signal line coupled to the first light-emitting device. Another portion of the sub-anodes in the first light-emitting device is located on the other side of the data signal line coupled to the first light-emitting device.

[0008] In some embodiments, the orthographic projection of the connecting portion on the base substrate partially overlaps with the orthographic projection of the data signal line on the base substrate. The area of ​​the connecting portion is smaller than the area of ​​a single sub-anode.

[0009] In some embodiments, along a direction parallel to the substrate, in the first light-emitting device, an area of ​​a single sub-anode in a portion of the sub-anodes is greater than an area of ​​a single sub-anode in another portion of the sub-anodes.

[0010] In some embodiments, the driving circuit layer further includes a plurality of repair signal lines; the plurality of repair signal lines are located between the base substrate and the plurality of data signal lines, and the plurality of repair signal lines are located in the non-luminous area; an extension direction of the repair signal lines intersects with an extension direction of the data signal lines.

[0011] In some embodiments, a portion of the sub-anodes in the first light-emitting device are located on one side of the repair signal line; another portion of the sub-anodes in the first light-emitting device are located on the other side of the repair signal line.

[0012] In some embodiments, the anode of the first light-emitting device includes four sub-anodes and a connecting portion, wherein the connecting portion is located between two adjacent sub-anodes. The four sub-anodes include a first sub-anode, a second sub-anode, a third sub-anode, and a fourth sub-anode. The data signal line coupled to the first light-emitting device is located in the gap between the first and second sub-anodes, and between the third and fourth sub-anodes, of the first light-emitting device. The repair signal line is located in the gap between the first and third sub-anodes, and between the second and fourth sub-anodes, of the first light-emitting device.

[0013] In some embodiments, the driving circuit layer further includes a plurality of pixel circuits and a plurality of adapters. The pixel circuits are coupled to the data signal lines and the adapters, respectively. The pixel circuits are coupled to the light-emitting devices via the adapters. The orthographic projections of the adapters on the base substrate at least partially overlap with the orthographic projections of the repair signal lines on the base substrate.

[0014] In some embodiments, the adapter includes a first adapter portion and a second adapter portion. The first adapter portion is coupled to the anode of the light-emitting device, and the second adapter portion is coupled to the repair signal line. Along a direction perpendicular to the extension of the repair signal line, the second adapter portion is larger than the first adapter portion.

[0015] In some embodiments, the patterned shapes of the plurality of adapters respectively coupled to the plurality of light-emitting devices are substantially the same.

[0016] In some embodiments, the driver circuit layer further includes a plurality of first power lines. The plurality of first power lines are located on a side of the adapter proximate to the plurality of light-emitting devices. The first power lines are coupled to the pixel circuits. The orthographic projections of the first power lines on the substrate at least partially overlap with the light-emitting regions of the light-emitting devices. Within the light-emitting region, the surfaces of the first power lines proximate to the light-emitting devices are flat; and / or, within the light-emitting region, the patterned shapes of the first power lines are substantially symmetrically arranged.

[0017] In some embodiments, an orthographic projection area of ​​the first power line on the base substrate overlaps with a light-emitting area of ​​the second light-emitting device and a light-emitting area of ​​the third light-emitting device.

[0018] In some embodiments, the driving circuit layer further includes a plurality of second power lines, a plurality of first power lines, and a plurality of second power lines; the plurality of second power lines are respectively coupled to the plurality of light-emitting devices. The first power lines extend along a first direction, and the first power lines extend along a second direction. The plurality of first power lines are respectively connected to the plurality of first power lines to form a mesh structure for transmitting a first power signal. The first direction and the second direction intersect with each other. The second power lines extend along the first direction. The second power lines extend along the second direction. The plurality of second power lines are connected to the plurality of second power lines to form a mesh structure for transmitting a second power signal.

[0019] In some embodiments, within the light-emitting region of at least one light-emitting device, a surface of the driving circuit layer close to the light-emitting device is a flat surface.

[0020] In some embodiments, within a light-emitting region of at least one light-emitting device, the patterned shape of the driving circuit layer close to the surface of the light-emitting device is substantially symmetrically arranged.

[0021] In some embodiments, the driving circuit layer further includes a leveling block. The leveling block is positioned between the data signal line coupled to the first light-emitting device and the first power line, and extends in a direction substantially parallel to the direction of extension of the data signal line. The orthographic projection of the leveling block on the substrate partially overlaps with the orthographic projection of the anodes of a portion of the first light-emitting devices on the substrate. The orthographic projection of the first power line on the substrate partially overlaps with the orthographic projection of the anodes of another portion of the first light-emitting devices on the substrate.

[0022] In the light-emitting area, a surface of the leveling block close to the light-emitting device is a flat surface; and / or, in the light-emitting area, the patterned shapes of the leveling blocks are substantially symmetrically arranged.

[0023] In some embodiments, the display substrate further includes a pixel defining layer. The pixel defining layer is located on a side of the drive circuit layer away from the base substrate and includes a plurality of light-emitting openings. The plurality of light-emitting devices respectively cover the plurality of light-emitting openings. The light-emitting opening of the first light-emitting device includes a plurality of sub-light-emitting openings. The orthographic projections of the plurality of sub-anodes in the first light-emitting device on the base substrate respectively cover the orthographic projections of the outlines of the plurality of sub-light-emitting openings on the base substrate. The orthographic projection of the pixel defining layer on the base substrate covers the orthographic projection of the connecting portion of the first light-emitting device on the base substrate.

[0024] In some embodiments, the driving circuit layer further includes a plurality of enable signal lines. The plurality of enable signal lines are respectively coupled to the plurality of light-emitting devices. An orthographic projection of an enable signal line coupled to a light-emitting device on the substrate does not overlap with an orthographic projection of the sub-anode on the substrate.

[0025] On the other hand, a method for preparing a display substrate is provided. The method for preparing the display substrate includes: providing a base substrate; the base substrate includes a light-emitting area and a non-light-emitting area other than the light-emitting area. Forming a driving circuit layer on the base substrate; the driving circuit layer includes a plurality of data signal lines; the plurality of data signal lines are located in the non-light-emitting area. On a side of the driving circuit layer away from the base substrate, a plurality of light-emitting devices are formed; wherein the plurality of light-emitting devices include a first light-emitting device. The anode of the first light-emitting device includes a plurality of sub-anodes and a connecting portion. There are gaps between adjacent sub-anodes, and the plurality of sub-anodes are respectively connected to the connecting portions. The orthographic projection of the data signal line on the base substrate does not overlap with the orthographic projection of the sub-anode on the base substrate.

[0026] In another aspect, a display device is provided. The display device includes a circuit board and a display substrate according to any of the above embodiments. The display substrate is located on one side of the circuit board and is coupled to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0028] FIG1 is a structural diagram of a display device according to some embodiments;

[0029] FIG2 is a perspective view of a display substrate according to some embodiments;

[0030] FIG3 is a cross-sectional view of a display substrate along line AA′ in FIG2 according to some embodiments;

[0031] FIG4 is an equivalent circuit diagram of a pixel circuit in a display substrate according to some embodiments;

[0032] FIG5 is a cross-sectional view of a base substrate and a driving circuit layer in a display substrate according to some embodiments;

[0033] FIG6 is a structural diagram of a semiconductor layer in a display substrate according to some embodiments;

[0034] FIG7 is a structural diagram of a first conductive layer in a display substrate according to some embodiments;

[0035] FIG8 is a structural diagram of a second conductive layer in a display substrate according to some embodiments;

[0036] FIG9 is a structural diagram of a third conductive layer in a display substrate according to some embodiments;

[0037] FIG10 is a structural diagram of a fourth conductive layer in a display substrate according to some embodiments;

[0038] FIG11 is a structural diagram of an anode of a light-emitting device in a display substrate according to some embodiments;

[0039] FIG12 is a structural diagram of a pixel circuit and an anode in a display substrate according to some embodiments;

[0040] FIG13 is a structural diagram of a fourth conductive layer and a sub-anode in a display substrate according to some embodiments;

[0041] 14A to 14C are structural diagrams of pixel circuits and anodes in a display substrate according to some embodiments;

[0042] 15 to 17 are flow charts of methods for preparing a display substrate according to some embodiments. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0045] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0046] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0047] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0048] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0049] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0050] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0051] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0052] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0053] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within ±5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within ±5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0054] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0055] In addition, as used herein, "the potential of a signal is at an effective potential" means that the signal can control the potential of a transistor to be in the on state. For example, the gate of a transistor receives a signal at an effective potential, causing the transistor to be in the on state. As used herein, "the potential of a signal is at an inactive potential" means that the signal can control the potential of a transistor to be in the off state. For example, the gate of a transistor receives a signal at an inactive potential, causing the transistor to be in the off state.

[0056] It should be noted that the transistors used in the pixel circuit provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors or other switching devices with the same characteristics. The transistors in the present disclosure may be enhancement-type transistors or depletion-type transistors, and the present disclosure does not limit this.

[0057] The control electrode of each transistor used in the pixel circuit is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0058] It should also be noted that the high potential signal and low potential signal mentioned in this disclosure are relative high and low, that is, it only means that the potential of the high potential signal is higher than that of the low potential signal, and does not limit the specific potential values ​​of the high potential and the low potential.

[0059] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0060] Currently, data signal lines and anodes of light-emitting devices are arranged in a direction perpendicular to the display substrate, starting from the base substrate. The data signal lines are arranged within the light-emitting region of the light-emitting device. The data signal lines are coupled to the light-emitting devices. The light-emitting devices include red, green, and blue light-emitting devices. The anode area of ​​the blue light-emitting device is larger than that of the red light-emitting device, and the anode area of ​​the blue light-emitting device is also larger than that of the green light-emitting device.

[0061] However, the inventors of the present disclosure have discovered that, in current display substrates, data signal lines are positioned within the light-emitting area of ​​the light-emitting device. This creates a parasitic capacitor between the anode of the light-emitting device and the data signal line, with the two plates of the parasitic capacitor being the anode of the light-emitting device and the data signal line at the overlapping portion. Compared to red and green light-emitting devices, the anode area of ​​blue light-emitting devices is larger, resulting in a larger parasitic capacitance between the anode of the blue light-emitting device and the data signal line. This results in poor operating voltage stability for the blue light-emitting device, making it prone to poor charging and reducing the display quality of the display substrate. Furthermore, the large number of light-emitting devices in large-scale display substrates increases the probability of damage during the production process, reducing the display substrate's manufacturing yield. Furthermore, in large-scale display substrates, the larger anode area of ​​the light-emitting device leads to poor anode flatness, making the light-emitting device prone to tilting. This, in turn, causes the light-emitting device's light output direction to tilt toward the non-light-emitting area, which can also lead to poor display quality.

[0062] Based on this, embodiments of the present disclosure provide a display substrate and a method for manufacturing the same, as well as a display device, to overcome the above-mentioned problems, which are described below.

[0063] FIG. 1 is a structural diagram of a display device according to some embodiments.

[0064] 1 , some embodiments of the present disclosure provide a display device 1000. The display device 1000 can be used to display static images or dynamic images. Exemplarily, the display device 1000 can be an OLED display device, a Mini LED display device, or a Micro LED display device, etc. For example, the display device 1000 can be a small or medium-sized display device such as a tablet computer, a smart phone, a head-mounted display, a car navigation unit, a camera, an in-vehicle center information display (CID), a watch-type display device or other wearable device, a personal digital assistant (PDA), a portable multimedia player (PMP), and a game console, as well as medium and large electronic devices such as televisions, external billboards, monitors, home appliances including display screens, personal computers, and laptop computers. The above electronic devices can represent simple examples of application of the display device 1000, so those skilled in the art can recognize that the display device 1000 can also be other electronic devices without departing from the spirit and scope of the present disclosure.

[0065] As shown in FIG1 , a display device 1000 may include a display substrate 100 and a circuit board 200, wherein the display substrate 100 is coupled to the circuit board 200. The circuit board 200 may be located on the backlight side of the display substrate 100 (i.e., the side opposite to the display side of the display substrate 100). For example, the circuit board 200 may be a flexible printed circuit board (FPC) or a printed circuit board 200. The circuit board 200 may provide a light-emitting data signal, and the display substrate 100 emits light based on the light-emitting data signal provided by the circuit board 200.

[0066] FIG. 2 is a perspective view of a display substrate according to some embodiments.

[0067] Referring to FIG2 , some embodiments of the present disclosure provide a display substrate 100 . The display substrate 100 is a display component capable of emitting display light. The display substrate 100 can emit monochromatic light (single-color light) or colored light. The display substrate 100 can be used in the display device 1000 described above.

[0068] As shown in FIG2 , the display substrate 100 includes a display area AA for displaying images and a non-display area SA for not displaying images. The display area AA includes an emission area EA and a non-emission area FA excluding the emission area EA. The non-display area SA surrounds at least one side of the display area AA. In some examples, the non-display area SA may enclose the display area AA or be located outside the display area AA in at least one direction.

[0069] For example, the shape of the display substrate 100 in a plan view may include a rectangle, a circle, an ellipse, a diamond, a trapezoid, a square, or other shapes according to display requirements.

[0070] Exemplarily, the display substrate 100 may be an OLED display substrate, a QLED display substrate, or a Micro Light Emitting Diode (Micro LED) display substrate, etc., which is not limited here.

[0071] The following embodiments of the present disclosure are all described by taking the display substrate 100 as an OLED display substrate as an example, but it should be considered that it is not limited to the OLED display substrate.

[0072] FIG. 3 is a cross-sectional view of a display substrate taken along line AA′ in FIG. 2 according to some embodiments.

[0073] As shown in Figure 3, the display substrate 100 may include a base substrate SUB, a driving circuit layer 10, and a plurality of light-emitting devices 20. The driving circuit layer 10 is located on one side of the base substrate SUB, and the plurality of light-emitting devices 20 are located on a side of the driving circuit layer 10 away from the base substrate SUB. The driving circuit layer 10 is coupled to the plurality of light-emitting devices 20, and the driving circuit layer 10 can control and drive the plurality of light-emitting devices 20 to emit light.

[0074] The substrate SUB may be a flexible substrate SUB or a rigid substrate SUB. The rigid substrate SUB may be made of glass, quartz, or the like. The flexible substrate SUB may be made of polyethylene terephthalate (PET), polyimide (PI), cycloolefin polymer (COP), or the like.

[0075] The base substrate SUB may include a plurality of repeatedly arranged pixel unit areas PU. Each pixel unit area PU may include a plurality of light emitting areas EA and a plurality of non-light emitting areas FA.

[0076] In some examples, as shown in Figures 2 and 3, the multiple emission areas EA of each pixel unit area PU may include a first sub-pixel area P1, a second sub-pixel area P2, and a third sub-pixel area P3 that display different colors. For example, the first sub-pixel area P1 is configured to display blue light, the second sub-pixel area P2 is configured to display green light, and the third sub-pixel area P3 is configured to display red light.

[0077] The non-emission area FA may be located between the first sub-pixel area P1 and the second sub-pixel area P2 , between the second sub-pixel area P2 and the third sub-pixel area P3 , and between the third sub-pixel area P3 and the first sub-pixel area P1 .

[0078] In other examples, each pixel unit area PU may include a first sub-pixel area P1, two second sub-pixel areas P2, and a third sub-pixel area P3. The first sub-pixel area P1, the two second sub-pixel areas P2, and the third sub-pixel area P3 may be spaced apart and arranged repeatedly. In this case, the non-luminous area FA may also be located between the two second sub-pixel areas P2.

[0079] As shown in Figure 3, the driving circuit layer 10 may include multiple pixel circuits. A pixel unit area PU may include a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3. For example, the first pixel circuit PC1 is located in the first sub-pixel area P1, the second pixel circuit PC2 is located in the second sub-pixel area P2, and the third pixel circuit PC3 is located in the third sub-pixel area P3. For another example, the thin film transistor of at least one of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may be located in the non-luminescent area FA between the sub-pixel areas.

[0080] The specific structure of the pixel circuit is not limited. For example, a 2T1C, 3T1C, 4T1C, 7T1C, 7T2C, 8T1C, 9T1C, 9T2C, etc. structure may be used. The number before "T" is the number of transistors in the pixel circuit, and the number before "C" is the number of capacitors in the pixel circuit.

[0081] The transistor of at least one of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may be a thin film transistor including polysilicon or a thin film transistor including an oxide semiconductor. For example, when the thin film transistor is a thin film transistor including an oxide semiconductor, it may have a top-gate thin film transistor structure.

[0082] FIG. 4 is an equivalent circuit diagram of a pixel circuit in a display substrate according to some embodiments.

[0083] In some embodiments, as shown in FIG4 , the pixel circuit may have a 9T2C structure, including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a second capacitor C2. The pixel circuit may further include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5.

[0084] The driving circuit layer 10 may include a plurality of signal lines. The plurality of signal lines are respectively coupled to the pixel circuits. The plurality of signal lines may include a scan signal line Scan, a first gate line S1, a second gate line S2, a third gate line S3, a fourth gate line S4, a first enable signal line EM1, a second enable signal line EM2, a first initial signal line Vinit1, a second initial signal line Vinit2, a first reference signal line Ref1, a second reference signal line Ref2, a data signal line Data, a first power line VDD, and a second power line VSS.

[0085] The first node N1 is coupled to the second electrode of the first transistor, the second electrode of the second transistor T2, the control electrode of the third transistor T3, and the second plate of the first capacitor C1, respectively. The second node N2 is coupled to the first electrode of the third transistor T3, the second electrode of the eighth transistor T8, and the second electrode of the fifth transistor T5, respectively. The third node N3 is coupled to the first electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is coupled to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively. The fifth node N5 is coupled to the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the first plate of the first capacitor C1, and the second plate of the second capacitor C2, respectively.

[0086] The control electrode of the first transistor T1 is coupled to the first gate line S1, the first electrode of the first transistor T1 is coupled to the first initialization signal line Vinit1, and the second electrode of the first transistor T1 is coupled to the first node N1. The first transistor T1 transmits the first initialization voltage to the control electrode of the third transistor T3 and the first capacitor C1, thereby releasing the charge accumulated in the first capacitor C1 and initializing the first transistor. The first transistor T1 can be referred to as a first initialization transistor.

[0087] The control electrode of the second transistor T2 is coupled to the second gate line S2, the second electrode of the second transistor T2 is coupled to the first node N1, and the first electrode of the second transistor T2 is coupled to the third node N3. When a turn-on signal is applied to the second gate line S2, the second transistor T2 couples the control electrode of the third transistor T3 to the second electrode of the third transistor T3. The second transistor T2 can be referred to as a compensation transistor.

[0088] A control electrode of the third transistor T3 is coupled to the first node N1, a first electrode of the third transistor T3 is coupled to the second node N2, and a second electrode of the third transistor T3 is coupled to the third node N3. The third transistor T3 determines the magnitude of the driving current based on the potential difference between its control electrode and the first electrode. The third transistor T3 can be referred to as a driving transistor.

[0089] A control electrode of the fourth transistor T4 is coupled to the third gate line S3, a first electrode of the fourth transistor T4 is coupled to the data signal line Data, and a second electrode of the fourth transistor T4 is coupled to a fifth node N5. When a turn-on signal is applied to the third gate line S3, the fourth transistor T4 inputs the data voltage of the data signal line Data into the first capacitor C1 and the second capacitor C2. The fourth transistor T4 can be referred to as a data write transistor.

[0090] The control electrode of the fifth transistor T5 is coupled to the first enable signal line EM1, the first electrode of the fifth transistor T5 is coupled to the first power line VDD, and the second electrode of the fifth transistor T5 is coupled to the second node N2. The control electrode of the sixth transistor T6 is coupled to the second enable signal line EM2, the first electrode of the sixth transistor T6 is coupled to the third node N3, and the second electrode of the sixth transistor T6 is coupled to the fourth node N4. When a turn-on signal is applied to the first enable signal line EM1 and the second enable signal line EM2, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light-emitting device 20 to emit light. The fifth transistor T5 can be referred to as a first light-emitting write transistor. The sixth transistor T6 can be referred to as a second light-emitting write transistor.

[0091] A control electrode of the seventh transistor T7 is coupled to the scan signal line Scan, a first electrode of the seventh transistor T7 is coupled to the second initialization signal line Vinit2, and a second electrode of the seventh transistor T7 is coupled to the fourth node N4. When a turn-on signal is applied to the scan signal line Scan, the seventh transistor T7 transmits the second initialization voltage to the first electrode of the light-emitting device 20, releasing the charge accumulated in the first electrode of the light-emitting device 20, thereby initializing the light-emitting device 20. The seventh transistor T7 can be referred to as a second initialization transistor.

[0092] The control electrode of the eighth transistor T8 is coupled to the scan signal line Scan, the first electrode of the eighth transistor T8 is coupled to the second reference signal line Ref2, and the second electrode of the eighth transistor T8 is coupled to the second node N2. When a turn-on signal is applied to the scan signal line Scan, the eighth transistor T8 transmits the second reference signal to the second node N2. The eighth transistor T8 can be referred to as a second reference transistor.

[0093] A control electrode of the ninth transistor T9 is coupled to the fourth gate line S4, a first electrode of the ninth transistor T9 is coupled to the first reference signal line Ref1, and a second electrode of the ninth transistor T9 is coupled to the fifth node N5. When a turn-on signal is applied to the fourth gate line S4, the ninth transistor T9 transmits the first reference signal to the fifth node N5. The ninth transistor T9 can be referred to as a first reference transistor.

[0094] A first plate (upper plate) of the first capacitor C1 is coupled to the fifth node N5 , and a second plate (lower plate) of the first capacitor C1 is coupled to the first node N1 .

[0095] A first plate (upper plate) of the second capacitor C2 is coupled to the first power line VDD, and a second plate (lower plate) of the second capacitor C2 is coupled to the fifth node N5.

[0096] The first electrode of the light emitting device 20 is connected to the fourth node N4, the second electrode of the light emitting device 20 is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low level signal, and the signal of the first power line VDD is a continuously provided high level signal.

[0097] In some examples, the first transistor T1 to the ninth transistor T9 may be P-type transistors, or the first transistor T1 to the ninth transistor T9 may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of the display substrate process, and improve the product yield. In other examples, the first transistor T1 to the ninth transistor T9 may include P-type transistors and N-type transistors.

[0098] Exemplarily, the first transistor T1 to the ninth transistor T9 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor adopts an oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0099] In some examples, the operation process of the pixel circuit shown in FIG. 4 may include the first stage to the fifth stage.

[0100] Phase 1. The first phase may include multiple sub-phases that are repeatedly executed, and each sub-phase may include a first sub-phase and a second sub-phase that are executed sequentially.

[0101] In the first sub-stage, the signals of the first gate line S1 and the first enable signal line EM1 are on signals, and the signals of the other signal lines are off signals. The signal of the first gate line S1 being an on signal can turn on the first transistor T1, and the first initial signal of the first initial signal line Vinit1 can be provided to the first node N1 to initialize the first node N1. When the third transistor T3 is a P-type transistor, the third transistor T3 is turned on. The on signal of the first enable signal line EM1 can turn on the fifth transistor T5, and the first power signal of the first power line VDD can be provided to the second node N2.

[0102] In the second sub-stage, the signal of the second gate line S2, the fourth gate line S4 and the first enable signal line EM1 is a conduction signal, and the signal of other signal lines is a disconnection signal.Wherein, the signal of the second gate line S2 and the signal of the fourth gate line S4 can be identical.The signal of the second gate line S2 is a conduction signal that can make the second transistor T2 conducting, and the first node N1 is connected to the third node N3, and the threshold voltage of the third transistor T3 is written to the first node N1.The signal of the fourth gate line S4 is a conduction signal that can make the ninth transistor T9 conducting, and the first reference signal of the first reference signal line Ref1 is provided to the fifth node N5, and the fifth node N5 is initialized.The conduction signal of the first enable signal line EM1 can make the fifth transistor T5 conducting, and the first power signal of the first power line VDD can be provided to the second node N2.

[0103] Phase 2: The signal of the third gate line S3 is an on signal, and the signals of other signal lines are off signals. The signal of the third gate line S3 is an on signal, which can turn on the fourth transistor T4, and the data voltage provided by the data signal line Data is written into the fifth node N5.

[0104] Phase 3. The signal on the scan signal line Scan is an on signal, and the signals on the other signal lines are off signals. The signal on the scan signal line Scan turns on the seventh transistor T7, and the second initial signal on the second initial signal line Vinit2 can be written to the fourth node N4 to initialize the fourth node N4 and prevent residual signals from the previous frame from affecting the display of the current frame. The signal on the scan signal line Scan turns on the eighth transistor T8, and the second reference signal on the second reference signal line Ref2 can be written to the second node N2.

[0105] Phase 4: The signal on the second enable signal line EM2 is an on signal, and the signals on the other signal lines are off signals. The signal on the second enable signal line EM2 is an on signal, turning on the sixth transistor T6, connecting the third node N3 and the fourth node N4, so that the potentials of the third node N3 and the fourth node N4 are the same.

[0106] Phase 5. The signals on the first enable signal line EM1 and the second enable signal line EM2 are on signals, and the signals on the other signal lines are off signals. The signals on the first enable signal line EM1 and the second enable signal line EM2 are on signals, turning on the fifth transistor T5 and the sixth transistor T6. The first power signal on the first power line VDD can provide a driving signal to the light-emitting device 20 through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting device 20 to emit light.

[0107] For example, when the driving transistor (i.e., the third transistor T3) is in a state for a long time, electrons will be trapped in the trap, causing hysteresis. Therefore, in the first stage, by performing the initialization and threshold voltage writing process on the first node N1 multiple times (for example, three times), not only the hysteresis of the driving transistor can be reduced, but also the potential stability of the first node N1 can be ensured. In the third stage, the second reference signal is written to the second node N2, and by changing the potential of the second node N2, it can help to reduce the hysteresis of the driving transistor. In the fourth stage, by connecting the third node N3 and the fourth node N4, the potential of the fourth node N4 can be increased, which is beneficial to reducing the time required to subsequently reach the turn-on voltage of the light-emitting device 20. The pixel circuit provided by the present disclosure can effectively improve the hysteresis of the driving transistor, which is beneficial to improving the display effect of the display substrate 100.

[0108] In other examples, the operation process of the pixel circuit shown in FIG4 may include the sixth stage to the tenth stage.

[0109] Phase 6. The signal on the first gate line S1 is a turn-on signal, and the signals on the other signal lines are turn-off signals. The signal on the first gate line S1 is a turn-on signal, which turns on the first transistor T1. The first initial signal on the first initial signal line Vinit1 is provided to the first node N1, initializing the first node N1. The voltage of the first node N1 is the voltage of the first initial signal.

[0110] Stage 7. The signal of the scan signal line Scan is a turn-on signal, and the signals of other signal lines are turn-off signals. The signal of the scan signal line Scan is a turn-on signal, which turns on the seventh transistor T7. The second initial signal of the second initial signal line Vinit2 can be written into the fourth node N4 to initialize the fourth node N4, thereby preventing the residual signal of the previous frame from affecting the display of the current frame. The signal of the scan signal line Scan is a turn-on signal, which turns on the eighth transistor T8, and the second reference signal of the second reference signal line Ref2 can be written into the second node N2. When the third transistor T3 is a P-type transistor, the third transistor T3 is turned on. The turn-on signal of the second gate line S2 can turn on the second transistor T2, connecting the first node N1 and the third node N3. The second reference signal can be written into the first node N1 through the eighth transistor T8, the third transistor T3 and the second transistor T2 in sequence, and the voltage of the first node N1 is the voltage of the second reference signal.

[0111] Phase 8. The signals of the second gate line S2, the fourth gate line S4, and the first enable signal line EM1 are on signals, and the signals of the other signal lines are off signals. The signal of the second gate line S2 and the signal of the fourth gate line S4 may be the same. The signal of the second gate line S2 is a on signal, which can turn on the second transistor T2, connecting the first node N1 and the third node N3. The signal of the fourth gate line S4 is a on signal, which can turn on the ninth transistor T9, and the first reference signal of the first reference signal line Ref1 is provided to the fifth node N5, initializing the fifth node N5. The on signal of the first enable signal line EM1 can turn on the fifth transistor T5, and the first power signal of the first power line VDD can be provided to the second node N2. The first power signal can be provided to the first node N1 through the fifth transistor T5, the third transistor T3, and the second transistor T2 in sequence. The voltage of the first node N1 is the sum of the voltage of the first power signal and the threshold voltage of the third transistor T3.

[0112] Stage 9. The signal of the third gate line S3 is a turn-on signal, and the signals of the other signal lines are turn-off signals. The signal of the third gate line S3 is a turn-on signal, which can turn on the fourth transistor T4, and the data voltage provided by the data signal line Data is written to the fifth node N5. The data voltage provided by the data signal line Data can be provided to the first node N1 through the fifth node N5 and the first capacitor C1. The potential difference between the first plate of the first capacitor C1 and the second plate of the first capacitor C1 will not change instantaneously. The voltage change on the first plate of the first capacitor C1 is the voltage difference between the data voltage and the voltage of the first reference signal. Correspondingly, the voltage on the second plate of the first capacitor C1 will also produce the same change. The voltage of the first node N1 is the difference between the sum of the voltage of the first power signal, the threshold voltage of the third transistor T3 and the data voltage, and the voltage of the first reference signal.

[0113] Stage 10. The signals on the first enable signal line EM1 and the second enable signal line EM2 are on signals, and the signals on the other signal lines are off signals. The signals on the first enable signal line EM1 and the second enable signal line EM2 are on signals, turning on the fifth transistor T5 and the sixth transistor T6. The first power signal on the first power line VDD can provide a driving signal to the light-emitting device 20 through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting device 20 to emit light.

[0114] As shown in FIG3 , the driving circuit layer 10 may further include an insulating layer INL. The insulating layer INL may be located on the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3. The insulating layer INL may have a planarized surface. The insulating layer INL may be formed from an organic layer. For example, the insulating layer INL may include an acrylic resin, an epoxy resin, an imide resin, or an ester resin. The insulating layer INL may have through holes that expose the electrodes of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 to achieve electrical connection.

[0115] FIG. 5 is a cross-sectional view of a base substrate and a driving circuit layer in a display substrate according to some embodiments.

[0116] As shown in Figure 5, the driving circuit layer 10 provided in the embodiment of the present disclosure may include a semiconductor layer POLY, a first conductive layer EC1, a second conductive layer EC2, a third conductive layer EC3 and a fourth conductive layer EC4 located between the substrate SUB and the light-emitting device 20, and arranged in sequence from the direction away from the substrate SUB.

[0117] FIG. 6 is a structural diagram of a semiconductor layer in a display substrate according to some embodiments.

[0118] 6 , the semiconductor layer POLY may include active layers of multiple transistors in the pixel circuit. Taking the pixel circuit including the first transistor T1 to the ninth transistor T9 as an example, the semiconductor layer POLY may include the active layers p1 to p9 of the first transistor T1 to the ninth transistor T9.

[0119] In some examples, the active layers p1 to p3 of the first to third transistors T1 and p5 to p8 of the fifth to eighth transistors T5 to T8 may be interconnected in an integrated structure.

[0120] In some examples, the active layer p4 of the fourth transistor T4 and the active layer p9 of the ninth transistor T9 are interconnected and integrally formed.

[0121] In some examples, as shown in FIG6 , the semiconductor layers POLY in multiple pixel circuits located in the same column (parallel to the second direction Y) may be separated from each other. In other examples, the semiconductor layers POLY in multiple pixel circuits located in the same column (parallel to the second direction Y) may be interconnected and integrally formed.

[0122] In some examples, as shown in FIG6 , the semiconductor layers POLY in multiple pixel circuits located in the same row (parallel to the first direction X) may be interconnected as an integrated structure. In other examples, the semiconductor layers POLY in multiple pixel circuits located in the same row (parallel to the first direction X) may also be separated from each other.

[0123] For example, the semiconductor layer POLY may include a low-temperature polysilicon (LTPS) material, or a low-temperature polycrystalline oxide (LTPO), or other suitable materials, which are not limited here.

[0124] In some embodiments, a first insulating layer may be included between the semiconductor layer POLY and the first conductive layer EC1. The material of the first insulating layer may be oxide, nitride, or a combination of one or more of oxynitrides, which is not limited herein.

[0125] FIG. 7 is a structural diagram of a first conductive layer in a display substrate according to some embodiments.

[0126] In some embodiments, as shown in FIG7 , the first conductive layer EC1 may include a scan signal line Scan, a second plate C1-2 of a first capacitor C1, and a second plate C2-2 of a second capacitor C2. The scan signal line Scan extends parallel to a first direction X. In a second direction Y, the scan signal line Scan, the second plate C1-2 of the first capacitor C1, and the second plate C2-2 of the second capacitor C2 are spaced apart from each other, and the second plate C1-2 of the first capacitor C1 may be located between the second plate C2-2 of the second capacitor C2 and the scan signal line Scan. The first direction X and the second direction Y intersect with each other.

[0127] In some examples, as shown in Figure 7, the control electrode g3 of the third transistor T3 and the second plate C1-2 of the first capacitor C1 can be connected to each other as an integral structure. It is understood that the second plate C1-2 of the first capacitor C1 can be reused as the control electrode g3 of the third transistor T3.

[0128] In some examples, as shown in FIG7 , the control electrode g7 of the seventh transistor T7 , the control electrode g8 of the eighth transistor T8 , and the scan signal line Scan can be connected to each other as an integral structure. It is understood that a portion of the scan signal line Scan is multiplexed as the control electrode g7 of the seventh transistor T7 , and another portion of the scan signal line Scan is multiplexed as the control electrode g8 of the eighth transistor T8 .

[0129] For example, the first conductive layer EC1 , the second conductive layer EC2 , the third conductive layer EC3 , and the fourth conductive layer EC4 may include metal materials, alloy materials, or other conductive materials.

[0130] For example, the material of the first conductive layer EC1 and the material of the second conductive layer EC2 may include copper Cu or molybdenum Mo.

[0131] For example, the material of the third conductive layer EC3 and the material of the fourth conductive layer EC4 may include titanium Ti, aluminum Al, or a Ti / Al / Ti laminated composite material.

[0132] In some embodiments, a second insulating layer may be included between the first conductive layer EC1 and the second conductive layer EC2. The material of the second insulating layer may be similar to that of the first insulating layer, and will not be described in detail here.

[0133] FIG. 8 is a structural diagram of a second conductive layer in a display substrate according to some embodiments.

[0134] As shown in FIG8 , the second conductive layer EC2 may include a repair signal line Repair, a first enable signal line EM1, a second enable signal line EM2, a first plate C1-1 of a first capacitor C1, a first plate C2-1 of a second capacitor C2, and a second reference signal line Ref2. The repair signal line Repair, the first enable signal line EM1, the second enable signal line EM2, and the second reference signal line Ref2 generally extend in a direction parallel to the first direction X, and the repair signal line Repair, the first enable signal line EM1, the second enable signal line EM2, and the second reference signal line Ref2 are spaced apart along the second direction Y.

[0135] In which, along the second direction Y, the second enable signal line EM2 can be located between the first enable signal line EM1 and the repair signal line Repair, the first plate C1-1 of the first capacitor C1 and the first plate C2-1 of the second capacitor C2 can be located between the first enable signal line EM1 and the second reference signal line Ref2, and the first plate C2-1 of the second capacitor C2 can be located between the first plate C1-1 of the first capacitor C1 and the second reference signal line Ref2.

[0136] In some examples, as shown in FIG8 , the repair signal line Repair may include a repair block 123. In a direction perpendicular to the extension of the repair signal line Repair (i.e., a second direction Y), a dimension d1 of the repair block 123 (the width of the repair block 123 ) is greater than a dimension d2 of the repair signal line Repair. The repair block 123 and the repair signal line Repair may be an integral, interconnected structure.

[0137] In this way, the area of ​​the repair signal line Repair can be made larger, so that the repair signal line Repair can provide a relatively stable voltage for the light-emitting device 20 to be repaired, which can improve the repair effect of the light-emitting device 20 to be repaired, and thus improve the production yield of the display substrate 100.

[0138] Exemplarily, the shape of the repair signal line Repair may be a straight line with a main portion extending along the first direction X.

[0139] In some examples, the first plates C2 - 1 of the second capacitors C2 in a plurality of pixel circuits located in the same row (parallel to the first direction X) may be interconnected in an integrated structure.

[0140] In some embodiments, a third insulating layer may be included between the second conductive layer EC2 and the third conductive layer EC3. The material of the third insulating layer may be similar to that of the first insulating layer, and will not be described in detail here.

[0141] FIG. 9 is a structural diagram of a third conductive layer in a display substrate according to some embodiments.

[0142] In some embodiments, as shown in Figure 9, the third conductive layer EC3 may include a plurality of adapters 12, a first initial signal line Vinit1, a second initial signal line Vinit2, a first gate line S1, a second gate line S2, a third gate line S3, a fourth gate line S4, a first power connection line 15, a second power connection line 16, and a first reference signal connection line 17. The first initial signal line Vinit1, the second initial signal line Vinit2, the first gate line S1, the second gate line S2, the third gate line S3, the fourth gate line S4, and the first reference signal connection line 17 generally extend in a direction parallel to the first direction X, and the second initial signal line Vinit2, the first gate line S1, the second gate line S2, the third gate line S3, the fourth gate line S4, and the first reference signal connection line 17 are spaced apart in the second direction Y.

[0143] The second gate line S2 can be located between the first initial signal line Vinit1 and the second initial signal line Vinit2. Along the second direction Y, from the first initial signal line Vinit1 to the side away from the second gate line S2, the first gate line S1, the second power connection line 16, the first power connection line 15, the first reference signal connection line 17, the fourth gate line S4, and the third gate line S3 are sequentially spaced apart. A plurality of adapters 12 can be located between the second gate line S2 and the second initial signal line Vinit2. Along the first direction X, the plurality of adapters 12 are spaced apart from each other.

[0144] In some examples, as shown in FIG9 , the third conductive layer EC3 may further include a first connection block 149. The first connection block 149 may include a fifth node N5. The first connection block 149 may be located between the first reference signal connection line 17 and the first power connection line 15. A first end of the first connection block 149 is coupled to the second electrode of the fourth transistor T4 and the second electrode of the ninth transistor T9, respectively. A second end of the first connection block 149 is coupled to the second plate C2-2 of the second capacitor C2. A third end of the first connection block 149 is coupled to the first plate C1-1 of the first capacitor C1.

[0145] Exemplarily, the shape of the first connection block 149 may be L-shaped, or other shapes.

[0146] 9 , the third conductive layer EC3 may further include a second connection block 151 . A first end of the second connection block 151 is coupled to the first plate C2 - 1 of the second capacitor C2 , and a second end of the second connection block 151 is coupled to the first power connection line 15 .

[0147] Exemplarily, the first power connection line 15 and the second connection block 151 may be an integrated structure connected to each other.

[0148] In some examples, as shown in FIG9 , the third conductive layer EC3 may further include a third connection block 112. The third connection block 112 may be located between the second power connection line 16 and the first gate line S1. The third connection block 112 may include a first node N1. A first end of the third connection block 112 is coupled to the second plate C1-2 of the first capacitor C1, and a second end of the third connection block 112 is coupled to the second electrode of the first transistor T1 and the first electrode of the second transistor T2, respectively.

[0149] In some examples, as shown in Figures 4 and 9, the adapter 12 is coupled to the pixel circuit and the light-emitting device 20, respectively. For example, the adapter 12 may include a fourth node N4, one end of the adapter 12 may be coupled to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the other end of the adapter 12 may be coupled to the anode of the light-emitting device 20. In this way, the pixel circuit can be coupled to the light-emitting device 20 through the adapter 12, thereby controlling the brightness of the light-emitting device 20.

[0150] 9 , the adapter 12 includes a first adapter portion 121 and a second adapter portion 122. The first adapter portion 121 is coupled to the anode of the light emitting device 20, and the second adapter portion 122 is coupled to the repair signal line Repair.

[0151] Along an extending direction perpendicular to the repair signal line Repair, a size d3 of the second transition portion 122 (a width of the second transition portion 122 ) is greater than a size d4 of the first transition portion 121 (a width of the first transition portion 121 ).

[0152] In this way, the second adapter part 122 and the repair signal line Repair can form a repair unit. The size d3 of the second adapter part 122 is larger than the size d4 of the first adapter part 121, so that the area of ​​the repair unit can be larger, so that the repair unit can provide a relatively stable voltage for the light-emitting device 20 to be repaired, which can improve the repair effect of the repair unit on the light-emitting device 20 to be repaired, and thereby improve the production yield of the display substrate 100.

[0153] In some examples, as shown in FIG. 9 , the patterned shapes of the plurality of adapters 12 respectively coupled to the plurality of light emitting devices 20 are substantially the same.

[0154] The patterned structures of multiple adapters 12 are the same, and the repair unit can provide a stable voltage for the different color light-emitting devices 20 to be repaired, so that the repair unit has the same repair effect on the different color light-emitting devices 20 to be repaired, thereby improving the uniformity of the luminous efficiency between the different color light-emitting devices 20 in the display substrate 100.

[0155] Exemplarily, the patterned shape of the adapter 12 coupled to the first light emitting device LD1 is substantially the same as the patterned shape of the adapter 12 coupled to the second light emitting device LD2 .

[0156] In this way, the repair unit can provide a stable voltage for the first light-emitting device LD1 to be repaired and the second light-emitting device LD2 to be repaired, so that the repair unit has the same repair effect on the first light-emitting device LD1 to be repaired and the second light-emitting device LD2 to be repaired, thereby improving the uniformity of the luminous efficiency between the first light-emitting device LD1 to be repaired and the second light-emitting device LD2 to be repaired in the display substrate 100.

[0157] Exemplarily, the patterned shape of the adapter 12 coupled to the first light emitting device LD1 is substantially the same as the patterned shape of the adapter 12 coupled to the third light emitting device LD3 .

[0158] In this way, the repair unit can provide a stable voltage for the first light-emitting device LD1 to be repaired and the third light-emitting device LD3 to be repaired, so that the repair unit has the same repair effect on the first light-emitting device LD1 to be repaired and the third light-emitting device LD3 to be repaired, thereby improving the uniformity of the luminous efficiency between the first light-emitting device LD1 to be repaired and the third light-emitting device LD3 to be repaired in the display substrate 100.

[0159] Exemplarily, the patterned shape of the adapter 12 coupled to the first light emitting device LD1 , the patterned shape of the adapter 12 coupled to the second light emitting device LD2 , and the patterned shape of the adapter 12 coupled to the third light emitting device LD3 are substantially the same.

[0160] In this way, the repair unit can provide a stable voltage for the first light-emitting device LD1 to be repaired, the second light-emitting device LD2 to be repaired, and the third light-emitting device LD3 to be repaired, so that the repair unit has the same repair effect on the first light-emitting device LD1 to be repaired, the second light-emitting device LD2 to be repaired, and the third light-emitting device LD3 to be repaired, thereby improving the uniformity of the luminous efficiency among the first light-emitting device LD1 to be repaired, the second light-emitting device LD2 to be repaired, and the third light-emitting device LD3 to be repaired in the display substrate 100.

[0161] For example, the shape of the adapter 12 may include a convex shape, a polygonal shape, or other shapes.

[0162] 9 , a reference signal connection block 171 may be provided on the first reference signal connection line 17. The first reference signal connection line 17 may be connected to the first reference signal line Ref1 through the reference signal connection block 171.

[0163] FIG. 10 is a structural diagram of a fourth conductive layer in a display substrate according to some embodiments.

[0164] In some embodiments, a fourth insulating layer may be further included between the third conductive layer EC3 and the fourth conductive layer EC4. The material of the fourth insulating layer may be similar to that of the first insulating layer, and will not be described in detail here.

[0165] In some embodiments, the fourth conductive layer EC4 may be located between the third conductive layer EC3 and the anode of the light-emitting device 20. As shown in FIG10 , the fourth conductive layer EC4 may include a plurality of first power lines VDD, a plurality of second power lines VSS, a plurality of data signal lines Data, and a plurality of first reference signal lines Ref1. The plurality of first power lines VDD, the plurality of second power lines VSS, the plurality of data signal lines Data, and the plurality of first reference signal lines Ref1 generally extend in a direction parallel to the second direction Y and are spaced apart in the first direction X.

[0166] The first power line VDD and the data signal line Data may be located between the first reference signal line Ref1 and the second power line VSS. The first power line VDD may be located between the first reference signal line Ref1 and the data signal line Data.

[0167] It can be understood that the first power line VDD, the second power line VSS, the data signal line Data and the first reference signal line Ref1 can be provided on the same layer.

[0168] In some embodiments, the first power line VDD, the second power line VSS, the data signal line Data, and the first reference signal line Ref1 are arranged on different layers, requiring at least two conductive layers to be provided for arranging the first power line VDD, the second power line VSS, the data signal line Data, and the first reference signal line Ref1, respectively. In this embodiment, the first power line VDD, the second power line VSS, the data signal line Data, and the first reference signal line Ref1 are arranged on the same layer. This reduces the number of conductive layers required for the display substrate 100, thereby simplifying the manufacturing process and reducing the manufacturing cost of the display substrate 100. Furthermore, the dimension of the display substrate 100 in the third direction Z (i.e., the thickness of the display substrate 100) can be reduced, facilitating a thinner and lighter display substrate 100.

[0169] For example, the second power line VSS may be in the shape of a straight line with a main portion extending along the second direction Y.

[0170] In some examples, as shown in FIG10 , a data signal connection block 411 is provided on the data signal line Data. A first end of the data signal connection block 411 is connected to the data signal line Data, and a second end of the data signal connection block 411 can be coupled to the first electrode of the fourth transistor T4, so that the data signal line Data can write the data signal to the first electrode of the fourth transistor T4.

[0171] For example, the shape of the data signal line Data may be a straight line with a main portion extending along the second direction Y.

[0172] 10 , the fourth conductive layer EC4 may further include a spacer 160. The spacer 160 is located between the data signal line Data and the first power line VDD.

[0173] For example, the leveling block 160 may be in the shape of a straight line with a main portion extending along the second direction Y.

[0174] FIG. 11 is a structural diagram of an anode of a light-emitting device in a display substrate according to some embodiments.

[0175] As shown in FIG3 , the display substrate 100 may include a pixel defining layer (PDL) on a base substrate (SUB). The pixel defining layer (PDL) may be formed on an insulating layer (INL) and include a plurality of light emitting openings. A plurality of light emitting devices 20 may cover the plurality of light emitting openings, respectively.

[0176] As shown in Figures 3 and 11, in a pixel unit area PU, the multiple light-emitting devices 20 may include a first light-emitting device LD1, a second light-emitting device LD2, and a third light-emitting device LD3, each displaying a different color. The first light-emitting device LD1 may be located in the first sub-pixel area P1, the second light-emitting device LD2 may be located in the second sub-pixel area P2, and the third light-emitting device LD3 may be located in the third sub-pixel area P3. For example, the first light-emitting device LD1 may be a blue light-emitting device, the second light-emitting device LD2 may be a green light-emitting device, and the third light-emitting device LD3 may be a red light-emitting device.

[0177] For example, among the plurality of light-emitting devices 20, the light-emitting area EA of the first light-emitting device LD1 may be larger than the light-emitting area EA of the second light-emitting device LD2, and the light-emitting area EA of the first light-emitting device LD1 may be larger than the light-emitting area EA of the third light-emitting device LD3. It is understood that the anode area of ​​the first light-emitting device LD1 may be larger than the anode area of ​​the second light-emitting device LD2, and the anode area of ​​the first light-emitting device LD1 may be larger than the anode area of ​​the third light-emitting device LD3.

[0178] For example, the light-emitting device 20 may be an OLED, which includes a stacked first electrode (e.g., an anode), an organic light-emitting layer, and a second electrode (e.g., a cathode). Alternatively, the light-emitting device 20 may be a QLED, which includes a stacked first electrode (e.g., an anode), a quantum dot light-emitting layer, and a second electrode (e.g., a cathode).

[0179] FIG. 12 is a structural diagram of a pixel circuit and an anode in a display substrate according to some embodiments.

[0180] In some embodiments, as shown in Figures 11 and 12, the anode of the first light-emitting device LD1 may include multiple sub-anodes 22 and a connecting portion 23. The multiple sub-anodes 22 are respectively connected to the connecting portion 23. For example, the multiple sub-anodes 22 and the connecting portion 23 in the first light-emitting device LD1 may be an integrated structure connected to each other.

[0181] There are gaps between adjacent sub-anodes 22. It can be understood that there are gaps between adjacent sub-anodes 22 in the first light emitting device LD1 along the first direction X. There are also gaps between adjacent sub-anodes 22 in the first light emitting device LD1 along the second direction Y.

[0182] For example, the shape of the sub-anode 22 may be a rectangle, a trapezoid, or a polygon. The shape of the sub-anode 22 may also be other shapes that facilitate the exposure of key signal lines.

[0183] FIG. 13 is a structural diagram of a fourth conductive layer and a sub-anode in a display substrate according to some embodiments.

[0184] As shown in Figure 13, a plurality of data signal lines Data are located in the non-luminescent area FA. The orthographic projections of the data signal lines Data on the base substrate SUB do not overlap with the orthographic projections of the sub-anode 22 on the base substrate SUB.

[0185] In this way, the data signal line Data can avoid the sub-anode 22, and the overlapping area between the data signal line Data and the anode of the light-emitting device 20 can be reduced as much as possible, thereby reducing the parasitic capacitance between the data signal line Data and the anode of the light-emitting device 20, improving the stability of the operating voltage of the light-emitting device 20, and further improving the display effect of the display substrate 100.

[0186] 14A to 14C are structural diagrams of pixel circuits and anodes in a display substrate according to some embodiments.

[0187] In some examples, as shown in Figures 13 and 14B , a portion of the sub-anodes 22 in the first light-emitting device LD1 is located on one side of the data signal line Data coupled to the first light-emitting device LD1. Another portion of the sub-anodes 22 in the first light-emitting device LD1 is located on the other side of the data signal line Data coupled to the first light-emitting device LD1. It can be understood that the data signal line Data coupled to the first light-emitting device LD1 is located in the gap between adjacent sub-anodes 22 in the first light-emitting device LD1.

[0188] In this way, when the anode area of ​​the first light-emitting device LD1 in the display substrate 100 is large, the data signal line Data can be set away from the sub-anode 22 of the first light-emitting device LD1, and the overlapping area between the data signal line Data and the anode of the first light-emitting device LD1 can be reduced as much as possible, thereby reducing the parasitic capacitance between the data signal line Data and the anode of the first light-emitting device LD1, improving the stability of the operating voltage of the first light-emitting device LD1, and thereby improving the display effect of the display substrate 100.

[0189] In some embodiments, an orthographic projection of an enable signal line coupled to the light emitting device 20 on the substrate SUB does not overlap with an orthographic projection of the sub-anode 22 on the substrate SUB.

[0190] For example, as shown in FIG8 and FIG14B , the orthographic projection of the second enable signal line EM2 on the substrate SUB does not overlap with the orthographic projection of the sub-anode 22 on the substrate SUB.

[0191] In this way, an enable signal line coupled to the light-emitting device 20 can be set to avoid the area where the sub-anode 22 is located. No parasitic capacitance will be generated between the enable signal line and the sub-anode 22 of the light-emitting device 20, and the parasitic capacitance between the enable signal line and the anode of the light-emitting device 20 in the overlapping area can be reduced, so that the enable signal line can provide a stable enable signal to the light-emitting device 20, so that the light-emitting device 20 can emit light stably, thereby improving the display effect of the display substrate 100.

[0192] In some embodiments, a plurality of repair signal lines Repair may be located in the non-light emitting area FA.

[0193] In this way, the repair signal line Repair can be coupled to the light-emitting device 20 to be repaired, so that the repair signal line Repair can provide a stable voltage for the light-emitting device 20 to be repaired, thereby realizing the repair of the light-emitting device 20 to be repaired, and improving the manufacturing yield of the display substrate 100.

[0194] In some examples, as shown in FIG14B , a portion of the sub-anode 22 in the first light-emitting device LD1 can be located on one side of the repair signal line Repair. Another portion of the sub-anode 22 in the first light-emitting device LD1 can be located on the other side of the repair signal line Repair. It will be appreciated that, along the second direction Y, the repair signal line Repair can be located in the non-luminescent area FA between adjacent portions of the sub-anode 22 and the other portion of the sub-anode 22 in the first light-emitting device LD1.

[0195] The repair signal line Repair is set in the non-luminous area FA between the multiple sub-anodes 22 of the first light-emitting device LD1, which can avoid the overlap of the multiple sub-anodes 22 in the first light-emitting device LD1 with the repair signal line Repair, and minimize the overlap between the anode of the first light-emitting device LD1 and the repair signal line Repair, so that when the repair signal line Repair is coupled to the light-emitting device 20 to be repaired, the repair signal line Repair can provide a stable voltage for the light-emitting device 20 to be repaired, thereby realizing the repair of the light-emitting device 20 to be repaired, and can improve the production yield of the display substrate 100.

[0196] For example, as shown in FIG14B , the anode of the first light-emitting device LD1 may include four sub-anodes 22 and a connecting portion 23. A connecting portion 23 may be located between any two adjacent sub-anodes 22. The four sub-anodes 22 may include a first sub-anode 221, a second sub-anode 222, a third sub-anode 223, and a fourth sub-anode 224. Along the first direction X, the first sub-anode 221 and the second sub-anode 222 may be located in the same row, while the third sub-anode 223 and the fourth sub-anode 224 may be located in another row.

[0197] The data signal line Data coupled to the first light emitting device LD1 is located in the gap between the adjacent first and second sub-anodes 221 and 222 and between the adjacent third and fourth sub-anodes 223 and 224 in the first light emitting device LD1 .

[0198] In this way, when the anode area of ​​the first light-emitting device LD1 in the display substrate 100 is large, the data signal line Data can be set in the gap between the four adjacent sub-anodes 22, so that the overlapping area between the data signal line Data and the anode of the first light-emitting device LD1 can be reduced to the overlapping area between the data signal line Data and the connecting portion 23, thereby greatly reducing the parasitic capacitance between the data signal line Data and the anode of the first light-emitting device LD1, improving the stability of the operating voltage of the first light-emitting device LD1, and thereby improving the display effect of the display substrate 100.

[0199] 8 , 12 , and 14B , the repair signal line Repair may also be located between the adjacent first sub-anode 221 and third sub-anode 223 in the first light-emitting device LD1, and between the adjacent second sub-anode 222 and fourth sub-anode 224. It is understood that the repair signal line Repair may be located between any two adjacent first and second sub-anodes 221, 222 and third and fourth sub-anodes 223, 224 in the first light-emitting device LD1.

[0200] On the basis of improving the display effect of the display substrate 100, it is also possible to avoid the overlap of the four sub-anodes 22 in the first light-emitting device LD1 with the repair signal line Repair, and minimize the overlap of the anode of the first light-emitting device LD1 and the repair signal line Repair, so that when the repair signal line Repair is coupled to the light-emitting device 20 to be repaired, the repair signal line Repair can provide a stable voltage for the light-emitting device 20 to be repaired, thereby realizing the repair of the light-emitting device 20 to be repaired, and can improve the manufacturing yield of the display substrate 100.

[0201] In some embodiments, as shown in FIG12 and FIG14B , the orthographic projection of the adapter 12 on the base substrate SUB can at least partially overlap with the orthographic projection of the repair signal line Repair on the base substrate SUB. It is understood that the orthographic projection of the adapter 12 on the base substrate SUB can partially overlap with the orthographic projection of the repair signal line Repair on the base substrate SUB; or the orthographic projection of the adapter 12 on the base substrate SUB can overlap with the orthographic projection of the repair signal line Repair on the base substrate SUB.

[0202] In this way, the repair signal line Repair and the adapter 12 at least partially overlapping locations can form a repair unit, which can avoid the anode of the light-emitting device 20. The adapter 12 coupled to the light-emitting device 20 to be repaired can be connected to the repair signal line Repair, so that the repair unit can provide a stable voltage to the light-emitting device 20 to be repaired, thereby allowing the light-emitting device 20 to be repaired to operate normally, thereby improving the manufacturing yield of the display substrate 100.

[0203] In some examples, the orthographic projection of the adapter 12 on the substrate SUB may partially overlap with the orthographic projection of the repair signal line Repair on the substrate SUB.

[0204] In this way, the partially overlapping repair signal line Repair and the adapter 12 can form a repair unit, which can avoid the anode of the light-emitting device 20. The adapter 12 coupled to the light-emitting device 20 to be repaired can be connected to the repair signal line Repair, so that the repair unit can provide a stable voltage to the light-emitting device 20 to be repaired, thereby allowing the light-emitting device 20 to be repaired to operate normally, thereby improving the manufacturing yield of the display substrate 100.

[0205] In some examples, the orthographic projection of the adapter 12 on the base substrate SUB may overlap with the orthographic projection of the repair signal line Repair on the base substrate SUB. It is understandable that the orthographic projection of the repair signal line Repair on the base substrate SUB may completely cover the orthographic projection of the adapter 12 on the base substrate SUB.

[0206] In this way, the repair signal line Repair and the adapter 12 at the overlapping portion can form a repair unit, which can avoid the anode of the light-emitting device 20. The adapter 12 coupled to the light-emitting device 20 to be repaired can be connected to the repair signal line Repair, so that the repair unit can provide a relatively stable voltage to the light-emitting device 20 to be repaired, thereby allowing the light-emitting device 20 to be repaired to operate normally, which can significantly improve the manufacturing yield of the display substrate 100.

[0207] In some examples, as shown in FIG14A , when a sub-pixel has a defective pixel that needs repair, a through hole 125 can be opened at the overlapping portion of the repair signal line Repair and the adapter 12. For example, through hole 125 can be opened by laser drilling, and the adapter 12 is connected to the repair signal line Repair through the through hole 125. It will be appreciated that when no defective pixel exists in the sub-pixel, laser drilling between the adapter 12 and the repair signal line Repair is not necessary; reference can be made to FIG12 .

[0208] In this way, the light-emitting device 20 to be repaired at the defective point can be electrically connected to the repair signal line Repair, and the repair signal line Repair can transmit a repair drive signal to the light-emitting device 20 to be repaired to drive the light-emitting device 20 to be repaired.

[0209] For example, the plurality of light-emitting devices 20 may include a plurality of normal light-emitting devices and at least one dummy light-emitting device. The pixel circuits of the dummy light-emitting devices may be coupled to the repair signal line Repair and the light-emitting device 20 to be repaired, respectively. The pixel circuits of the dummy light-emitting devices may transmit the repair drive signal to the light-emitting device 20 to be repaired via the repair signal line Repair.

[0210] For another example, the repair signal line Repair may transmit a constant voltage repair driving signal to the light emitting device 20 to be repaired, so that the light emitting device 20 to be repaired becomes a dark spot (ie, does not emit light).

[0211] For example, as shown in FIG14A , the orthographic projection of the outline of the through hole 125 on the substrate SUB does not at least partially overlap with the orthographic projection of the anode of the light-emitting device 20 on the substrate SUB. It is understood that the orthographic projection of the outline of the through hole 125 on the substrate SUB does not partially overlap with the orthographic projection of the anode of the light-emitting device 20 on the substrate SUB. Alternatively, the orthographic projection of the outline of the through hole 125 on the substrate SUB does not overlap with the orthographic projection of the anode of the light-emitting device 20 on the substrate SUB.

[0212] For example, the orthographic projection of the outline of the through hole 125 on the substrate SUB does not at least partially overlap with the orthographic projection of the outline of the light-emitting opening of the light-emitting device 20 on the substrate SUB. It is understandable that the orthographic projection of the outline of the through hole 125 on the substrate SUB does not partially overlap with the orthographic projection of the outline of the light-emitting opening of the light-emitting device 20 on the substrate SUB. Alternatively, the orthographic projection of the outline of the through hole 125 on the substrate SUB does not overlap with the orthographic projection of the outline of the light-emitting opening of the light-emitting device 20 on the substrate SUB.

[0213] In this way, the flatness of the anode of the light emitting device 20 can be ensured.

[0214] In some examples, as shown in FIG14C , the area of ​​the adapter 12 corresponding to the green sub-pixel can be designed to be larger than the area of ​​the adapter 12 corresponding to the red sub-pixel, and the area of ​​the adapter 12 corresponding to the green sub-pixel can be designed to be larger than the area of ​​the adapter 12 corresponding to the blue sub-pixel.

[0215] Since the adapter 12 is connected to the anode of each corresponding sub-pixel, considering that the luminous efficiency and brightness of the green sub-pixel are higher, the area of ​​the adapter 12 corresponding to the green sub-pixel can be made larger, so that the overlapping area of ​​the adapter 12 corresponding to the green sub-pixel and the repair signal line Repair thereunder can be larger, thereby increasing the capacitance of the coupling capacitor corresponding to the anode of the green sub-pixel, so that the display effect of the sub-pixels of each color is uniform.

[0216] In some examples, considering other characteristics of the sub-pixels, the area of ​​the adapter 12 corresponding to one of the green, blue, or red sub-pixels can be designed to be different from the area of ​​the adapter 12 corresponding to sub-pixels of other luminous colors. This can ensure that the area of ​​the overlapping region between the adapter 12 corresponding to one of the green, blue, or red sub-pixels and the underlying repair signal line Repair is larger or smaller than the area of ​​the overlapping region between the adapter 12 corresponding to sub-pixels of other luminous colors and the underlying repair signal line Repair. In this way, uniform light emission can be ensured.

[0217] In some examples, the display substrate 100 can be divided into a normal display area and a special function display area. For example, the special function display area can include a high brightness display area or a low brightness display area. The area of ​​the overlap between the adapter 12 and the underlying repair signal line Repair corresponding to the sub-pixel in the normal display area can be designed to be larger or smaller than the area of ​​the overlap between the adapter 12 and the underlying repair signal line Repair corresponding to the sub-pixel in the special function display area, so that the coupling capacitance of the corresponding anode can be adjusted according to the area of ​​the overlap between the adapter 12 and the underlying repair signal line Repair, thereby further improving the uniformity of the display effect.

[0218] In some examples, as shown in Figures 13 and 14B, in the first light-emitting device LD1, the area of ​​a single sub-anode 22 in a portion of the sub-anodes 22 may be different from the area of ​​a single sub-anode 22 in another portion of the sub-anodes 22 along a direction parallel to the substrate SUB.

[0219] For example, the area of ​​a single sub-anode 22 in one portion of the sub-anodes 22 may be larger than the area of ​​a single sub-anode 22 in another portion of the sub-anodes 22 .

[0220] The area of ​​a single sub-anode 22 in the first light-emitting device LD1 can be flexibly designed according to actual needs, so that the sub-anode 22 can avoid the data signal line Data or the repair signal line Repair setting, and minimize the overlapping area between the data signal line Data and the anode of the first light-emitting device LD1 or the overlapping area between the repair signal line Repair and the anode of the first light-emitting device LD1.

[0221] In other examples, along a direction parallel to the substrate SUB, the area of ​​a single sub-anode 22 in one portion of the sub-anodes 22 may be the same as the area of ​​a single sub-anode 22 in another portion of the sub-anodes 22 .

[0222] 14B , the area of ​​the first sub-anode 221 may be greater than that of the second sub-anode 222 along the first direction X. The area of ​​the first sub-anode 221 may be the same as that of the third sub-anode 223 along the second direction Y.

[0223] In some embodiments, as shown in Figures 3, 12, and 14B, the light-emitting opening K1 of the first light-emitting device LD1 may include multiple sub-light-emitting openings K11. The orthographic projections of the multiple sub-anodes 22 in the first light-emitting device LD1 on the substrate SUB respectively overlap the orthographic projections of the outlines of the multiple sub-light-emitting openings K11 on the substrate SUB. For example, the light-emitting opening K1 of the first light-emitting device LD1 may include four sub-light-emitting openings K11. The orthographic projections of the four sub-anodes 22 in the first light-emitting device LD1 on the substrate SUB respectively overlap the orthographic projections of the outlines of the four sub-light-emitting openings K11 on the substrate SUB.

[0224] The orthographic projection of the pixel defining layer PDL on the base substrate SUB may cover the orthographic projection of the connecting portion 23 of the first light emitting device LD1 on the base substrate SUB. It is understandable that the orthographic projection of the pixel defining layer PDL on the base substrate SUB may overlap with the orthographic projection of the connecting portion 23 of the first light emitting device LD1 on the base substrate SUB.

[0225] In this way, the pixel defining layer PDL can better support the light-emitting layer and cathode of the first light-emitting device LD1, improve the flatness of the light-emitting layer and cathode of the first light-emitting device LD1, and avoid the light-emitting direction of the light-emitting device 20 from tilting toward the non-light-emitting area FA, thereby improving the display effect of the display substrate 100.

[0226] 14B , the orthographic projection of the connection portion 23 on the substrate SUB partially overlaps with the orthographic projection of the data signal line Data on the substrate SUB. The area of ​​the connection portion 23 is smaller than the area of ​​a single sub-anode 22 .

[0227] In this way, the overlapping area between the data signal line Data and the connecting portion 23 can be reduced, thereby significantly reducing the parasitic capacitance between the data signal line Data and the anode of the first light-emitting device LD1, improving the stability of the operating voltage of the first light-emitting device LD1, and further improving the display effect of the display substrate 100.

[0228] 14B , the orthographic projection of the connection portion 23 on the substrate SUB also partially overlaps with the orthographic projection of the repair signal line Repair on the substrate SUB. The area of ​​the connection portion 23 is smaller than the area of ​​a single sub-anode 22.

[0229] In this way, the overlapping area between the repair signal line Repair and the connecting part 23 can also be reduced, thereby greatly reducing the parasitic capacitance between the repair signal line Repair and the anode of the first light-emitting device LD1, improving the stability of the transmission voltage of the repair signal line Repair, and improving the repair effect on the light-emitting device to be repaired.

[0230] For example, the shape of the connection portion 23 can be H-shaped, rectangular, or polygonal. The shape of the connection portion 23 can also be other shapes to minimize the overlapping area between the connection portion 23 and the data signal line Data, and minimize the overlapping area between the connection portion 23 and the repair signal line Repair.

[0231] 13 and 14B , within the light emitting area EA of at least one light emitting device 20, the surface of the driving circuit layer 10 close to the light emitting device 20 is a flat surface. For example, the surface of the fourth conductive layer EC4 close to the light emitting device 20 is a flat surface.

[0232] For example, within the light-emitting area EA of the first light-emitting device LD1, the surface of the driving circuit layer 10 close to the light-emitting device 20 is a flat surface. For example, within the light-emitting area EA of the second light-emitting device LD2, the surface of the driving circuit layer 10 close to the light-emitting device 20 is a flat surface. For another example, within the light-emitting area EA of the third light-emitting device LD3, the surface of the driving circuit layer 10 close to the light-emitting device 20 is a flat surface.

[0233] In this way, the surface of the driving circuit layer 10 close to the light-emitting device 20 can level the anode of the light-emitting device 20, improve the flatness of the anode of the light-emitting device 20, and prevent the light-emitting direction of the light-emitting device 20 from tilting toward the non-light-emitting area FA, thereby improving the display effect of the display substrate 100.

[0234] In some examples, as shown in Figures 3, 13, and 14B, multiple first power lines VDD are located on a side of the adapter 12 proximate to the multiple light-emitting devices 20. The first power lines VDD are coupled to the pixel circuits. The orthographic projections of the first power lines VDD on the substrate SUB at least partially overlap with the light-emitting areas EA of the light-emitting devices 20. It is understood that the orthographic projections of the first power lines VDD on the substrate SUB partially overlap with the light-emitting areas EA of the light-emitting devices 20; alternatively, the orthographic projections of the first power lines VDD on the substrate SUB cover the light-emitting areas EA of the light-emitting devices 20.

[0235] In the light emitting area EA, the surface of the first power line VDD close to the anode of the light emitting device 20 is a flat surface.

[0236] In this way, the first power line VDD can level the anode of the light emitting device 20 , improve the flatness of the anode of the light emitting device 20 , and prevent the light emitting direction of the light emitting device 20 from tilting toward the non-light emitting area FA, thereby improving the display effect of the display substrate 100 .

[0237] For example, when the light-emitting area EA of the first light-emitting device LD1 is larger than the light-emitting area EA of the second light-emitting device LD2, and the light-emitting area EA of the first light-emitting device LD1 is larger than the light-emitting area EA of the third light-emitting device LD3, the orthographic projection area of ​​the first power line VDD on the substrate SUB overlaps with the light-emitting area EA of the second light-emitting device LD2 and the light-emitting area EA of the third light-emitting device LD3. It can be understood that the orthographic projection area of ​​the first power line VDD on the substrate SUB covers the light-emitting area EA of the second light-emitting device LD2 and the light-emitting area EA of the third light-emitting device LD3.

[0238] In this way, when the area of ​​the light-emitting area EA of the first light-emitting device LD1 in the display substrate 100 (i.e., the anode area of ​​the first light-emitting device LD1) is relatively large, the first power line VDD can at least level the anode of the second light-emitting device LD2 and the anode of the third light-emitting device LD3, thereby improving the flatness of the anode of the second light-emitting device LD2 and the anode of the third light-emitting device LD3, and preventing the light emitting directions of the second light-emitting device LD2 and the third light-emitting device LD3 from tilting toward the non-light-emitting area FA, thereby improving the display effect of the display substrate 100.

[0239] Illustratively, when the light emitting area EA of the first light emitting device LD1 is larger than the light emitting area EA of the second light emitting device LD2, and the light emitting area EA of the first light emitting device LD1 is larger than the light emitting area EA of the third light emitting device LD3, the orthographic projection area of ​​the first power line VDD on the substrate SUB partially overlaps with the light emitting area EA of the first light emitting device LD1.

[0240] In this way, when the anode area of ​​the first light-emitting device LD1 in the display substrate 100 is relatively large, the first power line VDD can partially pad the anode of the first light-emitting device LD1, improve the flatness of the anode of the first light-emitting device LD1, and avoid the light emitting direction of the first light-emitting device LD1 from tilting toward the non-light-emitting area FA, thereby improving the display effect of the display substrate 100.

[0241] In some examples, as shown in FIG. 14B , the light emitting area EA of the first light emitting device LD1 overlaps with the orthographic projection area of ​​the second power line VSS on the base substrate SUB.

[0242] In the light emitting area EA of the first light emitting device LD1 , the surface of the second power line VSS close to the light emitting device 20 is a flat surface.

[0243] In this way, when the anode area of ​​the first light-emitting device LD1 is large, the second power line VSS can level the anode of the first light-emitting device LD1, improve the flatness of the anode of the first light-emitting device LD1, and prevent the light emitting direction of the first light-emitting device LD1 from tilting toward the non-light-emitting area FA, thereby improving the display effect of the display substrate 100.

[0244] In some embodiments, as shown in FIG. 13 , the orthographic projection of the leveling block 160 on the base substrate SUB partially overlaps with the orthographic projection of the anode of the first light emitting device LD1 on the base substrate SUB.

[0245] In this way, the leveling block 160 can level a portion of the anode of the first light-emitting device LD1, thereby improving the flatness of the anode of the first light-emitting device LD1 and preventing the light emitting direction of the first light-emitting device LD1 from tilting toward the non-light-emitting area FA, thereby improving the display effect of the display substrate 100.

[0246] In some examples, as shown in FIG13 , the orthographic projection of the leveling block 160 on the base substrate SUB partially overlaps with the orthographic projection of a portion of the anode of the first light-emitting device LD1 on the base substrate SUB. Within the light-emitting area EA, the surface of the leveling block 160 adjacent to the light-emitting device 20 is flat. For example, the orthographic projection of the leveling block 160 on the base substrate SUB partially overlaps with the orthographic projections of a portion of the second sub-anode 222 and a portion of the fourth sub-anode 224 on the base substrate SUB.

[0247] The orthographic projection of the first power line VDD on the substrate SUB partially overlaps with the orthographic projection of another portion of the anode of the first light-emitting device LD1 on the substrate SUB. Within the light-emitting area EA, the surface of the first power line VDD near the light-emitting device 20 is a flat surface. For example, the orthographic projection of the first power line VDD on the substrate SUB partially overlaps with the orthographic projections of another portion of the second sub-anode 222 and another portion of the fourth sub-anode 224 on the substrate SUB.

[0248] In this way, the leveling block 160 can level a portion of the anode of the first light-emitting device LD1, and the first power line VDD can level another portion of the anode of the first light-emitting device LD1, which can greatly improve the flatness of the anode of the first light-emitting device LD1 and prevent the light emitting direction of the first light-emitting device LD1 from tilting toward the non-luminous area FA, thereby greatly improving the display effect of the display substrate 100.

[0249] In some embodiments, as shown in FIG13 and FIG14B , within the light-emitting area EA of at least one light-emitting device 20, the patterned shape of the driving circuit layer 10 near the surface of the light-emitting device 20 is substantially symmetrical. For example, within the light-emitting area EA of the first light-emitting device LD1, the patterned shape of the driving circuit layer 10 near the surface of the light-emitting device 20 is substantially symmetrical. For example, within the light-emitting area EA of the second light-emitting device LD2, the patterned shape of the driving circuit layer 10 near the surface of the light-emitting device 20 is substantially symmetrical. For another example, within the light-emitting area EA of the third light-emitting device LD3, the patterned shape of the driving circuit layer 10 near the surface of the light-emitting device 20 is substantially symmetrical.

[0250] In this way, the surface of the driving circuit layer 10 close to the light-emitting device 20 can symmetrically level the anode of the light-emitting device 20, improve the flatness of the anode of the light-emitting device 20, and prevent the light-emitting direction of the light-emitting device 20 from tilting toward the non-light-emitting area FA, thereby improving the display effect of the display substrate 100.

[0251] In some examples, as shown in FIG. 13 and FIG. 14B , within the emission area EA, the patterned shapes of the first power lines VDD are substantially symmetrically disposed.

[0252] In this way, the first power line VDD can symmetrically pad the anode of the light-emitting device 20, improve the flatness of the anode of the light-emitting device 20, and prevent the light emitting direction of the light-emitting device 20 from tilting toward the non-light-emitting area FA, thereby improving the display effect of the display substrate 100.

[0253] In some examples, as shown in FIG. 13 and FIG. 14B , within the light emitting area EA of the first light emitting device LD1 , the patterned shapes of the second power line VSS are substantially symmetrically disposed.

[0254] In this way, when the anode area of ​​the first light-emitting device LD1 is large, the second power line VSS can symmetrically pad the anode of the first light-emitting device LD1, improve the flatness of the anode of the first light-emitting device LD1, and prevent the light emitting direction of the first light-emitting device LD1 from tilting toward the non-luminous area FA, thereby improving the display effect of the display substrate 100.

[0255] In some examples, as shown in FIG. 13 , within the emission area EA, the patterned shapes of the leveling blocks 160 are substantially symmetrically arranged.

[0256] For example, within the light emitting area EA of the first light emitting device LD1 , the patterned shapes of the leveling blocks 160 are substantially symmetrically arranged.

[0257] In this way, the leveling block 160 can symmetrically level the anode of the first light-emitting device LD1, improve the flatness of the anode of the first light-emitting device LD1, and prevent the light emitting direction of the first light-emitting device LD1 from tilting toward the non-light-emitting area FA, thereby improving the display effect of the display substrate 100.

[0258] 14B , the first power connection lines 15 extend along a first direction X, and the first power lines VDD extend along a second direction Y. A plurality of first power connection lines 15 are respectively connected to a plurality of first power lines VDD to form a mesh structure for transmitting the first power signal.

[0259] The first power line VDD and the first power connection line 15 form a mesh structure on the display substrate 100 for transmitting the first power signal, which can not only effectively reduce the resistance of the first power line VDD and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate 100 and effectively improve the uniformity of the display effect.

[0260] The second power connection lines 16 extend along the first direction X, and the second power lines VSS extend along the second direction Y. The plurality of second power connection lines 16 and the plurality of second power lines VSS are connected to form a mesh structure for transmitting the second power signal.

[0261] The second power line VSS and the second power connection line 16 form a mesh structure on the display substrate 100 for transmitting the second power signal. This structure can not only effectively reduce the resistance of the second power line VSS and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate 100, thereby effectively improving the uniformity of the display effect.

[0262] In some embodiments, as shown in FIG. 9 and FIG. 14B , an orthographic projection of the first power line VDD on the base substrate SUB at least partially overlaps with an orthographic projection of the first connection block 149 on the base substrate SUB.

[0263] Since the first connection block 149 includes the fifth node N5, the constant voltage first power line VDD can effectively shield the influence of other signals in the pixel circuit on the fifth node N5, avoiding other signals affecting the potential of the fifth node N5 of the pixel circuit, and improving the display effect of the display substrate 100.

[0264] In some embodiments, as shown in FIG. 9 and FIG. 14B , the orthographic projection of the first power line VDD on the base substrate SUB at least partially overlaps with the orthographic projection of the third connection block 112 on the base substrate SUB.

[0265] Since the third connection block 112 includes the first node N1, the constant voltage first power line VDD can effectively shield the influence of other signals in the pixel circuit on the first node N1, thereby preventing other signals from affecting the potential of the first node N1 of the pixel circuit and improving the display effect of the display substrate 100.

[0266] It should be noted that the first power line VDD can be designed with unequal widths. The unequal width design of the first power line VDD can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the first power line VDD and the repair signal line Repair.

[0267] In some examples, as shown in FIG14B , along the first direction X, the size of the first power line VDD at the portion overlapping the first power connection line 15 is larger than the size of the first power line VDD at the portion overlapping the repair signal line Repair. Furthermore, the orthographic projection of the first power line VDD on the base substrate SUB does not overlap with the orthographic projection of the second transition portion 122 on the base substrate SUB.

[0268] In this way, on the basis of improving the uniformity of the first power signal in the display substrate 100, the first power line VDD can also be set to avoid the second adapter part 122, thereby ensuring the repair effect of the repair unit on the light-emitting device 20 to be repaired and improving the production yield of the display substrate 100.

[0269] In some embodiments, as shown in FIG14B , the first reference signal connection line 17 of the main body extending approximately along the first direction X is connected to the first reference signal line Ref1 of the main body extending approximately along the second direction Y, so that the first reference signal line Ref1 and the first reference signal connection line 17 form a mesh structure on the display substrate 100 for transmitting the first reference signal.

[0270] In this way, not only can the resistance of the first reference signal line Ref1 be effectively reduced, thereby reducing the voltage drop of the first reference signal, but also the uniformity of the first reference signal in the display substrate 100 can be effectively improved, thereby improving the uniformity of the display effect.

[0271] In some embodiments, as shown in FIG. 14B , on a plane parallel to the substrate SUB, the first transistor T1 , the fourth transistor T4 , the fifth transistor T5 , the seventh transistor T7 , and the ninth transistor T9 may be located between the data signal line Data and the first reference signal line.

[0272] In some embodiments, as shown in FIG. 14B , on a plane parallel to the substrate SUB, the second transistor T2 , the sixth transistor T6 , and the eighth transistor T8 may be located on a side of the data signal line Data away from the second power line VSS.

[0273] To sum up, in the display substrate 100 provided by the embodiment of the present disclosure, the data signal line Data can be set away from the sub-anode 22, and the overlapping area between the data signal line Data and the anode of the light-emitting device 20 can be reduced as much as possible, thereby reducing the parasitic capacitance between the data signal line Data and the anode of the light-emitting device 20, improving the stability of the operating voltage of the light-emitting device 20, and further improving the display effect of the display substrate 100.

[0274] 15 to 17 are flow charts of methods for preparing a display substrate according to some embodiments.

[0275] Some embodiments of the present disclosure provide a method for preparing a display substrate. This method can produce a display substrate 100 according to any of the above embodiments. As shown in FIG15 , this method can include steps S100 to S300.

[0276] Step S100: providing a base substrate SUB, wherein the base substrate SUB includes a light emitting area EA and a non-light emitting area FA except the light emitting area EA.

[0277] For example, the material of the substrate SUB may include polyethylene terephthalate (PET), polyimide (PI), or cycloolefin polymer (COP).

[0278] The specific introductions of the first sub-pixel region P1 , the second sub-pixel region P2 and the third sub-pixel region P3 have been described in detail before and will not be repeated here.

[0279] Step S200: forming a driving circuit layer 10 on the base substrate SUB. The driving circuit layer 10 includes a plurality of data signal lines Data, and the plurality of data signal lines Data are located in the non-luminous area FA.

[0280] In some examples, as shown in FIG. 16 , step S200 may include step S210 and step S220 .

[0281] Step S210: forming a plurality of repair signal lines Repair on the base substrate SUB. The plurality of repair signal lines Repair are located in the non-luminous area FA.

[0282] For example, step S210 may include forming a metal material layer on the substrate SUB using a deposition process. Then, using a mask and an etching process, the metal material layer located in the light-emitting area EA is removed, while the metal material layer located in the non-light-emitting area FA is retained to form a plurality of repair signal lines Repair.

[0283] For example, step S210 may include: sequentially forming a semiconductor layer POLY, a first conductive layer EC1, and a second conductive layer EC2 on the substrate SUB.

[0284] The specific process of forming the first conductive layer EC1 and the second conductive layer EC2 can refer to the process of forming multiple repair signal lines Repair, which will not be repeated here. The second conductive layer EC2 can include multiple repair signal lines Repair located in the non-luminous area FA.

[0285] In this way, the repair signal line Repair can be coupled to the light-emitting device 20 to be repaired, so that the repair signal line Repair can provide a stable voltage for the light-emitting device 20 to be repaired, thereby realizing the repair of the light-emitting device 20 to be repaired, and improving the manufacturing yield of the display substrate 100.

[0286] The specific structure of the semiconductor layer POLY, the specific structure of the first conductive layer EC1 and the specific structure of the second conductive layer EC2 have been described in detail above and will not be repeated here.

[0287] Exemplarily, step S210 may further include forming an insulating layer covering the semiconductor layer POLY. Vias are provided in the insulating layer. The insulating layer may be made of a material selected from the group consisting of oxide, nitride, and oxynitride, and the like, without limitation.

[0288] For example, a deposition process is used to form an insulating material layer covering the semiconductor layer POLY on the substrate SUB. An etching process is then used to remove a portion of the insulating material layer to form a via hole, with the remaining insulating material layer serving as the first insulating layer. The orthographic projection of the via hole's outline on the substrate SUB may overlap with the orthographic projection of the transistor's active layer on the substrate.

[0289] Illustratively, after forming the first conductive layer EC1, a second insulating layer may be formed. The second insulating layer is located between the first conductive layer EC1 and the second conductive layer EC2. The material of the second insulating layer may be similar to that of the first insulating layer. The method for preparing the second insulating layer may refer to the method for preparing the first insulating layer, and is not further described here.

[0290] In some examples, as shown in FIG8 , the repair signal line Repair may include a repair block 123. In a direction perpendicular to the extension of the repair signal line Repair (i.e., a second direction Y), the size of the repair block 123 (the width of the repair block 123) is greater than the size of the repair signal line Repair. The repair block 123 and the repair signal line Repair may be an integrated structure connected to each other.

[0291] In this way, the area of ​​the repair signal line Repair can be made larger, so that the repair signal line Repair can provide a relatively stable voltage for the light-emitting device 20 to be repaired, which can improve the repair effect of the light-emitting device 20 to be repaired, and thus improve the production yield of the display substrate 100.

[0292] Exemplarily, the shape of the repair signal line Repair may be a straight line with a main portion extending along the first direction X.

[0293] In some examples, as shown in FIG16 , step S210 may be followed by step S211 .

[0294] Step S211 : forming a plurality of adapters 12 on a side of the plurality of repair signal lines Repair away from the substrate SUB.

[0295] For example, step S210 may include forming a metal layer on a side of the second conductive layer EC2 away from the substrate SUB using a deposition process. Then, a portion of the metal layer is removed using a mask and an etching process, with the remaining metal layer forming a third conductive layer EC3. The third conductive layer EC3 may include a plurality of adapters 12.

[0296] It should be noted that the specific structure of the third conductive layer EC3 has been described in detail above and will not be repeated here.

[0297] As shown in FIG14B , the orthographic projection of the adapter 12 on the base substrate SUB at least partially overlaps with the orthographic projection of the repair signal line Repair on the base substrate SUB. It is understood that the orthographic projection of the adapter 12 on the base substrate SUB can partially overlap with the orthographic projection of the repair signal line Repair on the base substrate SUB; alternatively, the orthographic projection of the adapter 12 on the base substrate SUB can overlap with the orthographic projection of the repair signal line Repair on the base substrate SUB.

[0298] In this way, the repair signal line Repair and the adapter 12 at least partially overlapping locations can form a repair unit, which can avoid the anode of the light-emitting device 20. The adapter 12 coupled to the light-emitting device 20 to be repaired can be connected to the repair signal line Repair, so that the repair unit can provide a stable voltage to the light-emitting device 20 to be repaired, thereby allowing the light-emitting device 20 to be repaired to operate normally, thereby improving the manufacturing yield of the display substrate 100.

[0299] The patterned shapes of the multiple adapters 12 are substantially the same. The repair unit can provide a stable voltage to each of the light-emitting devices 20 of different colors to be repaired, so that the repair unit has the same repair effect on the light-emitting devices 20 of different colors to be repaired, thereby improving the uniformity of the luminous efficiency among the light-emitting devices 20 of different colors in the display substrate 100.

[0300] 9 , the adapter 12 includes a first adapter portion 121 and a second adapter portion 122. The first adapter portion 121 is coupled to the anode of the light emitting device 20, and the second adapter portion 122 is coupled to the repair signal line Repair.

[0301] Along an extending direction perpendicular to the repair signal line Repair, a dimension d3 of the second transition portion 122 is greater than a dimension d4 of the first transition portion 121 .

[0302] In this way, the second adapter part 122 and the repair signal line Repair can form a repair unit. The size d3 of the second adapter part 122 is larger than the size d4 of the first adapter part 121, so that the area of ​​the repair unit can be larger, so that the repair unit can provide a relatively stable voltage for the light-emitting device 20 to be repaired, which can improve the repair effect of the repair unit on the light-emitting device 20 to be repaired, and thereby improve the production yield of the display substrate 100.

[0303] For example, the shape of the adapter 12 may include a convex shape, a polygonal shape, or other shapes.

[0304] Illustratively, after forming the second conductive layer EC2, a third insulating layer may be formed. The third insulating layer may be located between the second conductive layer EC2 and the third conductive layer EC3. The material of the third insulating layer may be similar to that of the first insulating layer. The preparation method of the third insulating layer may refer to the preparation method of the first insulating layer, and is not further described here.

[0305] Step S220: Forming a plurality of data signal lines Data on a side of the substrate SUB away from the plurality of repair signal lines Repair. The data signal lines Data extend in a direction that intersects with the direction of the repair signal lines Repair. For example, the data signal lines Data and the repair signal lines Repair may extend in a direction perpendicular to each other.

[0306] In some examples, step S220 may include forming a metal layer using a deposition process on a side of the third conductive layer EC3 away from the substrate SUB (i.e., on a surface of the fourth insulating layer away from the substrate SUB). A portion of the metal layer is then removed using a mask and an etching process, with the remaining metal layer forming the fourth conductive layer EC4. Thus, a pixel circuit consisting of multiple transistors and capacitors (e.g., 9T2C) can be formed on the substrate SUB.

[0307] It should be noted that the specific structure of the fourth conductive layer EC4 has been described in detail above and will not be repeated here.

[0308] 13 and 14B , the fourth conductive layer EC4 may include a plurality of data signal lines Data located in the non-emission area FA. Forming the plurality of data signal lines Data may include removing the metal material layer located in the emission area EA through a mask and an etching process, and retaining the metal material layer located in the non-emission area FA to form the plurality of data signal lines Data.

[0309] For example, the shape of the data signal line Data may be a straight line with a main portion extending along the second direction Y.

[0310] In this way, the overlapping area between the data signal line Data and the anode of the light-emitting device 20 can be reduced as much as possible, thereby reducing the parasitic capacitance between the data signal line Data and the anode of the light-emitting device 20, improving the stability of the operating voltage of the light-emitting device 20, and further improving the display effect of the display substrate 100.

[0311] Illustratively, after forming the third conductive layer EC3, a fourth insulating layer may be formed. The fourth insulating layer is located between the third conductive layer EC3 and the fourth conductive layer EC4. The material of the fourth insulating layer may be similar to that of the first insulating layer. The preparation method of the fourth insulating layer may refer to the preparation method of the first insulating layer, and is not further described here.

[0312] In some examples, step S220 may further include forming a plurality of first power lines VDD on a side of the plurality of repair signal lines Repair away from the base substrate SUB. After forming the plurality of first power lines VDD, planarizing the surface of the plurality of first power lines VDD away from the base substrate SUB in the emission area EA.

[0313] In this way, the first power line VDD can level the anode of the light emitting device 20 , improve the flatness of the anode of the light emitting device 20 , and prevent the light emitting direction of the light emitting device 20 from tilting toward the non-light emitting area FA, thereby improving the display effect of the display substrate 100 .

[0314] Exemplarily, within the light emitting area EA, the patterned shapes of the first power lines VDD are substantially symmetrically arranged.

[0315] In this way, the first power line VDD can symmetrically pad the anode of the light-emitting device 20, further improve the flatness of the anode of the light-emitting device 20, and prevent the light emitting direction of the light-emitting device 20 from tilting toward the non-light-emitting area FA, thereby further improving the display effect of the display substrate 100.

[0316] In some examples, step S220 may further include forming a plurality of second power lines VSS on a side of the plurality of repair signal lines Repair away from the substrate SUB. After forming the plurality of second power lines VSS, planarizing the surface of the second power lines VSS away from the substrate SUB within the light-emitting area EA of the first light-emitting device LD1.

[0317] In this way, the second power line VSS can level the anode of the first light emitting device LD1, improve the flatness of the anode of the first light emitting device LD1, and prevent the light emitting direction of the first light emitting device LD1 from tilting toward the non-light emitting area FA, thereby improving the display effect of the display substrate 100.

[0318] Exemplarily, within the light emitting area EA of the first light emitting device LD1 , the patterned shapes of the second power lines VSS are substantially symmetrically arranged.

[0319] In this way, the second power line VSS can symmetrically pad the anode of the first light-emitting device LD1, further improve the flatness of the anode of the first light-emitting device LD1, and prevent the light emitting direction of the first light-emitting device LD1 from tilting toward the non-light-emitting area FA, thereby further improving the display effect of the display substrate 100.

[0320] The specific structures of the first power line VDD and the second power line VSS have been described in detail above and will not be repeated here.

[0321] Step S300 : forming a plurality of light emitting devices 20 on a side of the driving circuit layer 10 away from the base substrate SUB.

[0322] The specific structure of the plurality of light emitting devices 20 has been described in detail above and will not be repeated here.

[0323] As shown in FIG11 , the anode of the first light-emitting device LD1 may include multiple sub-anodes 22 and a connecting portion 23. Gaps exist between adjacent sub-anodes 22, and the multiple sub-anodes 22 are respectively connected to the connecting portion 23. For example, the multiple sub-anodes 22 and the connecting portion 23 in the first light-emitting device LD1 may be an interconnected, integrated structure.

[0324] There are gaps between adjacent sub-anodes 22. It can be understood that there are gaps between adjacent sub-anodes 22 in the first light emitting device LD1 along the first direction X. There are also gaps between adjacent sub-anodes 22 in the first light emitting device LD1 along the second direction Y.

[0325] In some examples, among the plurality of light-emitting devices 20, the light-emitting area EA of the first light-emitting device LD1 is larger than the light-emitting area EA of the second light-emitting device LD2, and the light-emitting area EA of the first light-emitting device LD1 is larger than the light-emitting area EA of the third light-emitting device LD3. It can be understood that the anode area of ​​the first light-emitting device LD1 is larger than the anode area of ​​the second light-emitting device LD2, and the anode area of ​​the first light-emitting device LD1 is larger than the anode area of ​​the third light-emitting device LD3.

[0326] In some embodiments, as shown in FIG. 14B , the orthographic projection of the data signal line Data on the base substrate SUB does not overlap with the orthographic projection of the sub-anode 22 on the base substrate SUB.

[0327] In this way, the data signal line Data can avoid the sub-anode 22, and the overlapping area between the data signal line Data and the anode of the light-emitting device 20 can be reduced as much as possible, thereby reducing the parasitic capacitance between the data signal line Data and the anode of the light-emitting device 20, improving the stability of the operating voltage of the light-emitting device 20, and further improving the display effect of the display substrate 100.

[0328] In some examples, as shown in FIG14B , a portion of the sub-anodes 22 in the first light-emitting device LD1 is located on one side of the data signal line Data coupled to the first light-emitting device LD1. Another portion of the sub-anodes 22 in the first light-emitting device LD1 is located on the other side of the data signal line Data coupled to the first light-emitting device LD1. It is understood that the data signal line Data coupled to the first light-emitting device LD1 is located in the gap between adjacent sub-anodes 22 in the first light-emitting device LD1.

[0329] In this way, when the anode area of ​​the first light-emitting device LD1 in the display substrate 100 is large, the data signal line Data can be set away from the sub-anode 22 of the first light-emitting device LD1, and the overlapping area between the data signal line Data and the anode of the first light-emitting device LD1 can be reduced as much as possible, thereby reducing the parasitic capacitance between the data signal line Data and the anode of the first light-emitting device LD1, improving the stability of the operating voltage of the first light-emitting device LD1, and thereby improving the display effect of the display substrate 100.

[0330] In some embodiments, as shown in FIG. 16 , step S300 may include step S310 .

[0331] Step S310: forming a plurality of light emitting devices 20 on a side of the plurality of data signal lines Data away from the substrate SUB.

[0332] As shown in Figure 14B , a portion of the sub-anodes 22 in the first light-emitting device LD1 is located on one side of the repair signal line Repair. Another portion of the sub-anodes 22 in the first light-emitting device LD1 is located on the other side of the repair signal line Repair. It will be appreciated that, along the second direction Y, the repair signal line Repair can be located in the non-luminescent area FA between adjacent portions of the sub-anodes 22 and the other portion of the sub-anodes 22 in the first light-emitting device LD1.

[0333] The repair signal line Repair is set in the non-luminous area FA between the multiple sub-anodes 22 of the first light-emitting device LD1, which can avoid the overlap of the multiple sub-anodes 22 in the first light-emitting device LD1 with the repair signal line Repair, and minimize the overlap between the anode of the first light-emitting device LD1 and the repair signal line Repair, so that when the repair signal line Repair is coupled to the light-emitting device 20 to be repaired, the repair signal line Repair can provide a stable voltage for the light-emitting device 20 to be repaired, thereby realizing the repair of the light-emitting device 20 to be repaired, and can improve the production yield of the display substrate 100.

[0334] In some examples, as shown in Figures 11, 13, and 14B, the anode of the first light-emitting device LD1 may include four sub-anodes 22 and a connecting portion 23. A connecting portion 23 may be located between two adjacent sub-anodes 22. The four sub-anodes 22 may include a first sub-anode 221, a second sub-anode 222, a third sub-anode 223, and a fourth sub-anode 224. Along the first direction X, the first sub-anode 221 and the second sub-anode 222 may be located in the same row, while the third sub-anode 223 and the fourth sub-anode 224 may be located in another row.

[0335] The data signal line Data coupled to the first light emitting device LD1 is located in the gap between the adjacent first and second sub-anodes 221 and 222 and between the adjacent third and fourth sub-anodes 223 and 224 in the first light emitting device LD1 .

[0336] In this way, when the anode area of ​​the first light-emitting device LD1 in the display substrate 100 is large, the data signal line Data can be set in the gap between the four adjacent sub-anodes 22, so that the overlapping area between the data signal line Data and the anode of the first light-emitting device LD1 can be reduced to the overlapping area between the data signal line Data and the connecting portion 23, thereby greatly reducing the parasitic capacitance between the data signal line Data and the anode of the first light-emitting device LD1, improving the stability of the operating voltage of the first light-emitting device LD1, and thereby improving the display effect of the display substrate 100.

[0337] The repair signal line Repair may also be located between the adjacent first sub-anode 221 and the third sub-anode 223 in the first light-emitting device LD1, and between the adjacent second sub-anode 222 and the fourth sub-anode 224. It is understandable that the repair signal line Repair may be located between the adjacent first sub-anode 221, the second sub-anode 222, and the third sub-anode 223, the fourth sub-anode 224 in the first light-emitting device LD1.

[0338] On the basis of improving the display effect of the display substrate 100, it is also possible to avoid the overlap of the four sub-anodes 22 in the first light-emitting device LD1 with the repair signal line Repair, and minimize the overlap of the anode of the first light-emitting device LD1 and the repair signal line Repair, so that when the repair signal line Repair is coupled to the light-emitting device 20 to be repaired, the repair signal line Repair can provide a stable voltage for the light-emitting device 20 to be repaired, thereby realizing the repair of the light-emitting device 20 to be repaired, and can improve the manufacturing yield of the display substrate 100.

[0339] In some examples, as shown in Figures 13 and 14B, in the first light-emitting device LD1, the area of ​​a single sub-anode 22 in a portion of the sub-anodes 22 may be different from the area of ​​a single sub-anode 22 in another portion of the sub-anodes 22 along a direction parallel to the substrate SUB.

[0340] For example, the area of ​​a single sub-anode 22 in one portion of the sub-anodes 22 may be larger than the area of ​​a single sub-anode 22 in another portion of the sub-anodes 22 .

[0341] The area of ​​a single sub-anode 22 in the first light-emitting device LD1 can be flexibly designed according to actual needs, so that the sub-anode 22 can avoid the data signal line Data or the repair signal line Repair setting, and minimize the overlapping area between the data signal line Data and the anode of the first light-emitting device LD1 or the overlapping area between the repair signal line Repair and the anode of the first light-emitting device LD1.

[0342] In other examples, along a direction parallel to the substrate SUB, the area of ​​a single sub-anode 22 in one portion of the sub-anodes 22 may be the same as the area of ​​a single sub-anode 22 in another portion of the sub-anodes 22 .

[0343] 14B , the area of ​​the first sub-anode 221 may be greater than that of the second sub-anode 222 along the first direction X. The area of ​​the first sub-anode 221 may be the same as that of the third sub-anode 223 along the second direction Y.

[0344] For example, the shape of the sub-anode 22 may be a rectangle, a trapezoid, or a polygon. The shape of the sub-anode 22 may also be other shapes that facilitate the exposure of key signal lines.

[0345] 14B , the orthographic projection of the connection portion 23 on the base substrate SUB partially overlaps with the orthographic projection of the data signal line Data on the base substrate SUB. The area of ​​the connection portion 23 is smaller than the area of ​​a single sub-anode 22 .

[0346] In this way, the overlapping area between the data signal line Data and the connecting portion 23 can be reduced, thereby significantly reducing the parasitic capacitance between the data signal line Data and the anode of the first light-emitting device LD1, improving the stability of the operating voltage of the first light-emitting device LD1, and further improving the display effect of the display substrate 100.

[0347] 14B , the orthographic projection of the connection portion 23 on the substrate SUB also partially overlaps with the orthographic projection of the repair signal line Repair on the substrate SUB. The area of ​​the connection portion 23 is smaller than the area of ​​a single sub-anode 22.

[0348] In this way, the overlapping area between the repair signal line Repair and the connecting part 23 can also be reduced, thereby greatly reducing the parasitic capacitance between the repair signal line Repair and the anode of the first light-emitting device LD1, improving the stability of the transmission voltage of the repair signal line Repair, and improving the repair effect on the light-emitting device to be repaired.

[0349] For example, the shape of the connection portion 23 can be H-shaped, rectangular, or polygonal. The shape of the connection portion 23 can also be other shapes to minimize the overlapping area between the connection portion 23 and the data signal line Data, and minimize the overlapping area between the connection portion 23 and the repair signal line Repair.

[0350] In some examples, as shown in FIG. 17 , forming a light-emitting device in step S300 may further include steps S311 to S313 .

[0351] Step S311 : forming an anode AE ​​on a side of the driving circuit layer 10 away from the base substrate SUB. The anode AE ​​includes at least one sub-anode 22 and a connecting portion 23 .

[0352] For example, before step S311, the process may include forming an insulating layer INL on a side of the driving circuit layer 10 away from the base substrate SUB. Subsequently, forming an anode AE ​​on a side of the insulating layer INL away from the base substrate SUB. Subsequently, forming a pixel definition layer PDL on a side of the insulating layer INL away from the base substrate SUB. The pixel definition layer PDL includes a plurality of light-emitting openings.

[0353] In some embodiments, as shown in Figures 3, 12, and 14B, the light-emitting opening K1 of the first light-emitting device LD1 may include multiple sub-light-emitting openings K11. The orthographic projections of the multiple sub-anodes 22 in the first light-emitting device LD1 on the substrate SUB respectively overlap the orthographic projections of the outlines of the multiple sub-light-emitting openings K11 on the substrate SUB. For example, the light-emitting opening K1 of the first light-emitting device LD1 may include four sub-light-emitting openings K11. The orthographic projections of the four sub-anodes 22 in the first light-emitting device LD1 on the substrate SUB respectively overlap the orthographic projections of the outlines of the four sub-light-emitting openings K11 on the substrate SUB.

[0354] The orthographic projection of the pixel defining layer PDL on the base substrate SUB may cover the orthographic projection of the connecting portion 23 of the first light emitting device LD1 on the base substrate SUB. It is understandable that the orthographic projection of the pixel defining layer PDL on the base substrate SUB may overlap with the orthographic projection of the connecting portion 23 of the first light emitting device LD1 on the base substrate SUB.

[0355] In this way, the pixel defining layer PDL can better support the light-emitting layer and cathode of the first light-emitting device LD1, improve the flatness of the light-emitting layer and cathode of the first light-emitting device LD1, and avoid the light-emitting direction of the light-emitting device 20 from tilting toward the non-light-emitting area FA, thereby improving the display effect of the display substrate 100.

[0356] Step S312 : forming a light-emitting layer EL on the side of the anode AE ​​away from the substrate SUB. The light-emitting layer EL covers the sub-anode 22 .

[0357] Step S313: A cathode CE is formed on the side of the light emitting layer EL away from the substrate SUB. The cathode CE covers the light emitting layer EL. The at least one sub-anode 22 and the connecting portion 23, the light emitting layer EL, and the cathode CE together form a light emitting device 20.

[0358] Exemplarily, the light emitting device 20 may be an OLED, or the light emitting device 20 may be a QLED or the like.

[0359] To sum up, through the manufacturing method of the display substrate provided by the embodiment of the present disclosure, in the display substrate 100 manufactured, the data signal line Data can avoid the sub-anode 22 setting, and the overlapping area between the data signal line Data and the anode of the light-emitting device 20 can be reduced as much as possible, thereby reducing the parasitic capacitance between the data signal line Data and the anode AE ​​of the light-emitting device 20, improving the stability of the operating voltage of the light-emitting device 20, and further improving the display effect of the display substrate 100.

[0360] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A substrate, comprising a light-emitting area and a non-light-emitting area except the light-emitting area; A driving circuit layer, located on one side of the base substrate, comprising a plurality of data signal lines; the plurality of data signal lines are located in the non-luminous area; A plurality of light emitting devices are located on a side of the driving circuit layer away from the base substrate; Among them, the multiple light-emitting devices include a first light-emitting device; the anode of the first light-emitting device includes multiple sub-anodes and a connecting part; there are gaps between adjacent sub-anodes, and the multiple sub-anodes are respectively connected to the connecting parts; the orthographic projection of the data signal line on the base substrate does not overlap with the orthographic projection of the sub-anodes on the base substrate.

2. The display substrate according to claim 1, wherein: The plurality of light emitting devices further include a second light emitting device and a third light emitting device; the light emitting area of ​​the first light emitting device is larger than the light emitting area of ​​the second light emitting device, and the light emitting area of ​​the first light emitting device is larger than the light emitting area of ​​the third light emitting device; A portion of the sub-anodes in the first light-emitting device are located on one side of the data signal line coupled to the first light-emitting device; another portion of the sub-anodes in the first light-emitting device are located on the other side of the data signal line coupled to the first light-emitting device.

3. The display substrate according to claim 1 or 2, wherein: The orthographic projection of the connecting portion on the base substrate partially overlaps with the orthographic projection of the data signal line on the base substrate; The area of ​​the connecting portion is smaller than the area of ​​a single sub-anode.

4. The display substrate according to claim 2 or 3, wherein: Along a direction parallel to the substrate, in the first light-emitting device, an area of ​​a single sub-anode in a portion of the sub-anodes is greater than an area of ​​a single sub-anode in another portion of the sub-anodes.

5. The display substrate according to any one of claims 1 to 4, wherein: The driving circuit layer also includes a plurality of repair signal lines; the plurality of repair signal lines are located between the base substrate and the plurality of data signal lines, and the plurality of repair signal lines are located in the non-luminous area; an extension direction of the repair signal lines intersects with an extension direction of the data signal lines.

6. The display substrate according to claim 5, wherein: A portion of the sub-anodes in the first light-emitting device are located on one side of the repair signal line; another portion of the sub-anodes in the first light-emitting device are located on the other side of the repair signal line.

7. The display substrate according to claim 6, wherein: The anode of the first light emitting device includes four sub-anodes and a connecting portion, wherein the connecting portion is located between the four sub-anodes adjacent to each other; the four sub-anodes include a first sub-anode, a second sub-anode, a third sub-anode and a fourth sub-anode; The data signal line coupled to the first light emitting device is located between the first sub-anode and the second sub-anode adjacent to each other in the first light emitting device, and between the third sub-anode and the fourth sub-anode adjacent to each other. in the gap; The repair signal line is located in a gap between the first sub-anode and the third sub-anode that are adjacent to each other in the first light-emitting device, and in a gap between the second sub-anode and the fourth sub-anode that are adjacent to each other.

8. The display substrate according to any one of claims 5 to 7, wherein: The driving circuit layer further includes a plurality of pixel circuits and a plurality of adapters; the pixel circuits are coupled to the data signal lines and the adapters respectively; the pixel circuits are coupled to the light emitting devices via the adapters; The orthographic projection of the adapter on the base substrate at least partially overlaps with the orthographic projection of the repair signal line on the base substrate.

9. The display substrate according to claim 8, wherein: The adapter includes a first adapter portion and a second adapter portion; the first adapter portion is coupled to the anode of the light emitting device, and the second adapter portion is coupled to the repair signal line; Along an extending direction perpendicular to the repair signal line, a size of the second transition portion is larger than a size of the first transition portion.

10. The display substrate according to claim 8 or 9, wherein: The patterned shapes of the plurality of adapters respectively coupled to the plurality of light emitting devices are substantially the same.

11. The display substrate according to any one of claims 8 to 10, wherein: The driving circuit layer further comprises a plurality of first power lines; the plurality of first power lines are located on a side of the adapter close to the plurality of light-emitting devices; the first power lines are coupled to the pixel circuit; and an orthographic projection area of ​​the first power lines on the substrate at least partially overlaps with a light-emitting area of ​​the light-emitting device; In the light-emitting area, a surface of the first power line close to the light-emitting device is a flat surface; and / or, in the light-emitting area, a patterned shape of the first power line is substantially symmetrically arranged.

12. The display substrate according to claim 11, wherein: The orthographic projection area of ​​the first power line on the base substrate overlaps with the light emitting area of ​​the second light emitting device and the light emitting area of ​​the third light emitting device.

13. The display substrate according to claim 11 or 12, wherein: The driving circuit layer further includes a plurality of second power lines, a plurality of first power connection lines and a plurality of second power connection lines; the plurality of second power lines are respectively coupled to the plurality of light emitting devices; The first power connection line extends along a first direction, and the first power line extends along a second direction; the plurality of first power connection lines are respectively connected to the plurality of first power lines to form a mesh structure for transmitting a first power signal; The first direction and the second direction intersect each other; The second power connection line extends along the first direction, and the second power line extends along the second direction; the plurality of second power connection lines and the plurality of second power lines are connected to form a mesh structure for transmitting a second power signal.

14. The display substrate according to any one of claims 1 to 13, wherein: In a light emitting area of ​​at least one light emitting device, a surface of the driving circuit layer close to the light emitting device is a flat surface.

15. The display substrate according to any one of claims 1 to 14, wherein: In a light emitting region of at least one light emitting device, the patterned shape of the surface of the driving circuit layer close to the light emitting device is substantially symmetrically arranged.

16. The display substrate according to any one of claims 11 to 15, wherein: The driving circuit layer further includes a leveling block; the leveling block is located between the data signal line coupled to the first light emitting device and the first power line, and an extending direction of the leveling block is substantially parallel to an extending direction of the data signal line; The orthographic projection of the leveling block on the base substrate overlaps with the orthographic projection of a portion of the anode of the first light-emitting device on the base substrate; The orthographic projection of the first power line on the base substrate overlaps with the orthographic projection of another part of the anode of the first light-emitting device on the base substrate; In the light-emitting area, a surface of the leveling block close to the light-emitting device is a flat surface; and / or, in the light-emitting area, the patterned shapes of the leveling blocks are substantially symmetrically arranged.

17. The display substrate according to any one of claims 1 to 16, further comprising: The pixel defining layer is located on a side of the driving circuit layer away from the base substrate, and includes a plurality of light-emitting openings; the plurality of light-emitting devices respectively cover the plurality of light-emitting openings; The light-emitting opening of the first light-emitting device includes a plurality of sub-light-emitting openings; The orthographic projections of the plurality of sub-anodes in the first light-emitting device on the base substrate respectively cover the orthographic projections of the outlines of the plurality of sub-light-emitting openings on the base substrate; The orthographic projection of the pixel defining layer on the base substrate covers the orthographic projection of the connecting portion of the first light-emitting device on the base substrate.

18. The display substrate according to any one of claims 1 to 17, wherein: The driving circuit layer also includes a plurality of enable signal lines; the plurality of enable signal lines are respectively coupled to the plurality of light-emitting devices; the orthographic projection of an enable signal line coupled to the light-emitting device on the base substrate does not overlap with the orthographic projection of the sub-anode on the base substrate.

19. A method for preparing a display substrate, comprising: providing a substrate base plate; The base substrate comprises a light emitting area and a non-light emitting area except the light emitting area; forming a driving circuit layer on the base substrate; The driving circuit layer includes a plurality of data signal lines; the plurality of data signal lines are located in the non-luminescent area; A plurality of light-emitting devices are formed on a side of the driving circuit layer away from the base substrate; wherein the plurality of light-emitting devices include a first light-emitting device; an anode of the first light-emitting device includes a plurality of sub-anodes and a connecting portion; there are gaps between adjacent sub-anodes, and the plurality of sub-anodes are respectively connected to the connecting portions; an orthographic projection of the data signal line on the base substrate does not overlap with an orthographic projection of the sub-anodes on the base substrate.

20. A display device, comprising: Circuit boards; The display substrate according to any one of claims 1 to 18; The display substrate is located at one side of the circuit board, and the display substrate is coupled to the circuit board.

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