Micro-led chip and manufacturing method therefor

Abstract

The present disclosure provides a micro-LED chip and a manufacturing method therefor. The method for manufacturing a micro-LED chip comprises: forming a buffer layer on the surface of a substrate; and forming a blue light pixel column, a green light pixel column and a red light pixel column on one side of the buffer layer. A method for forming pixel columns comprises: epitaxially growing a plurality of first n-type doped GaN layers arranged at intervals on one side of the buffer layer; growing a first barrier layer on the surfaces of the first n-type doped GaN layers; growing a quantum well structure layer on the surface of the first barrier layer; successively growing a blue light quantum well light-emitting layer, a green light quantum well light-emitting layer and a red light quantum well light-emitting layer on the surface of the quantum well structure layer; etching a position used for forming a blue light pixel column to remove the red light quantum well light-emitting layer and the green light quantum well light-emitting layer therein; and etching a position used for forming a green light pixel column to remove the red light quantum well light-emitting layer therein.

Description

Micro LED chip and preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 202310777777.8, filed on June 28, 2023, entitled “Micro LED Chip and Preparation Method Thereof,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to the field of chip technology, and more specifically, to a Micro LED chip and a method for preparing the same. Background Art

[0004] Compared with LCD and OLED, micro-LED uses a self-luminous mechanism, has great advantages in inherent brightness and device stability, and is a strong competitor for realizing AR technology.

[0005] Summary of the Invention

[0006] One purpose of the present disclosure is to provide a method for preparing a Micro-LED chip.

[0007] In one aspect of the present disclosure, a method for preparing a Micro-LED chip is provided. According to an embodiment of the present disclosure, the method for preparing a Micro-LED chip includes: providing a substrate; forming a buffer layer on the surface of the substrate; forming a plurality of spaced pixel columns on a side of the buffer layer away from the substrate, the pixel columns including blue pixel columns, green pixel columns, and red pixel columns, and the method for forming the pixel columns includes: epitaxially growing a plurality of spaced first n-type doped GaN layers on a side of the buffer layer away from the substrate; growing a first barrier layer on a surface of the first n-type doped GaN layer away from the substrate; growing a quantum well structure layer on a surface of the first barrier layer away from the substrate; sequentially growing a blue quantum well light-emitting layer, a green quantum well light-emitting layer, and a red quantum well light-emitting layer on a surface of the quantum well structure layer away from the substrate to obtain the red pixel columns; etching and removing the red quantum well light-emitting layer and the green quantum well light-emitting layer used to form the blue pixel columns to obtain the blue pixel columns; etching and removing the red quantum well light-emitting layer used to form the green pixel columns to obtain the green pixel columns. Therefore, by epitaxially growing RGB Micro LED pixel columns, on the one hand, monolithic integration can be achieved and full colorization can be realized. On the other hand, the damage to the side walls of the pixel columns caused by etching during the chip preparation process can be reduced to a certain extent, thereby improving the chip's luminescence performance.

[0008] According to an embodiment of the present disclosure, the method for preparing a Micro-LED chip also includes: depositing a first isolation layer in the gap between the blue light pixel column, the green light pixel column and the red light pixel column, and the first isolation layer covers the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column; etching and removing the first isolation layer corresponding to the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column to expose the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column; growing a protective layer, an electron blocking layer and a first partial hole injection layer on the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column, so that the first partial hole injection layer is flush with the surface of the first isolation layer away from the substrate; growing a second partial hole injection layer on the surfaces of the first partial hole injection layer and the first isolation layer away from the substrate; and depositing an ohmic contact layer on the surface of the second partial hole injection layer away from the substrate.

[0009] According to an embodiment of the present disclosure, the method for preparing a Micro-LED chip also includes: S1: growing a first undoped GaN layer on the surface of the buffer layer away from the substrate, the thickness of the first undoped GaN layer is 0.5 to 1 μm; S2: forming a first inorganic layer on the surface of the first undoped GaN layer away from the substrate, the first inorganic layer having a plurality of spaced-apart openings, and the thickness of the first inorganic layer is 10 to 30 nm; S3: growing a second undoped GaN layer on the surface of the first undoped GaN layer not covered by the first inorganic layer, and the second undoped GaN layer covers the surface of the first inorganic layer, the thickness of the second undoped GaN layer is 0.5 to 1 μm; S4: repeating steps S2 and S3 until the total thickness of the undoped GaN layer is 3.5 to 4 μm, wherein the orthographic projection of the pixel column on the substrate is within the orthographic projection of the first inorganic layer on the substrate.

[0010] According to an embodiment of the present disclosure, the method for preparing a Micro-LED chip also includes: etching a first groove and a second groove on the surface of the undoped GaN layer, the orthographic projection of the first groove on the substrate overlaps with the orthographic projection of the green light pixel column on the substrate, the orthographic projection of the second groove on the substrate overlaps with the orthographic projection of the red light pixel column on the substrate, and the depth of the second groove is greater than the depth of the first groove; depositing a second inorganic layer on the surface of the undoped GaN layer away from the substrate, and the second inorganic layer has a first through hole, a second through hole and a third through hole passing through the second inorganic layer, the first through hole exposes the first groove, the second through hole exposes the second groove, and the third through hole exposes a predetermined area of ​​the undoped GaN layer, wherein the orthographic projection of the predetermined area on the substrate overlaps with the orthographic projection of the blue light pixel column on the substrate, wherein the blue light pixel column is arranged in the third through hole, the green light pixel column is arranged in the first through hole, and the red light pixel column is arranged in the second through hole.

[0011] According to an embodiment of the present disclosure, the depth of the first groove is 28 to 145 nm, the depth of the second groove is 50 to 300 nm, and optionally, the thickness of the second inorganic layer is 100 to 300 nm.

[0012] According to an embodiment of the present disclosure, the step of growing the first n-type doped GaN layer includes sequentially growing an n-type heavily doped GaN layer and an n-type lightly doped GaN layer, wherein the doping concentration of the n-type heavily doped GaN layer is 5×10 18 ~1×10 19 cm -3 The thickness of the n-type heavily doped GaN layer is 1.5 to 2.5 μm, and the doping concentration of the n-type lightly doped GaN layer is 3×10 17 ~6×10 17 cm -3 The thickness of the n-type lightly doped GaN layer is 0.3 to 0.5 μm; the first barrier layer is non-doped GaN, and the thickness of the first barrier layer is 20 to 60 nm; the step of growing the quantum well structure layer includes sequentially growing the first quantum well structure layer and the second quantum well structure layer, and the first quantum well structure layer includes a stacked arrangement of In x Ga 1-x N potential well layer and GaN barrier layer, x is 0.01 to 0.03, the In x Ga 1-x The thickness of the N potential well layer is 2.5 to 3.5 nm, and the thickness of the GaN barrier layer is 5 to 15 nm; the second quantum well structure layer includes a stacked In y Ga 1-yN potential well layer and the second n-type doped GaN barrier layer, y is 0.03 to 0.05, the In y Ga 1-y The thickness of the N-type well layer is 2.5 to 3.5 nm, the thickness of the second n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the second n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 .

[0013] According to an embodiment of the present disclosure, the blue light quantum well light emitting layer includes a first non-doped GaN film layer, an In a Ga 1-a N potential well layer, second undoped GaN film layer and In b Ga 1-b N barrier layer, wherein a is 0.18-0.21, b is 0.01-0.05; the green light quantum well light-emitting layer includes a stacked third non-doped GaN film layer, In c Ga 1-c N potential well layer, the fourth undoped GaN film layer and the first n-type doped GaN barrier layer, the fifth undoped GaN film layer, In d Ga 1-d N potential well layer, the sixth non-doped GaN film layer and the second n-type doped GaN barrier layer, wherein c is 0.24-0.25, d is 0.25-0.28; the red light quantum well light-emitting layer includes a stacked seventh non-doped GaN film layer, In e Ga 1-e N potential well layer, eighth undoped GaN film layer, p-type doped GaN barrier layer and Al h Ga 1-h N layer, wherein e is 0.35 to 0.38, and h is 0.10 to 0.30.

[0014] According to an embodiment of the present disclosure, the blue quantum well light emitting layer, the green quantum well light emitting layer and the red quantum well light emitting layer further satisfy at least one of the following conditions: the thickness of the first non-doped GaN film layer to the eighth non-doped GaN film layer is 2 to 8 nm respectively; a Ga 1-a The thickness of the N potential well layer is 2.5 to 3.5 nm. b Ga 1-b The thickness of the N barrier layer is 5 to 15 nm; c Ga 1-c The thickness of the N-type well layer is 2.5 to 3.5 nm, the thickness of the first n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the first n-type doped GaN barrier layer is 1×1017 ~5×10 17 cm -3 , the In d Ga 1-d The thickness of the N-type well layer is 2.5 to 3.5 nm, the thickness of the second n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the second n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 ; The In e Ga 1-e The thickness of the N potential well layer is 2.5 to 3.5 nm, the thickness of the p-type doped GaN barrier layer is 5 to 15 nm, and the Al h Ga 1-h The thickness of the N layer is 1 to 2 nm.

[0015] According to an embodiment of the present disclosure, the total thickness of the protective layer, the electron blocking layer and the first portion of the hole injection layer is 120 to 180 nm.

[0016] According to an embodiment of the present disclosure, the substrate is a sapphire substrate, and the buffer layer is an aluminum nitride layer; or, the substrate is a silicon substrate, and the buffer layer is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in the direction away from the substrate; or, the substrate is an n-type doped silicon carbide substrate, and the buffer layer is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in the direction away from the substrate.

[0017] According to an embodiment of the present disclosure, the substrate is an n-type doped silicon carbide substrate, the buffer layer is an n-type doped aluminum gallium nitride layer, and the pixel column is directly formed on the surface of the buffer layer away from the substrate; or, the substrate is an n-type doped gallium nitride substrate, the buffer layer is an aluminum nitride layer, and the pixel column is directly formed on the surface of the buffer layer away from the substrate.

[0018] According to an embodiment of the present disclosure, the method for preparing a Micro-LED chip further includes: sequentially depositing a first conductive film layer, a reflector, and a binding metal layer on the surface of the ohmic contact layer away from the substrate; binding a pixel driving circuit on the surface of the binding metal layer away from the substrate; peeling off the substrate; etching the layer structure between the pixel column and the substrate and a portion of the n-type heavily doped GaN layer in the pixel column using an etching method until the surface of the blue light pixel column away from the first conductive film layer, the surface of the green light pixel column away from the first conductive film layer, and the surface of the red light pixel column away from the first conductive film layer are located in the same plane; removing the first isolation layer between the blue light pixel column, the green light pixel column, and the red light pixel column ; forming a sidewall passivation layer and a reflective film layer in sequence on the surface of the pixel column; etching and removing portions of the sidewall passivation layer, the reflective film layer, the second portion of the hole injection layer, the ohmic contact layer and the first conductive film layer between different pixel columns to form an isolation groove; depositing a second isolation layer in the isolation groove; removing at least portions of the sidewall passivation layer and the reflective film layer on the table of the pixel column to expose the surface of the n-type heavily doped GaN layer; forming a second conductive film layer on the table of the pixel column, on the sidewalls of the reflective film layer and on the surface of the second isolation layer; depositing a third isolation layer on the sidewalls and bottom wall of the second conductive film layer; forming a high-reflection electrode in the third isolation layer, and the high-reflection electrode is arranged in contact with the second conductive film layer.

[0019] In another aspect of the present disclosure, a Micro LED chip is provided. According to an embodiment of the present disclosure, the Micro LED chip is prepared using the method described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present disclosure will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0021] FIG1 is a flow chart showing a partial structure of preparing a Micro-LED chip according to an embodiment of the present disclosure;

[0022] FIG2 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present disclosure;

[0023] FIG3 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present disclosure;

[0024] FIG4 is a structural diagram of a blue light quantum well light-emitting layer in another embodiment of the present disclosure;

[0025] FIG5 is a structural diagram of a green quantum well light-emitting layer in another embodiment of the present disclosure;

[0026] FIG6 is a structural diagram of a red light quantum well light-emitting layer in another embodiment of the present disclosure;

[0027] FIG7 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present disclosure;

[0028] FIG8 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present disclosure;

[0029] FIG9 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present disclosure;

[0030] FIG10 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present disclosure;

[0031] FIG11 is a flow chart showing a partial structure of a Micro-LED chip prepared in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The scheme of the present disclosure will be explained below in conjunction with the examples. Those skilled in the art will understand that the following examples are only used to illustrate the present disclosure and should not be regarded as limiting the scope of the present disclosure. Where specific techniques or conditions are not specified in the examples, they are carried out according to the techniques or conditions described in the literature in this field or according to the product instructions. The present disclosure will be described below with reference to specific examples. It should be noted that these examples are merely illustrative and do not limit the present disclosure in any way.

[0033] The electro-optical conversion efficiency of red light Micro-LEDs based on AlGaInP materials decreases significantly when the size is small (<10μm), which limits the development of full-color Micro-LED display technology.

[0034] During the production of red light Micro-LED arrays, due to the high surface recombination velocity and long minority carrier diffusion length of the AlGaInP material system, small-scale etching and cutting will lead to severe carrier leakage and cause the quantum efficiency to drop by more than 90% at the expected Micro-LED size; secondly, when integrating the three primary color tube cores in the Micro-LED full-color display, due to the different material systems, the current mainstream blue and green light InGaN-based Micro-LED chips and AlGaInP red light cannot be directly integrated, resulting in a complex circuit structure, a significantly reduced transfer yield, and a large amount of additional costs.

[0035] The disclosed method for preparing a Micro-LED chip can achieve monolithic integration and full color, or can reduce damage to the pixel column sidewalls caused by etching during the chip preparation process to a certain extent. The disclosed Micro LED chip can better achieve monolithic integration and full color, and can further improve the chip's luminous performance. Those skilled in the art will understand that the disclosed Micro LED chip has all the features and advantages of the aforementioned method for preparing a Micro LED chip, and no further elaboration will be given here.

[0036] In one aspect of the present disclosure, a method for preparing a Micro-LED chip is provided. According to an embodiment of the present disclosure, referring to FIG1 to FIG11 , the method for preparing a Micro-LED chip includes:

[0037] S100: providing a substrate 10.

[0038] Among them, the specific type of the substrate can be a sapphire substrate, a silicon substrate, an n-type doped silicon carbide substrate or an n-type doped gallium nitride substrate. Those skilled in the art can flexibly select a suitable substrate type according to the specific structural type of the Micro-LED chip.

[0039] S200: forming a buffer layer 20 on the surface of the substrate 10. The buffer layer may be deposited by physical vapor deposition (PVD), and the thickness of the buffer layer is 10-100 nm.

[0040] Among them, those skilled in the art can select an appropriate buffer layer structure based on the specific type of substrate. In some embodiments, the substrate 10 is a sapphire substrate, and the buffer layer 20 is an aluminum nitride layer with a thickness of 10 to 100 nm. In other embodiments, the substrate 10 is a silicon substrate, and the buffer layer 20 is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in the direction away from the substrate 10. In other embodiments, the substrate 10 is an n-type doped silicon carbide substrate, and the buffer layer 20 is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in the direction away from the substrate 10. In other embodiments, the substrate 10 is an n-type doped silicon carbide substrate, and the buffer layer 20 is an n-type doped aluminum gallium nitride layer. In still other embodiments, the substrate is an n-type doped gallium nitride substrate, and the n-GaN layer is directly grown.

[0041] According to some embodiments of the present disclosure, when the substrate 10 is an n-type doped silicon carbide substrate and the buffer layer 20 is an n-type doped aluminum gallium nitride layer (vertical structure epitaxial wafer (Epi-Wafer)), and when the substrate is an n-type doped gallium nitride substrate and the buffer layer is an aluminum nitride layer, subsequent pixel columns can be directly formed on the surface of the buffer layer.

[0042] According to other embodiments of the present disclosure, when the substrate 10 is a sapphire substrate and the buffer layer 20 is an aluminum nitride layer, when the substrate 10 is a silicon substrate and the buffer layer 20 is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in a direction away from the substrate 10, and when the substrate 10 is an n-type doped silicon carbide substrate and the buffer layer 20 is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in a direction away from the substrate 10 (horizontally structured epitaxial wafer (Epi-Wafer)), referring to FIG. 1 , the method for preparing a Micro-LED chip further includes:

[0043] S1: A first undoped GaN layer 31 is grown on a surface of the buffer layer 10 away from the substrate 10. The thickness of the first undoped GaN layer 31 is 0.5 to 1 μm (e.g., 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, or 1.0 μm). Specifically, the first undoped GaN layer 31 can be epitaxially grown using a MOCVD (Metal Organic Chemical Vapor Deposition) device, which is a high-purity chemical vapor deposition technology used to prepare semiconductor materials and devices.

[0044] S2: A first inorganic layer 32 is formed on the surface of the first undoped GaN layer 31 away from the substrate 10. The first inorganic layer 32 has a plurality of spaced openings 322. The thickness of the first inorganic layer 32 is 10 to 30 nm (e.g., 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 23 nm, 25 nm, 28 nm, 30 nm), as shown in (a) and (b) of FIG1 . By depositing the first inorganic layer 32, the dislocation density within the first undoped GaN layer 31 can be reduced. The first inorganic layer 32 can be formed by the following method: depositing an inorganic film layer 321 using PECVD (Plasma Enhanced Chemical Vapor Deposition), and then etching the inorganic film layer into a first inorganic layer 32 with a stripe structure or a mesh structure through processes such as coating a photoresist, exposure, development, etching, degumming, and cleaning. The size and shape of the openings in the first inorganic layer 32 need to be set according to the size and shape of the pixel. In addition, the first inorganic layer of the aforementioned thickness can effectively reduce the dislocation density in the first undoped GaN layer 31 without making the first inorganic layer too thick, thereby wasting material.

[0045] S3: A second undoped GaN layer 33 is grown on the surface of the first undoped GaN layer 31 that is not covered by the first inorganic layer 32, and the second undoped GaN layer 33 covers the surface of the first inorganic layer 32, as shown in (c) in Figure 1. The thickness of the second undoped GaN layer 33 is 0.5 to 1 μm (for example, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm). Specifically, the second undoped GaN layer 33 can be epitaxially grown using MOCVD equipment. Since undoped GaN material cannot grow directly on the surface of the inorganic layer, the surface of the first undoped GaN layer 31 exposed by the first inorganic layer continues to nucleate, and after the thickness exceeds 10 to 30 nm, undoped GaN is gradually grown laterally epitaxially. At this time, the first inorganic layer 32 can act as a good mask to prevent further extension of dislocations.

[0046] S4: Repeat steps S2 and S3 at least once until the total thickness of the undoped GaN layer (including the first undoped GaN layer 31, the second undoped GaN layer 33 and the second undoped GaN layer 33 repeatedly grown in step S4) is 3.5 to 4 μm, wherein the orthographic projection of the subsequently prepared pixel column on the substrate is located within the orthographic projection of the first inorganic layer 32 on the substrate, as shown in (d) in Figure 1. Through the above steps, the first inorganic layer 32 is formed multiple times, which can effectively reduce the further extension of dislocations in the undoped GaN layer corresponding to the pixel column, so that the penetration dislocation density in this area is low, that is, the non-radiative recombination center is reduced, which is conducive to obtaining a high-performance Micro LED pixel array and improving the luminescence performance of the Micro LED chip to a certain extent.

[0047] Furthermore, as shown in FIG1 , the orthographic projections of different first inorganic layers 32 on the substrate substantially overlap. Thus, in steps S1 to S4, the same mask can be used to prepare different first inorganic layers 32, saving the number of masks and reducing production costs. The first inorganic layers of different layers can be the same or different, as long as the thickness is between 10 and 30 nm.

[0048] According to an embodiment of the present disclosure, in order to better grow pixel columns later, referring to FIG. 2 , the method for preparing a Micro-LED chip further includes:

[0049] S5: Etch a first groove 331 and a second groove 332 on the surface of the undoped GaN layer (i.e., the second undoped GaN layer 33 on the top in step S4), the orthographic projection of the first groove 331 on the substrate 10 overlaps with the orthographic projection of the green light pixel column on the substrate, and the orthographic projection of the second groove 332 on the substrate 10 overlaps with the orthographic projection of the red light pixel column on the substrate, and the depth of the second groove 332 is greater than the depth of the first groove 331.

[0050] Another mask may be used to etch the first groove 331 and the second groove 332 through processes such as photoresist coating, exposure, development, etching, stripping, and cleaning. Furthermore, the depth of the first groove is 28 to 145 nm (e.g., 28 nm, 35 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, and 145 nm), and the depth of the second groove is 50 to 300 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, and 300 nm).

[0051] S6: Depositing a second inorganic layer 34 on the surface of the undoped GaN layer away from the substrate 10, and the second inorganic layer 34 has a first through hole 341, a second through hole 342 and a third through hole 343 penetrating the second inorganic layer 34, the first through hole 341 exposes the first groove 331, the second through hole 342 exposes the second groove 332, and the third through hole 343 exposes a predetermined area of ​​the undoped GaN layer (that is, the uppermost second undoped GaN layer 33 in step S4), wherein the orthographic projection of the predetermined area on the substrate 10 overlaps with the orthographic projection of the blue light pixel column on the substrate, wherein the blue light pixel column is arranged in the third through hole 343, the green light pixel column is arranged in the first through hole 341, and the red light pixel column is arranged in the second through hole 342, that is, the first through hole 341, the second through hole 342 and the third through hole 343 expose the growth surfaces of the green light pixel column, the red light pixel column and the blue light pixel column respectively. The thickness of the second inorganic layer 34 is 100-300 nm, such as 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, and 300 nm. The material of the second inorganic layer may be silicon nitride or silicon oxide.

[0052] In some examples, the method for forming the second inorganic layer 34 can be: depositing an inorganic thin film on the surface of the undoped GaN layer away from the substrate 10 and in the first groove and the second groove, and then using another mask to etch through processes such as exposure, development, etching, degumming, and cleaning to obtain a patterned second inorganic layer 34.

[0053] S300: Referring to FIG3 , a plurality of pixel columns are formed on a side of the buffer layer 20 away from the substrate (in FIG3 , a blue pixel column, a green pixel column, and a red pixel column are grown in a predetermined area, a first groove, and a second groove, respectively). The pixel columns include a blue pixel column B, a green pixel column G, and a red pixel column R. The method for forming the pixel columns includes:

[0054] S310: epitaxially growing a plurality of first n-type doped GaN layers 41 spaced apart on a side of the buffer layer 20 away from the substrate (in FIG3 , a plurality of first n-type doped GaN layers 41 spaced apart are grown on the surface of the undoped GaN layer exposed in the predetermined area, the first groove, and the second groove), refer to FIG3 .

[0055] In some examples, the step of growing the first n-type doped GaN layer 41 includes sequentially growing an n-type heavily doped GaN layer 411 and an n-type lightly doped GaN layer 412, wherein the n-type heavily doped GaN layer 411 can be grown by a vapor phase epitaxial growth technique (MOCVD) at a growth temperature of 1040° C. to 1060° C., SiH4 is used as an n-type dopant, and the doping concentration of the n-type heavily doped GaN layer 411 is 5×10 18 ~1×10 19 cm -3 The thickness of the n-type heavily doped GaN layer 411 is 1.5 to 2.5 μm; the n-type lightly doped GaN layer 412 can be grown by vapor phase epitaxial growth technology (MOCVD) at a growth temperature of 1040°C to 1060°C, with SiH4 as the n-type dopant, and the doping concentration of the n-type lightly doped GaN layer 412 is 3×10 17 ~6×10 17 cm -3 The thickness of the n-type lightly doped GaN layer 412 is 0.3-0.5 μm.

[0056] S320: growing a first barrier layer 42 on the surface of the first n-type doped GaN layer 41 away from the substrate, as shown in FIG3 . The thickness of the first barrier layer 42 is 20-60 nm, and the material of the first barrier layer 42 is undoped GaN.

[0057] S330 : growing a quantum well structure layer 43 on the surface of the first barrier layer 42 away from the substrate 10 , refer to FIG. 3 .

[0058] In some embodiments of the present disclosure, the step of growing the quantum well structure layer 43 includes sequentially growing a first quantum well structure layer 431 and a second quantum well structure layer 432, wherein the first quantum well structure layer 431 is grown for 3 to 5 cycles, and the first quantum well structure layer 431 includes a stacked arrangement In x Ga 1-x N potential well layer and GaN barrier layer, x is 0.01~0.03, that is, In x Ga 1-x The In content in the N-well layer is 1% to 3%. x Ga 1-xThe N potential well layer is disposed close to the first barrier layer (First barrier) 42, and the GaN barrier layer is disposed away from the first barrier layer (First barrier) 42. x Ga 1-x The thickness of the N potential well layer is 2.5 to 3.5 nm, and the thickness of the GaN barrier layer is 5 to 15 nm; the second quantum well structure layer includes a stacked In y Ga 1-y N potential well layer and the second n-type doped GaN barrier layer, y is 0.03 to 0.05, that is, In y Ga 1-y The In content in N is 3% to 5%. y Ga 1-y The N-type potential well layer is disposed close to the first barrier layer (First barrier) 42, and the second n-type doped GaN barrier layer is disposed away from the first barrier layer (First barrier) 42. y Ga 1-y The thickness of the N-type well layer is 2.5 to 3.5 nm, the thickness of the second n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the second n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 .

[0059] In the process of growing the first quantum well structure layer 431, x Ga 1-x A non-doped GaN layer is pre-grown before the N potential well layer, and a non-doped GaN layer is pre-grown before the GaN layer is grown. The thickness of these two non-doped GaN layers is 1 to 5 microns, and the growth temperature is the same as that of the In growth layer. x Ga 1-x The temperature of the N potential well layer is the same, both 1040 ~ 1060 ° C.

[0060] S340: A blue quantum well light-emitting layer 44, a green quantum well light-emitting layer 45, and a red quantum well light-emitting layer 46 are sequentially grown on the surface of the quantum well structure layer 43 away from the substrate 10 to obtain a red pixel column R, as shown in (a) of FIG3 . The blue quantum well light-emitting layer has an emission wavelength of 455 to 465 nm, the green quantum well light-emitting layer has an emission wavelength of 520 to 535 nm, and the red quantum well light-emitting layer has an emission wavelength of 620 to 635 nm.

[0061] According to the embodiments of the present disclosure, since the subsequent steps S350 and S360 enter the etching stage (hydrogen atmosphere), the blue quantum well light-emitting layer 44, the green quantum well light-emitting layer 45, and the red quantum well light-emitting layer 46 formed in step S340 are carried out in a nitrogen atmosphere. Because there is a more serious etching phenomenon when the nitrogen film-forming atmosphere is switched to a hydrogen atmosphere, a 30-60 nm thick protective layer (whose material can be non-doped GaN) can be pre-formed before the product obtained in step S340 is removed from the nitrogen atmosphere to prevent the formed blue quantum well light-emitting layer 44, the green quantum well light-emitting layer 45, and the red quantum well light-emitting layer 46 from being damaged.

[0062] S350 : etching and removing the red quantum well light-emitting layer 46 and the green quantum well light-emitting layer 45 used to form the blue pixel column B to obtain the blue pixel column B, as shown in FIG3( b ).

[0063] S360: etching and removing the red quantum well light-emitting layer 46 used to form the green pixel column G to obtain the green pixel column G, as shown in FIG3 (c).

[0064] In some embodiments of the present disclosure, referring to FIG. 4 , the blue light quantum well light emitting layer 44 includes a first non-doped GaN film layer 441, an In a Ga 1-a N potential well layer 442, second undoped GaN film layer 443 and In b Ga 1-b N barrier layer 444, where a is 0.18-0.21, b is 0.01-0.05, i.e., In a Ga 1-a The In composition of the N-well layer 4812 is 18% to 21%. b Ga 1-b The In content in the N barrier layer 4814 is 1% to 5%. a Ga 1-a Growing a first non-doped GaN film layer 441 before the N potential well layer 442 can effectively improve the surface flatness of the film layer and increase the In a Ga 1-a The growth quality of the N potential well layer 442 is beneficial to the improvement of the device's luminous brightness; b Ga 1-b A second non-doped GaN film layer 443 is grown before the N barrier layer 444 to prevent In a Ga 1-aThe precipitation of In in the N potential well layer is beneficial to the improvement of the device's luminous brightness. The thickness of the first non-doped GaN film layer 441 and the second non-doped GaN film layer 443 are 1 to 8 nm respectively. The growth temperature of the first non-doped GaN film layer 441 is 1 to 8 nm. a Ga 1-a The growth temperature of the N potential well layer 442 is the same as that of the second non-doped GaN film layer 443. b Ga 1-b The growth temperature of the N barrier layer 444 is the same, which can effectively alleviate the problem of wave shift under large current injection; a Ga 1-a The thickness of the N potential well layer is 2.5 to 3.5 nm, and In b Ga 1-b The thickness of the N barrier layer is 5-15 nm, thereby ensuring good luminescence properties of the blue quantum well light-emitting layer 44 .

[0065] In some embodiments of the present disclosure, referring to FIG. 5 , the green quantum well light emitting layer 45 includes a third non-doped GaN film layer 451, an In c Ga 1-c N potential well layer 452, fourth non-doped GaN film layer 453 and first n-type doped GaN barrier layer 454, fifth non-doped GaN film layer 455, In d Ga 1-d N potential well layer 456, sixth non-doped GaN film layer 457 and second n-type doped GaN barrier layer 458, wherein c is 0.24-0.25, d is 0.25-0.28, that is, In c Ga 1-c The composition of In in the N452 potential well layer is 24% to 25%. d Ga 1-d The In content in the N potential well layer 456 is 25% to 28%. c Ga 1-c Growing a third non-doped GaN film layer 451 before the N potential well layer 452 can effectively improve the surface flatness of the film layer and increase the In c Ga 1-c The growth quality of the N-type potential well layer 452 is beneficial to the improvement of the device's luminous brightness; before growing the first n-type doped GaN barrier layer 454, a fourth non-doped GaN film layer 453 is grown to prevent In c Ga 1-c The precipitation of In in the N-well layer is beneficial to the improvement of the device's luminous brightness; d Ga 1-dGrowing a fifth non-doped GaN film layer 455 before the N potential well layer 456 can effectively improve the surface flatness of the film layer and increase the In d Ga 1-d The growth quality of the N-type potential well layer 456 is beneficial to the improvement of the device's luminous brightness; before growing the second n-type doped GaN barrier layer 458, a sixth non-doped GaN film layer 457 is grown to prevent In d Ga 1-d The precipitation of In in the N-well layer 456 is beneficial to improving the luminance of the device.

[0066] The thickness of the third to sixth non-doped GaN film layers are 2 to 8 nm respectively, and the growth temperature of the third non-doped GaN film layer 451 is about 100 nm. c Ga 1-c The growth temperature of the N-type well layer 452 is the same as that of the fourth undoped GaN film layer 453, the growth temperature of the first n-type doped GaN barrier layer 454 is the same as that of the fifth undoped GaN film layer 455, and the growth temperature of the fifth undoped GaN film layer 455 is the same as that of the In-type doped GaN barrier layer 454. d Ga 1-d The growth temperature of the N-type well layer 456 is the same as that of the sixth non-doped GaN film layer 457, and the growth temperature of the second n-type doped GaN barrier layer 458 is the same, thereby effectively alleviating the problem of wave shift under large current injection. c Ga 1-c The thickness of the N-type well layer is 2.5 to 3.5 nm, the thickness of the first n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the first n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 ,In d Ga 1-d The thickness of the N-type well layer is 2.5 to 3.5 nm, the thickness of the second n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the second n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 In this way, good luminescence properties of the green quantum well light-emitting layer 45 are ensured.

[0067] In some embodiments of the present disclosure, referring to FIG. 6 , the red light quantum well light emitting layer 46 includes a seventh non-doped GaN film layer 461, an In e Ga 1-e N potential well layer 462, eighth non-doped GaN film layer 463, p-type doped GaN barrier layer 464 and Al h Ga 1-hN layer 465, where e is 0.35 to 0.38 and h is 0.10 to 0.30, i.e., In e Ga 1-e The composition of In in the N-well layer 462 is 35% to 38%, and Al h Ga 1-h The Al content in the N layer 465 is 10% to 30%. e Ga 1-e Growing a seventh non-doped GaN film layer 461 before the N potential well layer 462 can effectively improve the surface flatness of the film layer and increase the In e Ga 1-e The growth quality of the N potential well layer 462 is beneficial to improving the luminance of the device; growing an eighth undoped GaN film layer 463 before growing the p-type doped GaN barrier layer 464 is beneficial to improving the luminance of the device.

[0068] The thickness of the seventh non-doped GaN film layer and the eighth non-doped GaN film layer are 2-8 nm, respectively. e Ga 1-e The thickness of the N-type well layer is 2.5 to 3.5 nm, the thickness of the p-type doped GaN barrier layer is 5 to 15 nm, and the thickness of the Al h Ga 1-h The thickness of the N layer is 1-2 nm, thus ensuring good luminescence properties of the red light quantum well light emitting layer 46. In addition, the growth temperature of the seventh non-doped GaN film layer 461 is the same as that of the In e Ga 1-e The growth temperature of the N-type well layer 462 is the same as that of the eighth undoped GaN film layer 463 and the p-type doped GaN barrier layer 464, thereby effectively alleviating the problem of wave shift under large current injection.

[0069] According to an embodiment of the present disclosure, referring to FIG. 7 and FIG. 8 , the method for preparing a Micro-LED chip further includes:

[0070] S400: Depositing a first isolation layer 51 in the gaps between the blue pixel column B, the green pixel column G, and the red pixel column R. The first isolation layer 51 covers the surfaces of the blue pixel column B, the green pixel column G, and the red pixel column R, as shown in FIG7(a). The material of the first isolation layer 51 can be silicon nitride or silicon oxide, which can be prepared by vapor deposition.

[0071] S500: Parts of the first isolation layer 51 corresponding to the surfaces of the blue pixel column B, the green pixel column G, and the red pixel column R are etched away to expose the surfaces of the blue pixel column B, the green pixel column G, and the red pixel column R, as shown in FIG7(b). Specifically, a mask can be used to obtain the surface through exposure, development, etching, de-bonding, cleaning, etc. The mask used in this step can be the same mask used in step S6.

[0072] S600: A protective layer 52, an electron blocking layer 53, and a first portion of a hole injection layer 54 are grown on the surfaces of the blue pixel column B, the green pixel column G, and the red pixel column R, so that the first portion of the hole injection layer 54 is flush with the surface of the first isolation layer 51 away from the substrate, as shown in FIG8(a). Prior to growing the protective layer, the product etched in step S500 is cleaned in sequence with toluene, acetone, ethanol, and deionized water, and dried with nitrogen. After heating in a nitrogen atmosphere, the protective layer is grown.

[0073] Furthermore, in some embodiments, the total thickness of the protective layer 52, the electron blocking layer 53 and the first portion of the hole injection layer 54 is 120 to 180 nm, that is, the total thickness of the protective layer 52, the electron blocking layer 53 and the first portion of the hole injection layer 54 is the thickness of the first isolation layer etched away in step S500.

[0074] The thickness of the protective layer 52 is 20-40 nm, and the material of the protective layer is non-doped gallium nitride. The electron blocking layer 53 is formed by growing 4-6 pairs of p-type doped Al m Ga 1-m The hole concentration of the N layer and the first p-type doped GaN layer and the electron blocking layer is 1.5×10 18 ~2×10 18 cm -3 , p-type doped Al m Ga 1-m The thickness of the N layer is 2.5 to 3.5 nm, and the Al composition is 20% to 30% (i.e., Al m Ga 1-m m in N is 0.2-0.3), and the thickness of the first p-type doped GaN layer is 5-8 nm.

[0075] S700: A second portion of the hole injection layer 55 is grown on the surface of the first portion of the hole injection layer 54 and the first isolation layer 51 away from the substrate 10, as shown in FIG8(b). The hole injection layer (including the first portion of the hole injection layer and the second portion of the hole injection layer) is formed by growing 8 to 14 pairs of stacked p-type doped Al n Ga 1-n The hole concentration of the N layer and the second p-type doped GaN layer and the electron blocking layer is 1×10 18~2×10 18 cm -3 , p-type doped Al n Ga 1-n The thickness of the N layer is 2.5 to 3.5 nm, and the Al composition is 10% to 20% (i.e., Al n Ga 1-n The n in N is 0.1 to 0.2), and the thickness of the second p-type doped GaN layer is 5 to 8 nm.

[0076] S800: Deposit an ohmic contact layer 56 on the surface of the second portion of the hole injection layer 55 away from the substrate 10, as shown in (b) of Figure 8. The ohmic contact layer 56 is a p-type heavily doped GaN layer with a thickness of 20-40 nm.

[0077] After step S800 is completed, the product after step S800 may be subjected to an annealing treatment in a nitrogen atmosphere to complete the growth of the epitaxial structure.

[0078] According to an embodiment of the present disclosure, referring to FIG. 9 to FIG. 11 , the method for preparing a Micro-LED chip further includes:

[0079] S900 : A first conductive film layer 61 , a reflector 62 , and a binding metal layer 63 are sequentially deposited on the surface of the ohmic contact layer 56 away from the substrate 10 , as shown in FIG9 ( a ).

[0080] In some embodiments, the first conductive film layer 61 may be deposited to a thickness of 30 to 120 nm by electron beam evaporation or sputtering, and may be further combined with a rapid annealing process to increase the transmittance of the first conductive film layer 61 and reduce the resistance of the first conductive film layer 61. The material of the first conductive film layer may be ITO.

[0081] In some embodiments, a reflector 62 with a thickness of 100 to 300 nm can be deposited by electron beam evaporation or sputtering to improve the light extraction efficiency of the Micro LED chip. The reflector 62 can be made of silver or aluminum.

[0082] In some embodiments, the binding metal layer 63 may be deposited by electron beam evaporation or Sputter (magnetron sputtering), and the material thereof includes but is not limited to at least one of Cr, Pt, Ni, Ti, Ni, and Ag.

[0083] S1000 : bonding the pixel driving circuit 64 on the surface of the bonding metal layer 63 away from the substrate 10 , as shown in FIG9 ( a ).

[0084] In some embodiments, electron beam evaporation or Sputter (magnetron sputtering) can be used to deposit binding metal (Cr, Pt, Ag, In and other materials) on the pixel driving circuit 64, and then the binding metal layer 64 and the pixel driving circuit 64 are bound by the binding metal.

[0085] S1100 : peeling off the substrate 10 , as shown in FIG9 ( b ).

[0086] In some embodiments, the substrate is a sapphire substrate, and the substrate 10 can be stripped using a laser lift-off process (LLO) with a laser wavelength of 355 nm, 266 nm, or 248 nm. In other embodiments, the substrate is a silicon substrate, and the substrate 10 can be stripped using a wet etching method. In other embodiments, the substrate is an n-type doped silicon carbide substrate, and the substrate 10 can be stripped using a wet etching method or inductively coupled plasma etching (ICP-RIE). In other embodiments, the substrate is an n-type doped gallium nitride substrate, and the substrate 10 can be stripped using an inductively coupled plasma etching (ICP-RIE).

[0087] S1200: Use an etching method (ICP-RIE) to etch the layer structure between the pixel column and the substrate and part of the n-type heavily doped GaN layer 411 in the pixel column until the surface of the blue light pixel column B away from the first conductive film layer 61, the surface of the green light pixel column G away from the first conductive film layer, and the surface of the red light pixel column R away from the first conductive film layer are in the same plane, as shown in (a) in Figure 10.

[0088] S1300 : removing the first passivation isolation layer 51 between the blue pixel column B, the green pixel column G, and the red pixel column R, as shown in (b) of FIG10 .

[0089] In some embodiments, the method for removing the first isolation layer 51 between the blue light pixel column B, the green light pixel column G and the red light pixel column R can be: using HF solution or BOE solution (buffered oxide etching solution) to remove the first isolation layer (SiNx or SiO2 material) between the blue light pixel column B, the green light pixel column G and the red light pixel column R, and then cleaning it with deionized water.

[0090] S1400 : forming a sidewall passivation layer 65 and a reflective film layer 66 in sequence on the surface of the pixel column, as shown in (c) of FIG. 10 .

[0091] In some embodiments, before forming the sidewall passivation layer 65, after removing the first isolation layer in step S1300, a PECVD device is used to perform a plasma treatment (including hydrogen, oxygen, ammonia, etc.) before film formation to remove defects on the sidewalls of the pixel columns. A sidewall passivation layer 65 having a thickness of 60 to 200 nm is then deposited. Furthermore, a reflective film layer 66 can be grown using a sputtering (magnetron sputtering) or ALD (atomic layer deposition) method to further enhance the light extraction efficiency of the chip. The reflective film layer 66 can be a DBR reflective film layer (distributed Bragg reflector).

[0092] S1500 : etching and removing part of the sidewall passivation layer 65 , the reflective film layer 66 , the second part of the hole injection layer 55 , the ohmic contact layer 56 and the first conductive film layer 61 between different pixel columns to form an isolation trench 67 , as shown in FIG11 ( a ).

[0093] In some embodiments, the isolation trench 67 may be etched using photolithography and ICP-RIE processes, and then acetone, ethanol, and deionized water may be used for desizing and surface cleaning.

[0094] S1600 : forming a second isolation layer 68 by deposition in the isolation trench 67 , as shown in FIG. 11 ( b ).

[0095] In some embodiments, the second isolation layer 68 may further cover the bottom wall and part of the side wall of the reflective film layer 66 . Specifically, the second isolation layer 68 may be deposited by physical vapor deposition.

[0096] S1700 : removing at least a portion of the sidewall passivation layer 65 and the reflective film layer 66 on the mesa of the pixel column to expose the surface of the n-type heavily doped GaN layer 411 , as shown in FIG11 ( b ).

[0097] S1800 : forming a second conductive film layer 69 on the mesas of the pixel columns, the sidewalls of the reflective film layer 66 , and the surface of the second isolation layer 68 , as shown in FIG11 ( c ).

[0098] In some embodiments, a second conductive film layer 69 with a thickness of 30 to 120 nm can be deposited by magnetron sputtering, and combined with an RTA (rapid annealing) process to improve the transmittance of the second conductive film layer 69 and reduce the material resistance, wherein the second conductive film layer 69 can be an ITO film layer.

[0099] S1900 : depositing a third isolation layer 70 on the sidewalls and bottom wall of the second conductive film layer 69 , as shown in ( d ) of FIG11 , so as to achieve electrical insulation between the pixel column mesas.

[0100] S2000: A highly reflective electrode 71 is formed in the third isolation layer 70, and the highly reflective electrode 71 is disposed in contact with the second conductive film layer 69, as shown in (d) of Figure 11. The highly reflective electrode 71 can reduce light crosstalk and light divergence between pixels, while also improving light extraction efficiency.

[0101] In some embodiments, the material of the high reflective electrode 71 may be aluminum or silver.

[0102] According to the embodiments of the present disclosure, the RGB Micro LED pixel column is monolithically integrated through the epitaxial growth method. On the one hand, monolithic integration can be achieved to realize full colorization. On the other hand, the damage to the side wall of the pixel column caused by etching during the chip preparation process can be reduced to a certain extent, thereby improving the luminous performance of the chip.

[0103] In another aspect of the present disclosure, a Micro LED chip is provided. According to an embodiment of the present disclosure, the Micro LED chip is manufactured using the method described above. As a result, the Micro LED chip can achieve better monolithic integration, achieve full color, and further improve the chip's luminous performance. Those skilled in the art will appreciate that the Micro LED chip possesses all the features and advantages of the method for manufacturing a Micro LED chip described above, and no further elaboration is required here.

[0104] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0105] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

[0106] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are illustrative and are not to be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A method for preparing a Micro-LED chip, comprising: providing a substrate; forming a buffer layer on a surface of the substrate; A plurality of pixel columns are formed at intervals on a side of the buffer layer away from the substrate, the pixel columns comprising a blue pixel column, a green pixel column and a red pixel column, and a method for forming the pixel columns comprises: epitaxially growing a plurality of first n-type doped GaN layers spaced apart on a side of the buffer layer away from the substrate; Growing a first barrier layer on a surface of the first n-type doped GaN layer away from the substrate; growing a quantum well structure layer on a surface of the first barrier layer away from the substrate; On the surface of the quantum well structure layer away from the substrate, a blue light quantum well light emitting layer, a green light quantum well light emitting layer and a red light quantum well light emitting layer are sequentially grown to obtain the red light pixel column; The red light quantum well light emitting layer and the green light quantum well light emitting layer used to form the blue light pixel column are removed by etching to obtain the blue light pixel column; The red light quantum well light-emitting layer used to form the green light pixel column is removed by etching to obtain the green light pixel column.

2. The method according to claim 1, further comprising: Depositing a first isolation layer in the gaps between the blue light pixel column, the green light pixel column and the red light pixel column, wherein the first isolation layer covers the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column; The first isolation layer corresponding to the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column is removed by etching to expose the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column; Growing a protective layer, an electron blocking layer and a first portion of a hole injection layer on the surfaces of the blue light pixel column, the green light pixel column and the red light pixel column, so that the first portion of the hole injection layer is flush with the surface of the first isolation layer away from the substrate; growing a second portion of the hole injection layer on the surface of the first portion of the hole injection layer and the first isolation layer away from the substrate; An ohmic contact layer is deposited on a surface of the second portion of the hole injection layer away from the substrate.

3. The method according to claim 1 or 2, further comprising: S1: growing a first undoped GaN layer on a surface of the buffer layer away from the substrate, wherein the thickness of the first undoped GaN layer is 0.5-1 μm; S2: forming a first inorganic layer on a surface of the first undoped GaN layer away from the substrate, wherein the first inorganic layer has a plurality of openings arranged at intervals, and a thickness of the first inorganic layer is 10 to 30 nm; S3: growing a second undoped GaN layer on the surface of the first undoped GaN layer not covered by the first inorganic layer, and the second undoped GaN layer covers the surface of the first inorganic layer, and the thickness of the second undoped GaN layer is 0.5-1 μm; S4: Repeat steps S2 and S3 until the total thickness of the non-doped GaN layer is 3.5-4 μm, wherein the orthographic projection of the pixel column on the substrate is located within the orthographic projection of the first inorganic layer on the substrate.

4. The method according to claim 3, further comprising: Etching a first groove and a second groove on the surface of the non-doped GaN layer, wherein the orthographic projection of the first groove on the substrate overlaps with the orthographic projection of the green pixel column on the substrate, the orthographic projection of the second groove on the substrate overlaps with the orthographic projection of the red pixel column on the substrate, and the depth of the second groove is greater than the depth of the first groove; A second inorganic layer is deposited on a surface of the non-doped GaN layer away from the substrate, and the second inorganic layer has a first through hole, a second through hole, and a third through hole penetrating the second inorganic layer, the first through hole exposes the first groove, the second through hole exposes the second groove, and the third through hole exposes a predetermined area of ​​the non-doped GaN layer, wherein an orthographic projection of the predetermined area on the substrate overlaps with an orthographic projection of the blue light pixel column on the substrate, Wherein, the blue light pixel column is arranged in the third through hole, the green light pixel column is arranged in the first through hole, and the red light pixel column is arranged in the second through hole.

5. The method according to claim 4, wherein: The depth of the first groove is 28-145 nm, the depth of the second groove is 50-300 nm, Optionally, the thickness of the second inorganic layer is 100-300 nm.

6. The method according to any one of claims 1 to 5, wherein: The step of growing the first n-type doped GaN layer includes sequentially growing an n-type heavily doped GaN layer and an n-type lightly doped GaN layer, wherein the doping concentration of the n-type heavily doped GaN layer is 5×10 18 ~1×10 19 cm -3 The thickness of the n-type heavily doped GaN layer is 1.5 to 2.5 μm, and the doping concentration of the n-type lightly doped GaN layer is 3×10 17 ~6×10 17 cm -3 , the thickness of the n-type lightly doped GaN layer is 0.3 to 0.5 μm; The first barrier layer is non-doped GaN, and the thickness of the first barrier layer is 20-60 nm; The step of growing the quantum well structure layer comprises sequentially growing a first quantum well structure layer and a second quantum well structure layer, wherein the first quantum well structure layer comprises a stacked arrangement of In x Ga 1-x N potential well layer and GaN barrier layer, x is 0.01 to 0.03, the In x Ga 1-x The thickness of the N potential well layer is 2.5 to 3.5 nm, and the thickness of the GaN barrier layer is 5 to 15 nm; The second quantum well structure layer includes a stacked arrangement of In y Ga 1-y N potential well layer and the second n-type doped GaN barrier layer, y is 0.03 to 0.05, the In y Ga 1-y The thickness of the N-type doped GaN barrier layer is 2.5 to 3.5 nm, the thickness of the second n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the second n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 .

7. The method according to any one of claims 1 to 6, wherein: The blue light quantum well light emitting layer includes a first non-doped GaN film layer, an In a Ga 1-a N potential well layer, second non-doped GaN film layer and In b Ga 1-b N barrier layer, wherein a is 0.18 to 0.21, and b is 0.01 to 0.05; The green light quantum well light emitting layer includes a third non-doped GaN film layer, an In c Ga 1-c N potential well layer, a fourth non-doped GaN film layer and a first n-type doped GaN barrier layer, a fifth non-doped GaN film layer, In d Ga 1-d N potential well layer, a sixth non-doped GaN film layer and a second n-type doped GaN barrier layer, wherein c is 0.24 to 0.25, and d is 0.25 to 0.28; The red light quantum well light emitting layer includes a seventh non-doped GaN film layer, an In e Ga 1-e N potential well layer, eighth non-doped GaN film layer, p-type doped GaN barrier layer and Al h Ga 1-h N layer, wherein e is 0.35 to 0.38 and h is 0.10 to 0.

30.

8. The method according to claim 7, wherein: The blue light quantum well light emitting layer, the green light quantum well light emitting layer and the red light quantum well light emitting layer further satisfy at least one of the following conditions: The thicknesses of the first to eighth undoped GaN film layers are 12 to 8 nm respectively; In a Ga 1-a The thickness of the N potential well layer is 2.5 to 3.5 nm. b Ga 1-b The thickness of the N barrier layer is 5 to 15 nm; In c Ga 1-c The thickness of the N-type doped GaN barrier layer is 2.5 to 3.5 nm, the thickness of the first n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the first n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 , the In d Ga 1-d The thickness of the N-type doped GaN barrier layer is 2.5 to 3.5 nm, the thickness of the second n-type doped GaN barrier layer is 5 to 15 nm, and the doping concentration of the second n-type doped GaN barrier layer is 1×10 17 ~5×10 17 cm -3 ; In e Ga 1-e The thickness of the N potential well layer is 2.5 to 3.5 nm, the thickness of the p-type doped GaN barrier layer is 5 to 15 nm, and the thickness of the Al h Ga 1-h The thickness of the N layer is 1 to 2 nm.

9. The method according to claim 2, wherein: The total thickness of the protective layer, the electron blocking layer and the first portion of the hole injection layer is 120-180 nm.

10. The method according to claim 3, wherein: The substrate is a sapphire substrate, and the buffer layer is an aluminum nitride layer; Alternatively, the substrate is a silicon substrate, the buffer layer is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in a direction away from the substrate; Alternatively, the substrate is an n-type doped silicon carbide substrate, the buffer layer is an aluminum nitride layer and an aluminum gallium nitride layer, and the aluminum content in the aluminum gallium nitride layer gradually decreases in a direction away from the substrate.

11. The method according to any one of claims 1 to 10, wherein: The substrate is an n-type doped silicon carbide substrate, the buffer layer is an n-type doped aluminum gallium nitride layer, and the pixel column is directly formed on the surface of the buffer layer away from the substrate; Alternatively, the substrate is an n-type doped gallium nitride substrate, the buffer layer is an aluminum nitride layer, and the pixel column is directly formed on a surface of the buffer layer away from the substrate.

12. The method according to claim 2, further comprising: Depositing a first conductive film layer, a reflector, and a binding metal layer in sequence on a surface of the ohmic contact layer away from the substrate; Binding a pixel driving circuit on a surface of the binding metal layer away from the substrate; peeling off the substrate; Etching the layer structure between the pixel column and the substrate and part of the n-type heavily doped GaN layer in the pixel column by an etching method until the surface of the blue light pixel column away from the first conductive film layer, the surface of the green light pixel column away from the first conductive film layer, and the surface of the red light pixel column away from the first conductive film layer are located in the same plane; removing the first isolation layer between the blue light pixel column, the green light pixel column and the red light pixel column; Sequentially forming a sidewall passivation layer and a reflective film layer on the surface of the pixel column; Etching and removing the sidewall passivation layer, the reflective film layer, the second hole injection layer, the ohmic contact layer and the first conductive film layer between different pixel columns to form an isolation groove; Depositing a second isolation layer in the isolation trench; removing at least a portion of the sidewall passivation layer and the reflective film layer on the mesa of the pixel column to expose the surface of the n-type heavily doped GaN layer; forming a second conductive film layer on the mesa of the pixel column, the sidewall of the reflective film layer, and the surface of the second isolation layer; Depositing a third isolation layer on the sidewalls and bottom wall of the second conductive film layer; A high-reflection electrode is formed in the third isolation layer, and the high-reflection electrode is disposed in contact with the second conductive film layer.

13. A Micro LED chip, prepared by the method according to any one of claims 1 to 12.

Images