Flexible circuit board, cof module, and electronic device comprising same

Abstract

A flexible circuit board according to an embodiment comprises: a first substrate and a second substrate; an adhesive layer disposed between the first substrate and the second substrate; a circuit pattern disposed on the first substrate and the second substrate; and a protective layer disposed on the circuit pattern. The circuit pattern includes first to third circuit patterns disposed at different positions and a plurality of vias passing through at least a portion of the first substrate and the second substrate. Each of the first substrate and the second substrate includes one surface and another surface opposite the one surface. At least one of the plurality of vias includes a plurality of first inclines formed passing through the first substrate, the second substrate, and the adhesive layer and decreasing in horizontal width, and a second incline which is provided between the plurality of first inclines and different from the first inclines.

Description

Flexible circuit boards, COF modules and electronic devices including the same

[0001] The embodiments relate to a flexible circuit board, a COF module and an electronic device including the same.

[0002] Recently, various electronic products are becoming thinner, smaller, and lighter. Accordingly, various research is being conducted to achieve high-density semiconductor chip mounting in narrow spaces within electronic devices.

[0003] Among these, the Chip-On-Film (COF) method can be applied to flexible displays because it uses a flexible substrate. This makes the COF method a promising technology for a variety of wearable electronic devices. Furthermore, because it can achieve fine pitch, it can be used to implement high-resolution displays with increased pixel counts.

[0004] COF (Chip-On-Film) is a method of mounting semiconductor chips on a flexible substrate in the form of a thin film. For example, the semiconductor chips can be integrated circuit (IC) chips or large-scale integrated circuit (LSI) chips.

[0005] The chip can be connected to an external circuit board and display panel through a circuit pattern. For example, pads are arranged at one end and the other end of the circuit pattern, respectively. One pad is electrically connected to a terminal of the chip. In addition, the other pad is connected to a terminal of the printed circuit board and a terminal of the display panel. Accordingly, the chip, the circuit board, and the display panel are electrically connected through the COF. In addition, a signal is transmitted to the display panel through the circuit pattern.

[0006] Meanwhile, the size of the flexible circuit board is limited. As the size of the flexible circuit board increases, the bezel area of ​​the display panel may increase.

[0007] Circuit patterns are arranged on the flexible circuit board. The circuit patterns are spaced apart at set intervals to prevent short circuits. Additionally, the circuit patterns are formed with a set width for electrical characteristics and process efficiency. Therefore, the number of circuit patterns arranged on the flexible circuit board may be limited.

[0008] Accordingly, there is a problem that the size of the flexible circuit board increases when connecting to a display panel with a large number of channels.

[0009] Therefore, a new structure of flexible circuit board, COF module and electronic device including the same that can solve the above problems are required.

[0010] As a patent related to the above flexible circuit board, Korean registered patent KR10-0618898 (2006.09.01) is disclosed.

[0011] An embodiment provides a flexible circuit board having a large number of circuit patterns.

[0012] The embodiment provides a flexible circuit board having a large circuit pattern width and spacing.

[0013] An embodiment provides a small-sized flexible circuit board.

[0014] The embodiment provides a flexible circuit board having improved heat dissipation characteristics.

[0015] The embodiment provides a flexible circuit board with improved flatness.

[0016] A flexible circuit board according to an embodiment comprises: a first substrate and a second substrate; an adhesive layer disposed between the first substrate and the second substrate; a circuit pattern disposed on the first substrate and the second substrate; and a protective layer disposed on the circuit pattern, wherein the circuit pattern comprises first to third circuit patterns disposed at different positions, and a plurality of vias penetrating at least a portion of the first substrate and the second substrate, each of the first substrate and the second substrate including one surface and an opposite surface, and at least one of the plurality of vias is formed penetrating the first substrate, the second substrate, and the adhesive layer and includes a plurality of first slopes having a width decreasing in a horizontal direction, and a second slope provided between the plurality of first slopes and different from the first slopes.

[0017] A flexible circuit board according to an embodiment comprises: a first substrate and a second substrate; an adhesive layer between the first substrate and the second substrate; a circuit pattern on the first substrate and the second substrate; and a protective layer on the circuit pattern, wherein the first substrate includes one side and a second side opposite the first side, and the second substrate includes one side and a second side opposite the first side, the second side of the first substrate facing the second substrate, and one side of the second substrate facing the first substrate, the circuit pattern including first to fourth circuit patterns, the first circuit pattern being connected to a printed circuit board, the second to fourth circuit patterns being connected to a display panel, and the fourth circuit pattern being a 4a pad portion disposed on one side of the first substrate; It includes a 4b pad portion arranged on the other side of the second substrate and a 4th wiring portion arranged on one side of the second substrate, and the 4a pad portion, the 4b pad portion, and the 4th wiring portion are connected by a via.

[0018] A flexible circuit board according to an embodiment includes a first substrate and a second substrate.

[0019] A circuit pattern is arranged on at least one of one side and the other side of the first substrate. In addition, a circuit pattern is arranged on at least one of one side and the other side of the second substrate. In addition, the first substrate and the second substrate are bonded by a bonding layer.

[0020] Accordingly, the area over which the circuit pattern is arranged increases. Consequently, the number of circuit patterns arranged on a single flexible circuit board increases. Alternatively, the spacing between the circuit patterns increases. Consequently, the electrical characteristics and reliability of the flexible circuit board are improved.

[0021] Additionally, the flexible circuit board includes a plurality of vias. At least one of the plurality of vias penetrates the adhesive layer. Additionally, the width of the via formed in the adhesive layer may be greater than the width of the other vias.

[0022] The above via is formed from one direction to the other. Therefore, the via is formed in a shape that narrows in width as it extends from one direction to the other. However, since the width of the via formed in the adhesive layer increases, the width of the central region of the via may increase.

[0023] Accordingly, since the contact area of ​​the via increases, de-filming of the via is prevented. In addition, since the area of ​​the via increases, heat dissipation characteristics are improved. Accordingly, the reliability of the flexible circuit board is improved.

[0024] The first substrate and the second substrate provided in the flexible circuit board according to the embodiment are bonded by an adhesive layer.

[0025] Accordingly, the flexible circuit board according to the embodiment can further arrange the four circuit patterns. The fourth circuit pattern can be arranged on one side of the first substrate, one side of the second substrate, and the other side of the second substrate.

[0026] In detail, the 4a pad portion and the 4b pad portion are arranged on one surface of the first substrate and the other surface of the second substrate. In addition, the fourth wiring portion is arranged on one surface of the second substrate.

[0027] Accordingly, the fourth wiring section can be arranged regardless of the positions of the second wiring section, the third wiring section, and the fifth wiring section. The second wiring section, the third wiring section, and the fifth wiring section are arranged on one surface of the first substrate and the other surface of the second substrate. That is, the surface on which the fourth wiring section is arranged is different from the surface on which the second wiring section, the third wiring section, and the fifth wiring section are arranged.

[0028] Accordingly, when the display panel has a large number of channels, more circuit patterns can be formed on a substrate of the same size. Alternatively, when the display panel has the same number of channels, the substrate can be made smaller. This can reduce the size of the flexible circuit board. Alternatively, when the display panel has the same number of channels, the width or area of ​​the circuit patterns on the substrate can be increased. This can improve the reliability and electrical characteristics of the flexible circuit board.

[0029] In addition, bowing of the flexible circuit board according to the embodiment can be prevented. In the flexible circuit board, the first substrate and the second substrate are bonded by the adhesive layer. The first substrate and the second substrate are arranged in the same area. Therefore, the stress magnitudes at the upper and lower portions can be similar based on the adhesive layer. Accordingly, the stress difference between the upper and lower surfaces of the flexible circuit board can be reduced. Accordingly, the flexible circuit board can be prevented from being bent in one direction due to the stress difference.

[0030] Figure 1 is a top view of the first layer of a flexible circuit board according to an embodiment.

[0031] Figure 2 is a bottom view of the first layer of a flexible circuit board according to an embodiment.

[0032] Figure 3 is a top view of the second layer of a flexible circuit board according to an embodiment.

[0033] Figure 4 is a bottom view of the second layer of a flexible circuit board according to an embodiment.

[0034] Figure 5 is a cross-sectional view taken along area AA' of Figure 1.

[0035] Figure 6 is a cross-sectional view taken along the BB' area of ​​Figure 2.

[0036] Fig. 7 is a cross-sectional view taken along the CC' area of ​​Fig. 2.

[0037] Figure 8 is a cross-sectional view taken along the DD' area of ​​Figure 1.

[0038] Figure 9 is a cross-sectional view taken along the EE' area of ​​Figure 3.

[0039] Fig. 10 is a cross-sectional view taken along the FF' area of ​​Fig. 1.

[0040] Fig. 11 is a cross-sectional view taken along the GG' region of Fig. 1.

[0041] Figures 12 and 13 are cross-sectional views taken along the H'-H section of Figure 1.

[0042] Figure 14 is a top view of the first layer of a flexible circuit board according to the first modified example.

[0043] Figure 15 is a top view of the first layer of the flexible circuit board in the second modified example.

[0044] Figure 16 is a bottom view of the first layer of a flexible circuit board according to a third modified example.

[0045] Figure 17 is a bottom view of the second layer of a flexible circuit board according to the fourth modified example.

[0046] Figure 18 is a top view of the first layer of a flexible circuit board according to the second embodiment.

[0047] Figure 19 is a top view of the second layer of a flexible circuit board according to the second embodiment.

[0048] Figure 20 is a bottom view of the second layer of a flexible circuit board according to the second embodiment.

[0049] Fig. 21 is a cross-sectional view taken along area AA' of Fig. 18.

[0050] Fig. 22 is a cross-sectional view taken along the BB' area of ​​Fig. 18.

[0051] Figure 23 is a cross-sectional view taken along the CC' area of ​​Figure 18.

[0052] Fig. 24 is a cross-sectional view taken along the DD' area of ​​Fig. 18.

[0053] Figure 25 is a cross-sectional view taken along the EE' area of ​​Figure 20.

[0054] Figure 26 is a cross-sectional view taken along the FF' area of ​​Figure 20.

[0055] Figures 27 and 28 are cross-sectional views taken along the G'G region of Figure 18.

[0056] Figures 29 to 32 are cross-sectional views taken along the HH' region of Figure 20.

[0057] Figure 33 is a drawing for explaining the connection of a COF module and other members according to an embodiment.

[0058] FIGS. 34 to 36 are drawings of electronic devices including flexible circuit boards according to embodiments.

[0059] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the described embodiments, but may be implemented in various different forms. Within the scope of the technical concept of the present invention, one or more of the components of the embodiments may be selectively combined or substituted for use.

[0060] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0061] In addition, the terminology used in the embodiments of the present invention is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0062] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and are not intended to limit the nature, order, or sequence of the components.

[0063] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0064] Additionally, when it is described as being formed or disposed "above or below" each component, above or below includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or disposed between the two components.

[0065] Additionally, when expressed as “upper or lower,” it can include the meaning of not only the upward direction but also the downward direction based on one component.

[0066]

[0067] Hereinafter, a flexible circuit board, a COF module, and an electronic device including the same according to a first embodiment will be described with reference to the drawings.

[0068] Referring to FIGS. 1 to 8, a flexible circuit board (1000) according to an embodiment includes a substrate, a circuit pattern, an adhesive layer, and a protective layer.

[0069] The above description may include multiple descriptions. For example, the description may include a first description (110) and a second description (120).

[0070] The first substrate (110) may be disposed on the second substrate (120). The circuit pattern and the protective layer may be disposed on the first substrate (110) and the second substrate (120). In addition, the adhesive layer is disposed between the first substrate (110) and the second substrate (120). The first substrate (110) and the second substrate (120) are adhered by the adhesive layer. The first substrate (110) and the second substrate (120) may have the same or similar areas.

[0071] The first substrate (110) includes one side (1-1S) and another side (1-2S) opposite to the one side (1-1S). The other side (1-2S) is a side facing the second substrate (120). The second substrate (120) includes one side (2-1S) and another side (2-2S) opposite to the one side (2-1S). The one side (2-1S) is a side facing the first substrate (110).

[0072] The first substrate (110) and the second substrate (120) may include cutting lines. The first substrate (110) may include a first cutting line (CL1). The second substrate (1200) may include a second cutting line (CL2). The first cutting line (CL1) and the second cutting line (CL2) overlap in the thickness direction of the flexible circuit board (1000).

[0073] The flexible circuit board (1000) is cut along the cutting lines (CL1, CL2). Accordingly, the end of the substrate is determined by the cutting lines (CL1, CL2). Specifically, the substrate (110, 120) includes cutting lines (CL1, CL2) arranged on the inner side of the end of the substrate before the flexible circuit board is cut. In addition, after the flexible circuit board is cut, the substrate (110, 120) includes an end determined by the cutting lines (CL1, CL2).

[0074] For example, after the circuit pattern, the protective layer, and the chip are placed on the substrate (110, 120), the substrate (110, 120) can be cut along the cutting lines (CL1, CL2). Accordingly, the flexible circuit board (1000) can be manufactured into a COF module (2000).

[0075]

[0076] The above-described substrate (110, 120) includes an effective area (AA) and an ineffective area (UA). The effective area (AA) and the ineffective area (UA) are separated by the cutting lines (CL1, CL2). Specifically, the effective area (AA) is defined as an inner area of ​​the cutting lines (CL1, CL2). In addition, the ineffective area (UA) is defined as an outer area of ​​the cutting lines (CL1, CL2).

[0077] The circuit pattern, the protective layer, and the chip are arranged in the effective area (AA). In addition, a dummy pattern and a sprocket hole (SH) are arranged in the ineffective area (UA). The dummy pattern can increase the strength of the substrate (100). This can prevent the flexible circuit board (1000) from bending. In addition, the flexible circuit board (1000) can be rolled or unrolled in a roll-to-roll manner by the sprocket hole (SH).

[0078] The first substrate (110) includes a chip mounting area (CHA). The chip mounting area (CHA) is disposed on the one surface (1-1S). The chip mounting area (CHA) is disposed on the effective area (AA). A chip is disposed in the chip mounting area (CHA). In addition, the pad portions of the circuit pattern extend into the interior of the chip mounting area (CHA). In addition, the protective layer is not disposed on the chip mounting area (CHA).

[0079] The substrate (110, 120) may include a flexible material. For example, the substrate (110, 120) may include polyimide (PI). However, the embodiment is not limited thereto. The substrate (110, 120) may include a polymer material including polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). Accordingly, the flexible circuit board may be used in various electronic devices, including curved display devices. For example, the flexible circuit board may mount a semiconductor chip of a wearable electronic device.

[0080] The first substrate (110) and the second substrate (120) may contain the same material.

[0081] Alternatively, the first substrate (110) and the second substrate (120) may have identical or similar physical properties. For example, the first substrate (110) and the second substrate (120) may include materials having identical or similar coefficients of thermal expansion. Accordingly, the flexible circuit board can be prevented from warping due to differences in coefficients of thermal expansion.

[0082] Alternatively, the first substrate (110) and the second substrate (120) may include materials having the same or similar dielectric properties (Dk, Df). Accordingly, the difference in dielectric properties of the flexible circuit board is reduced, so that signal loss of the flexible circuit board can be reduced.

[0083] The substrate (110, 120) may have a thickness within a set range. The thickness (T1) of the substrate (110, 120) may be 15 µm to 40 µm, 17 µm to 38 µm, or 20 µm to 35 µm. If the thickness of the substrate (110, 120) exceeds 40 µm, the thickness of the flexible circuit board may increase. This may reduce the flexible characteristics of the flexible circuit board. In addition, if the thickness of the substrate (110, 120) is less than 15 µm, the substrate (110, 120) may be damaged. Specifically, when the chip or circuit pattern is placed on the flexible circuit board, the substrate (110, 120) may be damaged by heat and pressure transmitted to the substrate.

[0084] The first substrate (110) and the second substrate (120) may have the same or similar thickness. Accordingly, substrates having the same area may be placed above and below the adhesive layer. Accordingly, the stress difference between the upper and lower portions of the flexible circuit board may be reduced. Accordingly, the flexible circuit board may be prevented from bending due to stress.

[0085] The adhesive layer (400) may be disposed on the second substrate (120). Specifically, the adhesive layer (400) may be disposed between the first substrate (110) and the second substrate (120). The first substrate (110) and the second substrate (120) may be adhered by the adhesive layer (400).

[0086] The above adhesive layer (400) may include a resin material. For example, the above adhesive layer (400) may include at least one of an epoxy resin, an acrylic resin, and a silicone resin.

[0087] The thickness (T2) of the adhesive layer and the thickness (T1) of the substrate may be different. Specifically, the thickness (T2) of the adhesive layer may be smaller than the thickness (T1) of the substrate. In addition, the thickness (T2) of the adhesive layer and the thickness (T3) of the circuit pattern may be different. Specifically, the thickness (T2) of the adhesive layer may be larger than the thickness (T3) of the circuit pattern.

[0088] The adhesive layer (400) may have a thickness within a set range. The thickness (T2) of the adhesive layer may be 20 μm or less. Specifically, the thickness (T2) of the adhesive layer may be 10 μm to 20 μm, 12 μm to 18 μm, or 14 μm to 16 μm. If the thickness (T2) of the adhesive layer exceeds 20 μm, the thickness of the flexible circuit board may increase. As a result, the flexible characteristics of the flexible circuit board may decrease. In addition, if the thickness of the adhesive layer (400) is less than 10 μm, the adhesive strength of the adhesive layer (400) may decrease. As a result, the adhesive characteristics of the first substrate (110) and the second substrate (120) may decrease.

[0089] The circuit pattern and the protective layer are disposed on the substrate (110, 120). In detail, the circuit pattern and the protective layer are disposed on the effective area (AA) and the non-effective area (UA).

[0090] The circuit pattern may include a first circuit pattern, a second circuit pattern, a third circuit pattern, and a fourth circuit pattern. In addition, the protective layer may include a first protective layer (310) and a second protective layer (320).

[0091] Referring to FIGS. 1 to 7, the first circuit pattern is disposed on the first substrate (110). The first circuit pattern includes a 1-1 circuit pattern and a 1-2 circuit pattern. The 1-1 circuit pattern is disposed on the first surface (1-1S). The 1-2 circuit pattern is disposed on the first surface (1-1S) and the other surface (1-2S).

[0092] The above 1-1 circuit pattern includes a 1-1 wiring portion (211a), a 1-1a pad portion (211b), and a 1-1b pad portion (211c). The 1-1 wiring portion (211a), the 1-1a pad portion (211b), and the 1-1b pad portion (211c) may include the same material. In addition, the 1-1 wiring portion (211a), the 1-1a pad portion (211b), and the 1-1b pad portion (211c) may be formed integrally.

[0093] The above 1-1a pad portion (211b) is positioned within the chip mounting area (CHA). Accordingly, the 1-1a pad portion (211b) is connected to the terminal of the chip. As a result, the 1-1 circuit pattern and the chip are connected.

[0094] The above 1-1b pad portion (211c) is positioned outside the chip mounting area (CHA). The 1-1b pad portion (211c) is connected to a terminal of an external circuit board. As a result, the 1-1 circuit pattern and the circuit board are connected.

[0095] The above-mentioned 1-1b pad portion (211c) may include a first test pad portion (TP1). That is, the above-mentioned 1-1b pad portion (211c) may be a first test pad portion. In detail, the first circuit pattern may be tested before connecting the circuit board and the above-mentioned 1-1b pad portion (211c). For example, whether the above-mentioned 1-1b pad portion (211c) is open or short-circuited may be checked.

[0096] The above-mentioned 1-1 wiring portion (211a) is arranged between the 1-1a pad portion (211b) and the 1-1b pad portion (211c). That is, the 1-1 wiring portion (211a) connects the 1-1a pad portion (211b) and the 1-1b pad portion (211c). Accordingly, the chip and the circuit board are connected. Accordingly, a signal generated from the chip is transmitted to the circuit board.

[0097] The first protective layer (310) is disposed on the above 1-1 circuit pattern. In detail, the first protective layer (310) is disposed on an area excluding the 1-1a pad portion (211b) and the 1-1b pad portion (211c).

[0098]

[0099] The above 1-2 circuit pattern includes a 1-2 wiring portion (212a), a 1-2a pad portion (212b), and a 1-2b pad portion (212c). The 1-2 wiring portion (212a), the 1-2a pad portion (212b), and the 1-2b pad portion (212c) may include the same material.

[0100] The above 1-2a pad portion (212b) is arranged on the surface (1-1S). The 1-2a pad portion (212b) is arranged within the chip mounting area (CHA). Accordingly, the 1-2a pad portion (212b) is connected to the terminal of the chip. As a result, the 1-2 circuit pattern and the chip are connected.

[0101] The above 1-2b pad portion (212c) is arranged on the surface (1-1S). The 1-2b pad portion (212c) is arranged outside the chip mounting area (CHA). The 1-2b pad portion (212c) is connected to a terminal of an external circuit board. As a result, the 1-2 circuit pattern and the circuit board are connected.

[0102] The above 1-2b pad portion (212c) may include a first test pad portion (TP1). That is, the 1-2b pad portion (212c) may be a first test pad portion. In detail, the first circuit pattern may be tested before connecting the circuit board and the 1-2b pad portion (212c). For example, whether the first circuit pattern is open or shorted can be checked by the 1-2b pad portion (212c).

[0103]

[0104] The above 1-2 wiring portion (212a) is arranged on the other surface (1-2S). The above 1-2 circuit pattern includes a first via. The first via includes a 1a via (V1a) and a 1b via (V1v). The 1a via (V1a) and the 1b via (V1b) are formed by penetrating the first substrate (110).

[0105] Referring to Fig. 6, the 1-2 wiring portion (212a) is connected to the 1-2a pad portion (212b) via the 1a via (V1a). Referring to Fig. 7, the 1-2 wiring portion (212a) is connected to the 1-2b pad portion (212c) via the 1b via (V1b). Accordingly, the chip and the circuit board are connected. Accordingly, a signal generated from the chip is transmitted to the circuit board.

[0106]

[0107] Referring to FIGS. 1 to 4, 8 and 9, the second circuit pattern may be disposed on the first substrate (110) and the second substrate (120). The second circuit pattern includes a 2-1 circuit pattern and a 2-2 circuit pattern. The 2-1 circuit pattern is disposed on one surface (1-1S) of the first substrate and the other surface (2-2S) of the second substrate. The 2-2 circuit pattern is disposed on the other surface (1-2S) of the first substrate and the other surface (2-2S) of the second substrate.

[0108] The above 2-1 circuit pattern includes a 2-1 wiring portion (221a), a 2-1a pad portion (221b), and a 2-1b pad portion (221c). The 2-1 wiring portion (221a), the 2-1a pad portion (221b), and the 2-1b pad portion (221c) may include the same material.

[0109] The above 2-1a pad portion (221b) is arranged on the surface (1-1S). The 2-1a pad portion (221b) is arranged within the chip mounting area (CHA). Accordingly, the 2-1a pad portion (221b) is connected to the terminal of the chip. As a result, the 2-1 circuit pattern and the chip are connected.

[0110] The above-mentioned 2-1b pad portion (221c) is placed on the surface (2-2S). The above-mentioned 2-1b pad portion (221c) is connected to a terminal of an external display panel. Thus, the second circuit pattern and the display panel are connected.

[0111] The above 2-1 wiring portion (221a) is arranged on the first substrate (110) and the second substrate (120). In detail, the above 2-1 wiring portion (221a) is arranged on the one side (1-1S) and the other side (2-2S).

[0112] The above 2-1 circuit pattern includes a 2a via (V2a). The 2-1 wiring portion (221a) of the first substrate (110) and the 2-1b pad portion (221c) of the second substrate (120) are connected through the 2a via (V2a).

[0113] Accordingly, the 2-1a pad portion (221b) and the 2-1b pad portion (221c) are connected by the 2-1 wiring portion (221a). Accordingly, the chip and the display panel can be connected. Accordingly, a signal generated from the chip can be transmitted to the display panel.

[0114] The first protective layer (310) and the second protective layer (320) may be disposed on the 2-1 circuit pattern. Specifically, the first protective layer (310) is disposed on the one surface (1-1S). More specifically, the first protective layer (310) is disposed on the 2-1 wiring portion (221a). In addition, the second protective layer (320) is disposed on the other surface (2-2S). More specifically, the second protective layer (320) is disposed on the 2-1 wiring portion (221a). The first protective layer (310) and the second protective layer (320) may be disposed on an area excluding the 2-1a pad portion (221b) and the 2-1b pad portion (221c).

[0115] The above 2-1 circuit pattern may include a second test pad portion (TP2). The second test pad portion (TP2) may be disposed on the other surface (2-2S). The second test pad portion (TP2) may be disposed in the non-effective area (UA). In addition, a second protective layer (320) is not disposed on the second test pad portion (TP2). The second test pad portion (TP2) may be connected to the 2-1 wiring portion (221a) of the other surface (2-2S). In detail, the second test pad portion (TP2) may be formed integrally with the 2-1 wiring portion (221a) of the other surface (2-2S).

[0116] The second circuit pattern can be tested before connecting the display panel and the second-1b pad portion (221c). For example, whether the second-1 circuit pattern is open or shorted can be checked through the second test pad portion (TP2).

[0117]

[0118] The above 2-2 circuit pattern includes a 2-2 wiring portion (222a), a 2-2a pad portion (222b), and a 2-2b pad portion (222c). The 2-2 wiring portion (222a), the 2-2a pad portion (222b), and the 2-2b pad portion (222c) may include the same material.

[0119] The above-mentioned 2-2a pad portion (222b) is arranged on the above-mentioned surface (1-1S). The above-mentioned 2-2a pad portion (222b) is arranged inside the above-mentioned chip mounting area (CHA). Accordingly, the above-mentioned 2-2a pad portion (222b) is connected to the terminal of the above-mentioned chip. As a result, the above-mentioned 2-2 circuit pattern and the above-mentioned chip are connected.

[0120] The above-mentioned 2-2b pad portion (222c) is placed on the surface (2-2S). The above-mentioned 2-2b pad portion (222c) is connected to a terminal of an external display panel. Thus, the second circuit pattern and the display panel are connected.

[0121] The above 2-2 wiring portion (222a) is arranged on the above 1st substrate (110). In detail, the above 2-2 wiring portion (222a) is arranged on the other surface (2-2S).

[0122] The above 2-2 circuit pattern includes a 2b via (V2b) and a 2c via (V2C). The 2-2 wiring portion (222a) is connected to the 2-2a pad portion (222b) by the 2b via (V2b). The 2-2 wiring portion (222a) is connected to the 2-2b pad portion (222c) by the 2c via (V2c). Accordingly, the chip and the display panel can be connected. Accordingly, a signal generated in the chip can be transmitted to the display panel.

[0123]

[0124] Referring to Fig. 8, the second a via (V2a) penetrates the first substrate (110), the adhesive layer (400), and the second substrate (120). Referring to Fig. 9, the second b via (V2b) penetrates the adhesive layer (400) and the second substrate (120).

[0125] The size of the above-mentioned second a via (V2a) may vary from the first substrate (110) toward the second substrate (120). The above-mentioned second a via (V2a) may be divided into a second a1 via portion (V2a1), a second a2 via portion (V2a2), and a second a3 via portion (V2a3).

[0126] The above-mentioned second a1 via portion (V2a1) penetrates the adhesive layer (400). The above-mentioned second a2 via portion (V2a2) penetrates the first substrate (110). The above-mentioned second a3 via portion (V2a3) penetrates the second substrate (120).

[0127] The above-described second a1 via portion (V2a1) has a first width (W1). Specifically, the first width (W1) is a maximum width of the second a1 via portion (V2a1). The width of the second a1 via portion (V2a1) may be greater in a central region than in an upper region or a lower region. Specifically, the width of the second a1 via portion (V2a1) may be greatest in a central region or a region adjacent to the central region. In addition, the width of the second a1 via portion (V2a1) may increase while extending from the upper region to the central region. In addition, the width of the second a1 via portion (V2a1) may decrease while extending from the central region to the lower region.

[0128] The above-described second a2 via portion (V2a2) has a second width (W2) and a third width (W3). The second width (W2) is the maximum width of the second a2 via portion (V2a2), and the third width (W3) is the minimum width of the second a2 via portion (V2a2). The width of the second a2 via portion (V2a2) becomes smaller as it extends downward. That is, the width of the second a2 via portion (V2a2) becomes smaller as it extends toward the adhesive layer (400). That is, the width of the second a2 via portion (V2a2) is largest in an upper region and smallest in a lower region.

[0129] The above-described second a3 via portion (V2a3) has a fourth width (W4) and a fifth width (W5). The fourth width (W4) is the maximum width of the second a3 via portion (V2a3), and the fifth width (W5) is the minimum width of the second a3 via portion (V2a3). The width of the second a3 via portion (V2a3) becomes smaller as it extends downward. That is, the width of the second a3 via portion (V2a3) becomes smaller as it extends toward the second protective layer (320). That is, the width of the second a3 via portion (V2a3) is largest in an upper region and smallest in a lower region.

[0130] The first width (W1) may be greater than at least one of the second width (W2) and the third width (W3). For example, the first width (W1) may be greater than the second width (W2) and the third width (W3). Alternatively, the first width (W1) may be greater than the third width (W3). That is, the first width (W1) may be greater than the short width of the second a2 via portion (V2a2). In addition, the first width (W1) may be equal to or different from the long width of the second a2 via portion (V2a2).

[0131] Additionally, the first width (W1) may be greater than the fourth width (W4) and the fifth width (W5). That is, the first width (W1) may be greater than the short width and long width of the second a3 via portion (V2a3).

[0132] Accordingly, the width of the second a via (V2a) may sequentially decrease, increase, and decrease while extending from the first substrate (110) toward the second substrate (120). That is, it may decrease in the second a2 via portion (V2a2), increase in the second a1 via portion (V2a1), and decrease in the second a3 via portion (V2a3).

[0133] Accordingly, the de-filming of the second a via (V2a) can be prevented. The second a1 via portion (V2a1) is arranged in the central region of the second a via (V2a). Therefore, the contact area of ​​the second a via (V2a) with the adhesive layer (400) in the central portion increases. Accordingly, since the second a via (V2a) is fixed by the adhesive layer (400) in the central portion of the second a via (V2a), the adhesion of the second a via (V2a) can be improved.

[0134] In addition, since the area of ​​the second a via (V2a) increases, the heat dissipation characteristics of the flexible circuit board increase. Accordingly, heat generation of the COF module during operation can be reduced.

[0135] Accordingly, the second a via (V2a) may be provided with a plurality of different slopes having a width that changes in the horizontal direction. For example, the second a via (V2a) may include a plurality of first slopes in which the width in the horizontal direction gradually decreases in the direction from the upper surface to the lower surface, and may include a second slope different from the first slope between the plurality of first slopes. In this case, the second slope may be a slope in which the width in the horizontal direction increases and then decreases. The second slope may be a curve having a specific curvature.

[0136] The size of the above-mentioned second c via (V2c) may vary from the first substrate (110) toward the second substrate (120). The above-mentioned second c via (V2c) may be divided into a second c1 via portion (V2c1) and a second c2 via portion (V2c2).

[0137] The above-mentioned second c1 via portion (V2c1) penetrates the adhesive layer (400). The above-mentioned second C2 via portion (V2c2) penetrates the second substrate (120).

[0138] The above-mentioned second c1 via portion (V2c1) has a first width (W1'). In detail, the first width (W1') is the maximum width of the above-mentioned second c1 via portion (V2b1).

[0139] The above-described second c2 via portion (V2c2) has a second width (W2') and a third width (W3'). The second width (W2') is the maximum width of the second c2 via portion (V2c2), and the third width (W3') is the minimum width of the second c2 via portion (V2c2). The width of the second c2 via portion (V2c2) increases as it extends downward. That is, the width of the second c2 via portion (V2c2) increases as it extends toward the second protective layer (320).

[0140] The first 'width (W1') may be greater than at least one of the second 'width (W2') and the third 'width (W3'). For example, the first 'width (W1') may be greater than the second 'width (W2') and the third 'width (W3'). Alternatively, the first 'width (W1') may be greater than the third 'width (W3'). That is, the first 'width (W1') may be greater than the short width of the second c2 via portion (V2c2). In addition, the first 'width (W1') may be the same as or different from the long width of the second c2 via portion (V2c2).

[0141] Accordingly, the width of the second c via (V2c) can be sequentially decreased and increased while extending from the second substrate (120) toward the first substrate (110). That is, it can decrease in the second c2 via portion (V2c2) and increase in the second c1 via portion (V2c1).

[0142] Accordingly, the de-filming of the second c via (V2c) can be prevented. The second c via (V2c) has an increased contact area with the adhesive layer (400). Accordingly, since the second c via (V2c) is fixed by the adhesive layer (400), the adhesion of the second c via (V2c) can be improved.

[0143] In addition, since the area of ​​the second c via (V2c) increases, the heat dissipation characteristics of the flexible circuit board increase. Accordingly, heat generation of the COF module during operation can be reduced.

[0144]

[0145] Referring to FIG. 8, the second a via (V2a) may contact the circuit pattern in various ways. For example, the second a via (V2a) may contact the side surface of the second-first wiring portion (221a). Alternatively, referring to the enlarged view (a) of FIG. 8, the second a via (V2a) may contact the side surface and the upper surface of the second-first wiring portion (221a). In addition, the upper surface of the second a via (V2a) may be concave. Alternatively, referring to the enlarged view (b) of FIG. 8, the second a via (V2a) may contact the side surface and the upper surface of the second-first wiring portion (221a). In addition, the upper surface of the second a via (V2a) may be convex.

[0146] The above second c via (V2c) can also contact the circuit pattern similarly to the above second a via (V2a).

[0147]

[0148] Referring to FIGS. 1 to 4, 10 and 11, the third circuit pattern may be disposed on the first substrate (110) and the second substrate (120). The third circuit pattern includes a 3-1 circuit pattern and a 3-2 circuit pattern. The 3-1 circuit pattern and the 3-2 circuit pattern are disposed on the first substrate (110) and the second substrate (120).

[0149] The above 3-1 circuit pattern includes a 3-1 wiring portion (231a), a 3-1a pad portion (231b), and a 3-1b pad portion (231c). The 3-1 wiring portion (231a), the 3-1a pad portion (231b), and the 3-1b pad portion (231c) may include the same material.

[0150] The above 3-1a pad portion (231b) is disposed on the first substrate (110). The 3-1a pad portion (231b) is disposed on the one surface (1-1S). The 3-1a pad portion (231b) is disposed within the chip mounting area (CHA). Accordingly, the 3-1a pad portion (231b) is connected to the terminal of the chip. As a result, the 3-1 circuit pattern and the chip are connected.

[0151] The above 3-1b pad portion (231c) is placed on the second substrate (120). The above 3-1b pad portion (231c) is placed on the other surface (2-2S). The above 3-1b pad portion (231c) is connected to a terminal of an external display panel. Thus, the above 3-1 circuit pattern and the above display panel are connected.

[0152] The above 3-1 wiring portion (231a) is arranged on the above 2nd substrate (120). In detail, the above 3-1 wiring portion (231a) is arranged on the above one surface (2-1S).

[0153] The above 3-1 circuit pattern includes a 3a via (V3a), a 3b via (V3b), and a 3c via (V3c). Referring to FIG. 10, the 3-1 wiring portion (231a) is connected to the 3-1a pad portion (231b) through the 3a via (V3a). The 3a via (V3a) penetrates the first substrate (110) and the adhesive layer (400). Accordingly, the shape of the 3a via (V3a) may be similar to the shape of the 2c via (V2c).

[0154] In addition, the 3-1 wiring portion (231a) is connected to the 3-1b pad portion (231c) through the 3b via (V3b). The 3b via (V3b) is formed by penetrating the second substrate (120). Accordingly, the chip and the display panel can be connected. Accordingly, a signal generated from the chip can be transmitted to the display panel.

[0155] The above 3-1 circuit pattern may include a 3-1 test pad portion (TP3-1). The 3-1 test pad portion (TP3-1) may be disposed on the other surface (2-2S). The 3-1 test pad portion (TP3-1) may be disposed in the unactive area (UA). In addition, a second protective layer (320) is not disposed on the 3-1 test pad portion (TP3-1). The 3-1 test pad portion (TP3-1) may be connected to the 3-1 wiring portion (231a) on the one surface (2-1S). In detail, the 3-1 test pad portion (TP3-1) may be connected to the 3-1 wiring portion (231a) through the 3c via (V3c).

[0156] The third circuit pattern can be tested before connecting the display panel and the third-1b pad portion (231c). For example, whether the third-1 circuit pattern is open or shorted can be checked through the third-1 test pad portion (TP3-1).

[0157]

[0158] The above 3-2 circuit pattern includes a 3-2 wiring portion (232a), a 3-2a pad portion (233b), and a 3-2b pad portion (232c). The 3-2 wiring portion (232a), the 3-2a pad portion (232b), and the 3-2b pad portion (232c) may include the same material.

[0159] The above 3-2a pad portion (232b) is disposed on the first substrate (110). The 3-2a pad portion (232b) is disposed on the one surface (1-1S). The 3-2a pad portion (232b) is disposed within the chip mounting area (CHA). Accordingly, the 3-2a pad portion (232b) is connected to the terminal of the chip. As a result, the 3-2 circuit pattern and the chip are connected.

[0160] The above 3-2b pad portion (232c) is placed on the second substrate (120). The above 3-2b pad portion (232c) is placed on the other surface (2-2S). The above 3-2b pad portion (232c) is connected to a terminal of an external display panel. Thus, the above 3-2 circuit pattern and the above display panel are connected.

[0161] The above 3-2 wiring portion (232a) is arranged on the second substrate (120). In detail, the above 3-2 wiring portion (232a) is arranged on the other surface (2-2S).

[0162] The above 3-2 circuit pattern includes a 3d via (V3d). Referring to FIG. 11, the 3-2 wiring portion (232a) is connected to the 3-2a pad portion (232b) via the 3d via (V3d). In addition, the 3-2 wiring portion (232a) and the 3-2b pad portion (232c) are connected on the other surface (2-2S). Accordingly, the chip and the display panel can be connected. Accordingly, a signal generated from the chip can be transmitted to the display panel.

[0163] The size of the above 3d via (V3d) may vary from the first substrate (110) toward the second substrate (120). The above 3d via (V3d) may be divided into a 3d1 via portion (V3d1), a 3d2 via portion (V3d2), and a 3d3 via portion (V3d3).

[0164] The above 3d1 via portion (V3d1) penetrates the adhesive layer (400). The above 3d2 via portion (V3d2) penetrates the first substrate (110). The above 3d3 via portion (V3d3) penetrates the second substrate (120).

[0165] The above-mentioned third d1 via portion (V3d1) has a first width (W1). In detail, the first width (W1) is the maximum width of the above-mentioned third d1 via portion (V3d1).

[0166] The above-described third d2 via portion (V3d2) has a second width (W2'') and a third width (W3''). The second width (W2'') is the maximum width of the third d2 via portion (V3d2), and the third width (W3'') is the minimum width of the third d2 via portion (V3d2). The width of the third d2 via portion (V3d2) decreases as it extends downward. That is, the width of the third d2 via portion (V3d2) decreases as it extends toward the adhesive layer (400).

[0167] The above-described third d3 via portion (V3d3) has a fourth width (W4'') and a fifth width (W5''). The fourth width (W4'') is the maximum width of the third d3 via portion (V3d3), and the fifth width (W5'') is the minimum width of the third d3 via portion (V3d3). The width of the third d3 via portion (V3d3) decreases as it extends downward. That is, the width of the third d3 via portion (V3d3) decreases as it extends toward the second protective layer (320).

[0168] The first width (W1) may be greater than at least one of the second width (W2) and the third width (W3). For example, the first width (W1) may be greater than the second width (W2) and the third width (W3). Alternatively, the first width (W1) may be greater than the third width (W3). That is, the first width (W1) may be greater than the short width of the third d2 via portion (V3d2). In addition, the first width (W1) may be equal to or different from the long width of the third d2 via portion (V3d2).

[0169] In addition, the first width (W1'') may be greater than the fourth width (W4'') and the fifth width (W5''). That is, the first width (W1'') may be greater than the short width and the long width of the third d3 via portion (V3d3).

[0170] Accordingly, the width of the 3d via (V3d) may sequentially decrease, increase, and decrease while extending from the first substrate (110) toward the second substrate (120). That is, it may decrease in the 3d2 via portion (V3d2), increase in the 3d1 via portion (V3d1), and decrease in the 3d3 via portion (V3d3).

[0171] Accordingly, the de-filming of the 3d via (V3d) can be prevented. The 3d1 via portion (V3d1) is arranged in the central region of the 3d via (V3d). Therefore, the contact area of ​​the 3d via (V3d) with the adhesive layer (400) in the central portion increases. Accordingly, since the 3d via (V3d) is fixed by the adhesive layer (400) in the central portion of the 3d via (V3d), the adhesion of the 3d via (V3d) can be improved.

[0172] In addition, since the area of ​​the third d via (V3d) increases, the heat dissipation characteristics of the flexible circuit board increase. Accordingly, heat generation of the COF module during operation can be reduced.

[0173] The second protective layer (320) may be disposed on the above 3-2 circuit pattern. Specifically, the second protective layer (320) is disposed on the other surface (2-2S). More specifically, the second protective layer (320) is disposed on the 3-2 wiring portion (232a). The second protective layer (320) may be disposed on an area excluding the 3-2b pad portion (232c).

[0174] The above 3-2 circuit pattern may include a 3-2 test pad portion (TP3-2). The 3-2 test pad portion (TP3-2) may be disposed on the other surface (2-2S). The 3-2 test pad portion (TP3-2) may be disposed in the non-effective area (UA). In addition, a second protective layer (320) is not disposed on the 3-2 test pad portion (TP2). The 3-2 test pad portion (TP2) may be connected to the 3-2 wiring portion (232a). In detail, the 3-2 test pad portion (TP3-2) may be formed integrally with the 3-2 wiring portion (232a).

[0175] The above 3-2 circuit pattern can be tested before connecting the display panel and the 3-2b pad portion (232c). For example, whether the 3-2 circuit pattern is open or shorted can be checked through the 3-2 test pad portion (TP2).

[0176]

[0177] Referring to FIGS. 1 to 4, the fourth circuit pattern (240) may be arranged on the first substrate (110) and the second substrate (120). The fourth circuit pattern may be arranged on the one side (1-1S) and the other side (2-2S). The fourth circuit patterns on the one side (1-1S) and the other side (2-2S) are connected through a fourth via (V4).

[0178] The fourth circuit pattern (240) is not connected to the chip. The fourth circuit pattern may be a power supply pattern. Accordingly, the fourth circuit pattern (240) may be connected to the circuit board and the display panel.

[0179] Additionally, the fourth circuit pattern (240) may be placed in an edge area of ​​the flexible circuit board.

[0180]

[0181] Figures 12 and 13 are drawings for explaining the layer structure of a circuit pattern. Figures 12 and 13 are cross-sectional views taken along the H'-H region of the first substrate.

[0182] For convenience of explanation, the first circuit pattern is described as an example. The following description applies equally to the second to fourth circuit patterns.

[0183] Referring to Fig. 12, the first circuit pattern is formed in multiple layers. In detail, the 1-1 wiring portion (211a), the 1-1a pad portion (211b), and the 1-1b pad portion (211c) include a buffer layer (205), a metal layer (201), and a bonding layer (203).

[0184] The buffer layer (205) may include multiple layers. Specifically, the buffer layer (205) includes a first buffer layer (205a) and a second buffer layer (205b). The first buffer layer (205a) is disposed on the first substrate (110). The second buffer layer (205b) is disposed on the first buffer layer (205a).

[0185] The first buffer layer (205a) includes a material having good adhesion to the first substrate (110). For example, the first buffer layer (205a) may include nickel (Ni). In addition, the second buffer layer (205b) includes a material having good adhesion to the first circuit pattern. For example, the second buffer layer (205b) may include chromium (Cr).

[0186] The above buffer layer (205) may have a thin film thickness in nanometer units. For example, the above buffer layer (205) may have a thickness of 20 nm or less.

[0187] The adhesion between the first substrate (110) and the first circuit pattern is improved by the buffer layer (205).

[0188] The metal layer (201) is disposed on the buffer layer (205). Specifically, the metal layer (201) is disposed on the second buffer layer (205b). The metal layer (201) includes a metal material. For example, the metal layer (201) may include copper (Cu).

[0189] The above metal layer (201) can be formed by electroplating using the buffer layer as a seed layer. That is, the above metal layer (201) can be a plating layer.

[0190] The thickness of the above metal layer (201) may be 10 µm to 30 µm.

[0191] The above bonding layer (203) is placed on the above metal layer (201).

[0192] The above bonding layer (203) is arranged on the side and upper surface of the metal layer (201). For example, the bonding layer (203) may be arranged to surround the metal layer (201).

[0193] The above bonding layer (203) includes a metal. For example, the above bonding layer (203) may include tin (Sn).

[0194] The thickness of the above bonding layer (203) may be 0.3 µm to 0.7 µm. The tin content may increase as it extends from the lower surface to the upper surface of the above bonding layer (203).

[0195] That is, the bonding layer (203) is in contact with the metal layer (201). Therefore, the tin content increases from the lower surface of the bonding layer (203) toward the upper surface. In addition, the copper content decreases from the lower surface of the bonding layer (203) toward the upper surface.

[0196] Accordingly, pure tin may remain in a thickness range of 0.1 µm to 0.3 µm from the upper surface of the bonding layer (203).

[0197] The pad portion can be easily bonded to the terminals of the chip, the circuit board, and the display panel by the bonding layer (203). For example, when heat and pressure are applied to the pad portion, the upper surface of the bonding layer melts. Pure tin remains on the upper surface of the bonding layer. Therefore, the pad portion can be easily bonded to the terminals of the chip, the circuit board, and the display panel.

[0198]

[0199] Referring to Fig. 13, the metal layer (201) may include a first metal layer (201a) and a second metal layer (201b). The first metal layer (201a) is disposed on the buffer layer (205). The second metal layer (201b) is disposed on the first metal layer (201a).

[0200] The thickness of the first metal layer (201a) may be smaller than the thickness of the second metal layer (201b).

[0201] For example, the thickness of the first metal layer (201a) may be 0.7 µm to 2 µm, and the thickness of the second metal layer (201b) may be 10 µm to 25 µm.

[0202] The first metal layer (201a) and the second metal layer (201b) may include the same metal material. For example, the first metal layer (201a) and the second metal layer (201b) may include copper (Cu).

[0203] The first metal layer (201a) and the second metal layer (201b) can be formed through a plating process. For example, the first metal layer (201a) is formed thinly on the buffer layer (205). Subsequently, the second metal layer (201b) can be formed using the first metal layer (201a) as a seed layer.

[0204] Additionally, the bonding layer (203) may include a first bonding layer (203a) and a second bonding layer (203b).

[0205] The first bonding layer (203a) is disposed on the metal layer (201). In detail, the first bonding layer (203a) is disposed on the first wiring portion (211), the first pad portion (212a), and the second pad portion (212b).

[0206] The second bonding layer (203b) is disposed on the first bonding layer (203a). In detail, the second bonding layer (203b) is disposed on the 1-1a pad portion (211b) and the 1-1b pad portion (211c).

[0207] Accordingly, the 1-1 wiring portion (211a) includes the buffer layer (205), the metal layer (201), and the first bonding layer (203a). In addition, the 1-1a pad portion (211b) and the 1-1b pad portion (211c) include the buffer layer (205), the metal layer (201), the first bonding layer (203a), and the second bonding layer (203b).

[0208] Accordingly, the layer structure of the 1-1 wiring section (211a) is different from the layer structures of the 1-1a pad section (211b) and the 1-1b pad section (211c).

[0209] The first bonding layer (203a) and the second bonding layer (203b) contain metal. In detail, the first bonding layer (203a) and the second bonding layer (203b) may contain tin (Sn).

[0210] The first bonding layer (203a) and the second bonding layer (203b) are arranged with different thicknesses. Specifically, the thickness of the second bonding layer (203b) is greater than the thickness of the first bonding layer (203a).

[0211] For example, the first bonding layer (203a) has a thickness of 0.02 μm to 0.06 μm. In addition, the second bonding layer (203b) has a thickness of 0.2 μm to 0.6 μm.

[0212] Accordingly, the thickness of the first-first wiring portion (211a) is reduced. Accordingly, when the flexible circuit board is bent, cracks in the first-first wiring portion (211a) can be prevented.

[0213] The thickness of the first circuit pattern may be 2 μm to 25 μm. Specifically, the thickness of the first circuit pattern may be 5 μm to 20 μm. Specifically, the thickness of the first circuit pattern may be 7 μm to 15 μm.

[0214] If the thickness of the first circuit pattern is less than 2 μm, the resistance of the first circuit pattern may increase. If the thickness of the first circuit pattern exceeds 25 μm, it becomes difficult to implement a fine pattern.

[0215] The above description describes that circuit patterns are arranged on both sides of the first substrate and both sides of the second substrate. However, the embodiment is not limited thereto.

[0216] Referring to Fig. 14, a flexible circuit board according to another embodiment has a circuit pattern arranged only on one side (1-1S) of the first substrate. In detail, no circuit pattern is arranged on the other side (1-2S).

[0217] That is, the flexible circuit board includes only the 1-1 circuit pattern and does not include the 1-2 circuit pattern.

[0218] Since the circuit pattern arranged in the above second description is the same, the following description is omitted.

[0219] Referring to FIGS. 15 to 17, a flexible circuit board according to another embodiment has a circuit pattern arranged only on the other side (2-2S) of the second substrate. In detail, no circuit pattern is arranged on the one side (2-1S).

[0220] That is, the flexible circuit board includes only the 2-2 circuit pattern and does not include the 2-1 circuit pattern.

[0221] According to an embodiment, a flexible circuit board can be formed by mounting a chip (CH) in the chip mounting area (CHA) and cutting along the cutting line (CL). As a result, a COF module is formed.

[0222] The above COF module (2000) is positioned between the display panel (4000) and the circuit board (3000) and can connect electrical signals.

[0223]

[0224] Below, a flexible circuit board according to the second embodiment is described.

[0225] FIG. 18 is a top view of a first layer of a flexible circuit board according to a second embodiment, FIG. 19 is a top view of a second layer of a flexible circuit board according to a second embodiment, FIG. 20 is a bottom view of a second layer of a flexible circuit board according to a second embodiment, FIG. 21 is a cross-sectional view taken along the AA' region of FIG. 18, FIG. 22 is a cross-sectional view taken along the BB' region of FIG. 18, FIG. 23 is a cross-sectional view taken along the CC' region of FIG. 18, FIG. 24 is a cross-sectional view taken along the DD' region of FIG. 18, FIG. 25 is a cross-sectional view taken along the EE' region of FIG. 20, FIG. 26 is a cross-sectional view taken along the FF' region of FIG. 20, FIGS. 27 and 28 are cross-sectional views taken along the G'G region of FIG. 18, and FIGS. 29 to 32 are cross-sectional views taken along the HH' region of FIG. 20. This is a cut cross-section.

[0226] Referring to FIGS. 18 to 25, a flexible circuit board (1000A) according to the second embodiment includes a substrate, a circuit pattern, an adhesive layer, and a protective layer. In the following description, a description of the same configuration as that of the flexible circuit board described with reference to FIGS. 1 to 17 is omitted.

[0227] The flexible circuit board (1000A) includes a first substrate (1110), a second substrate (1120), and an adhesive layer (1400).

[0228] In addition, the flexible circuit board (1000A) includes a circuit pattern and a protective layer. The circuit pattern may include a first circuit pattern (1210), a second circuit pattern (1220), a third circuit pattern (1230), a fourth circuit pattern (1240), and a fifth circuit pattern (1250). In addition, the protective layer may include a first protective layer (1310) and a second protective layer (1320).

[0229] Referring to FIG. 18 and FIG. 21, the first circuit pattern (1210) is disposed on the first substrate (1110). In detail, the first circuit pattern (1210) is disposed on the one side (1-1S).

[0230] The first circuit pattern (1210) may include a first wiring portion (1211), a first a pad portion (1212a), and a first b pad portion (1212b). The first wiring portion (1211), the first a pad portion (1212a), and the first b pad portion (1212b) may include the same material. In addition, the first wiring portion (1211), the first a pad portion (1212a), and the first b pad portion (1212b) may be formed integrally.

[0231] The first a pad portion (1212a) is positioned within the chip mounting area (CHA). Accordingly, the first a pad portion (1212a) is connected to the terminal of the chip. As a result, the first circuit pattern (1210) and the chip are connected.

[0232] In addition, the first b pad portion (1212b) is positioned outside the chip mounting area (CHA). The first b pad portion (1212b) is connected to a terminal of an external circuit board. As a result, the first circuit pattern (1210) and the circuit board are connected.

[0233] Meanwhile, the first b pad portion (1212b) may be a first test pad portion (TP1). In detail, the first circuit pattern (1210) may be tested before connecting the circuit board and the first b pad portion (1212b). For example, whether the first circuit pattern is open or shorted can be checked by the first b pad portion (1212b).

[0234] In addition, the first wiring portion (1211) is arranged between the first a pad portion (1212a) and the first b pad portion (1212b). That is, the first wiring portion (1211) connects the first a pad portion (1212a) and the first b pad portion (1212b). Accordingly, the chip and the circuit board are connected. Accordingly, a signal generated from the chip is transmitted to the circuit board.

[0235] The first protective layer (1310) is disposed on the first circuit pattern (1210). In detail, the first protective layer (1310) is disposed on an area excluding the first a pad portion (1212a) and the first b pad portion (1212b).

[0236] Referring to FIGS. 18, 20, and 22, the second circuit pattern (1220) can be disposed on the first substrate (1110) and the second substrate (1120). In detail, the second circuit pattern (1220) is disposed on one surface (1-1S) of the first substrate and the other surface (2-2S) of the second substrate.

[0237] The second circuit pattern (1220) may include a second wiring portion (1221a, 1221b), a second a pad portion (1222a), a second b pad portion (1222b), and a first connection portion (V1). The second wiring portion (1221a, 1221b), the second a pad portion (1222a), and the second b pad portion (1222b) may include the same material. In addition, the second wiring portion (1221a, 1221b), the second a pad portion (1222a), and the second b pad portion (1222b) may be formed integrally.

[0238] The second circuit pattern (1220) includes a plurality of circuit patterns. In addition, one second circuit pattern (1220) includes one first via (V1).

[0239] The second a pad portion (1222a) is positioned on the surface (1-1S). The second a pad portion (1222a) is positioned within the chip mounting area (CHA). Accordingly, the second a pad portion (1222a) is connected to the terminal of the chip. As a result, the second circuit pattern (1220) and the chip are connected.

[0240] In addition, the second b pad portion (1222b) is positioned on the other surface (2-2S). The second b pad portion (1222b) is connected to a terminal of an external display panel. As a result, the second circuit pattern (1220) and the display panel are connected.

[0241] The second wiring section includes a second a wiring section (1221a) and a second b wiring section (1221b). The second a wiring section (1221a) is disposed on the first surface (1-1S). In addition, the second b wiring section is disposed on the other surface (2-2S).

[0242] The second wiring portion connects the second a pad portion (1222a) and the second b pad portion (1222b). Specifically, the second a wiring portion (1221a) is connected to the second a pad portion (1222a). In addition, the second b wiring portion (1221b) is connected to the second b pad portion (1222b).

[0243] Accordingly, the chip and the display panel can be connected. Accordingly, a signal generated from the chip can be transmitted to the display panel.

[0244] The first protective layer (1310) and the second protective layer (1320) may be disposed on the second circuit pattern (1220). In detail, the first protective layer (1310) is disposed on the one surface (1-1S). In more detail, the first protective layer (1310) is disposed on the second circuit pattern (1220). In addition, the second protective layer (1320) is disposed on the other surface (2-2S). In more detail, the second protective layer (1320) is disposed on the second circuit pattern (1220). The first protective layer (1310) and the second protective layer (1320) may be disposed on an area excluding the 2a pad portion (1222a) and the 2b pad portion (1222b).

[0245] The second a wiring portion (1221a) and the second b wiring portion (1221b) are electrically connected. In detail, the second a wiring portion (1221a) and the second b wiring portion (1221b) are connected by the first via (V1). The first via (V1) is formed by penetrating the first substrate (1110), the adhesive layer (1400), and the second substrate (1120). Accordingly, the thickness of the first via (V1) is greater than the thickness of the substrates (1110, 1120). In addition, the thickness of the first via (V1) is greater than the thickness of the adhesive layer (1400).

[0246] The second circuit pattern (1220) may include a second test pad portion (TP2). The second test pad portion (TP2) may be disposed on the other surface (2-2S). The second test pad portion (TP2) may be disposed in the non-effective area (UA). In addition, a second protective layer (1320) is not disposed on the second test pad portion (TP2). The second test pad portion (TP2) may be connected to the secondb wiring portion (1221b). In detail, the second test pad portion (TP2) may be formed integrally with the secondb wiring portion (1221b).

[0247] The second circuit pattern (1220) can be tested before connecting the display panel and the second b pad portion (1222b). For example, whether the second circuit pattern is open or shorted can be checked through the second test pad portion (TP2).

[0248] Referring to FIGS. 18, 20, and 23, the third circuit pattern (1230) is disposed on the one surface (1-1S) and the other surface (2-2S). The third circuit pattern (1230) includes a third wiring portion (1231), a third a pad portion (1232a), a third b pad portion (1232b), and a second via (V2). The third wiring portion (1231), the third a pad portion (1232a), and the third b pad portion (1232b) may include the same material. In addition, the third wiring portion (1231), the third a pad portion (1232a), and the third b pad portion (1232b) may be formed integrally.

[0249] The third a pad portion (1232a) is positioned on the surface (1-1S). The third a pad portion (1232a) is positioned within the chip mounting area (CHA). Accordingly, the third a pad portion (1232a) is connected to the terminal of the chip. As a result, the third circuit pattern (1230) and the chip are connected.

[0250] In addition, the third b pad portion (1232b) is positioned on the other surface (2-2S). The third b pad portion (1232b) is connected to a terminal of an external display panel. Thus, the third circuit pattern (1230) and the display panel are connected.

[0251] In addition, the third wiring section (1231) is arranged on the other surface (2-2S). The third wiring section (1231) connects the third a pad section (1232a) and the third b pad section (1232b). Accordingly, the chip and the display panel are connected. Accordingly, a signal generated from the chip is transmitted to the display panel.

[0252] The second protective layer (1320) may be disposed on the third circuit pattern (1230). Specifically, the second protective layer (1320) is disposed on the other surface (2-2S). More specifically, the second protective layer (1320) is disposed on the third wiring portion (1231). The second protective layer (1320) may be disposed on an area excluding the third b pad portion (1232b).

[0253] The third a pad portion (1232a) and the third wiring portion (1231) are electrically connected. In detail, the third a pad portion (1232a) and the third wiring portion (1231) are connected by the second via (V2). The second via (V2) is formed by penetrating the first substrate (1110), the adhesive layer (1400), and the second substrate (1120). Accordingly, the thickness of the second via (V2) is greater than the thickness of the substrates (1110, 1120). In addition, the thickness of the second via (V2) is greater than the thickness of the adhesive layer (1400).

[0254] The third circuit pattern (1230) may include a third test pad portion (TP3). The third test pad portion (TP3) may be disposed on the second-second surface (2-2S). The third test pad portion (TP3) may be disposed in the unactive area (UA). In addition, a second protective layer (1320) is not disposed on the third test pad portion (TP3). The third test pad portion (TP3) may be connected to the third wiring portion (1231). In detail, the third test pad portion (TP3) may be formed integrally with the third wiring portion (1231).

[0255] The third circuit pattern (1230) can be tested before connecting the display panel and the third b pad portion (1232b). For example, whether the third circuit pattern is open or shorted can be checked by the third test pad portion (TP3).

[0256] Referring to FIGS. 18, 19, 20, 24, 25, and 26, the fourth circuit pattern (1240) is disposed on the first substrate (1110), the second substrate (1120), and the adhesive layer (1400).

[0257] The fourth circuit pattern (1240) includes a fourth wiring portion (1241), a fourth a pad portion (1242a), a fourth b pad portion (1242b), and a third via. The fourth wiring portion (1241), the fourth a pad portion (1242a), and the fourth b pad portion (1242b) may include the same material. In addition, the fourth wiring portion (1241), the fourth a pad portion (1242a), and the fourth b pad portion (1242b) may be formed integrally.

[0258] The above 4a pad portion (1232a) is disposed on the first substrate (1110). The 4a pad portion (1232a) is disposed on the one surface (1-1S). The 4a pad portion (1242a) is disposed within the chip mounting area (CHA). Accordingly, the 4a pad portion (1242a) is connected to the terminal of the chip. As a result, the 4th circuit pattern (1240) and the chip are connected.

[0259] In addition, the 4th b pad portion (1232b) is disposed on the second substrate (1120). The 4th b pad portion (1232b) is disposed on the other surface (2-2S). The 4th b pad portion (1232b) is connected to a terminal of an external display panel. As a result, the 4th circuit pattern (1240) and the display panel are connected.

[0260] In addition, the fourth wiring portion (1241) is arranged on the second substrate (1120). The fourth wiring portion (1241) is arranged on the one surface (2-1S). The fourth wiring portion (1241) connects the fourth a pad portion (1242a) and the fourth b pad portion (1242b). Accordingly, the chip and the display panel are connected. Accordingly, a signal generated from the chip is transmitted to the display panel.

[0261] Referring to Fig. 19, the fourth wiring portion (1241) extends upwardly in the second direction and downwardly in the second direction from the one surface (2-1S). The fourth wiring portion (1241) extending upwardly in the second direction may be connected to the fourthb pad portion (1242b). In addition, the fourth wiring portion (1241) extending downwardly in the second direction may be connected to the fourth test pad portion (TP4).

[0262] The number of the fourth circuit patterns may be different from the number of the third circuit patterns. For example, the number of the fourth circuit patterns may be greater than the number of the third circuit patterns. No other circuit patterns are arranged on one surface of the second substrate, and only the fourth wiring portion is arranged. Accordingly, since the area on which the fourth wiring portion is arranged is sufficient, the number of the fourth circuit patterns may be formed greater than the number of the third circuit patterns.

[0263] Additionally, the fourth wiring portion may overlap the third wiring portion in the thickness direction of the second substrate.

[0264] The 4a wiring portion (1241), the 4a pad portion (1242a), and the 4b pad portion (1242a) are electrically connected. The 4a wiring portion (1241), the 4a pad portion (1242a), and the 4b pad portion (1242a) are connected by a third via. The third via may include a 3a via (V3a), a 3b via (V3b), and a 3c via (V3c) depending on the location.

[0265] Referring to FIG. 24, the 4a pad portion (1242a) and the 4th wiring portion (1241) are connected by the 3a via (V3a). The 3a via (V3a) penetrates the first substrate (1110). In addition, the 3rd via (V3) partially penetrates the adhesive layer (1400). Accordingly, the thickness of the 3a via (V3a) is greater than the thickness of the substrates (1110, 1120). In addition, the thickness of the 3a via (V3a) is greater than the thickness of the adhesive layer (1400). In addition, the thickness of the 3a via (V3a) is smaller than the thickness of the first via (V1). In addition, the thickness of the 3rd via (V3) is smaller than the thickness of the second via (V2).

[0266] The thickness of the fourth circuit pattern may be smaller than the thickness (T2) of the adhesive layer. In detail, the thickness (T3) of the fourth wiring portion (1241) may be smaller than the thickness (T2) of the adhesive layer. Accordingly, the adhesive layer (1400) may surround the fourth wiring portion (1241). Accordingly, the fourth wiring portion (1241) may be protected by the adhesive layer (1400). The difference (G) between the thickness of the adhesive layer and the thickness of the fourth wiring portion (1241) and the thickness (T3) of the fourth wiring portion (1241) may be different. For example, the thickness (T3) of the fourth wiring portion (1241) may be larger than the thickness difference (G).

[0267] The fourth wiring portion (1241) may have a thickness within a set range. The thickness (T3) of the fourth wiring portion (1241) may be 8 μm or less. Specifically, the thickness (T3) of the fourth wiring portion (1241) may be 1 μm to 8 μm, 2 μm to 7 μm, or 3 μm to 6 μm. If the thickness (T3) of the fourth wiring portion (1241) exceeds 8 μm, the thickness of the adhesive layer also increases. Accordingly, the thickness of the flexible circuit board may increase. This may reduce the flexible characteristics of the flexible circuit board. In addition, if the thickness (T3) of the fourth wiring portion (1241) is set to less than 1 μm, process efficiency may decrease.

[0268] Referring to FIG. 25, the 4b pad portion (1242b) and the 4th wiring portion (1241) are connected by the 3b via (V3b). The 3b via (V3b) penetrates the first substrate (1110). Accordingly, the thickness of the 3b via (V3b) is equal to or similar to the thickness of the substrates (1110, 1120). In addition, the thickness of the 3b via (V3b) is greater than the thickness of the adhesive layer (1400). In addition, the thickness of the 3b via (V3b) is smaller than the thickness of the first via (V1). In addition, the thickness of the 3b via (V3b) is smaller than the thickness of the second via (V2). In addition, the thickness of the 3b via (V3b) is smaller than the thickness of the 3a via (V3a).

[0269] The fourth circuit pattern (1240) may include a fourth test pad portion (TP4). The fourth test pad portion (TP4) may be disposed on the second-second surface (2-2S). The fourth test pad portion (TP4) may be disposed on the unusable area (UA). In addition, the second protective layer (1320) is not disposed on the fourth test pad portion (TP4).

[0270] The fourth circuit pattern (1240) can be tested before connecting the display panel and the fourthb pad portion (1242b). For example, whether the fourth circuit pattern is open or shorted can be checked by the fourth test pad portion (TP4).

[0271] Referring to FIG. 26, the fourth test pad portion (TP4) and the fourth wiring portion (1241) are connected by the third c via (V3c). The third c via (V3c) penetrates the first substrate (1110). Accordingly, the thickness of the third c via (V3c) is equal to or similar to the thickness of the substrates (1110, 1120). In addition, the thickness of the third c via (V3c) is greater than the thickness of the adhesive layer (1400). In addition, the thickness of the third c via (V3c) is smaller than the thickness of the first via (V1). In addition, the thickness of the third c via (V3c) is smaller than the thickness of the second via (V2). In addition, the thickness of the third c via (V3c) is smaller than the thickness of the third a via (V3a). Additionally, the thickness of the third b via (V3b) and the thickness of the third c via (V3c) may be the same or similar.

[0272] Referring to FIGS. 18 and 20, the fifth circuit pattern (1250) may be disposed on the first substrate (1110) and the second substrate (1120). In detail, the fifth circuit pattern (1250) may be disposed on the one surface (1-1S) and the other surface (2-2S).

[0273] The fifth circuit pattern (1250) includes a fifth a wiring portion (1251a), a fifth b wiring portion (1251b), a fifth a pad portion (1252a), a fifth b pad portion (1252b), and a fourth via (V4). The fifth a wiring portion (1251a), the fifth b wiring portion (1251b), the fifth a pad portion (1252a), and the fifth b pad portion (1252b) may include the same material. In addition, the fifth a wiring portion (1251a), the fifth b wiring portion (1251b), the fifth a pad portion (1252a), and the fifth b pad portion (1252b) may be formed integrally.

[0274] The above 5a pad portion (1252a) is arranged on the surface (1-1S). The 5a pad portion (1252a) may be arranged adjacent to the 1a pad portion (1212a). The 5a pad portion (1252a) is connected to a terminal of an external circuit board. Thus, the 5th circuit pattern (1250) and the circuit board may be connected.

[0275] In addition, the 5th b pad portion (1252b) is positioned on the other surface (2-2S). The 5th b pad portion (1252b) is connected to a terminal of an external display panel. Thus, the 5th circuit pattern (1250) and the display panel are connected.

[0276] The fifth wiring section may include the fifth a wiring section (1251a) and the fifth b wiring section (1251b). The fifth a wiring section (1251a) and the fifth b wiring section (1251b) may be electrically connected by the fourth via (V).

[0277] The fifth wiring section connects the fifth a pad section (1252a) and the fifth b pad section (1252b). Specifically, the fifth a wiring section (1251a) is connected to the fifth a pad section (1252a). In addition, the fifth b wiring section (1251b) is connected to the fifth b pad section (1252b).

[0278] The fifth circuit pattern (1250) may be a power supply pattern. Power may be transmitted to the circuit board and the display panel by the fifth circuit pattern (1250).

[0279] The first protective layer (1310) and the second protective layer (1320) are disposed on the fifth circuit pattern (1250). In detail, the first protective layer (1310) is disposed on the fifth circuit pattern (1250) on the one side (1-1S). In addition, the second protective layer (1320) is disposed on the fifth circuit pattern (1250) on the other side (2-2S). The first protective layer (1310) and the second protective layer (1320) may be disposed on an area excluding the 5a pad portion (1252a) and the 5b pad portion (1252b).

[0280] Meanwhile, the above description described a flexible circuit board comprising two substrates. However, the embodiment is not limited thereto. The flexible circuit board may comprise three or more substrates.

[0281] At least one circuit pattern among the first circuit pattern (1210), the second circuit pattern (1220), the third circuit pattern (1230), the fourth circuit pattern (1240), and the fifth circuit pattern (1250) may include a metal material having excellent electrical conductivity. In detail, at least one circuit pattern among the first circuit pattern (1210), the second circuit pattern (1220), the third circuit pattern (1230), the fourth circuit pattern (1240), and the fifth circuit pattern (1250) may include copper (Cu). However, the embodiment is not limited thereto. At least one circuit pattern among the first circuit pattern (1210), the second circuit pattern (1220), the third circuit pattern (1230), and the fourth circuit pattern (1240) may include copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), molybdenum (Mo). It may include at least one metal selected from the group consisting of gold (Au), titanium (Ti) and alloys thereof.

[0282] Additionally, at least one of the first protective layer (1310) and the second protective layer (1320) may include solder paste. For example, at least one of the first protective layer (1310) and the second protective layer (1320) may include solder paste containing a thermosetting resin, a thermoplastic resin, a filler, a curing agent, or a curing accelerator.

[0283] Hereinafter, the layer structure of the first to fifth circuit patterns will be described with reference to FIGS. 27 and 28. For convenience of explanation, FIGS. 27 and 28 are described with reference to the first circuit pattern. However, the embodiments of FIGS. 27 and 28 can be equally applied to the second to fifth circuit patterns.

[0284] Referring to Fig. 27, the first circuit pattern may be formed in multiple layers. Specifically, the first wiring portion (1211) and the first a pad portion (1212a) may include a first metal layer (1201) and a second metal layer (1202). In addition, although not shown in Fig. 10, the first b pad portion (1212b) may also include the first metal layer (1201) and the second metal layer (1202).

[0285] The first metal layer (1201) may be a seed layer of the circuit pattern. For example, the first metal layer (1201) may be a seed layer formed through electroless plating using a metal material such as copper (Cu) on the first substrate (1110).

[0286] Additionally, the second metal layer (1202) may be a plating layer. For example, the second metal layer (1202) may be a plating layer formed by electrolytic plating using the first metal layer (1201) as a seed layer.

[0287] The thickness of the first metal layer (1201) may be smaller than the thickness of the second metal layer (1202).

[0288] For example, the thickness of the first metal layer (1201) may be 0.7 μm to 2 μm. Additionally, the thickness of the second metal layer (1202) may be 10 μm to 25 μm.

[0289] The first metal layer (1201) and the second metal layer (1202) may include the same metal material. For example, the first metal layer (1201) and the second metal layer (1202) may include copper (Cu).

[0290] Additionally, a bonding layer (1203) may be disposed on the second metal layer (1201). In detail, the bonding layer (1203) may be disposed on the side of the first metal layer (1201), the side of the second metal layer (1202), and the upper surface of the second metal layer (1202). That is, the bonding layer (1203) may be disposed while surrounding the metal layer.

[0291] The above bonding layer (1203) may include a metal. In detail, the above bonding layer (1203) may include tin (Sn).

[0292] The above bonding layer (1203) may be formed to a thickness of 0.3 μm to 0.7 μm. The bonding layer (1203) may have an increased tin content as it extends from the lower surface to the upper surface.

[0293] That is, the bonding layer (1203) is placed in contact with the second metal layer (1202). Accordingly, the tin content may increase and the copper content may decrease from the lower surface to the upper surface of the bonding layer (1203).

[0294] Accordingly, only pure tin can remain in the thickness range of 0.1 µm to 0.3 µm on the upper surface of the bonding layer (1203).

[0295] By the bonding layer (1203), the terminals of the chip, the terminals of the printed circuit board, and the terminals of the display panel can be easily bonded to the pad portion by heat and pressure. That is, when heat and pressure are applied to the pad portion, the upper surface of the bonding layer where pure tin remains is melted. As a result, the terminals of the chip, the terminals of the printed circuit board, and the terminals of the display panel can be easily bonded to the pad portion.

[0296] The above bonding layer (1203) is not separated from the first pad portion (1212a) and the second pad portion (1212b), but can become a part of the first pad portion (1212a) and the second pad portion (1212b).

[0297] The first circuit pattern is subjected to a flash etching process to separate the circuit patterns during the manufacturing process. As a result, the first metal layer (1201) is etched. Accordingly, the thickness of the first circuit pattern ultimately manufactured may be smaller than the sum of the thicknesses of the first metal layer (1201), the second metal layer (1202), and the bonding layer (1203).

[0298] Meanwhile, a buffer layer (1205) may be further disposed between the substrate (100) and the first circuit pattern. The adhesion between the first substrate (10) and the circuit pattern may be improved by the buffer layer (1205).

[0299] The above buffer layer (1205) may be formed in multiple layers. Specifically, the buffer layer (1205) may include a first buffer layer (1205a) and a second buffer layer (1205b) on the first buffer layer (1205a). Accordingly, the first buffer layer (1205a) is in contact with the first substrate (1110). In addition, the second buffer layer (1205b) is in contact with the first circuit pattern (1210).

[0300] The first buffer layer (1205a) may include a material having good adhesion to the first substrate (1110). For example, the first buffer layer (1205a) may include nickel (Ni). In addition, the second buffer layer (1205b) may include a material having good adhesion to the second circuit pattern. For example, the second buffer layer (1205b) may include chromium (Cr).

[0301] The above buffer layer (1205) may have a thin film thickness in nanometer units. For example, the above buffer layer (1205) may have a thickness of 20 nm or less.

[0302] The adhesion between the first substrate (1110) and the first circuit pattern is improved by the buffer layer (1205).

[0303] Referring to FIG. 28, the bonding layer (1203) may include multiple bonding layers. For example, the bonding layer (1203) may include a first bonding layer (1203a) and a second bonding layer (1203b).

[0304] In detail, the first bonding layer (1203a) may be disposed on the first wiring portion (1211) and the first pad portion (1212a). In addition, the first bonding layer (1203a) may also be disposed on the second pad portion (1212b). That is, the first bonding layer (1203a) may be disposed on the first circuit pattern.

[0305] In addition, the second bonding layer (1203b) may be placed only on the first a pad portion (1212a) and the first b pad portion (1212b). That is, the first wiring portion (1211) and the pad portions (1212a, 212b) may have different layer structures due to the second bonding layer (1203b).

[0306] The first bonding layer (1203a) and the second bonding layer (1203b) may include a metal. Specifically, the first bonding layer (1203a) and the second bonding layer (1203b) may include tin (Sn).

[0307] The first bonding layer (1203a) and the second bonding layer (1203b) may be arranged with different thicknesses. Specifically, the second bonding layer (1203b) may have a thickness greater than that of the first bonding layer (1203a).

[0308] For example, the first bonding layer (1203a) may have a thin film thickness of 0.02 μm to 0.06 μm, and the second bonding layer (1203b) may have a thickness of 0.2 μm to 0.6 μm.

[0309] When the first bonding layer is thickly disposed between the first protective layer (1310) and the first wiring portion (1211), cracks may occur in the first bonding layer when the flexible circuit board is bent. Accordingly, the first bonding layer (1231) is formed with a thin film thickness. This prevents cracks in the first bonding layer when the flexible circuit board is bent.

[0310] Additionally, the second bonding layer (1203b) may have a higher tin content as it extends from the lower surface to the upper surface.

[0311] That is, the second bonding layer (1203b) may have a tin content that increases and a copper content that decreases as it moves from the lower surface to the upper surface.

[0312] Accordingly, only pure tin can remain in the thickness range of 0.1 µm to 0.3 µm on the upper surface of the second bonding layer (1203b).

[0313] The terminals of the chip, the terminals of the printed circuit board, and the terminals of the display panel can be easily bonded to the pad portion by heat and pressure through the second bonding layer (1203b). That is, when heat and pressure are applied to the pad portion, the upper surface of the bonding layer, where pure tin remains, is melted. As a result, the terminals of the chip, the terminals of the printed circuit board, and the terminals of the display panel can be easily bonded to the pad portion.

[0314] The above flexible circuit board (1000A) may have a defined separation area (IA). The second protective layer (1320) includes ends in the second direction (2D). Specifically, the second protective layer (1320) overlapping the chip mounting area (CHA) includes a first end (E1) adjacent to the 3b pad portion (1232b) and a second end (E2) facing the first end (E1).

[0315] The above separation area (IA) can be defined as an area between the first end (E1) and an area corresponding to the chip mounting area (CHA).

[0316] The flexible circuit board (1000A) can be bent. Specifically, the flexible circuit board (1000A) can be bent in all or part of the separation area (IA). Accordingly, the flexible circuit board (1000A) can include a bending area (BA). The bending area (BA) can be arranged within the separation area (IA).

[0317] When the above flexible circuit board (1000A) is bent, stress occurs. Specifically, tensile stress occurs on the outer surface of the bend, and compressive stress occurs on the inner surface of the bend. This stress may cause the buffer layer, the bonding layer, and the metal layer to delaminate. In other words, cracks may form in the circuit pattern overlapping the bending area.

[0318] Referring to FIGS. 29 and 30, the flexible circuit board (1000A) can be bent in the entire area or a portion of the separation area (IA). The flexible circuit board (1000A) can be bent so that one side (1-1S) of the first substrate faces each other. Accordingly, tensile stress can be generated on the other side (2-2S) of the second substrate.

[0319] Accordingly, the above-mentioned surface (2-2S) arranges the bonding layer differently for each area.

[0320] The first bonding layer (1203a) is disposed on the separation area (IA). In addition, the first bonding layer (1203a) is disposed on the area where the third b pad portion (1232b) is disposed.

[0321] The second bonding layer (1203b) is not disposed on the separation area (IA). The second bonding layer (1203b) is disposed on the area where the third b pad portion (1232b) is disposed.

[0322] The thickness of the first bonding layer (1203a) is smaller than the thickness of the second bonding layer (1203b). Only the first bonding layer (1203a) is disposed in the separation area (IA). Accordingly, the separation area (IA) can be easily bent.

[0323] In addition, the second bonding layer (1203b) is disposed on the area where the pad portion is disposed. Accordingly, the pad portion can be easily bonded to the pad portion of the chip.

[0324] One bonding layer or multiple bonding layers may be arranged on the one side (1-1S) corresponding to the above-mentioned surface (2-2S).

[0325] Referring to Fig. 29, only one bonding layer (1203) may be disposed on the surface (1-1S). The thickness of the bonding layer (1203) may be greater than or equal to the thickness of the second bonding layer (1203b). Accordingly, when disposing the bonding layer on the surface (1-1S), multiple plating processes are not required. Therefore, process efficiency can be improved.

[0326] Referring to Fig. 30, a plurality of bonding layers may be arranged on the one side (1-1S). Specifically, the first bonding layer (1203a) and the second bonding layer (1203b) on the first bonding layer (1203a) may be arranged on the one side (1-1S). Accordingly, the sizes of the bonding layers arranged above and below the bonding layer (1400) may be made similar. Accordingly, before folding the flexible circuit board, the flexible circuit board can be prevented from bending. In addition, the plating process of the one side (1-1S) and the other side (2-2S) may be performed simultaneously.

[0327] Referring to Fig. 31, the flexible circuit board (1000A) can be bent in the entire area or a portion of the separation area (IA). The flexible circuit board (1000A) can be bent so that one side (1-1S) of the first substrate faces each other. Accordingly, tensile stress can be generated on the other side (2-2S) of the second substrate.

[0328] Accordingly, the above-mentioned surface (2-2S) arranges the bonding layer differently for each area.

[0329] The first bonding layer (1203a) is partially disposed on the separation area (IA). Accordingly, the separation area (IA) may include an open area (OA) where the first bonding layer (1203a) is not disposed. In addition, the first bonding layer (1203a) is disposed on the area where the third b pad portion (1232b) is disposed.

[0330] The second bonding layer (1203b) is not disposed on the separation area (IA). The second bonding layer (1203b) is disposed on the area where the third b pad portion (1232b) is disposed.

[0331] The first bonding layer (1203a) is not positioned on the open area. In addition, the second bonding layer (1203b) is not positioned on the separation area and the open area. Therefore, the flexible circuit board can be easily bent. In addition, when bending the flexible circuit board, cracks can be prevented from forming in the bonding layer on the separation area.

[0332] Referring to Fig. 32, the flexible circuit board (1000A) can be bent in the entire area or a portion of the separation area (IA). The flexible circuit board (1000A) can be bent so that one side (1-1S) of the first substrate faces each other. Accordingly, tensile stress can be generated on the other side (2-2S) of the second substrate.

[0333] Accordingly, the above-mentioned surface (2-2S) arranges the bonding layer differently for each area.

[0334] The first bonding layer (1203a) is partially disposed on the separation area (IA). Accordingly, the separation area (IA) may include an open area (OA) where the first bonding layer (1203a) is not disposed. In addition, the first bonding layer (1203a) is disposed on the area where the third b pad portion (1232b) is disposed.

[0335] The second bonding layer (1203b) is not disposed on the separation area (IA). The second bonding layer (1203b) is disposed on the area where the third b pad portion (1232b) is disposed.

[0336] A plurality of protective layers may be disposed on the open area (OA). Specifically, a seconda protective layer (1320a) and a secondb protective layer (1320b) on the seconda protective layer (1320a) may be disposed on the open area (OA). The seconda protective layer (1320a) may be disposed only on the open area (OA).

[0337] Accordingly, the flexible circuit board can be easily bent. In addition, when bending the flexible circuit board, cracks can be prevented from forming in the bonding layer of the separated area. That is, the bonding layer is not disposed in the open area. In addition, a plurality of protective layers are disposed in the open area. Therefore, when bending the flexible circuit board, cracks can be prevented from forming in the bonding layer due to stress.

[0338] Referring to FIG. 33, one end of the COF module (2000) according to an embodiment may be connected to the display panel (4000), and the other end opposite to the one end may be connected to the circuit board (3000). For example, the display panel (4000) may be disposed on one surface of the COF module (2000), and the circuit board (3000) may be disposed on the other surface opposite to the one surface of the COF module (2000). However, the embodiment is not limited thereto, and the display panel (4000) and the circuit board (3000) may be disposed on the same surface of the COF module (2000).

[0339] The COF module (2000) includes a flexible substrate. Accordingly, it can have both a rigid form and a bent form between the display panel (3000) and the circuit board (4000). That is, the COF module (2000) can include a bending area (BA).

[0340] The COF module (2000) can be connected in a curved manner between the display panel (4000) and the circuit board (3000), which are arranged to face each other. Therefore, the thickness of the electronic device can be reduced. In addition, the degree of freedom in design can be improved. In addition, the COF module (2000) including the flexible substrate does not have wiring breakage even when in a curved manner. Accordingly, the reliability of the electronic device including the COF module can be improved.

[0341]

[0342] Since the above COF module is flexible, it can be used in various electronic devices.

[0343] For example, referring to FIG. 34, the COF module can be applied to a flexible touch window that can be bent. Accordingly, a touch device device including the touch window can be flexible. Accordingly, a user can bend or fold it by hand.

[0344] Referring to FIG. 35, the COF module can be applied to various wearable touch devices including curved displays. Accordingly, an electronic device including the COF module can be slimmed down or made lighter.

[0345] Referring to FIG. 36, the COF module can be used in various electronic devices having a display portion, such as a TV, monitor, or laptop.

[0346]

[0347] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the present invention.

[0348] In addition, although the above description focuses on embodiments, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiment. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. First description and second description; An adhesive layer disposed between the first substrate and the second substrate; Circuit patterns arranged on the first substrate and the second substrate; and including a protective layer disposed on the circuit pattern; The circuit pattern includes first to third circuit patterns arranged at different locations, and a plurality of vias penetrating at least a portion of the first substrate and the second substrate, Each of the first substrate and the second substrate includes one side and a second side opposite to the first side, A flexible circuit board, wherein at least one of the plurality of vias is formed through the first substrate, the second substrate, and the adhesive layer and includes a plurality of first slopes having a width decreasing in the horizontal direction, and a second slope provided between the plurality of first slopes and different from the first slope.

2. In paragraph 1, A flexible circuit board, wherein the second slope includes a first portion having an increasing width in the horizontal direction and a second portion having a decreasing width in the horizontal direction.

3. In paragraph 2, A flexible circuit board, wherein the second slope is a curve having a specific curvature including the first portion and the second portion.

4. In paragraph 1, The above second circuit pattern includes a 2-1 circuit pattern and a 2-2 circuit pattern, The above 2-1 circuit pattern includes a 2-1a pad portion on one surface of the first substrate, a 2-1b pad portion on the other surface of the second substrate, and a 2-1 wiring portion on one surface of the first substrate and the other surface of the second substrate. The above 2-1 wiring section and the 2-1b pad section are connected through the 2a via, A flexible circuit board in which the above second a via is formed by penetrating the first substrate, the adhesive layer, and the second substrate.

5. In paragraph 4, The above 2a via includes a 2a1 via portion penetrating the adhesive layer, a 2a2 via portion penetrating the first substrate, and a 2a3 via portion penetrating the second substrate. The width of the above 2a2 via portion and the width of the above 2a3 via portion become smaller as they extend from the first substrate in the direction of the second substrate, The above 2a1 via portion has a first width, The above 2a2 via portion has a second width of long width and a third width of short width, The above 2a3 via portion has a fourth width of long width and a fifth width of short width, A flexible circuit board wherein the first width is greater than at least one of the second width and the third width.

6. In paragraph 5, The above first width is larger than the above third width, A flexible circuit board having the first width greater than the fourth width and the fifth width.

7. In paragraph 5, The first width is greater than the second width and the third width, A flexible circuit board having the first width greater than the fourth width and the fifth width.

8. In paragraph 4, The above 2-2 circuit pattern includes a 2-2a pad portion on one surface of the first substrate, a 2-2b pad portion on the other surface of the second substrate, and a 2-2 wiring portion on the other surface of the second substrate. The above 2-2 wiring section is connected to the 2-2a pad section by the 2b via, A flexible circuit board in which the above-mentioned 2-2 wiring section is connected to the above-mentioned 2-2b pad section by the above-mentioned 2c via. The above 2b via is formed by penetrating the first substrate, A flexible circuit board in which the above 2c via is formed by penetrating the adhesive layer and the second substrate.

9. In paragraph 8, The above 2c via includes a 2c1 via portion penetrating the adhesive layer and a 2c2 via portion penetrating the second substrate, The width of the above 2c2 via portion becomes smaller as it extends from the first substrate in the direction of the second substrate, The above 2c1 via portion has a 1' width, The above 2c2 via portion has a 2' width of long width and a 3' width of short width, A flexible circuit board in which the first width is greater than at least one of the second width and the third width.

10. In paragraph 1, The above third circuit pattern includes a 3-1 circuit pattern and a 3-2 circuit pattern, The above 3-1 circuit pattern includes a 3-1a pad portion on one surface of the first substrate, a 3-1b pad portion on the other surface of the second substrate, and a 3-1 wiring portion on one surface of the second substrate. The above 3-1 wiring section and the above 3-1a pad section are connected through the 3a via, The above 3-1 wiring section and the 3-1b pad section are connected through the 3b via, The above 3a via is formed by penetrating the first substrate and the adhesive layer, A flexible circuit board in which the above-mentioned third b via is formed by penetrating the above-mentioned second substrate.

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