Buffer circuit and memory

Abstract

A buffer circuit (100) and a memory. The buffer circuit (100) is applied to the memory. A CA0 buffer circuit, a CA1 buffer circuit, a CA2 buffer circuit, a CA3 buffer circuit and a CA4 buffer circuit each comprise: a first command address input end (111) connected to a command address pin, different CA buffer circuits being connected to different command address pins; a first circuit output end (112) used for outputting a digital signal; a first comparator (113), a forward input end thereof being connected to the first command address input end (111), a reverse input end thereof receiving a reference signal, an enable end thereof receiving a power-down enable signal, an output end thereof being connected to the first circuit output end (112), and when the memory enters a power-down mode, the first comparator (113) being turned off on the basis of the level of the power-down enable signal; and a first voltage output circuit (114) used for outputting a high-level voltage or a low-level voltage to the first circuit output end (112) when the memory enters the power-down mode. In the power-down mode, when each CA buffer circuit is turned off, the memory can effectively exit the power-down mode.

Description

Buffer circuit and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 3, 2023, with application number 202310814094.5 and application name “Buffer Circuit and Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of integrated circuits, and in particular to a buffer circuit and a memory. Background Art

[0003] The fifth-generation Double Data Rate (DDR5) memory specification (SPEC) stipulates that in power-down mode, all command address (CA) buffer circuits must be disabled to reduce power consumption. Furthermore, even after the CA buffer circuits are disabled, the memory must still be able to correctly receive the power-down exit (PDE) command to exit power-down mode.

[0004] However, after the CA buffer circuit is turned off, the next PDE command will not be recognized. Therefore, a special setting is required to recognize the PDE command in power-down mode.

[0005] Summary of the Invention

[0006] Based on this, an embodiment of the present application provides a buffer circuit and a memory that can recognize PDE commands in power-down mode.

[0007] A buffer circuit, applied to a memory, includes a CA0 buffer circuit, a CA1 buffer circuit, a CA2 buffer circuit, a CA3 buffer circuit, and a CA4 buffer circuit, wherein each of the CA0 buffer circuit, the CA1 buffer circuit, the CA2 buffer circuit, the CA3 buffer circuit, and the CA4 buffer circuit includes:

[0008] A first command address input terminal is connected to a command address pin, and different CA buffer circuits are connected to different command address pins;

[0009] A first circuit output terminal, for outputting a digital signal;

[0010] a first comparator having a positive input connected to the first command address input, a negative input receiving a reference signal, an enable terminal receiving a power-down enable signal, and an output connected to the first circuit output; after the memory enters the power-down mode, the first comparator is turned off based on the level of the power-down enable signal;

[0011] The first voltage output circuit is configured to output a high level voltage or a low level voltage to the first circuit output terminal after the memory enters a power-down mode.

[0012] In one embodiment, the first voltage output circuit includes:

[0013] a first pull-up circuit, connected to the output end of the first circuit, and configured to output the high-level voltage to the output end of the first circuit;

[0014] The first pull-down circuit is connected to the first circuit output terminal and is configured to output the low-level voltage to the first circuit output terminal.

[0015] In one embodiment, the first pull-up circuit includes:

[0016] The first switch unit has one end connected to the output end of the first circuit and the other end connected to the high-level voltage.

[0017] In one embodiment, the first switch unit includes:

[0018] a first P-type transistor, a gate of which is connected to the power-down enable signal, and a source of which is connected to the high-level voltage;

[0019] The second P-type transistor has a gate connected to the command address inversion signal, a source connected to the drain of the first P-type transistor, and a drain connected to the output end of the first circuit.

[0020] In one embodiment, the lower pull-up circuit includes:

[0021] The second switch unit has one end connected to the output end of the first circuit and the other end connected to the low-level voltage.

[0022] In one embodiment, the second switch unit includes:

[0023] A first N-type transistor, having a gate connected to the command address inversion signal and a source connected to the low-level voltage;

[0024] The second N-type transistor has a gate connected to a power-down enable reverse signal, a source connected to the drain of the first N-type transistor, and a drain connected to the output end of the first circuit. The power-down enable reverse signal has a level opposite to that of the power-down enable signal.

[0025] In one embodiment, the command address buffer circuit further includes a CA12 buffer circuit and a CA13 buffer circuit.

[0026] The CA12 buffer circuit includes:

[0027] The second command address input terminal is connected to the CA12 pin;

[0028] The second circuit output terminal is used to output a digital signal;

[0029] a second comparator, wherein the positive input terminal is connected to the second command address input terminal, the negative input terminal is used to input a reference signal, the output terminal is connected to the second circuit output terminal, and the enable terminal is connected to the second enable signal, the level of the second enable signal is high when exiting the power-down mode and in the non-mirror mode, and is low in all other cases;

[0030] a second voltage output circuit, configured to output the high-level voltage or the low-level voltage to the second circuit output terminal after the memory enters a power-down mode;

[0031] The CA13 buffer circuit includes:

[0032] The third command address input terminal is connected to the CA13 pin;

[0033] The third circuit output terminal is used to output a digital signal;

[0034] a third comparator, wherein the positive input terminal is connected to the third command address input terminal, the negative input terminal is used to input a reference signal, the output terminal is connected to the output terminal of the third circuit, and the enable terminal is connected to a third enable signal, the level of the third enable signal is high when exiting the power-down mode and in the mirror mode, and is low in all other cases;

[0035] The third voltage output circuit is configured to output the high level voltage or the low level voltage to the third circuit output terminal after the memory enters the power-down mode.

[0036] In one embodiment, the CA12 buffer circuit further includes a NOR gate, the two output ends of the NOR gate are respectively connected to the power-off enable reverse signal and the mirror enable signal, and the output end is used to output the second enable signal to the enable end of the second comparator.

[0037] In one embodiment, the CA13 buffer circuit further includes an AND gate, two output ends of the AND gate are respectively connected to the power-down enable signal and the mirror enable signal, and the output end is used as the enable end of the third comparator to output the third enable signal.

[0038] In one embodiment, the second voltage output circuit includes a second pull-up circuit and a second pull-down circuit.

[0039] The second pull-up circuit includes:

[0040] a third P-type transistor, a gate of which is connected to the power-down enable signal, and a source of which is connected to the high-level voltage;

[0041] a fourth P-type transistor, having a gate connected to the command address inversion signal, a source connected to the drain of the third P-type transistor, and a drain connected to the output end of the second circuit;

[0042] The second pull-down circuit includes:

[0043] a third N-type transistor, a gate of which is connected to the command address inversion signal, and a source of which is connected to the low-level voltage;

[0044] a fourth N-type transistor, having a gate connected to a power-down enable reverse signal, a source connected to the drain of the third N-type transistor, and a drain connected to the output end of the second circuit, wherein the power-down enable reverse signal is a reverse signal of the power-down enable signal;

[0045] A fifth N-type transistor has a gate connected to the mirror enable signal, a source connected to the low-level voltage, and a drain connected to the output end of the second circuit.

[0046] In one embodiment, the third voltage output circuit includes a third pull-up circuit and a third pull-down circuit.

[0047] The third pull-up circuit comprises:

[0048] a fifth P-type transistor, a gate of which is connected to the power-down enable signal, and a source of which is connected to the high-level voltage;

[0049] a sixth P-type transistor, having a gate connected to the command address inversion signal, a source connected to the drain of the fifth P-type transistor, and a drain connected to the output end of the third circuit;

[0050] The third pull-down circuit comprises:

[0051] a sixth N-type transistor, a gate of which is connected to the command address inversion signal, and a source of which is connected to the low-level voltage;

[0052] a seventh N-type transistor, having a gate connected to a power-down enable reverse signal, a source connected to the drain of the sixth N-type transistor, and a drain connected to the output end of the third circuit, wherein the power-down enable reverse signal has a level opposite to that of the power-down enable signal;

[0053] An eighth N-type transistor has a gate connected to the mirror enable reverse signal, a source connected to the low-level voltage, and a drain connected to the output end of the third circuit, wherein the mirror enable reverse signal has a level opposite to that of the mirror enable signal.

[0054] In one embodiment, the command address buffer circuit further includes CA5 to CA11 buffer circuits, and the CA5 to CA11 buffer circuits have the same circuit structure as the CA0 to CA4 buffer circuits.

[0055] A memory comprising:

[0056] The buffer circuit described in any one of the above items;

[0057] a command address buffer control circuit, connected to the buffer circuit, and configured to output the power-down enable signal to the buffer circuit;

[0058] The decoder circuit is connected to the command address buffer control circuit and is used to send a power-down mode exit command to the command address buffer control circuit.

[0059] In one embodiment, the memory further comprises:

[0060] The address mirror circuit is connected to the buffer circuit and is used to send a mirror enable signal to the buffer circuit.

[0061] In one embodiment, the memory further comprises:

[0062] A command address inversion pin is connected to the buffer circuit and is used to send a command address inversion signal to the buffer circuit.

[0063] The above-mentioned buffer circuit and memory are equipped with a first voltage output circuit in the CA0 to CA4 buffer circuits. Therefore, after entering power-down mode and shutting down all CA buffer circuits, the CA0 to CA4 buffer circuits can still output a high-level voltage or a low-level voltage to the first circuit output terminal through the first voltage output circuit, thereby allowing the first circuit output terminal to output a digital signal even when the first comparator is turned off. At this time, after applying low-level data to the CS_N pin, the digital signal data output by the first voltage output circuit of the CA0 to CA4 buffer circuits is combined with the data on the CS_N pin to form a command to exit power-down mode that complies with the memory (such as DDR5) SPEC truth table, thereby exiting power-down mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0065] FIG1 is a module block diagram of a memory according to an embodiment;

[0066] FIG2 is a module block diagram of a memory according to another embodiment;

[0067] FIG3 shows a circuit structure of the buffer circuits CA0 to CA4 according to an embodiment of the present invention;

[0068] FIG4 shows a circuit structure of a CA12 buffer circuit according to an embodiment of the present invention;

[0069] FIG5 shows a circuit structure of a CA13 buffer circuit according to an embodiment of the present invention.

[0070] FIG6 shows the circuit structure of the NOR gate in the CA12 buffer circuit according to an embodiment of the present invention;

[0071] FIG. 7 shows the circuit structure of the AND gate in the CA13 buffer circuit according to an embodiment.

[0072] Explanation of the accompanying symbols: 100-buffer circuit, 111-first command address input terminal, 112-first circuit output terminal, 113-first comparator, 114-first voltage output circuit, 1141-first pull-up circuit, 1142-first pull-down circuit, 121-second command address input terminal, 122-second circuit output terminal, 123-second comparator, 124-second voltage output circuit, 1241-second pull-up circuit, 1242-second pull-down circuit, 125-NOR gate, 131-third command address input terminal, 132-third circuit output terminal, 133-third comparator, 134-third voltage output circuit, 1341-third pull-up circuit, 1342-third pull-down circuit, 135-AND gate, 200-command address buffer control circuit, 300-decoder circuit, 400-address mirror circuit, 500-command address inversion pin. DETAILED DESCRIPTION

[0073] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0075] It will be understood that the terms "first," "second," etc. used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.

[0076] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0077] It is understood that “at least one” refers to one or more, “a plurality” refers to two or more, and “at least a portion of an element” refers to a portion or all of an element.

[0078] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0079] In one embodiment, a memory is provided. The memory may include, but is not limited to, fifth generation double data rate memory (DDR5).

[0080] 1 , the memory includes a buffer circuit 100, a command and address buffer control circuit 200, and a decoder circuit 300. The memory may also include a plurality of command and address (CA) pins.

[0081] In the buffer circuit 100 , a CA buffer circuit may be correspondingly provided for each CA pin.

[0082] As an example, in DDR5, the memory is provided with 14 CA pins (CA0 to CA13 pins). Accordingly, in the buffer circuit 100, 14 CA buffer circuits (CA0 to CA13 buffer circuits) are provided.

[0083] DDR5 also features a chip select signal (CS_N) pin. Different CA pins can output different data through their corresponding CA buffer circuits. According to the DDR5 SPEC truth table, the data output by the CA buffer circuit corresponding to each CA pin is combined with the data on the CS_N pin to form a specific command. Different data combinations can generate different commands.

[0084] For example, as shown in the SPEC truth table in Table 1 below, when the data on the CS_N pin corresponds to a low level (L), and the data output by the CA buffer circuits corresponding to the CA0 to CA4 pins (i.e., the CA0 to CA4 buffer circuits) corresponds to a high level (H), this represents an "exit power-down mode" command. It is also understood that at this time, the data output by the CA buffer circuits corresponding to the CA5 to CA13 pins (i.e., the CA5 to CA13 buffer circuits) corresponds to a level (V), indicating that the data output by the CA buffer circuits corresponding to the CA5 to CA13 pins can correspond to either a high level (H) or a low level (L).

[0085] Table 1

[0086] The command address buffer control circuit 200 is connected to the buffer circuit 100 , and can generate and output a power-down enable signal En to the buffer circuit 100 .

[0087] As an example, the command address buffer control circuit 200 may further generate and output a power-down enable inverse signal Enb to the buffer circuit 100. The power-down enable inverse signal Enb has a level opposite to that of the power-down enable signal En. When the power-down enable signal En is at a high level, the power-down enable inverse signal Enb is at a low level. When the power-down enable signal En is at a low level, the power-down enable inverse signal Enb is at a high level.

[0088] The decoder circuit 300 is connected to the command address buffer control circuit 200 and is used to send a power-down mode exit command to the command address buffer control circuit 200 .

[0089] When the command address buffer control circuit 200 receives the command to exit the power-down mode decoded by the decoder circuit 300, it can generate a high-level power-down enable signal En and a low-level power-down enable inverse signal Enb;

[0090] At the same time, as an example, the decoder circuit 300 may also send a power-down mode entry command to the command address buffer control circuit 200 .

[0091] When the command address buffer control circuit 200 receives the command to enter the power-down mode decoded by the decoder circuit 300 , it may generate a low-level power-down enable signal En and a high-level power-down enable inverse signal.

[0092] In one embodiment, referring to FIG. 2 , the memory device may further include an address mirror circuit 400. Address mirror circuit 400 is connected to buffer circuit 100 and configured to send a mirror enable signal Mir to buffer circuit 100. When the mirror enable signal Mir is high, the device enters mirror mode. When the mirror enable signal Mir is low, the device enters non-mirror mode.

[0093] As an example, the address mirror circuit 400 may further send a mirror enable inverted signal Mirb to the buffer circuit 100. The mirror enable inverted signal Mirb has a level opposite to that of the mirror enable signal Mir.

[0094] The memory may further include a mirror (MIR) pin. An input terminal of the address mirror circuit 400 may be connected to the mirror (MIR) pin.

[0095] When the MIR pin is connected to the power supply voltage VDDQ, it indicates that the mirror mode is to be entered. At this time, the address mirror circuit 400 can generate and send a high-level mirror enable signal Mir to the buffer circuit 100, and can generate and send a low-level mirror enable reverse signal Mirb to the buffer circuit 100.

[0096] At the same time, the memory can control the mirroring of even-numbered CA buffer circuits with the next odd-numbered CA buffer circuit. For example, the CA2 buffer circuit can be mirrored with the CA3 buffer circuit (not the CA1 buffer circuit), or the CA4 buffer circuit can be mirrored with the CA5 buffer circuit (not the CA3 buffer circuit).

[0097] When the MIR pin is connected to the power supply voltage VSS, it indicates that the address is in non-mirror mode instead of mirror mode. At this point, the address mirror circuit 400 generates and sends a low-level mirror enable signal Mir to the buffer circuit 100, and also generates and sends a high-level mirror enable reverse signal Mirb to the buffer circuit 100. At this point, mirror exchange is not performed between the CA buffer circuits.

[0098] It's also important to note that the DDR5 specification specifies the CA13 pin as the R17 address bit only at 64Gb capacity or in a 3D stacking process. When the capacity and process don't require CA13, the CA13 buffer circuit can be kept closed to save power. Furthermore, when mirror mode is enabled, the CA12 buffer circuit needs to be mirrored and swapped with the CA13 buffer circuit, so the CA12 buffer circuit can be kept closed.

[0099] 2 , the memory further includes a command address inversion (CAI) pin 500 . The command address inversion pin 500 is connected to the buffer circuit 100 and configured to send a command address inversion signal Cai to the buffer circuit 100 .

[0100] When the CAI pin is connected to the power supply voltage VDDQ, a high-level command address inversion signal Cai is sent to the buffer circuit 100, indicating that the command address inversion mode is to be entered. Simultaneously, the signals output by all CA buffer circuits in the SPEC truth table when entering the command address inversion mode are inverted. For example, when not entering the command address inversion mode, in the SPEC truth table, when the data on the CS_N pin corresponds to a low level L, and the data output by the CA buffer circuits corresponding to the CA0 to CA4 pins (i.e., the CA0 to CA4 buffer circuits) corresponds to a high level H, it represents a command to "exit power-down mode." However, when entering the command address inversion mode, in the SPEC truth table, when the data on the CS_N pin corresponds to a low level L, and the data output by the CA buffer circuits corresponding to the CA0 to CA4 pins (i.e., the CA0 to CA4 buffer circuits) corresponds to a low level L, it represents a command to "exit power-down mode."

[0101] When the CAI pin is connected to the power supply voltage VSS, the command address inversion signal Cai sent to the buffer circuit 100 is a low level signal, indicating that the command address inversion mode is not entered.

[0102] In one embodiment, a buffer circuit for a memory is provided.

[0103] The buffer circuit 100 includes a CA0 buffer circuit, a CA1 buffer circuit, a CA2 buffer circuit, a CA3 buffer circuit, and a CA4 buffer circuit.

[0104] 3 , the CA0 buffer circuit, the CA1 buffer circuit, the CA2 buffer circuit, the CA3 buffer circuit, and the CA4 buffer circuit each include a first command address input terminal 111 , a first circuit output terminal 112 , a first comparator 113 , and a first voltage output circuit 114 .

[0105] Meanwhile, as an example, the command and address buffer circuit also includes CA5 to CA11 buffer circuits, which have the same circuit structure as the CA0 to CA4 buffer circuits. Of course, the CA5 to CA11 buffer circuits may have a portion (e.g., the CA5 buffer circuit) that has the same circuit structure as the CA0 to CA4 buffer circuits, while another portion (e.g., the CA6 to CA11 buffer circuit) may have a different circuit structure from the CA0 to CA4 buffer circuits. Alternatively, the CA5 to CA11 buffer circuits may all have different circuit structures from the CA0 to CA4 buffer circuits. This is not a limitation here.

[0106] The first command address input terminal 111 is connected to the CA pin. Different CA buffer circuits are connected to different CA pins.

[0107] For example, the first command address input terminal 111 of the CA0 buffer circuit is connected to the CA0 pin. The first command address input terminal 111 of the CA1 buffer circuit is connected to the CA1 pin. The first command address input terminal 111 of the CA2 buffer circuit is connected to the CA2 pin. The first command address input terminal 111 of the CA3 buffer circuit is connected to the CA3 pin.

[0108] The first circuit output terminal 112 is used to output a digital signal. The level of the digital signal output by the first circuit output terminal 112 can represent the data output by the CA buffer circuit.

[0109] The positive input of the first comparator 113 is connected to the first command address input 111, thereby receiving the voltage on the CA pin. At the same time, the negative input of the first comparator 113 receives the reference signal. At this time, the output of the first comparator 113 can output a digital signal based on the comparison between the analog voltage on the CA pin and the analog voltage of the reference signal.

[0110] At the same time, the output terminal of the first comparator 113 is connected to the first circuit output terminal 112 , so that the first circuit output terminal 112 can output a digital signal.

[0111] The enable terminal of the first comparator 113 can be connected to the command address buffer control circuit 200 to receive the power-down enable signal En. After receiving the power-down enable signal En, the enable terminal of the first comparator 113 can be turned on or off according to the level of the power-down enable signal En.

[0112] For example, when the enable terminal of the first comparator 113 receives a high-level power-down enable signal En, the first comparator 113 may be turned on, and when the enable terminal of the first comparator 113 receives a low-level power-down enable signal En, the first comparator 113 may be turned off.

[0113] After the memory enters the power-down mode, the command address buffer control circuit 200 may generate a low-level power-down enable signal En, thereby turning off the first comparator 113 based on the level of the power-down enable signal.

[0114] After the memory exits the power-down mode, the command address buffer control circuit 200 may generate a high-level power-down enable signal En, thereby enabling the first comparator 113 to be turned on based on the level of the power-down enable signal En.

[0115] The first voltage output circuit 114 is configured to output a high level voltage or a low level voltage to the first circuit output terminal after the memory enters the power-down mode.

[0116] As previously described, when the memory enters power-down mode, the first comparator 113 is turned off, thereby disabling the CA buffer circuit. At this point, the output of the first comparator 113 cannot output a digital signal based on the comparison result between the voltage at the CA pin received by the positive input of the first comparator 113 and the voltage of the reference signal. Therefore, the output of the first comparator 113 cannot output a digital signal to the first circuit output terminal 112.

[0117] At this time, the first voltage output circuit 114 outputs a high level voltage or a low level voltage to the first circuit output terminal 112 , so that the first circuit output terminal 112 can output a digital signal even when the first comparator 113 is turned off.

[0118] Therefore, after low-level data is applied to the CS_N pin, the digital signal data output by the first voltage output circuit 114 of the CA0 to CA4 buffer circuits is combined with the data on the CS_N pin to form a command to exit the power-down mode that complies with the memory (e.g., DDR5) SPEC truth table, and is sent to the decoder circuit 300. This allows the decoder circuit 300 to decode the command to exit the power-down mode and send the command to the command address buffer control circuit 200. After receiving the command to exit the power-down mode decoded by the decoder circuit 300, the command address buffer control circuit 200 can generate a high-level power-down enable signal En, thereby turning on the first comparator 113.

[0119] For example, when the command address inversion mode and the mirror mode are not enabled and power-down mode is entered, the comparators in all CA buffer circuits are disabled. In this case, the CA0 to CA4 buffer circuits can output a high-level voltage (high-level voltage) to the first circuit output terminal 112 via the first voltage output circuit 114, thereby causing the digital signal outputted by the first circuit output terminal 112 to be a high-level signal.

[0120] At this time, after low-level data is applied to the CS_N pin, the digital signal data output by the first voltage output circuit 114 of the CA0 to CA4 buffer circuit is combined with the data on the CS_N pin to form a command to exit the power-down mode that complies with the memory (such as DDR5) SPEC truth table.

[0121] As another example, when the command address inversion mode is enabled and the mirror mode is not enabled, if power-down mode has been entered, the comparators in all CA buffer circuits are disabled. In this case, the CA0 to CA4 buffer circuits can output a low-level voltage to the first circuit output terminal 112 via the first voltage output circuit 114, thereby causing the digital signal outputted from the first circuit output terminal 112 to be a low-level signal.

[0122] At this time, after low-level data is applied to the CS_N pin, the digital signal data output by the first voltage output circuit 114 of the CA0 to CA4 buffer circuit is combined with the data on the CS_N pin to form a command to exit the power-down mode in accordance with the SPEC truth table in the command address inversion mode.

[0123] In one embodiment, referring to FIG. 3 , the first voltage output circuit 114 includes a first pull-up circuit 1141 and a first pull-down circuit 1142 .

[0124] The first pull-up circuit 1141 is connected to the first circuit output terminal 112 and is configured to output a high-level voltage to the first circuit output terminal 112 .

[0125] The first pull-down circuit 1142 is connected to the first circuit output terminal 112 and is configured to output a low-level voltage to the first circuit output terminal 112 .

[0126] At this time, a high level voltage and a low level voltage are output to the first circuit output terminal 112 through the first pull-up circuit 1141 and the first pull-down circuit 1142 respectively, thereby facilitating circuit control.

[0127] Of course, in other embodiments, the circuit design of the first voltage output circuit 114 may be such that the first circuit output terminal 112 is connected to the same signal output terminal of the first voltage output circuit 114. The signal output terminal can output a high-level voltage when a high-level voltage is required, and can also output a low-level voltage when a low-level voltage is required.

[0128] In one embodiment, referring to Figure 3 , the first pull-up circuit 1141 includes a first switch unit. One end of the first switch unit is connected to the first circuit output terminal 112, and the other end is connected to the high-level voltage VDDQ.

[0129] The first switch unit can control whether the first pull-up circuit 1141 outputs a high-level voltage.

[0130] As an example, the first switching unit may include a first P-type transistor T P1 With the second P-type transistor T P2 .

[0131] The second P-type transistor T P2 The source of the first P-type transistor T P1 of the drain.

[0132] At the same time, the first P-type transistor T P1 The gate of the first P-type transistor T is connected to the power-down enable signal En. P1 The source of the second P-type transistor T is connected to the high level voltage VDDQ. P2The gate of the second P-type transistor T is connected to the command address inversion signal Cai. P2 The drain of the first circuit is connected to the first circuit output terminal 112.

[0133] When entering the power-down mode, the power-down enable signal En is at a low level. P1 conduction.

[0134] At the same time, if in the non-command address inversion mode, the command address inversion signal Cai is at a low level. P2 Therefore, at this time, the first P-type transistor T P1 The high-level voltage VDDQ connected to the source of the first circuit will be transmitted to the first circuit output terminal 112, so that the first circuit output terminal 112 can output a high-level signal.

[0135] At this time, the high level signal outputted by the first circuit output terminal 112 of the CA0 to CA4 buffer circuits may be combined with the low level data on the CS_N pin to form a command for exiting the power-down mode in accordance with the SPEC truth table.

[0136] If the command address inversion mode is in operation, the command address inversion signal Cai is at a high level. P2 Therefore, at this time, the first P-type transistor T P1 The high level voltage VDDQ connected to the source of the first pull-down circuit 1142 will not be transmitted to the first circuit output terminal 112. The first circuit output terminal 112 can receive the low level signal provided by the first pull-down circuit 1142.

[0137] At this time, the low level signal output by the first circuit output terminal 112 of the CA0 to CA4 buffer circuit can be combined with the low level data on the CS_N pin to form a command to exit the power-down mode in accordance with the SPEC truth table in the command address inversion mode.

[0138] When the power-down mode is exited, the power-down enable signal En is at a high level. P1 Therefore, no matter whether it is in the command address inversion mode or not, the first P-type transistor T P1 The high-level voltage VDDQ connected to the source of the first circuit output terminal 112 will not be transmitted to the first circuit output terminal 112. At the same time, the first pull-down circuit 1142 can be set to not output a low-level signal to the first circuit output terminal 112 based on the high level of the power-down enable signal En. At the same time, when the power-down mode is exited, the first comparator 113 is turned on, so that the first circuit output terminal 112 can receive the voltage signal output by the first comparator 113 based on the CA pin.

[0139] In one embodiment, referring to FIG3 , the first pull-down circuit 1142 includes a second switch unit. One end of the second switch unit is connected to the first circuit output terminal 112 , and the other end is connected to a low-level voltage VSS, which is, for example, a ground voltage.

[0140] The second switch unit can control whether the first pull-down circuit 1142 outputs a low-level voltage.

[0141] As an example, the second switch unit may include a first N-type transistor T N1 and the second N-type transistor T N2 .

[0142] The second N-type transistor T N2 The source of the first N-type transistor T N1 of the drain.

[0143] At the same time, the first N-type transistor T N1 The gate of the first N-type transistor T is connected to the command address inversion signal Cai. N1 The source of the second N-type transistor T is connected to the low level voltage VSS. N2 The gate of the second N-type transistor T is connected to the power-down enable reverse signal Enb. N2 The drain of the first circuit is connected to the first circuit output terminal 112.

[0144] When entering the power-down mode, the power-down enable reverse signal Enb is high. At this time, the second N-type transistor T N2 conduction.

[0145] At the same time, if in the command address inversion mode, the command address inversion signal Cai is at a high level. N1 Therefore, at this time, the first N-type transistor T N1 The low-level voltage VSS connected to the source of the first circuit will be transmitted to the first circuit output terminal 112, so that the first circuit output terminal 112 can output a low-level signal.

[0146] At this time, the low level signal output by the first circuit output terminal 112 of the CA0 to CA4 buffer circuit can be combined with the low level data on the CS_N pin to form a command to exit the power-down mode in accordance with the SPEC truth table in the command address inversion mode.

[0147] If in the non-command address inversion mode, the command address inversion signal Cai is at a low level. N1 Therefore, at this time, the first N-type transistor T N1The low level voltage VSS connected to the source of the first pull-up circuit 1141 will not be transmitted to the first circuit output terminal 112. The first circuit output terminal 112 can receive the high level signal provided by the first pull-up circuit 1141.

[0148] At this time, the high level signal outputted by the first circuit output terminal 112 of the CA0 to CA4 buffer circuits may be combined with the low level data on the CS_N pin to form a command for exiting the power-down mode in accordance with the SPEC truth table.

[0149] When the power-down mode is exited, the power-down enable reverse signal Enb is at a low level. N2 Therefore, no matter whether it is in the command address inversion mode or not, the first N-type transistor T N1 The low-level voltage VSS connected to the source of the first circuit will not be transmitted to the first circuit output terminal 112. At the same time, the first pull-up circuit 1141 can be set to not output a high-level signal to the first circuit output terminal 112 based on the high level of the power-down enable reverse signal Enb. At the same time, when the power-down mode is exited, the first comparator 113 is turned on, so that the first circuit output terminal 112 can receive the voltage signal output by the first comparator 113 based on the CA pin.

[0150] In one embodiment, the command address buffer circuit further includes a CA12 buffer circuit and a CA13 buffer circuit.

[0151] 4 , the CA12 buffer circuit includes a second command address input terminal 121 , a second circuit output terminal 122 , a second comparator 123 , and a second voltage output circuit 124 .

[0152] The second command address input terminal 121 is connected to the CA12 pin. The second circuit output terminal 122 is used to output a digital signal. The level of the digital signal output by the second circuit output terminal 122 can represent the data output by the CA12 buffer circuit.

[0153] The positive input of the second comparator 123 is connected to the second command address input 121, thereby receiving the voltage on the CA12 pin. The negative input of the second comparator 123 is used to input the reference signal. At this time, the output of the second comparator 123 can output a digital signal based on the comparison between the analog voltage on the CA12 pin and the analog voltage of the reference signal.

[0154] At the same time, the output terminal of the second comparator 123 is connected to the second circuit output terminal 122 , so that the second circuit output terminal 122 can output a digital signal.

[0155] The enable terminal of the second comparator 123 is connected to a second enable signal. The level of the second enable signal is high when the device exits power-down mode and enters non-mirror mode, and is low in all other cases. When the level of the second enable signal is high, the second comparator 123 is turned on. When the level of the second enable signal is low, the second comparator 123 is turned off. Therefore, at this time, the second comparator 123 is turned on only when the device exits power-down mode and enters non-mirror mode. Otherwise, the second comparator 123 is turned off when the device enters either power-down mode or mirror mode.

[0156] The second voltage output circuit 124 is configured to output a high level voltage or a low level voltage to the second circuit output terminal 122 after the memory enters the power-down mode.

[0157] 5 , the CA13 buffer circuit includes a third command address input terminal 131 , a third circuit output terminal 132 , a third comparator 133 , and a third voltage output circuit 134 .

[0158] The third command address input terminal 131 is connected to the CA13 pin. The third circuit output terminal 132 is used to output a digital signal. The level of the digital signal output by the third circuit output terminal 132 can represent the data output by the CA13 buffer circuit.

[0159] The positive input of the third comparator 133 is connected to the third command address input 131, thereby receiving the voltage on the CA13 pin. The negative input of the third comparator 133 is used to input a reference signal. At this time, the output of the third comparator 133 can output a digital signal based on the comparison between the analog voltage on the CA13 pin and the analog voltage of the reference signal.

[0160] At the same time, the output terminal of the third comparator 133 is connected to the third circuit output terminal 132 , so that the third circuit output terminal 132 can output a digital signal.

[0161] The enable terminal of the third comparator 133 receives a third enable signal. The level of the third enable signal is high when the power-down mode is exited and the mirror mode is in operation, and low in all other cases. When the level of the second enable signal is high, the third comparator 133 is turned on. When the level of the second enable signal is low, the third comparator 133 is turned off. Therefore, at this time, the third comparator 133 is turned on only when the power-down mode is exited and the mirror mode is in operation. Otherwise, the second comparator 133 is turned off when either the power-down mode or the non-mirror mode is entered.

[0162] The third voltage output circuit 134 is configured to output a high level voltage or a low level voltage to the third circuit output terminal 132 after the memory enters the power-down mode.

[0163] In this embodiment, by connecting the second enable signal to the enable terminal of the second comparator 123 and connecting the third enable signal to the enable terminal of the third comparator 133, both the CA12 buffer circuit and the CA13 buffer circuit can be turned off after entering the power-down mode, thereby saving power consumption.

[0164] After exiting power-down mode, if the device is in non-mirror mode, the CA12 buffer circuit is open and the CA13 buffer circuit is closed. If the device is in mirror mode, the CA13 buffer circuit is open and the CA12 buffer circuit is closed, effectively mirroring the CA13 buffer circuit with the CA12 buffer circuit. Furthermore, if the device's capacity and process determine that the CA13 pin is not required, the CA13 buffer circuit can be normally closed in non-mirror mode, and the CA12 buffer circuit, which is mirrored with the CA13 buffer circuit, can be normally closed in mirror mode, further saving power.

[0165] At the same time, similar to the first voltage output circuit 114 provided in the CA0 to CA4 buffer circuits, the second voltage output circuit 124 is provided in the CA12 buffer circuit, and the third voltage output circuit 134 is provided in the CA13 buffer circuit. In this case, in non-mirror mode, the second circuit output terminal 122 can output a digital signal even when the second comparator 123 is turned off due to entering power-down mode. Furthermore, in mirror mode, the third circuit output terminal 132 can output a digital signal even when the third comparator 133 is turned off due to entering power-down mode.

[0166] 6 , the CA12 buffer circuit further includes a NOR gate 125. The two output terminals of the NOR gate 125 are connected to the power-down enable reverse signal Enb and the mirror enable signal Mir, respectively, and the output terminals are used to output a second enable signal to the enable terminal of the second comparator 123.

[0167] At this time, the power-down enable reverse signal Enb is high when entering the power-down mode and low when exiting the power-down mode. The mirror enable signal Mir is high when entering the mirror mode and low when entering the non-mirror mode.

[0168] Therefore, at this time, the setting of the NOR gate 125 can effectively achieve that the level of the second enable signal is high when exiting the power-down mode and in the non-mirror mode, and is low in other cases.

[0169] In one embodiment, referring to FIG. 7 , the CA13 buffer circuit further includes an AND gate 135 , whose two output terminals are connected to the power-down enable signal En and the mirror enable signal Mir respectively, and whose output terminal is used as the enable terminal of the third comparator 133 to output the third enable signal.

[0170] At this time, the power-down enable signal En is low when entering the power-down mode and high when exiting the power-down mode. The mirror enable signal Mir is high when entering the mirror mode and low when entering the non-mirror mode.

[0171] Therefore, at this time, the setting of the AND gate 135 can effectively achieve that the level of the third enable signal is high when exiting the power-down mode and in the mirror mode, and is low in other cases.

[0172] In one embodiment, referring to FIG. 4 , the second voltage output circuit 124 includes a second pull-up circuit 1241 and a second pull-down circuit 1242 .

[0173] The second pull-up circuit 1241 includes a third P-type transistor T P3 and the fourth P-type transistor T P4 .

[0174] The third P-type transistor T P3 The gate of the third P-type transistor T is connected to the power-down enable signal En. P3 The source of the fourth P-type transistor T is connected to the high level voltage VDDQ. P4 The gate of the fourth P-type transistor T is connected to the command address inversion signal Cai. P4 The source of the third P-type transistor is connected to the drain of the fourth P-type transistor T P4 The drain is connected to the second circuit output terminal 122.

[0175] The working principle of the second pull-up circuit 1241 is similar to that of the first pull-up circuit 1141 , and will not be described in detail here.

[0176] The second pull-down circuit 1242 includes a third N-type transistor T N3 , the fourth N-type transistor T N4 and a fifth N-type transistor T N5 .

[0177] The third N-type transistor T N3 The gate of the third N-type transistor T is connected to the command address inversion signal Cai. N3 The source of the fourth N-type transistor T is connected to the low level voltage VSS. N4 The gate of the fourth N-type transistor T is connected to the power-down enable reverse signal Enb, N4 The source of the third N-type transistor T N3 The drain of the fourth N-type transistor T N4 The drain is connected to the second circuit output terminal 122.

[0178] The third N-type transistor T of the second pull-down circuit 1242 N3The working principle is similar to that of the first N-type transistor T of the first pull-down circuit 1241. N The working principle of the second pull-down circuit 1242 is similar. N4 The working principle is similar to that of the second N-type transistor T of the first pull-down circuit 1241. N2 The working principle is similar and will not be described here.

[0179] The fifth N-type transistor T N5 The gate of the fifth N-type transistor T is connected to the mirror enable signal Mir. N5 The source of the fifth N-type transistor T is connected to the low level voltage VSS. N5 The drain is connected to the second circuit output terminal 122.

[0180] The level of the mirror enable signal Mir is high when entering the mirror mode and low when entering the non-mirror mode. The low level voltage VSS may be a ground voltage.

[0181] Therefore, when entering the mirror mode, the fifth N-type transistor T N5 The second circuit output terminal 122 may be grounded, thereby effectively reducing the power consumption of the CA12 buffer circuit.

[0182] In one embodiment, referring to FIG. 5 , the third voltage output circuit 134 includes a third pull-up circuit 1341 and a third pull-down circuit 1342 .

[0183] The third pull-up circuit 1341 includes a fifth P-type transistor T P5 and a sixth P-type transistor T P6 .

[0184] The fifth P-type transistor T P5 The gate of the fifth P-type transistor T is connected to the power-down enable signal En. P5 The source is connected to the high level voltage VDDQ.

[0185] The sixth P-type transistor T P6 The gate of the sixth P-type transistor T is connected to the command address inversion signal Cai. P6 The source of the fifth P-type transistor T P5 The drain of the sixth P-type transistor T P6 The drain is connected to the third circuit output terminal 134.

[0186] The working principle of the third pull-up circuit 1341 is similar to that of the first pull-up circuit 1141 , and will not be described in detail here.

[0187] The third pull-down circuit 1342 includes a sixth N-type transistor T N6 , the seventh N-type transistor T N7and an eighth N-type transistor T N8 .

[0188] The sixth N-type transistor T N6 The gate of the sixth N-type transistor T is connected to the command address inversion signal Cai. N6 The source of the seventh N-type transistor T is connected to the low level voltage VSS. N7 The gate of the seventh N-type transistor T is connected to the power-down enable reverse signal Enb, N7 The source of the sixth N-type transistor T N6 The drain of the seventh N-type transistor T N7 The drain is connected to the third circuit output terminal 134.

[0189] The sixth N-type transistor T of the third pull-down circuit 1342 N6 The working principle is similar to that of the first N-type transistor T of the first pull-down circuit 1241. N The working principle of the seventh N-type transistor T of the second pull-down circuit 1242 is similar. N7 The working principle is similar to that of the second N-type transistor T of the first pull-down circuit 1241. N2 The working principle is similar and will not be described here.

[0190] The eighth N-type transistor T N8 The gate of the eighth N-type transistor T is connected to the mirror enable reverse signal Mirb. N8 The source of the eighth N-type transistor T is connected to the low level voltage VSS. N8 The drain is connected to the third circuit output terminal 134.

[0191] The level of the mirror enable reverse signal Mirb is low when entering the mirror mode and high when entering the non-mirror mode. The low level voltage VSS may be a ground voltage.

[0192] Therefore, when entering the non-mirror mode, the eighth N-type transistor T N8 The third circuit output terminal 134 may be grounded, thereby effectively reducing the power consumption of the CA13 buffer circuit.

[0193] In the description of this specification, reference to the terms "one embodiment," "other embodiments," etc., means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0194] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0195] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A buffer circuit (100), applied to a memory, characterized in that: It includes a CA0 buffer circuit, a CA1 buffer circuit, a CA2 buffer circuit, a CA3 buffer circuit and a CA4 buffer circuit, wherein the CA0 buffer circuit, the CA1 buffer circuit, the CA2 buffer circuit, the CA3 buffer circuit and the CA4 buffer circuit all include: A first command address input terminal (111) is connected to a command address pin, and different CA buffer circuits are connected to different command address pins; A first circuit output terminal (112), used for outputting a digital signal; a first comparator (113), wherein a positive input terminal is connected to the first command address input terminal (111), a negative input terminal receives a reference signal, an enable terminal receives a power-down enable signal, and an output terminal is connected to the first circuit output terminal (112); after the memory enters the power-down mode, the first comparator (113) is turned off based on the level of the power-down enable signal; The first voltage output circuit (114) is used to output a high level voltage or a low level voltage to the first circuit output terminal (112) after the memory enters a power-down mode.

2. The buffer circuit (100) according to claim 1, characterized in that: The first voltage output circuit (114) comprises: A first pull-up circuit (1141), connected to the first circuit output terminal (112), and configured to output the high-level voltage to the first circuit output terminal (112); A first pull-down circuit (1142) is connected to the first circuit output terminal (112) and is used to output the low-level voltage to the first circuit output terminal (112).

3. The buffer circuit (100) according to claim 2, characterized in that: The first pull-up circuit (1141) comprises: A first switch unit has one end connected to the first circuit output end (112) and the other end connected to the high level voltage.

4. The buffer circuit (100) according to claim 3, characterized in that: The first switch unit comprises: A first P-type transistor, a gate of which is connected to the power-down enable signal, and a source of which is connected to the high-level voltage; The second P-type transistor has a gate connected to the command address inversion signal, a source connected to the drain of the first P-type transistor, and a drain connected to the output end of the first circuit.

5. The buffer circuit (100) according to any one of claims 2 to 4, characterized in that: The first pull-down circuit (1142) comprises: A second switch unit has one end connected to the first circuit output end (112) and the other end connected to the low level voltage.

6. The buffer circuit (100) according to claim 5, characterized in that: The second switch unit comprises: A first N-type transistor, a gate of which is connected to the command address inversion signal, and a source of which is connected to the low level voltage; The second N-type transistor has a gate connected to a power-off enable reverse signal, a source connected to the drain of the first N-type transistor, and a drain connected to the output end of the first circuit. The power-off enable reverse signal has a level opposite to that of the power-off enable signal.

7. The buffer circuit (100) according to any one of claims 1 to 6, characterized in that: The command address buffer circuit also includes a CA12 buffer circuit and a CA13 buffer circuit. The CA12 buffer circuit comprises: The second command address input terminal (121) is connected to the CA12 pin; A second circuit output terminal (122) for outputting a digital signal; A second comparator (123), wherein the positive input terminal is connected to the second command address input terminal (121), the negative input terminal is used to input a reference signal, the output terminal is connected to the second circuit output terminal (122), and the enable terminal is connected to a second enable signal, the level of the second enable signal is high when exiting the power-down mode and in the non-mirror mode, and is low in other cases; A second voltage output circuit (124), configured to output the high level voltage or the low level voltage to the second circuit output terminal (122) after the memory enters a power-down mode; The CA13 buffer circuit comprises: A third command address input terminal (131), connected to the CA13 pin; A third circuit output terminal (132), used for outputting a digital signal; A third comparator (133), wherein the positive input terminal is connected to the third command address input terminal (131), the reverse input terminal is used to input a reference signal, the output terminal is connected to the third circuit output terminal (132), and the enable terminal is connected to a third enable signal, the level of the third enable signal is high when exiting the power-down mode and in the mirror mode, and is low in other cases; The third voltage output circuit (134) is used to output the high level voltage or the low level voltage to the third circuit output terminal (132) after the memory enters the power-down mode.

8. The buffer circuit (100) according to claim 7, characterized in that: The CA12 buffer circuit further comprises a NOR gate (125), two output ends of the NOR gate (125) are respectively connected to the power-off enable reverse signal and the mirror enable signal, and the output end is used to output the second enable signal to the enable end of the second comparator (123).

9. The buffer circuit (100) according to any one of claims 7 to 8, characterized in that: The CA13 buffer circuit further comprises an AND gate (135), two output ends of the AND gate (135) are respectively connected to a power-off enable signal and a mirror enable signal, and the output end is used for the enable end of the third comparator (133) to output the third enable signal.

10. The buffer circuit (100) according to any one of claims 7 to 9, characterized in that: The second voltage output circuit (124) comprises a second pull-up circuit (1241) and a second pull-down circuit (1242). The second pull-up circuit (1241) comprises: A third P-type transistor, a gate of which is connected to the power-down enable signal, and a source of which is connected to the high-level voltage; a fourth P-type transistor, the gate of which is connected to the command address inversion signal, the source of which is connected to the drain of the third P-type transistor, and the drain of which is connected to the output terminal (122) of the second circuit; The second pull-down circuit (1242) comprises: A third N-type transistor, a gate of which is connected to the command address inversion signal, and a source of which is connected to the low level voltage; a fourth N-type transistor, the gate of which is connected to a power-off enable reverse signal, the source of which is connected to the drain of the third N-type transistor, and the drain of which is connected to the second circuit output terminal (122), the power-off enable reverse signal being a reverse signal of the power-off enable signal; A fifth N-type transistor, having a gate connected to the mirror enable signal, a source connected to the low level voltage, and a drain connected to the second circuit output terminal (122).

11. The buffer circuit (100) according to any one of claims 7 to 10, characterized in that: The third voltage output circuit (134) comprises a third pull-up circuit (1341) and a third pull-down circuit (1342). The third pull-up circuit (1341) comprises: a fifth P-type transistor, a gate of which is connected to the power-down enable signal, and a source of which is connected to the high-level voltage; a sixth P-type transistor, the gate of which is connected to the command address inversion signal, the source of which is connected to the drain of the fifth P-type transistor, and the drain of which is connected to the output terminal (132) of the third circuit; The third pull-down circuit (1342) comprises: A sixth N-type transistor, a gate of which is connected to the command address inversion signal, and a source of which is connected to the low level voltage; a seventh N-type transistor, the gate of which is connected to the power-off enable reverse signal, the source of which is connected to the drain of the sixth N-type transistor, and the drain of which is connected to the output terminal (132) of the third circuit, the power-off enable reverse signal having a level opposite to that of the power-off enable signal; An eighth N-type transistor has a gate connected to a mirror enable reverse signal, a source connected to the low level voltage, and a drain connected to the third circuit output terminal (132), wherein the mirror enable reverse signal has a level opposite to that of the mirror enable signal.

12. The buffer circuit (100) according to any one of claims 1 to 11, characterized in that: The command address buffer circuit further includes a CA5 to CA11 buffer circuit, and the CA5 to CA11 buffer circuit has the same circuit structure as the CA0 to CA4 buffer circuit.

13. A memory, characterized in that: include: The buffer circuit (100) according to any one of claims 1 to 12; A command address buffer control circuit (200), connected to the buffer circuit (100), and configured to output the power-off enable signal to the buffer circuit (100); A decoder circuit (300) is connected to the command address buffer control circuit (200) and is used to send a power-down mode exit command to the command address buffer control circuit (200).

14. The memory according to claim 13, characterized in that: The memory also includes: The address mirror circuit (400) is connected to the buffer circuit (100) and is used to send a mirror enable signal to the buffer circuit (100).

15. The memory according to any one of claims 13 to 14, characterized in that: The memory also includes: A command address inversion pin (500) is connected to the buffer circuit (100) and is used to send a command address inversion signal to the buffer circuit (100).

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