Display panel and display apparatus

Abstract

Provided is a display panel, comprising: a base substrate, which comprises at least one side area and a display area; a plurality of pixel units, which are arranged in the display area, wherein at least one of the pixel units comprises a light emitting diode; a plurality of terminals, which are arranged on the base substrate and are located in the side area; and a plurality of traces, which are arranged on the base substrate, wherein one end of at least one of the traces is electrically connected to the terminal, and the other end thereof is electrically connected to the light emitting diode. The display panel further comprises: a first conductive layer, a first passivation layer and a second conductive layer, which are sequentially arranged on the base substrate, wherein the plurality of traces are located in the first conductive layer, the plurality of terminals are located in the second conductive layer, and an orthographic projection of at least one of the terminals on the base substrate falls within an orthographic projection of the first passivation layer on the base substrate.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display device, and a method for manufacturing a display panel. Background Art

[0002] Light emitting diode (LED) technology has been developed for nearly three decades, and its application range continues to expand. For example, it can be used in the display field as a backlight source for display devices or in LED display screens. With the development of technology, sub-millimeter light emitting diodes (Mini LED) and micro light emitting diodes (Micro LED) have gradually become a research hotspot in the field of display technology. For example, Mini LED or Micro LED can be used in the light-emitting modules of liquid crystal display devices as the light-emitting elements of the light-emitting modules.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display panel is provided, wherein the display panel includes: a substrate, the substrate including at least one side region and a display region, the at least one side region being closer to a side edge of the substrate than the display region; a plurality of pixel units disposed in the display region, the plurality of pixel units being distributed in an array on the substrate along a first direction and a second direction, at least one of the pixel units including a light-emitting diode; a plurality of terminals disposed on the substrate and located in the side region, the plurality of terminals being distributed at intervals along the side edge of the substrate; and a plurality of traces disposed on the substrate, at least one of the traces having one end electrically connected to the terminal and the other end electrically connected to the light-emitting diode, wherein the display panel includes: a first conductive layer disposed on the substrate, wherein the plurality of traces are located in the first conductive layer; a first passivation layer disposed on a side of the first conductive layer away from the substrate; and a second conductive layer disposed on a side of the first passivation layer away from the substrate, wherein the terminal is located in the second conductive layer, and wherein an orthographic projection of at least one of the terminals on the substrate falls within an orthographic projection of the first passivation layer on the substrate.

[0006] According to some exemplary embodiments, the first passivation layer includes a plurality of protrusions, and orthographic projections of the plurality of terminals on the base substrate respectively fall within orthographic projections of the plurality of protrusions on the base substrate.

[0007] According to some exemplary embodiments, the multiple terminals include a first terminal, the multiple routings include a first routing, the first routing is used to transmit a ground signal, the first terminal is electrically connected to the first routing; and the orthographic projection of the first terminal on the substrate falls within the orthographic projection of the first passivation layer on the substrate.

[0008] According to some exemplary embodiments, the orthographic projection of the first terminal on the substrate includes a first side edge close to the side edge of the substrate; and the first passivation layer includes a first protrusion, the orthographic projection of the first protrusion on the substrate includes a second side edge close to the side edge of the substrate, the orthographic projection of the first terminal on the substrate falls within the orthographic projection of the first protrusion on the substrate, and in a second direction, the second side edge is closer to the side edge of the substrate than the first side edge, wherein the second direction is perpendicular to the side edge of the substrate.

[0009] According to some exemplary embodiments, a size of an orthographic projection of the first protrusion on the base substrate along a first direction is larger than a size of an orthographic projection of the first terminal on the base substrate along the first direction, wherein the first direction is parallel to a side edge of the base substrate.

[0010] According to some exemplary embodiments, the multiple pixel units respectively include a first light-emitting diode, a second light-emitting diode and a third light-emitting diode, the first light-emitting diode is used to emit light of a first color, the second light-emitting diode is used to emit light of a second color, and the third light-emitting diode is used to emit light of a third color; the multiple wires also include a second wire and a third wire, the second wire is used to transmit a first voltage signal to the second light-emitting diode and the third light-emitting diode, and the third wire is used to transmit a second voltage signal to the first light-emitting diode; and the multiple terminals also include a second terminal and a third terminal, the second terminal is electrically connected to the second wire, and the third terminal is electrically connected to the third wire.

[0011] According to some exemplary embodiments, an orthographic projection of at least one of the second terminal and the third terminal on the base substrate falls within an orthographic projection of the first passivation layer on the base substrate.

[0012] According to some exemplary embodiments, the orthographic projection of the second terminal on the substrate includes a third side close to the side edge of the substrate; and the first passivation layer includes a second protrusion, the orthographic projection of the second protrusion on the substrate includes a fourth side close to the side edge of the substrate, and in the second direction, the fourth side is closer to the side edge of the substrate than the third side.

[0013] According to some exemplary embodiments, the orthographic projection of the third terminal on the substrate includes a fifth side close to the side edge of the substrate; and the first passivation layer includes a third protrusion, the orthographic projection of the third protrusion on the substrate includes a sixth side close to the side edge of the substrate, and in the second direction, the sixth side is closer to the side edge of the substrate than the fifth side.

[0014] According to some exemplary embodiments, an orthographic projection of at least one of the second terminal and the third terminal on the base substrate partially overlaps with an orthographic projection of the first passivation layer on the base substrate.

[0015] According to some exemplary embodiments, the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer, the second sub-passivation layer is located on a side of the first sub-passivation layer away from the base substrate; the display panel also includes a first covering layer, the first covering layer is located between the first sub-passivation layer and the second sub-passivation layer; and the orthographic projection of at least one of the terminals on the base substrate falls within the orthographic projection of each of the first sub-passivation layer and the second sub-passivation layer on the base substrate, and the orthographic projection of at least one of the terminals on the base substrate partially overlaps with the orthographic projection of the first covering layer on the base substrate.

[0016] According to some exemplary embodiments, the display panel also includes a second passivation layer, which is located on a side of the second conductive layer away from the base substrate; and the orthographic projection of the first passivation layer on the base substrate includes a seventh side close to the side edge of the base substrate, and the orthographic projection of the second passivation layer on the base substrate includes an eighth side close to the side edge of the base substrate, and in the second direction, the eighth side is closer to the side edge of the base substrate than the seventh side.

[0017] According to some exemplary embodiments, the second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer, the fourth sub-passivation layer is located on a side of the third sub-passivation layer away from the base substrate; the display panel also includes a second covering layer, the second covering layer is located between the third sub-passivation layer and the fourth sub-passivation layer; and the orthographic projection of at least one of the terminals on the base substrate partially overlaps with the orthographic projection of the second covering layer on the base substrate.

[0018] According to some exemplary embodiments, the display panel includes a plurality of vias penetrating the second passivation layer and the second covering layer, the plurality of vias respectively exposing at least a portion of the plurality of terminals; and an orthographic projection of at least one of the vias on the base substrate partially overlaps with an orthographic projection of at least one of the protrusions on the base substrate.

[0019] According to some exemplary embodiments, the multiple vias passing through the second passivation layer and the second covering layer include a first via, the orthographic projection of the first via on the base substrate partially overlapping with the orthographic projection of the first protrusion on the base substrate; the display panel also includes a second via passing through the first passivation layer and the first covering layer, the first terminal is electrically connected to the first trace through the second via; and the orthographic projection of the first via on the base substrate and the orthographic projection of the second via on the base substrate are at least partially aligned along a first direction.

[0020] According to some exemplary embodiments, the multiple vias passing through the second passivation layer and the second covering layer include a third via, the orthographic projection of the third via on the base substrate partially overlapping with the orthographic projection of the second protrusion on the base substrate; the display panel also includes a fourth via passing through the first passivation layer and the first covering layer, the second terminal is electrically connected to the second trace through the fourth via; and the orthographic projection of the third via on the base substrate and the orthographic projection of the fourth via on the base substrate are spaced apart along the second direction.

[0021] According to some exemplary embodiments, the multiple vias passing through the second passivation layer and the second covering layer include a fifth via, the orthographic projection of the fifth via on the base substrate partially overlapping with the orthographic projection of the third protrusion on the base substrate; the display panel also includes a sixth via passing through the first passivation layer and the first covering layer, the third terminal is electrically connected to the third trace through the sixth via; and the orthographic projection of the fifth via on the base substrate and the orthographic projection of the sixth via on the base substrate are at least partially aligned along a first direction.

[0022] According to some exemplary embodiments, an orthographic projection of the first passivation layer on the base substrate includes a side edge close to a side edge of the base substrate, and the side edge includes a shape selected from the group consisting of a wall shape, a sawtooth shape, a wave shape, and a continuous broken line shape.

[0023] According to some exemplary embodiments, at least one of the terminals includes a terminal body and a nickel-gold plating layer, the terminal body is located in the second conductive layer, and the nickel-gold plating layer is located on a surface of the terminal body away from the base substrate.

[0024] On the other hand, a display panel is provided, wherein the display panel includes: a substrate, the substrate including at least one side region and a display region, the at least one side region being closer to the side edge of the substrate than the display region; a plurality of pixel units arranged in the display region, the plurality of pixel units being distributed in an array on the substrate, at least one of the pixel units including a light emitting diode; a plurality of terminals arranged on the substrate and located in the side region, the plurality of terminals being distributed at intervals along the side edge of the substrate; a plurality of traces arranged on the substrate, at least one of the traces being electrically connected to the terminal at one end and electrically connected to the terminal at the other end. The light-emitting diode; and a lead arranged on the base substrate, one end of the lead being electrically connected to the terminal, and the lead extending from the terminal toward the side edge of the base substrate, wherein the display panel comprises: a first conductive layer arranged on the base substrate, wherein the multiple traces are located in the first conductive layer; a first passivation layer arranged on a side of the first conductive layer away from the base substrate; and a second conductive layer arranged on a side of the first passivation layer away from the base substrate, wherein the terminal is located in the second conductive layer, and wherein the orthographic projection of at least one of the terminals on the base substrate falls within the orthographic projection of the first passivation layer on the base substrate.

[0025] In yet another aspect, a display device is provided, wherein the display device includes the display panel as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0027] FIG1 is a top view of a display panel according to some exemplary embodiments of the present disclosure;

[0028] FIG2 is a schematic plan view of a display panel during processing according to some exemplary embodiments of the present disclosure;

[0029] FIG3 is a cross-sectional view of a display panel according to some exemplary embodiments of the present disclosure taken along line AA′ in FIG2 ;

[0030] FIG4 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure;

[0031] FIG5 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing an electrical connection structure of a plurality of pixel units, a plurality of wirings, and a plurality of terminals;

[0032] 6A and 6B are schematic plan views of display panels according to some embodiments of the present disclosure, and FIG. 7 is a schematic plan view of display panels according to other embodiments of the present disclosure, wherein FIG. 6A , FIG. 6B and FIG. 7 have different first passivation layer structure designs;

[0033] FIG8 is a planar structural diagram of a first passivation layer and a first covering layer in some other embodiments of the present disclosure;

[0034] FIG9 is a planar structural diagram of the first passivation layer and the second passivation layer in some other embodiments of the present disclosure;

[0035] FIG10 is a planar structural diagram of a second passivation layer and a second covering layer in some other embodiments of the present disclosure;

[0036] FIG11 is a plan view of a display panel according to some other embodiments of the present disclosure, showing a plurality of via structures;

[0037] 12 and 13 are plan views of display panels according to other embodiments of the present disclosure, wherein FIG. 12 and FIG. 13 illustrate edge structures of a first passivation layer;

[0038] FIG14 is a cross-sectional view of a display panel at a terminal according to some other embodiments of the present disclosure;

[0039] FIG15A is a partial enlarged view of a terminal defect of a display panel; FIG15B is a SEM image of the terminal defect shown in FIG15A;

[0040] FIG16 is a SEM image of one terminal in a display panel according to some exemplary embodiments of the present disclosure;

[0041] FIG17 is a schematic plan view of a display panel according to other exemplary embodiments of the present disclosure; and

[0042] FIG18 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, which shows a schematic view of at least two small screens spliced ​​together to form a large display screen. DETAILED DESCRIPTION

[0043] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0044] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0045] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on the other element, directly connected to the other element, or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent," or "on..." versus "directly on...", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0046] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0047] In this article, inorganic light-emitting diodes refer to light-emitting elements made of inorganic materials, where LED represents an inorganic light-emitting element that is different from OLED. Specifically, inorganic light-emitting elements can include sub-millimeter light-emitting diodes (Mini Light Emitting Diode, abbreviated as Mini LED in English) and micro light-emitting diodes (Micro LED in English). Among them, micro light-emitting diodes (i.e. Micro LEDs) refer to ultra-small light-emitting diodes with a grain size of less than 100 microns, and sub-millimeter light-emitting diodes (i.e. Mini LEDs) refer to small light-emitting diodes with a grain size between Micro LEDs and traditional LEDs. For example, the grain size of Mini LEDs can be between 50 and 400 microns.

[0048] With the development of technology, the development momentum of LED display devices is relatively fast. For example, they are gradually being used in outdoor displays and large-screen displays for central control. In the application scenario of outdoor displays, the size of the display screen used is usually large, and it is mainly used for users to watch from a distance. The commonly used technology at present is to splice multiple small screens into a large screen. The inventors have found through research that in order to display narrow gaps or seamless splicing, the size design and spatial layout of the connection lines are crucial to the imaging effect and stability of the display panel. When the existing display panels are leading out the connection lines, there is often a step difference in the film layer below some areas of the lead-out lines, which leads to corrosion or even fracture of the film layer during the preparation process and subsequent other film layer processes, thereby causing further deviations in the subsequent film layer preparation, resulting in poor connection of the display circuit, and the occurrence of open circuits or short circuits. Based on this, in the process of splicing multiple small screens into a large screen, it is necessary to optimize the design of the lead-out and connection of the lines, and provide a sufficiently stable electrical connection while occupying as little space as possible, so as to improve the reliability of the display panel.

[0049] FIG1 schematically shows a plan view of a display panel.

[0050] Referring to Figure 1 , a display panel includes a substrate 1. The substrate 1 includes at least one display area 2, a side area 3, and a side edge 4 of the substrate. The side edge 4 of the substrate is parallel to a first direction as shown in Figure 1 , and the distance between the side area 4 and the side edge 4 is less than the distance between the display area 2 and the side edge 4 of the substrate. Multiple pixel units 5 are disposed in the display area 2 and arranged in an array on the substrate 1. At least one of the pixel units comprises a light-emitting diode (LED). The LED may comprise a sub-millimeter LED or a micro-LED, which may employ a LED chip structure. Multiple terminals 6 are disposed on the substrate 1 and located in the side area 3. The terminals are spaced apart along a first direction D1 within the side area 3. Multiple traces 7 are disposed on the substrate 1. At least one of the traces 7 is electrically connected at one end to the terminal 6 and at the other end to a driver circuit for the pixel unit 5. The driver circuit for the pixel unit 5 may comprise at least one transistor, which may include a source, a gate, a drain, and an active layer. For example, the transistor can have a dual-gate structure, which can include a first gate located below the active layer and a second gate located above the active layer. In a narrow-slit or seamless connection scheme, the terminal 6 formed on the base substrate 1 of the display panel is used to export data signals, power signals, scan signals and other signals on the display panel to the side of the display panel or the back of the display panel, and a driver chip or driver circuit board is bound to the side of the display panel or the back of the display panel to achieve control of the display panel. In a narrow-slit or seamless splicing scheme, the design of the terminal 6 located on the front of the display panel is more important. On the one hand, the size of the terminal 6 should not be too large. If the terminal 6 is too large, it will easily cause the side area to occupy too much space, and the non-display area in the spliced ​​large screen will become larger, thereby affecting the display effect; on the other hand, the conductive performance of the terminal 6 must be good enough to form a good electrical connection with the external driver chip or driver circuit board and the multiple traces 7 on the front of the display panel, so as to achieve real-time control of the display panel by the external driver circuit board or driver chip.

[0051] In the exemplary embodiment of FIG1 , a first direction D1 and a second direction D2 are schematically shown. For example, a plurality of pixel units may be arranged in an array along the first direction D1 and the second direction D2. It should be noted that the embodiments of the present disclosure are not limited thereto.

[0052] FIG. 2 is a schematic plan view illustrating a display panel during processing according to some exemplary embodiments of the present disclosure.

[0053] 2 , the display panel includes: a base substrate 1; a first conductive layer 8 located on the base substrate 1; a plurality of traces 7, wherein the traces 7 are located in the first conductive layer 8; a first passivation layer 9 located on a side of the first conductive layer 8 away from the base substrate 1; a second conductive layer 10 located on a side of the first passivation layer 9 away from the base substrate 1; and a plurality of terminals 6 located in the second conductive layer 10. The orthographic projections of the plurality of terminals 6 on the base substrate 1 fall within the orthographic projections of the side regions 3 on the base substrate 1, and the plurality of terminals 6 are spaced apart in the side regions 3. The terminals 6 can have various shapes, such as a rectangle, square, trapezoid, triangle, circle, ellipse, or polygon.

[0054] The inventor has found through research that in the narrow gap or seamless splicing scheme, in the process of depositing the second conductive layer 10, due to the step difference at the edge of the first passivation layer 9 below the second conductive layer 10, it may cause film cracks or excessive bottom etching in the local area of ​​the second conductive layer 10 overlapping with the step difference, resulting in uneven bottom of the film layer, which in turn causes poor electrical performance of some terminals 6 located at defects such as film cracks or bottom etching, or film structure defects of at least part of the terminals 6, which in turn causes in subsequent processes, such as when depositing the nickel-gold layer by the nickel-gold process, the gold solution penetrates into the cracks of the second conductive layer 10 or the uneven gaps of the second conductive layer 10, resulting in abnormal gold growth during gold deposition, causing short circuit or open circuit in the electrical connection between some terminals 6 and multiple traces 7 or external driver circuit boards or driver chips, resulting in poor display.

[0055] To this end, in an embodiment of the present disclosure, the edge structure of the first passivation layer 9 is designed to be protruding, so that the orthographic projection of at least one of the terminals 6 on the base substrate 1 falls within the orthographic projection of the first passivation layer 9 on the base substrate 1, thereby avoiding the occurrence of a step difference in the first passivation layer 9 under at least one of the terminals, which is beneficial to improving the film layer quality of the terminal, ensuring that the terminal forms a good electrical connection with the corresponding wiring and external driving circuit, and improving the reliability of the display panel.

[0056] In an embodiment of the present disclosure, as shown in Figure 2, the edge of the first passivation layer 9 is shown to have a plurality of first passivation layer protrusions 91 corresponding to the plurality of terminals, so that the orthographic projection of the plurality of terminals 6 on the base substrate 1 falls within the orthographic projection of the first passivation layer 9 on the base substrate 1, reducing or eliminating the step difference of the lower film layer during the process of the plurality of terminals 6, thereby avoiding the occurrence of at least part of the film layer of the plurality of terminals 6 cracks or uneven bottom concave portions caused by excessive etching when forming the plurality of terminals 6, improving the film layer quality of the plurality of terminals 6, thereby facilitating the subsequent process, and further improving the conductive performance of the plurality of terminals 6, avoiding the occurrence of open circuit or short circuit.

[0057] FIG. 3 illustrates a cross-sectional view of a display panel taken along line AA′ in FIG. 2 according to some exemplary embodiments of the present disclosure.

[0058] Referring to Figure 3 , the display panel includes: a base substrate 1; a buffer layer 12 located on the base substrate 1; a first conductive layer 8 located on a side of the buffer layer 12 away from the base substrate 1; and a first passivation layer 9 located on a side of the first conductive layer 8 away from the base substrate 1. A portion of the first passivation layer 9 may cover the surface of the first conductive layer 8 away from the base substrate 1, while another portion may cover the surface of the buffer layer 12 away from the base substrate 1. The display panel includes multiple vias extending through the first passivation layer 9, each of which exposes at least a portion of the first conductive layer 8. The display panel also includes a second conductive layer 10 located on a side of the first passivation layer 9 away from the base substrate 1. At least a portion of the second conductive layer 10 is electrically connected to a portion of the first conductive layer 8 via the multiple vias in the first passivation layer 9. The display panel also includes a second passivation layer 11 located on a side of the second conductive layer 8 away from the base substrate 1. The display panel also includes multiple vias extending through the second passivation layer 11, each of which exposes at least a portion of the multiple terminals 6.

[0059] FIG. 4 shows a partial plan view of a display panel according to some other exemplary embodiments of the present disclosure.

[0060] 4 , the display panel includes: a base substrate 1; a plurality of terminals 6, including a first terminal 61. The display panel also includes a plurality of traces 7, including a first trace 71. The first trace 71 is configured to transmit a ground signal, and the first terminal 61 is electrically connected to the first trace 71. The orthographic projection of the first terminal 61 on the base substrate 1 falls within the orthographic projection of the first passivation layer 9 on the base substrate 1. The orthographic projection of the first terminal 61 on the base substrate 1 includes a first side edge 611 proximate to the side edge 4 of the base substrate. The first passivation layer 9 includes a first passivation layer protrusion 91, which includes a first protrusion 911. The orthographic projection of the first protrusion 911 on the substrate 1 includes a second side edge 9111 close to the side edge 4 of the substrate; the orthographic projection of the first terminal 61 on the substrate 1 falls within the orthographic projection of the first protrusion 911 on the substrate 1, and in the second direction D2, the second side edge 9111 is closer to the side edge 4 of the substrate than the first side edge 611, wherein the second direction is perpendicular to the side edge 4 of the substrate.

[0061] For example, in the display panel, the orthographic projection of the first protrusion 911 onto the base substrate 1 along a first direction D1 is a first predetermined distance L1, and the orthographic projection of the first terminal 61 onto the base substrate 1 along the first direction D1 is a second predetermined distance L2. In the disclosed embodiment, the first predetermined distance L1 is greater than the second predetermined distance L2. The first direction D1 is parallel to the side edge 4 of the base substrate.

[0062] FIG5 shows a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing a plurality of pixel units, a plurality of wirings, and an electrical connection structure of a plurality of terminals.

[0063] With reference to Figures 1 and 5, a display panel includes: a base substrate 1, a display area 2, and a plurality of pixel units 5, wherein the plurality of pixel units 5 are located within the display area 2 on the base substrate 1. The plurality of pixel units 5 include a first light-emitting diode 51, a second light-emitting diode 52, and a third light-emitting diode 53, respectively. The first light-emitting diode 51 is configured to emit light of a first color, the second light-emitting diode 52 is configured to emit light of a second color, and the third light-emitting diode is configured to emit light of a third color. The first light-emitting diode 51, the second light-emitting diode 52, and the third light-emitting diode 53 may be of the same or different sizes. The sizes of the first light-emitting diode 51, the second light-emitting diode 52, and the third light-emitting diode 53 may also be regularly distributed on the base substrate 1 with the same or different pixel densities according to actual needs. For example, in an embodiment of the present disclosure, the display panel further includes a plurality of traces 7, as shown in Figure 5. The plurality of traces further include a second trace 72 and a third trace 73. The second trace 72 is configured to transmit a first voltage signal to the second light-emitting diode 52 and the third light-emitting diode 53, and the third trace 73 is configured to transmit a second voltage signal to the first light-emitting diode. The display panel further includes a plurality of terminals 6, which further include a second terminal 62 and a third terminal 63. The second terminal 62 is electrically connected to the second trace 72, and the third terminal 63 is electrically connected to the third trace 73. The second terminal 62 and the third terminal 63 are respectively connected to an external driver circuit board or driver chip to control the lighting state of the light-emitting diodes and achieve different display effects.

[0064] 6A and 6B are plan view schematic diagrams of display panels according to some embodiments of the present disclosure, and FIG. 7 is a plan view schematic diagram of display panels according to other embodiments of the present disclosure, wherein FIG. 6A , FIG. 6B and FIG. 7 have different first passivation layer structure designs.

[0065] Referring to FIG6A , a display panel includes a substrate 1, a first passivation layer 9, and a plurality of terminals 6. The plurality of terminals 6 include a second terminal 62 and a third terminal 63, wherein an orthographic projection of at least one of the second terminal 62 and the third terminal 63 on the substrate 1 falls within an orthographic projection of the first passivation layer 9 on the substrate 1. The orthographic projection of the second terminal 62 on the substrate 1 falls within an orthographic projection of the first passivation layer 9 on the substrate 1, and the orthographic projection of the third terminal 63 on the substrate 1 partially overlaps with the orthographic projection of the first passivation layer 9 on the substrate 1. The orthographic projection of the second terminal 62 on the substrate 1 includes a third side 621 proximate to the side edge 4 of the substrate, the first passivation layer 9 includes a second protrusion 912, and the orthographic projection of the second protrusion 912 on the substrate 1 includes a fourth side 9121 proximate to the side edge 4 of the substrate. In a second direction D2, the fourth side 9121 is closer to the side edge 4 of the substrate than the third side 621.

[0066] In some other embodiments, as shown in FIG. 7 , the orthographic projections of the second terminal 62 and the third terminal 63 on the base substrate 1 partially overlap with the orthographic projection of the first passivation layer 9 on the base substrate 1 .

[0067] In addition to the two first passivation layer structural designs shown in Figures 6A and 7 above, the first passivation layer may also have other structural designs. For example, as shown in Figure 4, the orthographic projection of the second terminal 62 on the substrate 1 partially overlaps with the orthographic projection of the first passivation layer 9 on the substrate 1, and the orthographic projection of the third terminal 63 on the substrate 1 falls within the first passivation layer 9. With reference to Figure 6B, the orthographic projection of the third terminal 63 on the substrate 1 includes a fifth side 631 close to the side edge 4 of the substrate, the first passivation layer 9 includes a third protrusion 913, and the orthographic projection of the third protrusion 913 on the substrate includes a sixth side 9131 close to the side edge 4 of the substrate. In the second direction D2, the sixth side 9131 is closer to the side edge 4 of the substrate than the fifth side 631.

[0068] In other embodiments, as shown in FIG5 , the orthographic projections of the second terminal 62 and the third terminal 63 on the base substrate 1 both fall within the orthographic projection of the first passivation layer 9 on the base substrate 1. With reference to FIG6A , the orthographic projection of the second terminal 62 on the base substrate 1 includes a third side 621 proximate to the side edge 4 of the base substrate, the first passivation layer 9 includes a second protrusion 912, and the orthographic projection of the second protrusion 912 on the base substrate 1 includes a fourth side 9121 proximate to the side edge 4 of the base substrate. In the second direction D2, the fourth side 9121 is closer to the side edge 4 of the base substrate than the third side 621. 6B , the orthographic projection of the third terminal 63 on the substrate 1 includes a fifth side 631 close to the side edge 4 of the substrate, the first passivation layer 9 includes a third protrusion 913, and the orthographic projection of the third protrusion 913 on the substrate includes a sixth side 9131 close to the side edge 4 of the substrate. In the second direction D2, the sixth side 9131 is closer to the side edge 4 of the substrate than the fifth side 631.

[0069] FIG8 is a planar structural diagram of the first passivation layer and the first covering layer in some other embodiments of the present disclosure.

[0070] Referring to Figure 8 , the display panel includes: a base substrate 1; a first passivation layer 9, wherein the first passivation layer 9 includes a first sub-passivation layer 92 and a second sub-passivation layer 93. The second sub-passivation layer 93 is located on the side of the first sub-passivation layer 92 away from the base substrate 1. The orthographic projections of the first sub-passivation layer 92 and the second sub-passivation layer 93 on the base substrate 1 may completely overlap or partially overlap. The first sub-passivation layer 92 and the second sub-passivation layer 93 may be made of the same material or different materials. The processes for preparing the first sub-passivation layer 92 and the third sub-passivation layer 93 may be the same or different. By superimposing the first sub-passivation layer 92 and the second sub-passivation layer 93, the thickness of the first passivation layer in a direction perpendicular to the base substrate 1 can be increased, thereby improving the passivation effect of the first passivation layer 9 on the first conductive layer. The display panel also includes a first cover layer 13, which is located between the first sub-passivation layer 92 and the second sub-passivation layer 93. The first cover layer 13 may be a planar layer or an insulating layer. The display panel further includes a plurality of vias penetrating the first sub-passivation layer 92, the first cover layer 13, and the second sub-passivation layer 93, through which electrical connection between the first conductive layer 8 and the second conductive layer 9 can be achieved. The orthographic projection of the first cover layer 13 on the base substrate 1 falls within the orthographic projection of the first sub-passivation layer 92 on the base substrate 1. The display panel further includes a plurality of terminals 6, wherein the orthographic projection of at least one terminal on the base substrate 1 falls within the orthographic projection of each of the first sub-passivation layer 92 and the second sub-passivation layer 93 on the base substrate 1, and the orthographic projection of at least one terminal on the base substrate 1 partially overlaps with the orthographic projection of the first cover layer 13 on the base substrate 1.

[0071] FIG9 is a planar structural diagram of the first passivation layer and the second passivation layer in some other embodiments of the present disclosure.

[0072] Referring to Figure 9 , the display panel includes: a base substrate 1, a first passivation layer 9, a second conductive layer 10, and a second passivation layer 11; the second passivation layer 11 is located on a side of the second conductive layer 10 away from the base substrate 1. The orthographic projection of the first passivation layer 9 on the base substrate 1 includes a seventh side 907 proximate to the side edge 4 of the base substrate. The orthographic projection of the second passivation layer 11 on the base substrate 1 includes an eighth side 118 proximate to the side edge 4 of the base substrate. In the second direction D2, the eighth side 118 is closer to the side edge 4 of the base substrate than the seventh side 907. The second passivation layer 11 plays a role in protecting the second conductive layer 10. By designing the pattern of the second passivation layer, it can be ensured that the orthographic projection of the first passivation layer 9 on the base substrate 1 falls within the orthographic projection of the second passivation layer 11 on the base substrate 1. The second conductive layer 10 is located between the first passivation layer 9 and the second passivation layer 11. By wrapping the second passivation layer, the passivation protection effect of the second conductive layer 10 can be achieved, and the reaction of external water and oxygen with the second conductive layer 10 can be prevented, thereby improving the electrical transmission stability of the second conductive layer 10 and extending the service life of the display panel.

[0073] FIG10 is a planar structural diagram of the second passivation layer and the second covering layer in some other embodiments of the present disclosure.

[0074] Referring to Figure 10 , the display panel includes: a base substrate 1; a second passivation layer 11, wherein the second passivation layer 11 includes a third sub-passivation layer 111 and a fourth sub-passivation layer 112, wherein the fourth sub-passivation layer 112 is located on a side of the third sub-passivation layer 111 away from the base substrate 1. The display panel also includes a second cover layer 14, which is located between the third sub-passivation layer 111 and the fourth sub-passivation layer 112. The second cover layer 14 can be a planarization layer or an insulating layer. The display panel also includes a plurality of terminals 6, wherein the orthographic projection of at least one of the terminals on the base substrate 1 partially overlaps with the orthographic projection of the second cover layer on the base substrate.

[0075] FIG. 11 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing a plurality of via structures.

[0076] Referring to Figure 11 , a display panel includes: a base substrate 1; a first passivation layer 9; a second conductive layer 10; the second passivation layer 11 and a second cover layer 14; and a plurality of via holes 18 extending through the second passivation layer 11 and the second cover layer 14. The plurality of via holes 18 can be formed by etching portions of the second passivation layer 11 and the second cover layer 14 using a single process such as ion beam etching, sputtering etching, or laser etching, or by a combination of two or three of these processes. The plurality of via holes 18 are formed in the second passivation layer 11 and the second cover layer 14, exposing portions of the second conductive layer 10. The display panel also includes a plurality of terminals 6, wherein the plurality of via holes 18 each exposes at least a portion of the plurality of terminals 6. The first passivation layer 9 also includes a plurality of first passivation layer protrusions 91. The orthographic projection of at least one of the via holes 18 on the base substrate 1 at least partially overlaps with the orthographic projection of at least one of the first passivation layer protrusions 91 on the base substrate 1.

[0077] In the embodiment of the present disclosure, the multiple vias passing through the second passivation layer 11 and the second covering layer 14 include a first via 181. The first passivation layer protrusion 91 also includes a first protrusion 911. The orthographic projection of the first via 181 on the base substrate 1 at least partially overlaps with the orthographic projection of the first protrusion 911 on the base substrate 1. The display panel also includes a second via 171 passing through the first passivation layer 9 and the first covering layer 14, and the first terminal 61 is electrically connected to the first trace 71 through the second via 171. The orthographic projection of the first via 181 on the base substrate 1 and the orthographic projection of the second via 171 on the base substrate 1 are at least partially aligned along the first direction D1. The signal lines of the pixel driving circuit located in the first conductive layer 8 are electrically connected to the second conductive layer 10 through the second via 171, wherein the signal lines include data signal lines, power signal lines, scanning signal lines, etc. Part of the second conductive layer 10 is exposed through the first via hole to form a pad area of ​​the terminal 6 , which is further connected to an external driver circuit board or driver chip to control the display panel.

[0078] Continuing with FIG. 11 , the display panel includes: a base substrate 1; multiple terminals 6; a first passivation layer 9; a first cover layer 13; a second passivation layer 11 and a second cover layer 14. The display panel also includes multiple vias 18 extending through the second passivation layer 11 and the second cover layer 14. The multiple vias 18 include a third via 182. The first passivation layer 9 also includes a second protrusion 912. The orthographic projection of the third via 182 on the base substrate 1 at least partially overlaps with the orthographic projection of the second protrusion 912 on the base substrate 1. The display panel also includes a fourth via 172 extending through the first passivation layer 11 and the first cover layer 13. The display panel also includes a second terminal 62 and a second trace 72. The second terminal 62 is electrically connected to the second trace 72 via the fourth via 172. The orthographic projection of the third via 182 on the base substrate 1 and the projection of the fourth via 172 on the base substrate are spaced apart along the second direction.

[0079] In the embodiment of the present disclosure, the plurality of vias 18 passing through the second passivation layer 11 and the second cover layer 14 include a fifth via 183. The display panel further includes a first passivation layer 9. The first passivation layer 9 includes a third protrusion 913. The orthographic projection of the fifth via 183 on the base substrate 1 at least partially overlaps with the orthographic projection of the third protrusion 913 on the base substrate 1. The display panel further includes a sixth via 173 passing through the first passivation layer 9 and the first cover layer 13. The plurality of terminals 6 further include a third terminal 63. The orthographic projection of the fifth via 183 on the base substrate 1 and the orthographic projection of the sixth via 173 on the base substrate 1 are at least partially aligned along a first direction.

[0080] By optimizing the positional relationship between the third via 182 and the fifth via 183 and the protrusion of the first passivation layer, at least a portion of the orthographic projection of the third via 182 on the base substrate 1 falls within the orthographic projection of the second protrusion 912 on the base substrate 1, and at least a portion of the orthographic projection of the fifth via 183 on the base substrate 1 falls within the orthographic projection of the third protrusion 913 on the base substrate 1, thereby ensuring that when preparing the second conductive layer 10, there is no significant step difference in the first passivation layer 9 below the positions of the third via 182 and the fifth via 183, which will not cause the film quality of the second conductive layer 10 in the area where the third via 182 and the fifth via 183 are located to be reduced, thereby affecting the electrical performance of the terminals at the corresponding positions.

[0081] 12 and 13 are schematic plan views of display panels according to other embodiments of the present disclosure, wherein FIG12 and FIG13 illustrate edge structures of the first passivation layer.

[0082] 12 , the display panel includes: a base substrate 1; a plurality of terminals 6; a first passivation layer 9; and a second conductive layer 10. The base substrate 1 includes a side edge 4; the orthographic projection of the first passivation layer 9 on the base substrate includes a side edge 95 proximate to the side edge 4 of the base substrate, and the side edge 95 is serrated.

[0083] 13 , the display panel includes: a base substrate 1; a plurality of terminals 6; a first passivation layer 9; and a second conductive layer 10. The base substrate 1 includes a side edge 4; the orthographic projection of the first passivation layer 9 on the base substrate includes a side edge 95 proximate to the side edge 4 of the base substrate, and the side edge 95 is a continuous fold line.

[0084] In the embodiment of the present disclosure, the orthographic projection of at least one of the multiple terminals 6 on the base substrate 1 falls within the orthographic projection of the first passivation layer 9 on the base substrate 1. The multiple terminals 6 are located in the second conductive layer 10. By designing the shape of the side 95 of the orthographic projection of the first passivation layer 9 on the base substrate 1, the step difference of the film layer below the second conductive layer 10 during the process of preparing the second conductive layer 10 on the first passivation layer 9 can be reduced or even eliminated, that is, a more flat bottom supporting film layer is provided for the second conductive layer 10. When the second conductive layer 10 is grown in this way, the film layer of the second conductive layer 10 will be more uniform and dense, which can significantly reduce the defects in the second conductive layer 10, and can also reduce the gap between the second conductive layer 10 and the first passivation layer below, thereby reducing the probability of damage to the second conductive layer 10 by other subsequent processes of the second conductive layer 10, and improving the electrical stability of the second conductive layer 10, thereby reducing the probability of short circuit or open circuit on the second conductive layer 10 and improving the reliability of the display panel.

[0085] FIG. 14 is a cross-sectional view of a display panel at a terminal according to some other embodiments of the present disclosure.

[0086] Referring to Figure 14 , the display panel includes: a base substrate 1; a buffer layer 12; a first conductive layer 8; a first passivation layer 9; a second conductive layer 10; and a second passivation layer 11. The display panel also includes multiple terminals 6, at least one of which includes a terminal body 67 and a nickel-gold layer 68. The terminal body 67 is located in the second conductive layer, and the nickel-gold layer 68 is located on the surface of the terminal body 67 away from the base substrate 1. The nickel-gold layer 68 is prepared by forming an opening in a portion of the second passivation layer 11. The opening can be formed by laser etching, plasma etching, or reactive ion etching. After the opening is formed, a nickel-gold layer is formed in the opening region by electroplating nickel-gold or sputtering nickel-gold. The quality of the nickel-gold layer is closely related to the quality of the second conductive layer in the opening region. If the second conductive layer in the opening region has a high quality, the nickel-gold layer formed above the second conductive layer corresponding to the opening region will have fewer defects, significantly improving the electrical stability of the display panel terminal.

[0087] FIG15A is a partial enlarged view of a terminal defect of a display panel in the related art; FIG15B is a SEM image of the terminal defect shown in FIG15A .

[0088] The inventors have discovered that during the preparation of the second conductive layer at the corresponding opening area, if the underlying film layer, such as the first passivation layer, has a step difference in the opening area, the second conductive layer grown in the area with the step difference often has many defects. Figure 15A shows an enlarged image of one of the display panel's terminals with defects. The black straight line in the middle represents the area with the step difference. After the opening is formed in this area to prepare the nickel-gold layer, the quality of the nickel-gold layer significantly deteriorates, with defects such as surface unevenness and edge overflow. This can lead to abnormalities such as short circuits or disconnections in the electrical connection between the terminal and the external driver circuit board, reducing the display quality of the display panel. Referring to Figure 15B, microscopic analysis reveals that the second conductive layer in this area has cracks or that bottom etching has caused an uneven surface near the substrate. This can cause the gold solution to enter the cracks or uneven gaps in the second conductive layer during subsequent nickel-gold layer preparation, such as during the nickel-gold electroplating process, leading to abnormal nickel-gold deposition. This can cause short circuits or disconnections between the terminal and the external driver circuit board or driver chip, seriously affecting the reliability of the display panel.

[0089] FIG. 16 is a SEM image of one terminal in a display panel according to some exemplary embodiments of the present disclosure.

[0090] In an embodiment of the present disclosure, referring to FIG16 , by designing the protruding portion of the first passivation layer below the second conductive layer, such as the sawtooth design of FIG12 , the flatness of the film layer below the second conductive layer can be improved, and the step difference of the film layer below some terminals in the second conductive layer can be eliminated, thereby improving the film layer quality of the terminals in the non-step difference area. By eliminating the step difference of the film layer below the second conductive layer, the quality of the prepared second conductive layer film is significantly improved, the surface of the film is flat, there are no obvious cracks, and there is no uneven bottom caused by dry etching. Furthermore, when a nickel-gold layer is prepared in the corresponding opening area above the second conductive layer with higher quality, the quality of the nickel-gold layer film in the opening area above the second conductive layer can be improved, the probability of defective display panels can be reduced, and the reliability of the display panel can be improved.

[0091] FIG. 17 is a schematic plan view of a display panel according to other exemplary embodiments of the present disclosure.

[0092] 17 , the display panel includes: at least one display area 2 and a side area 3 and a side edge 4 of a substrate, wherein the side edge 4 of the substrate is parallel to the first direction shown in FIG17 , and the distance between the side area 4 and the side edge 4 of the substrate is less than the distance between the display area 2 and the side edge 4 of the substrate; a plurality of pixel units 5 are provided in the display area 2, and the plurality of pixel units 5 are distributed in an array on the substrate 1, wherein at least one of the pixel units includes a light-emitting diode, which may include a sub-millimeter light-emitting diode or a micro light-emitting diode, which may adopt the structure of a light-emitting diode chip; a plurality of terminals 6 are provided on the substrate 1 and located in the side area 3, and the plurality of terminals are distributed at intervals in the side area 3 along a first direction D1; a plurality of traces 7 are provided on the substrate 1, wherein one end of at least one of the traces 7 is electrically connected to the terminal 6, and the other end is electrically connected to a driving circuit of the pixel unit 5, and the driving circuit of the pixel unit 5 may include at least one transistor, and the transistor may include a source, a gate, a drain, and an active layer. For example, the transistor can have a dual-gate structure, which can include a first gate located below the active layer and a second gate located above the active layer. The display panel also includes a lead 20 disposed on the base substrate 1, one end of the lead electrically connected to the terminal 6, and the lead 20 extends from the terminal toward the side edge of the base substrate. The lead is used to lead the signal line to the driver circuit board or driver chip. Furthermore, the display panel can include multiple independent display panels, each of which can be individually connected to an independent sub-driver circuit board or sub-driver chip, and further controlled by the master control chip to achieve a coordinated display of the multiple display panels; the multiple independent display panels can also partially share certain sub-driver circuit boards or sub-driver chips, and further controlled by the master control chip to achieve a coordinated display of the multiple display panels; the multiple independent display panels can also all share a master control chip, and the master control chip can achieve coordinated control of the display panels. The specific matching of multiple display screens and driving circuits requires a comprehensive design based on the number of multiple display panels and driving requirements, combined with the driving circuits of the driving circuit board or the number of pins of the driving chip.

[0093] In the embodiment of the present disclosure, the display panel further includes: a first conductive layer 8 provided on the base substrate 1, wherein the plurality of traces 7 are located in the first conductive layer 8; the display panel further includes a first passivation layer 9 provided on the side of the first conductive layer 8 away from the base substrate 1; and a second conductive layer 10 provided on the side of the first passivation layer 9 away from the base substrate 1, wherein the terminal 6 is located in the second conductive layer, and at least one of the positive projections of the terminal 6 on the base substrate 1 falls within the positive projection of the first passivation layer 9 on the base substrate 1. By designing the structure of the first passivation layer, the probability of step differences in the first passivation layer 9 below the terminal 6 can be reduced or eliminated, thereby improving the film quality of the second conductive layer 10 where the terminal 6 is located, reducing the probability of abnormal nickel-gold process at the terminal in subsequent processes, improving the reliability and stability of the terminal 6, and reducing the probability of short circuits or open circuits. Furthermore, the signal lines of the display area, such as data signals, power signals, scanning signals, etc., are led out through the leads 20 to the driving circuit board or driving chip located on the side or back of the display panel through the terminals, which is beneficial to achieve narrow-slit splicing or seamless splicing of small screens during the small-screen splicing process, further improving the display effect of the display panel.

[0094] FIG18 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, which shows a schematic view of at least two small screens spliced ​​together to form a large display screen.

[0095] Referring to Figure 18 , the display panel includes multiple sub-display panels 100. These sub-display panels 100 are connected to a master control chip via connection traces in the 1S region, enabling coordinated control of the multiple sub-display panels. Before being connected to the master control circuit board or chip, the sub-display panels can also be connected to sub-control driver circuit boards or sub-driver chips, depending on actual control requirements, and then to the master control circuit board or chip.

[0096] Some exemplary embodiments of the present disclosure further provide a display device, comprising any one of the display panels described above.

[0097] Those skilled in the art will appreciate that the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways, even if such combinations and / or couplings are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or couplings are intended to fall within the scope of this disclosure.

[0098] Although the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made to the present disclosure without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by the equivalents of the appended claims.

Claims

1. A display panel, wherein: The display panel comprises: A base substrate, the base substrate comprising at least one side region and a display region, wherein the at least one side region is closer to a side edge of the base substrate than the display region; A plurality of pixel units are arranged in the display area, the plurality of pixel units are distributed in an array on the substrate along a first direction and a second direction, and at least one of the pixel units includes a light emitting diode; A plurality of terminals are disposed on the base substrate and located in the side region, wherein the plurality of terminals are spaced apart and distributed along the side edge of the base substrate; and A plurality of wirings are arranged on the substrate, at least one of the wirings having one end electrically connected to the terminal and the other end electrically connected to the light emitting diode, Wherein, the display panel comprises: A first conductive layer disposed on the substrate, wherein the plurality of traces are located in the first conductive layer; A first passivation layer disposed on a side of the first conductive layer away from the substrate; and a second conductive layer disposed on a side of the first passivation layer away from the base substrate, wherein the terminal is located in the second conductive layer, The orthographic projection of at least one of the terminals on the base substrate falls within the orthographic projection of the first passivation layer on the base substrate.

2. The display panel according to claim 1, wherein: The first passivation layer includes a plurality of protrusions, and the orthographic projections of the plurality of terminals on the base substrate respectively fall within the orthographic projections of the plurality of protrusions on the base substrate.

3. The display panel according to claim 1, wherein: The plurality of terminals include a first terminal, the plurality of traces include a first trace, the first trace is used to transmit a ground signal, and the first terminal is electrically connected to the first trace; as well as An orthographic projection of the first terminal on the base substrate falls within an orthographic projection of the first passivation layer on the base substrate.

4. The display panel according to claim 1, wherein: The orthographic projection of the first terminal on the base substrate includes a first side edge close to a side edge of the base substrate; and The first passivation layer includes a first protrusion, the orthographic projection of the first protrusion on the substrate includes a second side edge close to the side edge of the substrate, the orthographic projection of the first terminal on the substrate falls within the orthographic projection of the first protrusion on the substrate, and in a second direction, the second side edge is closer to the side edge of the substrate than the first side edge, wherein the second direction is perpendicular to the side edge of the substrate.

5. The display panel according to claim 1 or 2, wherein: A size of an orthographic projection of the first protrusion on the base substrate along a first direction is greater than a size of an orthographic projection of the first terminal on the base substrate along the first direction, wherein the first direction is parallel to a side edge of the base substrate.

6. The display panel according to claim 4, wherein: The plurality of pixel units respectively include a first light emitting diode, a second light emitting diode and a third light emitting diode, wherein the first light emitting diode is used to emit light of a first color, the second light emitting diode is used to emit light of a second color, and the third light emitting diode is used to emit light of a third color; The plurality of wires further include a second wire and a third wire, the second wire being used to transmit a first voltage signal to the second light emitting diode and the third light emitting diode, and the third wire being used to transmit a second voltage signal to the first light emitting diode; and The plurality of terminals further include a second terminal and a third terminal, the second terminal is electrically connected to the second trace, and the third terminal is electrically connected to the third trace.

7. The display panel according to any one of claims 1 to 5, wherein: An orthographic projection of at least one of the second terminal and the third terminal on the base substrate falls within an orthographic projection of the first passivation layer on the base substrate.

8. The display panel according to claim 7, wherein: The orthographic projection of the second terminal on the base substrate includes a third side edge close to the side edge of the base substrate; and The first passivation layer includes a second protrusion, the orthographic projection of the second protrusion on the base substrate includes a fourth side edge close to the side edge of the base substrate, and the fourth side edge is larger than the third side edge in the second direction. The side edge is closer to the side edge of the base substrate.

9. The display panel according to claim 7 or 8, wherein: The orthographic projection of the third terminal on the base substrate includes a fifth side close to the side edge of the base substrate; and The first passivation layer includes a third protrusion, the orthographic projection of the third protrusion on the base substrate includes a sixth side edge close to the side edge of the base substrate, and in the second direction, the sixth side edge is closer to the side edge of the base substrate than the fifth side edge.

10. The display panel according to any one of claims 1 to 6, wherein: An orthographic projection of at least one of the second terminal and the third terminal on the base substrate partially overlaps with an orthographic projection of the first passivation layer on the base substrate.

11. The display panel according to claim 9, wherein: The first passivation layer includes a first sub-passivation layer and a second sub-passivation layer, and the second sub-passivation layer is located on a side of the first sub-passivation layer away from the substrate; The display panel further includes a first covering layer, wherein the first covering layer is located between the first sub-passivation layer and the second sub-passivation layer; as well as The orthographic projection of at least one of the terminals on the base substrate falls within the orthographic projection of each of the first sub-passivation layer and the second sub-passivation layer on the base substrate, and the orthographic projection of at least one of the terminals on the base substrate partially overlaps with the orthographic projection of the first covering layer on the base substrate.

12. The display panel according to claim 10, wherein: The display panel further includes a second passivation layer, wherein the second passivation layer is located on a side of the second conductive layer away from the base substrate; and The orthographic projection of the first passivation layer on the base substrate includes a seventh side close to the side edge of the base substrate, and the orthographic projection of the second passivation layer on the base substrate includes an eighth side close to the side edge of the base substrate, and in the second direction, the eighth side is closer to the side edge of the base substrate than the seventh side.

13. The display panel according to any one of claims 1 to 12, wherein: The second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer, and the fourth sub-passivation layer is located on a side of the third sub-passivation layer away from the substrate; The display panel further includes a second covering layer, wherein the second covering layer is located between the third sub-passivation layer and the fourth sub-passivation layer; as well as An orthographic projection of at least one of the terminals on the base substrate partially overlaps with an orthographic projection of the second cover layer on the base substrate.

14. The display panel according to claim 11, wherein: The display panel includes a plurality of via holes penetrating the second passivation layer and the second cover layer, the plurality of via holes respectively exposing at least a portion of the plurality of terminals; as well as An orthographic projection of at least one of the via holes on the base substrate partially overlaps with an orthographic projection of at least one of the protrusions on the base substrate.

15. The display panel according to claim 14, wherein: The plurality of via holes penetrating the second passivation layer and the second cover layer include a first via hole, an orthographic projection of the first via hole on the base substrate partially overlaps with an orthographic projection of the first protrusion on the base substrate; The display panel further includes a second via hole penetrating the first passivation layer and the first covering layer, and the first terminal is electrically connected to the first trace through the second via hole; as well as An orthographic projection of the first via hole on the base substrate and an orthographic projection of the second via hole on the base substrate are at least partially aligned along a first direction.

16. The display panel according to any one of claims 1 to 12, wherein: The plurality of via holes penetrating the second passivation layer and the second cover layer include a third via hole, and an orthographic projection of the third via hole on the base substrate partially overlaps with an orthographic projection of the second protrusion on the base substrate; The display panel further includes a fourth via hole penetrating the first passivation layer and the first cover layer, and the second terminal is electrically connected to the second trace through the fourth via hole; as well as The orthographic projection of the third via hole on the base substrate and the orthographic projection of the fourth via hole on the base substrate are arranged at intervals along the second direction.

17. The display panel according to claim 16, wherein: The plurality of via holes penetrating the second passivation layer and the second cover layer include a fifth via hole, and an orthographic projection of the fifth via hole on the base substrate partially overlaps with an orthographic projection of the third protrusion on the base substrate; The display panel further includes a sixth via hole penetrating the first passivation layer and the first covering layer, and the third terminal is electrically connected to the third trace through the sixth via hole; as well as An orthographic projection of the fifth via hole on the base substrate and an orthographic projection of the sixth via hole on the base substrate are at least partially aligned along a first direction.

18. The display panel according to claim 17, wherein: The orthographic projection of the first passivation layer on the base substrate includes a side edge close to a side edge of the base substrate, and the side edge includes a shape selected from the group consisting of a wall shape, a sawtooth shape, a wave shape, and a continuous broken line shape.

19. The display panel according to claim 6, wherein: At least one of the terminals includes a terminal body and a nickel-gold plating layer, wherein the terminal body is located in the second conductive layer, and the nickel-gold plating layer is located on a surface of the terminal body away from the base substrate.

20. A display panel, wherein: The display panel comprises: A base substrate, the base substrate comprising at least one side region and a display region, wherein the at least one side region is closer to a side edge of the base substrate than the display region; A plurality of pixel units are arranged in the display area, the plurality of pixel units are distributed in an array on the substrate, and at least one of the pixel units comprises a light emitting diode; A plurality of terminals are arranged on the substrate and located in the side area, and the plurality of terminals are distributed at intervals along the side edge of the substrate; A plurality of wirings are arranged on the substrate, at least one of the wirings having one end electrically connected to the terminal and the other end electrically connected to the light emitting diode; and A lead wire is arranged on the base substrate, one end of the lead wire is electrically connected to the terminal, and the lead wire extends from the terminal toward the side edge of the base substrate. Wherein, the display panel comprises: A first conductive layer disposed on the substrate, wherein the plurality of traces are located in the first conductive layer; A first passivation layer disposed on a side of the first conductive layer away from the substrate; and a second conductive layer disposed on a side of the first passivation layer away from the base substrate, wherein the terminal is located in the second conductive layer, The orthographic projection of at least one of the terminals on the base substrate falls within the orthographic projection of the first passivation layer on the base substrate.

21. A display device, wherein: The display device comprises the display panel according to any one of claims 1 to 20.

Images