Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip

Abstract

A method for producing an optoelectronic semiconductor chip (100) is specified herein, comprising the steps of: - epitaxially growing a semiconductor layer sequence (1) with an active layer (2) for emitting electromagnetic radiation, wherein the active layer (2) comprises a phosphide compound semiconductor material or an arsenide compound semiconductor material, - forming a via (3) in the semiconductor layer sequence (1) for electrically contacting the semiconductor layer sequence (1), - forming an electron and hole barrier (4) within the semiconductor layer sequence (1) at an edge (31) of the via (3). Further, an optoelectronic semiconductor chip is specified herein.

Description

[0001] Description

[0002] METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP AND OPTOELECTRONIC SEMICONDUCTOR CHIP

[0003] A method for producing an optoelectronic semiconductor chip and an optoelectronic semiconductor chip are speci fied herein .

[0004] At least one obj ect of certain embodiments is to speci fy a method for producing an optoelectronic semiconductor chip with an increased ef ficiency . At least one further obj ect of certain embodiments is to speci fy an optoelectronic semiconductor chip with an increased ef ficiency .

[0005] According to at least one aspect of the method for producing an optoelectronic semiconductor chip, a semiconductor layer sequence with an active layer for emitting electromagnetic radiation is epitaxially grown, wherein the active layer comprises a phosphide compound semiconductor material or an arsenide compound semiconductor material . For example , the optoelectronic semiconductor chip is a light emitting diode chip ( short : LED chip ) . For example , the LED chip emits electromagnetic radiation due to spontaneous emission . For example , the active layer emits electromagnetic radiation with a wavelength in a spectral range between infrared light and yellow light during operation of the optoelectronic semiconductor chip .

[0006] In particular, the semiconductor layer sequence is epitaxially grown on a main surface of a growth substrate . For example , the growth substrate comprises gallium arsenide , gallium phosphide , or consists of one or more of these materials. For example, the semiconductor layer sequence is epitaxially grown using chemical vapor deposition (short: CVD) . At least one semiconductor layer stack can be formed from the semiconductor layer sequence and further transferred to a carrier, for example. In particular, the growth substrate can be removed from the semiconductor layer stack. For example, the optoelectronic semiconductor chip is a flip chip or a thin film LED chip.

[0007] For example, the semiconductor layer sequence comprises or consists of a III / V compound semiconductor material. A III / V compound semiconductor material comprises at least one element from the third main group, such as B, Al, Ga, In, and one element from the fifth main group, for example N, P, As. In particular, the term "III / V compound semiconductor material" includes the group of binary, ternary or quaternary compounds containing at least one element from the third main group and at least one element from the fifth main group. Moreover, the III / V semiconductor material may comprise one or more dopants.

[0008] For example, arsenide compound semiconductor materials such as aluminium indium gallium arsenide AlxInyGai-x-yAs with 0 < x < 1, 0 < y < 1 and x+y < 1 (short: AlInGaAs) , or phosphide compound semiconductor materials such as aluminium indium gallium phosphide AlxInyGai-x-yP with 0 < x < 1, 0 < y < 1 and x+y < 1 (short: AlInGaP) , are III / V compound semiconductor materials. In particular, the semiconductor layer sequence comprises the arsenide compound semiconductor material or the phosphide compound semiconductor material.

[0009] For example, the active layer is configured to convert an electric current into the electromagnetic radiation. For example , the active layer comprises or consists of a pn- j unction for converting the electromagnetic current into the electromagnetic radiation . The active layer comprises or consists of the phosphide compound semiconductor material , for example Al InGaP, or the active layer comprises or consists of the arsenide compound semiconductor material , for example Al InGaAs or AlxGai-xAs with 0 < x < 1 .

[0010] For example , the semiconductor layer sequence comprises a p- doped region and a n-doped region . In particular, the p-doped region comprises electron acceptor atoms as dopants , wherein the electron acceptor atoms exhibit electronic states that are energetically close to a valence band of the semiconductor layer sequence . In particular, the n-doped region comprises electron donor atoms as dopants , wherein the electron donor atoms exhibit electronic states that are energetically close to a conduction band of the semiconductor layer sequence . For example , the semiconductor layer sequence is epitaxially grown such that the p-doped region follows the n-doped region in a growth direction of the semiconductor layer sequence , or vice versa . In other words , the p-doped region faces away from the growth substrate , whereas the n- doped region faces towards the growth substrate , or vice versa .

[0011] According to at least one further aspect of the method for producing an optoelectronic semiconductor chip, a via for electrically contacting the semiconductor layer sequence is formed in the semiconductor layer sequence . The via is also known as a through connection or through plating . For example , the via is configured for electrically contacting a side of the active layer that faces away from the carrier on which the semiconductor layer sequence is arranged . In particular, the via comprises a blind hole or a groove . For example , the via is formed by etching the semiconductor layer sequence . For example , an etch mask is arranged on a main surface of the semiconductor layer sequence , such that the via is formed by etching a selective region of the semiconductor layer sequence .

[0012] In particular, the via extends in a direction parallel to the growth direction of the semiconductor layer sequence , i . e . in a direction perpendicular to the layers of the semiconductor layer sequence . For example , the via is formed after epitaxially growing the semiconductor layer sequence on the growth substrate . In particular, the via is formed before trans ferring the semiconductor layer stack onto the carrier .

[0013] Preferably, the via does not extend completely through the semiconductor layer sequence . For example , the via extends from the main surface of the semiconductor layer sequence , i . e . from a surface that is perpendicular to the growth direction of the semiconductor layer sequence , at least completely through the active layer . In particular, the via terminates on a side of the active layer facing away from the surface where the via is formed . For example , a bottom surface of the via is arranged on a side of the active layer facing the growth substrate . For example , the via extends through the p-doped region and the active layer, and terminates in the n-doped region . It is also possible that the via extends through the n-doped region and the active layer, and terminates in the p-doped region .

[0014] For example , the via has a columnar, pyramidal , or truncated pyramidal shape . In particular, an area and / or a shape of a cross section of the via can change along the extension of the via . For example , the cross section of the via has a circular, elliptical , oval , rectangular, square , hexagonal , or polygonal shape in plan view of the layers of the semiconductor layer sequence . A linear dimension of the cross section of the via, in particular a maximal diameter of the cross section, is between 1 micrometer and 100 micrometer, inclusive , for example . The optoelectronic semiconductor chip can comprise one , two , three or a plurality of vias .

[0015] According to at least one further aspect of the method for producing an optoelectronic semiconductor chip, an electron and hole barrier is formed within the semiconductor layer sequence at an edge of the via . In particular, the edge of the via corresponds to a side surface , or to the side surface and the bottom surface of the via . For example , the edge of the via corresponds to a side surface , or to the side surface and the bottom surface of the blind hole or groove that extends parallel to the growth direction . In particular, the side surface is a lateral surface or a circumferential surface of the via .

[0016] For example , the electron and hole barrier comprises or consists of a region of the semiconductor layer sequence with a band gap that is larger than a band gap of the active layer . In particular, the band gap in the electron and hole barrier is larger, for example at least 10% larger, than a band gap of a quantum well layer in the active layer .

[0017] For example , the electron and hole barrier is a region of the semiconductor layer sequence with a di f ferent material composition compared to the active layer . The electron and hole barrier can be formed by implanting atoms in the semiconductor layer sequence via di f fusion or ion implantation, for example .

[0018] Preferably, the electron and hole barrier surrounds the via in lateral directions . Here and in the following, lateral directions refer to directions parallel to the layers of the semiconductor layer sequence . In other words , the electron and hole barrier completely encloses the via in plan view of the semiconductor layers of the semiconductor layer sequence . For example , the electron and hole barrier is a ring shaped region of the semiconductor layer sequence , wherein the via is arranged at a center of the ring shaped region . For example , the electron and hole barrier extends between 1 nanometer and 100 micrometer, or at most 100 nm, or at most 10 nm, from the edge of the via in lateral directions . For example , the band gap of the electron and hole barrier is maximal at the edge of the via and decreases gradually with increasing distance from the edge of the via .

[0019] It is also possible that the band gap of the electron and hole barrier changes along the growth direction . For example , the band gap in the electron and hole barrier decreases gradually along the extension of the via from the main surface of the semiconductor layer sequence to the bottom surface of the via . For example , the material composition of the electron and hole barrier gradually changes along the extension of the via and / or the material composition of the electron and hole barrier gradually changes in lateral directions or in radial directions away from a center of the via .

[0020] For example , after forming the electron and hole barrier and the blind hole , further steps of forming the via can include forming a passivation on the side surface of the blind hole . For example , the passivation comprises a dielectric layer . Moreover, a metalli zation or a metallic layer can be formed inside the blind hole in order to establish an electrical contact between the bottom surface of the via and a mirrormetal , a solder-metal and / or the carrier . It is also possible that a bottom part of the side surface of the blind hole in the immediate vicinity of the bottom surface is in direct contact with the metalli zation or the metal layer inside the blind hole .

[0021] According to an embodiment , the method for producing an optoelectronic semiconductor chip comprises the steps of :

[0022] - epitaxially growing the semiconductor layer sequence with the active layer for emitting electromagnetic radiation, wherein the active layer comprises the phosphide compound semiconductor material or the arsenide compound semiconductor material ,

[0023] - forming the via in the semiconductor layer sequence for electrically contacting the semiconductor layer sequence ,

[0024] - forming the electron and hole barrier within the semiconductor layer sequence at the edge of the via .

[0025] The method described herein is based on the idea to employ vias for electrically contacting the n-doped region of an optoelectronic semiconductor chip, such as a thin film arsenide or phosphide LED chip, wherein the semiconductor layer sequence is grown with the p-doped region facing away from the growth substrate . Accordingly, no light absorbing contact metalli zation or contact layer is needed on the surface of the n-doped region for electrically contacting the active layer . Consequently, an ef ficiency of the optoelectronic semiconductor chip can be advantageously increased .

[0026] However, vias in a semiconductor layer sequence comprising phosphide or arsenide compound semiconductor materials can increase a rate of non-radiative recombination ( short : NRR) processes , thereby reducing an internal quantum ef ficiency of the optoelectronic semiconductor chip, possibly even down to zero . Here , the internal quantum ef ficiency corresponds to a ratio between the number of photons emitted per unit time and the number of electrons inj ected into the active layer per unit time . For example , forming the vias in the semiconductor layer sequence can lead to surface defects and / or defects in the crystal structure of the semiconductor layer sequence in the vicinity of the via . For example , electrons and / or holes can be trapped at such defects and undergo non-radiative recombination, i . e . recombination without emitting photons .

[0027] The electron and hole barrier described herein reali zes an NRR-termination of the via by blocking the movement of electrons and / or holes to the vicinity of the via, for example . Accordingly, the probability of electrons and / or holes getting trapped at defects in the vicinity of the via is reduced, thereby advantageously reducing NRR processes and thus increasing the internal quantum ef ficiency of the optoelectronic semiconductor chip . Moreover, the steps of forming the electron and hole barrier can be included in the chip processing flow . For example , the electron and hole barrier can be formed as an additional step in a CVD reactor where the semiconductor layer sequence is grown .

[0028] According to at least one further aspect of the method, the step of forming the electron and hole barrier is performed before the step of forming the via . For example , the material composition is altered in a region of the semiconductor layer sequence where the via is subsequently formed, e . g . by etching . For example , the band gap in the electron and hole barrier is increased relative to the band gap of the active layer by locally implanting atoms into the semiconductor layer sequence by di f fusion or ion implantation . Afterwards , the blind hole is formed in a part of the region where the atoms have been implanted .

[0029] According to at least one further aspect of the method, the step of forming the via comprises forming a hole , such as the blind hole or the groove , in the semiconductor layer sequence , and the electron and hole barrier is formed after forming the hole in the semiconductor layer sequence . For example , after forming the blind hole , the material composition of the semiconductor layer sequence is altered locally around the blind hole by implanting atoms into the semiconductor layer sequence .

[0030] According to at least one further aspect of the method, the semiconductor layer sequence comprises the p-doped region and the n-doped region, the semiconductor layer sequence is epitaxially grown such that the p-doped region faces away from the growth substrate , and the via extends from the main surface of the semiconductor layer sequence in the p-doped region through the active layer to the n-doped region . In particular, the n-doped region and the p-doped region follow each other in the growth direction . For example , the n-doped region faces the growth substrate . In particular, the bottom surface of the via is arranged inside the n-doped region . According to at least one further aspect of the method, the electron and hole barrier is formed by diffusing atoms into a region of the semiconductor layer sequence adjacent to the via. For example, zinc atoms thermally diffuse into the material of the semiconductor layer sequence. For example, the diffusion step is performed in the CVD reactor. Preferably, atoms such as Zn atoms are locally applied to the semiconductor sequence, such that the electron and hole barrier only forms in the vicinity of the via.

[0031] For example, the thermal diffusion of Zn atoms into the semiconductor layer sequence gives rise to a co-diffusion of aluminum atoms along with the Zn atoms. In particular, this diffusion of aluminum atoms can increase the band gap in the electron and hole barrier.

[0032] According to at least one further aspect of the method, a hardmask is deposited on the semiconductor layer sequence before the electron and hole barrier is formed. For example, the hardmask comprises an opening in the region where the via is formed. Accordingly, the material composition of the semiconductor layer sequence is only altered in the region where the Zn atoms, for example, can diffuse into the semiconductor layer sequence via the opening in the hardmask.

[0033] According to at least one further aspect of the method, the hardmask comprises or consists of SiON, a transparent conductive oxide, and / or a dielectric Bragg mirror. For example, the hardmask can be removed after forming the electron and hole barrier. For example, the transparent conductive oxide or the dielectric Bragg mirror are a part of the optoelectronic semiconductor chip, thus no further hardmask may be needed for forming the electron and hole barrier . In this case , the hardmask does not need to be removed after forming the electron and hole barrier . In particular, forming the electron and hole barrier can thus be integrated in the chip production process with a minimal number of additional processing steps .

[0034] For example , the dielectric Bragg mirror forms a reflector or is part of a reflector that is arranged on a back-side of the optoelectronic semiconductor chip . The reflector is configured to increase the ef ficiency by increasing the amount of electromagnetic radiation that is coupled out of a front-side of the optoelectronic semiconductor chip, for example .

[0035] According to at least one further aspect , the method comprises an additional step of removing the growth substrate from the semiconductor layer sequence after forming the via and / or the electron and hole barrier . For example , the semiconductor layer sequence is trans ferred to the carrier before removing the growth substrate . In particular, the optoelectronic semiconductor chip is a thin film LED chip .

[0036] According to at least one further aspect of the method, the via is formed by etching the semiconductor layer sequence . For example , the via is formed by dry etching, wet etching and / or electrochemical etching of the semiconductor layer sequence . For example , an etch mask with an opening at the position of the via is applied to the main surface of the semiconductor layer sequence before the etching process . The hard mask can also be used as the etch mask, for example .

[0037] Further, an optoelectronic semiconductor chip is speci fied herein . In particular, the method speci fied above can be used to produce the optoelectronic semiconductor chip . All features of the method for producing an optoelectronic semiconductor chip are also disclosed for the optoelectronic semiconductor chip, and vice versa .

[0038] According to at least one aspect , the optoelectronic semiconductor chip comprises the semiconductor layer sequence with the active layer for emitting electromagnetic radiation, wherein the active layer comprises the phosphide compound semiconductor material or the arsenide compound semiconductor material .

[0039] According to at least one further aspect , the optoelectronic semiconductor chip comprises the via in the semiconductor layer sequence for electrically contacting the semiconductor layer sequence .

[0040] According to at least one further aspect , the optoelectronic semiconductor chip comprises the electron and hole barrier within the semiconductor layer sequence at the edge of the via .

[0041] According to at least one embodiment , the optoelectronic semiconductor chip comprises :

[0042] - the semiconductor layer sequence with the active layer for emitting electromagnetic radiation, wherein the active layer comprises a phosphide compound semiconductor material or an arsenide compound semiconductor material ,

[0043] - the via in the semiconductor layer sequence for electrically contacting the semiconductor layer sequence ,

[0044] - the electron and hole barrier within the semiconductor layer sequence at the edge of the via . According to at least one further aspect of the optoelectronic semiconductor chip, the semiconductor layer sequence comprises the p-doped region and the n-doped region, the p-doped region is arranged on the carrier, and the via extends from the carrier through the active layer to the n- doped region . For example , the carrier comprises electrical contacts for electrically contacting the semiconductor layer sequence . In particular, the p-doped region is in direct contact with the carrier, whereas the n-doped region is electrically contacted with the carrier through the vias . For example , optoelectronic semiconductor chip is a flip chip or a thin film chip . In particular, electromagnetic radiation generated in the active layer during operation is primarily coupled out of the optoelectronic semiconductor chip via the n-doped side .

[0045] According to at least one further aspect , the optoelectronic semiconductor chip is free of an electrical contact metalli zation on a surface of the semiconductor layer sequence facing away from the carrier . In particular, the surface of the n-doped region does not comprise a contact metalli zation or an electrical contact layer .

[0046] According to at least one further aspect of the optoelectronic semiconductor chip, the semiconductor layer sequence comprises a current spreading layer in the n-doped region . For example , a concentration of dopants in the current spreading layer is higher than in other semiconductor layers in the n-doped region . Preferably, the current spreading layer has a low electrical resistance . In particular, the current spreading layer is configured to distribute the electrical current in lateral directions through the n-doped region of the semiconductor layer sequence .

[0047] According to at least one further aspect of the optoelectronic semiconductor chip, the via extends to the current spreading layer . In particular, the bottom surface of the via is arranged inside or adj acent to the current spreading layer .

[0048] According to at least one further aspect of the optoelectronic semiconductor chip, the active layer comprises multiple quantum well layers , and the band gap of the electron and hole barrier at the edge of the via is larger than a band gap of the quantum well layers . For example , the band gap of the electron and hole barrier at the edge of the via is larger than the band gap of the quantum well layers .

[0049] In particular, quantum well layers give rise to a confinement of electrons such their energy levels are quanti zed .

[0050] According to at least one further aspect of the optoelectronic semiconductor chip, an electrically conductive material is arranged inside the via . For example , the via is at least partially filled with a metal .

[0051] According to at least one further aspect of the optoelectronic semiconductor chip, the electron and hole barrier is configured to reduce non-radiative recombination processes at the edge of the via . For example , the electron and hole barrier reduces a probability that electrons and / or holes move from inside the active layer towards the edge of the via . Further advantageous embodiments and further embodiments of the method for producing an optoelectronic semiconductor chip and the optoelectronic semiconductor chip become apparent from the following exemplary embodiments described in connection with the figures .

[0052] Figures 1 to 3 show steps of a method for producing an optoelectronic semiconductor chip according to an exemplary embodiment .

[0053] Figures 4 to 8 show steps of a method for producing an optoelectronic semiconductor chip according to a further exemplary embodiment .

[0054] Figure 9 shows a schematic cross section of an optoelectronic semiconductor chip according to an exemplary embodiment .

[0055] Elements that are identical , similar, or have the same ef fect , are denoted by the same reference signs in the figures . The figures and the proportions of the elements shown in the figures are not to be regarded as true to scale . Rather, individual elements , may be shown exaggeratedly large for better representability and / or better understanding .

[0056] Figure 1 shows a schematic cross section of a state of an optoelectronic semiconductor chip 100 after a step of a method for producing an optoelectronic semiconductor chip 100 according to an exemplary embodiment . In this step, a semiconductor layer sequence 1 comprising Al InGaP or Al InGaAs is epitaxially grown on a growth substrate 6 . The semiconductor layer sequence 1 comprises an active layer 2 with multiple quantum well layers for generating electromagnetic radiation that are separated by barrier layers . In particular, a band gap of the barrier layers is larger than a band gap of the quantum well layers . The active layer 2 is arranged between a p-doped region 11 an n-doped region 12 . The p-doped region 11 follows the n-doped region 12 in a growth direction R of the semiconductor layer sequence 1 . The n-doped region 12 further comprises a current spreading layer 14 as well as a roughening layer 15 .

[0057] Electromagnetic radiation generated in the active layer 2 during operation is primarily emitted through the roughening layer 15 of the optoelectronic semiconductor chip 100 . For example , a surface roughening is formed in the roughening layer 15 in a later step of the method for producing an optoelectronic semiconductor chip, after the growth substrate

[0058] 6 has been removed from the semiconductor layer sequence 1 . In particular, the surface roughening is configured to increase an outcoupling ef ficiency for electromagnetic radiation generated in the active layer 2 .

[0059] A hardmask 7 consisting of SiON is deposited on the main surface 13 of the semiconductor layer sequence 1 . The hardmask 7 comprises an opening 73 in a region, where the via 3 is to be formed in a later step of the method . The hardmask

[0060] 7 is configured as an etch mask for etching a hole 5 of the via 3 . Further, the hardmask 7 is configured as a mask for forming the electron and hole barrier 4 around the via 3 by thermal di f fusion of Zn atoms in a further step of the method . In particular, the hardmask 7 ensures that the Zn atoms that di f fuse through the semiconductor layer sequence 1 for forming the electron and hole barrier 4 only come into contact with the semiconductor layer sequence 1 through the opening in the hardmask 7 . Figure 2 shows a schematic cross section of a state of an optoelectronic semiconductor chip 100 after a further step of a method for producing an optoelectronic semiconductor chip 100 according to the exemplary embodiment described in connection with Figure 1 . A hole 5 , in particular a blind hole , is formed in the semiconductor layer sequence 1 that extends from the main surface 13 through the p-doped region 11 and the active layer 2 into the n-doped region 12 . In particular, the hole 5 terminates in the n-doped region 12 , such that a bottom surface 51 of the hole 5 is arranged inside or in the vicinity of the current spreading layer 14 .

[0061] The hole 5 is formed via etching, such as dry etching, wet etching or electrochemical etching, using the hardmask 7 as an etch mask . In a later step of the method the hole 5 is filled with an electrically conductive material 9 (not shown in Figure 2 , c . f . Figure 9 ) , such as a metal , in order to form a via 3 for electrically contacting the n-doped region 12 . In particular, the electrically conductive material 9 is disposed in the hole 5 only after forming the electron and hole barrier 4 ( c . f . Figure 3 ) . The side surface 52 of the hole 5 forms an edge 31 of the via 3 . Between the side surface 52 and the electrically conductive material 9 an electrically insulating material , such as a dielectric layer, can be arranged .

[0062] Figure 3 shows a schematic cross section of a state of an optoelectronic semiconductor chip 100 after a further step of a method for producing an optoelectronic semiconductor chip 100 according to the exemplary embodiment described in connection with Figures 1 and 2 . In particular, an electron and hole barrier 4 is formed inside the semiconductor layer sequence 1 at an edge 31 of the via 3 . The electron and hole barrier 4 is formed by thermal di f fusion of Zn atoms that are deposited on the semiconductor layer sequence 1 through the opening 73 in the hardmask 7 in a CVD reactor, for example . Accordingly, the Zn atoms di f fuse primarily in lateral directions or radial directions away from the center of the hole 5 , i . e . perpendicular to the growth direction R . In particular, the Zn atoms di f fuse from the edge 31 of the via 3 into the semiconductor layer sequence 1 . Consequently, the electron and hole barrier 4 is a ring shaped region inside the semiconductor layer sequence 1 that completely surrounds the hole 5 .

[0063] The thermal di f fusion of Zn atoms gives rise to a codi f fusion of Al atoms . Accordingly, an increased Al content in the region of the electron and hole barrier 4 increases a band gap of the electron and hole barrier 4 . The electron and hole barrier 4 thus reduces a probability that electrons and / or holes move towards the edge 31 of the via 3 , where they could undergo non-radiative recombination at defects in the vicinity of the via 3 . The band gap of the electron and hole barrier 4 is proportional to the Al content and thus can decrease with increasing distance from the edge 31 of the via 3 .

[0064] It is also possible that the steps of the method described in connection with Figures 2 and 3 are interchanged . In particular, the electron and hole barrier 4 can be formed by thermal di f fusion of Zn atoms through the opening 73 in the hardmask, before the hole 5 of the via 3 is formed inside the semiconductor layer sequence 1 by etching . Accordingly, the Zn atoms di f fuse primarily in a vertical direction, i . e . anti-parallel to the growth direction R, into the semiconductor layer sequence 1 . The hole 5 for the via 3 can be formed subsequently inside the region of the semiconductor layer sequence 1 where the electron and hole barrier 4 was formed . In this case , the band gap of the electron and hole barrier 4 can decrease with increasing distance from the main surface 13 , for example .

[0065] Figure 4 shows a schematic cross section of a state of an optoelectronic semiconductor chip 100 after a step of a method for producing an optoelectronic semiconductor chip 100 according to a further exemplary embodiment . In contrast to the exemplary embodiment described in connection with Figure 1 , the hardmask 7 does not comprise SiON . Rather, in a first step a transparent conductive oxide 71 , such as indium tin oxide , is disposed on a region of the main surface 13 of the semiconductor layer sequence 1 . The transparent conductive oxide 71 is configured as a current spreading layer for electrically contacting the p-doped region 11 .

[0066] Figure 5 shows a further step of the method according to the exemplary embodiment described in connection with Figure 4 , where a dielectric Bragg reflector 72 is disposed on the main surface 13 of the semiconductor layer sequence 1 and on the transparent conductive oxide 71 . The dielectric Bragg reflector 72 comprises a plurality of dielectric layers with alternating refractive indices and is configured to at least partially reflect the electromagnetic radiation generated inside the active layer 2 during operation . The dielectric Bragg reflector 72 comprises an opening 73 that is used to form the via 3 in a later step of the method . The dielectric Bragg reflector 72 comprises a further opening for electrically contacting the transparent conductive oxide 71 . Figure 6 shows a further step of the method according to the exemplary embodiment described in connection with Figures 4 and 5 , where one or more metallic layers 74 , such as a metallic reflector and / or a metallic current spreading layer, are disposed on the dielectric Bragg reflector 72 . For example , the metallic reflector comprises Ag and is configured to at least partially reflect electromagnetic radiation generated in the active layer 2 during operation that is not already reflected by the dielectric Bragg reflector 72 .

[0067] Further, a passivation 75 is disposed on the metallic layer 74 . For example , the passivation 75 protects the metallic layer 74 during a later etching step where the hole 5 of the via 3 is formed . While the passivation 75 and the metallic layer 74 are disposed in the further opening of the dielectric Bragg reflector 72 for electrically contacting the transparent conductive oxide 71 , the opening 73 remains free of the metallic layer 74 and the passivation 75 .

[0068] Figure 7 shows a further step of the method according to the exemplary embodiment described in connection with Figures 4 to 6 , where a hole 5 for the via 3 is formed in the semiconductor layer sequence 1 . The via 3 is formed in analogy to the method described in connection with Figure 2 . In contrast to Figure 2 , the hardmask 7 is formed by the transparent conductive oxide 71 , the dielectric Bragg reflector 72 , the metallic layer 74 and the passivation 75 . Advantageously, the transparent conductive oxide 71 , the dielectric Bragg reflector 72 and the metallic layer 74 remain on the semiconductor layer sequence 1 and do not need to be removed after forming the via 3 . Figure 8 shows a further step of the method according to the exemplary embodiment described in connection with Figures 4 to 7 , where an electron and hole barrier 4 is formed in the semiconductor layer sequence 1 . The electron and hole barrier 4 is formed in analogy to the method described in connection with Figure 3 .

[0069] For example , further steps of the method include arranging a passivation on the side surface 52 of the hole 5 and filling the hole with an electrically conductive material 9 in order to form the via 3 . Moreover, the semiconductor layer sequence 1 can be trans ferred to a carrier 8 and the growth substrate 6 can be removed subsequently, thereby forming a thin- film chip .

[0070] It is also possible that the steps of the method described in connection with Figures 7 and 8 are interchanged and the electron and hole barrier 4 is formed before the hole 5 is etched into the semiconductor layer sequence 1 .

[0071] The optoelectronic semiconductor chip 100 according to the exemplary embodiment shown in Figure 9 comprises a semiconductor layer sequence 1 arranged on a carrier 8 . The carrier 8 mechanically stabili zes the optoelectronic semiconductor chip 100 and is configured for electrically contacting the semiconductor layer sequence 1 . A growth substrate 6 is removed from the semiconductor layer sequence 1 . The semiconductor layer sequence 1 consists of Al InGaAs or Al InGaP .

[0072] The semiconductor layer sequence comprises an active layer 2 arranged between a p-doped region 11 and an n-doped region 12 . The p-doped region 11 faces the carrier 8 , while the n- doped region 12 faces away from the carrier 8 . Accordingly, electromagnetic radiation generated due to an electric current flowing through the active layer 2 during operation is coupled out of the optoelectronic semiconductor chip 100 primarily via the surface of the n-doped region 12 facing away from the carrier 8 .

[0073] The n-doped region 12 is electrically contacted by a via 3 that extends from the carrier 8 through the p-doped region 11 and the active layer 2 into the n-doped region 12 . The via 3 comprises a blind hole 5 in the semiconductor layer sequence 1 that is filled with an electrically conductive material 9 , in particular a metal . The via 3 has a diameter between 1 micrometer and 100 micrometer, inclusive , in plan view of the carrier 8 , for example . Due to electrically contacting the n- doped region 12 by the via, no contact layer or contact metalli zation is required on the surface of the n-doped region 12 , through which the electromagnetic radiation is coupled out of the optoelectronic semiconductor chip 100 . As a contact layer or contact metalli zation would be at least partially light absorbing, the ef ficiency of the optoelectronic semiconductor chip 100 is advantageously increased .

[0074] Forming the blind hole 5 for the via 3 can create defects in the semiconductor layer sequence 1 in the vicinity of the via 3 . Such defects can increase a non-radiative recombination rate of electrons and holes , thereby reducing the internal quantum ef ficiency of the optoelectronic semiconductor chip 100 , potentially down to zero . In order to reduce or mitigate this ef fect , the optoelectronic semiconductor chip 100 comprises an electron and hole barrier 4 that completely surrounds the via 3 in lateral directions . The electron and hole barrier 4 extends between 1 nanometer and 100 micrometer into the semiconductor layer sequence 1 form the edge 31 of the via 3 in lateral directions . The electron and hole barrier 4 has a higher aluminum content and thus a higher band gap than the active layer 2 , thereby reducing a probability of electrons and / or holes moving towards the via 3 . Consequently, the non-radiative recombination rate is reduced and the internal quantum ef ficiency of the optoelectronic semiconductor chip 100 is advantageously increased .

[0075] This patent application claims the priority of German patent application DE 102023118811 . 9 , the disclosure content of which is hereby incorporated by reference .

[0076] The invention is not restricted to the exemplary embodiments by the description on the basis of said exemplary embodiments . Rather, the invention encompasses any new feature and also any combination of features , which in particular comprises any combination of features in the patent claims and any combination of features in the exemplary embodiments , even i f this feature or this combination itsel f is not explicitly speci fied in the patent claims or exemplary embodiments .

[0077] References

[0078] 1 semiconductor layer sequence

[0079] 11 p-doped region

[0080] 12 n-doped region

[0081] 13 main surface

[0082] 14 current spreading layer

[0083] 15 roughening layer

[0084] 2 active layer

[0085] 3 via

[0086] 31 edge of the via

[0087] 4 electron and hole barrier

[0088] 5 hole

[0089] 51 bottom surface

[0090] 52 side surface

[0091] 6 growth substrate

[0092] 7 hardmask

[0093] 71 transparent conductive oxide

[0094] 72 dielectric Bragg mirror

[0095] 73 opening

[0096] 74 metallic layer

[0097] 75 passivation

[0098] 8 carrier

[0099] 9 electrically conductive material

[0100] 100 optoelectronic semiconductor chip

Claims

Claims1. A method for producing an optoelectronic semiconductor chip (100) , comprising the steps of:- epitaxially growing a semiconductor layer sequence (1) with an active layer (2) for emitting electromagnetic radiation, wherein the active layer (2) comprises a phosphide compound semiconductor material or an arsenide compound semiconductor material ,- forming a via (3) in the semiconductor layer sequence (1) for electrically contacting the semiconductor layer sequence (1) ,- forming an electron and hole barrier (4) within the semiconductor layer sequence (1) at an edge (31) of the via (3) .

2. The method according to claim 1, wherein the step of forming the electron and hole barrier (4) is performed before the step of forming the via (3) .

3. The method according to claim 1, wherein- the step of forming the via (3) comprises forming a hole(5) in the semiconductor layer sequence (1) , and- the electron and hole barrier (4) is formed after forming the hole (5) in the semiconductor layer sequence (1) .

4. The method according to any of the previous claims, wherein- the semiconductor layer sequence (1) comprises a p-doped region (11) and an n-doped region (12) ,- the semiconductor layer sequence (1) is epitaxially grown such that the p-doped region (11) faces away from a growth substrate (6) , and- the via (3) extends from a main surface (13) of the semiconductor layer sequence (1) in the p-doped region (11) through the active layer (2) to the n-doped region (12) .

5. The method according to any of the previous claims, wherein the electron and hole barrier (4) is formed by diffusing atoms into a region of the semiconductor layer sequence (1) adjacent to the via (3) .

6. The method according to any of the previous claims, wherein a hardmask (7) is deposited on the semiconductor layer sequence (1) before the electron and hole barrier (4) is formed.

7. The method according to the previous claim, wherein the hardmask (7) comprises SiON, a transparent conductive oxide (71) , and / or a dielectric Bragg mirror (72) .

8. The method according to any of the previous claims, comprising an additional step of removing a growth substrate (6) from the semiconductor layer sequence (1) after forming the via (3) and / or the electron and hole barrier (4) .

9. The method according to any of the previous claims, wherein the via (3) is formed by etching the semiconductor layer sequence (1) .

10. An optoelectronic semiconductor chip (100) , comprising:- a semiconductor layer sequence (1) with an active layer (2) for emitting electromagnetic radiation, wherein the active layer (2) comprises a phosphide compound semiconductor material or an arsenide compound semiconductor material,- a via (3) in the semiconductor layer sequence (1) for electrically contacting the semiconductor layer sequence (1) ,- an electron and hole barrier (4) within the semiconductor layer sequence (1) at an edge (31) of the via (3) .

11. The optoelectronic semiconductor chip (100) according to claim 10, wherein- the semiconductor layer sequence (1) comprises a p-doped region (11) and an n-doped region (12) ,- the p-doped region (11) is arranged on a carrier (8) , and- the via (3) extends from the carrier (8) through the active layer (2) to the n-doped region (12) .

12. The optoelectronic semiconductor chip (100) according to the previous claim, wherein the optoelectronic semiconductor chip (100) is free of an electrical contact metallization on a surface of the semiconductor layer sequence (1) facing away from the carrier (8) .

13. The optoelectronic semiconductor chip (100) according to any of claims 10 to 12, wherein the semiconductor layer sequence (1) comprises a current spreading layer (14) in an n-doped region (12) .

14. The optoelectronic semiconductor chip (100) according to the previous claim, wherein the via (3) extends to the current spreading layer (14) .

15. The optoelectronic semiconductor chip (100) according to any of claims 10 to 14, wherein- the active layer (2) comprises multiple quantum well layers, and- a band gap of the electron and hole barrier (4) at the edge (31) of the via is larger than a band gap of the quantum well layers .

16. The optoelectronic semiconductor chip (100) according to any of claims 10 to 15, wherein an electrically conductive material (9) is arranged inside the via ( 3 ) .

17. The optoelectronic semiconductor chip (100) according to any of claims 10 to 16, wherein the electron and hole barrier (4) is configured to reduce non-radiative recombination processes at the edge (31) of the via ( 3 ) .

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