Controller for controlling converter, and controller system

Abstract

The present disclosure relates to a controller for controlling a converter, and a controller system. The controller for controlling a converter comprises: a main control unit, an output synchronization unit and a pulse control unit, wherein the output synchronization unit comprises an output synchronization control circuit and a pull-up circuit; the main control unit generates a pulse width modulation signal and an output control signal, the pulse width modulation signal being a driving signal which is generated for control logic of the converter, which is to be sent to a power semiconductor device of the converter, and which is used for controlling the turning-on and turning-off of the power semiconductor device, and the output control signal being at a "high" level or a "low" level, which either indicate "enabling" or "disabling" of the pulse width modulation signal, which is sent to the converter; the output synchronization control circuit of the output synchronization unit receives the output control signal from the main control unit and outputs a pulse enable control signal, and the pull-up circuit is connected to the pulse enable control signal; and the pulse control unit receives the pulse enable control signal from the output synchronization unit, receives the pulse width modulation signal from the main control unit, and on the basis of the pulse enable control signal, controls the driving signal, which is outputted to the power semiconductor device of the converter.

Description

Controller and controller system for controlling a converter Technical Field

[0001] The present disclosure generally relates to the field of converter technology, and more particularly, to a controller and a controller system for controlling a converter. Background Art

[0002] Many applications, including industry, transportation, power transmission, and power supply, require increasingly higher power converters. Due to the limited power a single power converter can provide, paralleling converters, connecting converters in series, and combining series and parallel converters are becoming increasingly popular. When converters are connected in parallel, they collectively power the load. Typically, the load capacity is much greater than the capacity of a single converter module. To prevent damage to the converter modules due to overload, the parallel converters must start and stop output synchronously. For example, if one parallel converter starts before the others, the load capacity far exceeds the design capacity of a single converter, resulting in an overload or overcurrent, and even hardware damage. If the parallel converters start asynchronously, this can also cause the entire parallel converter system to crash and fail. Alternatively, if one parallel converter stops output due to a fault while the others continue to output, an overload or overcurrent, or even system crash, can occur. Therefore, to protect the parallel converter system, all parallel converters should start and stop output synchronously. In special cases, when one or more converters stop output due to a fault, all converters should stop output synchronously.

[0003] In order to synchronously start or stop the output of parallel converters, the following three methods are mainly used.

[0004] The entire parallel converter system has a centralized controller. This controller receives information from all parallel converters and issues control commands to them. Commands to start or stop outputs should be issued synchronously. If one or more converter modules fails, the centralized controller, upon receiving the fault information, issues a synchronous stop command to all parallel converters.

[0005] Among all parallel converters, one is defined as the master converter, and the others are defined as slave converters. All converters are connected via a communication bus. The master converter can send control commands to the slave converters, and the slave converters can provide feedback on their status to the master converter. The master converter notifies all slave converters via the communication bus to start or stop. When one or more slave converters encounter a fault, they transmit this fault information to the master converter, which then commands all converters to stop. This approach requires a communication connection between the master and slave converters. Furthermore, a sophisticated master-slave management mechanism is required to manage the master-slave relationship. When the previous master converter fails, a specific converter becomes the master converter, with the remaining converters acting as slaves. Furthermore, when a slave converter fails, it notifies the master converter of the fault information via the communication connection, which in turn commands all converters to stop. This will cause a time delay, and the non-faulty machine will shut down later than the faulty machine, so there is a risk of overcurrent or overload, or even hardware damage.

[0006] One of the parallel converters is the master converter, and the others are slave converters. The master converter generates a synchronization signal to all other slave converters via a hardwired connection. This synchronization signal can be used to notify the other converters to start or stop output. If any converter stops output due to a fault, the master converter should be notified immediately. However, if the master converter fails, the entire system will collapse. If all converters can become masters, each converter must have a hardwired connection to all other converters. This connection would be very complex. If a slave converter must stop output due to a fault, there is a time delay before the master converter notifies all other converters to stop output. The risk of overcurrent or overload still exists.

[0007] Summary of the Invention

[0008] A brief overview of the present invention is provided below to provide a basic understanding of certain aspects of the present invention. It should be understood that this overview is not an exhaustive overview of the present invention. It is not intended to identify key or important aspects of the present invention, nor is it intended to limit the scope of the present invention. Its purpose is simply to present certain concepts in a simplified form as a prelude to the more detailed description discussed later.

[0009] In view of this, the present disclosure proposes a controller and a control system capable of achieving synchronous start and stop of multiple parallel-connected converters.

[0010] According to one aspect of the present disclosure, a controller for controlling a converter is provided, comprising: a main control unit, an output synchronization unit, and a pulse control unit, wherein the output synchronization unit comprises an output synchronization control circuit and a pull-up circuit.

[0011] The main control unit generates a pulse width modulation signal and an output control signal. The pulse width modulation signal is a drive signal generated by the control logic of the converter and sent to the power semiconductor device of the converter for controlling the switching thereof. The output control signal is a "high" level or a "low" level, respectively used to indicate "enabling" or "disabling" the pulse width modulation signal sent to the converter.

[0012] The output synchronization control circuit of the output synchronization unit receives the output control signal from the main control unit and outputs a pulse enable control signal, and the pull-up circuit is connected to the pulse enable control signal;

[0013] The pulse control unit receives the pulse enable control signal from the output synchronization unit and the pulse width modulation signal from the main control unit, and controls the drive signal output to the power semiconductor device of the converter according to the pulse enable control signal.

[0014] Optionally, in an example of the above aspect, the output synchronization control circuit is implemented by an OC gate circuit or an OD gate circuit.

[0015] In this way, a suitable circuit can be selected as needed to implement the output synchronization control circuit.

[0016] Optionally, in an example of the above aspect, the pull-up circuit includes: a power supply, a pull-up resistor and an on-off switch, the pull-up resistor and the on-off switch connect the pulse enable control signal to the power supply, the pull-up resistor is used to prevent a short circuit between the power supply and the ground, and the on-off switch is used to connect or disconnect the connection between the pulse enable control signal and the power supply.

[0017] In this way, a pull-up circuit can pull the pulse enable control signal to a "high" level when the output control signal is at a "high" level. The on-off switch can be used to control the on and off of the pull-up circuit, thereby flexibly adjusting the equivalent pull-up resistance of the entire "wired-AND" circuit. When only a single converter is operating independently, the converter's on-off switch must connect the pull-up circuit to enable the controller to operate normally. When multiple converters are operating in parallel, the pull-up circuits of one or more controllers can be connected, thereby flexibly adjusting the equivalent pull-up resistance of the entire circuit, but at least one pull-up circuit must be connected.

[0018] Optionally, in an example of the above aspect, the controller further includes a two-pin terminal, both contacts of the two-pin terminal are connected to the pulse enable control signal of the controller, and the two-pin terminal is used to connect the controller with other controllers.

[0019] In this way, the pulse enable control signals of all controllers are connected together. When the output control signals of all controllers are at a "high" level, the pulse enable control signals output by the output synchronization control circuits of each controller are also at a "high" level. When the output control signals output by the main control unit of one or more controllers are at a "low" level, the pulse enable control signals output by the output synchronization control circuits of all controllers are also at a "low" level. This allows for the synchronous start or stop of all parallel-connected converters.

[0020] According to another aspect of the present disclosure, a control system for controlling a converter is provided, comprising a plurality of controllers according to the above, wherein the plurality of controllers are connected in series, wherein:

[0021] The output synchronization control circuits of each controller are connected together through two-pin terminals, thereby realizing the "wired AND" between the output control signals of multiple controllers. When the output control signals of all controllers are "high", the pulse enable control signals of all controllers are "high"; when the output control signals of one or more controllers are "low", the pulse enable control signals of all controllers are "low".

[0022] Compared with the prior art, the technical solution of the present invention has at least one of the following advantages.

[0023] In the control system according to the present disclosure, there is no centralized controller and no relative connection between the centralized controller and the controller of each converter, so the hardware cost is very low and the connection is simple.

[0024] In the control system according to the present disclosure, control strategy development is simple because there is no need to develop a control system for controlling all converters, nor is there a need to develop a master-slave management mechanism.

[0025] The resources of a centralized controller are limited, so the number of converters connected in parallel is also limited. However, the control system according to the present disclosure has simple wiring, is more apt to implement distributed control, and can easily expand the number of converters connected in parallel.

[0026] In the control system according to the present disclosure, synchronous output control is implemented by hardware circuits, there is no time delay, and all converters will be shut down or started at the same time.

[0027] In the control system according to the present disclosure, there is no communication connection between different converters, the hardware cost is low, and the wiring is simple.

[0028] The control system according to the present disclosure can ensure that all converters are started or stopped simultaneously and can better protect the entire system in a fast response manner. In addition, the connection is also simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other purposes, features and advantages of the present invention will be more easily understood by referring to the following description of the embodiments of the present invention in conjunction with the accompanying drawings. The components in the accompanying drawings are only for illustrating the principles of the present invention. In the accompanying drawings, the same or similar technical features or components will be represented by the same or similar reference numerals. In the accompanying drawings:

[0030] FIG1 is a schematic circuit diagram of a controller for controlling synchronous start and stop of a converter according to an embodiment of the present disclosure.

[0031] FIG2 is an exemplary circuit topology diagram of an output synchronization control circuit implemented using an OC gate circuit.

[0032] FIG3 is an exemplary circuit topology diagram of an output synchronization control circuit implemented using an OD gate circuit.

[0033] FIG4 is a schematic diagram of a control system 400 for controlling a parallel converter system.

[0034] The reference numerals are as follows: 100: controller for controlling the converter 102: main control unit 104: output synchronization unit 106: pulse control unit 1042: output synchronization control circuit 1044: pull-up circuit output_ctrl: output control signal pwm_ctrl: pulse enable control signal Vcc: power supply R1: pull-up resistor J1: on-off switch pwm_x: pulse width modulation signal 400: control system X2: two-pin terminal DETAILED DESCRIPTION

[0035] The subject matter described herein will now be discussed with reference to exemplary embodiments. It should be understood that the discussion of these embodiments is intended solely to enable those skilled in the art to better understand and implement the subject matter described herein and is not intended to limit the scope, applicability, or examples set forth in the claims. The functions and arrangements of the elements discussed may be varied without departing from the scope of this disclosure. Various examples may omit, substitute, or add various processes or components as needed.

[0036] As used herein, the term "including" and its variations are open terms meaning "including but not limited to". The term "based on" means "based at least in part on". The terms "one embodiment" and "an embodiment" mean "at least one embodiment". The term "another embodiment" means "at least one other embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other definitions may be included below, whether explicit or implicit. Unless the context clearly indicates otherwise, the definition of a term is consistent throughout the specification.

[0037] The present invention provides a controller and a control system capable of realizing synchronous start and stop of a plurality of parallel-connected converters.

[0038] The controller and control system according to the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0039] FIG1 is a schematic circuit diagram of a controller 100 for controlling synchronous start and stop of a converter according to an embodiment of the present disclosure.

[0040] As shown in FIG. 1 , the controller 100 includes a main control unit 102 , an output synchronization unit 104 , and a pulse control unit 106 , wherein the output synchronization unit 104 includes an output synchronization control circuit 1042 and a pull-up circuit 1044 .

[0041] The main control unit 102 can generate an output control signal (output_ctrl) based on whether the converter to be controlled is in a normal state and whether the converter is to be started and drive signals are to be sent to the converter. When the converter is in a normal state and a drive signal is to be sent to the converter, the output control signal (output_ctrl) is at a high level, indicating that the drive signal to the converter is enabled. When the converter is in an abnormal state or the converter is to be shut down, the output control signal (output_ctrl) is at a low level, indicating that the drive signal to the converter is disabled. The output control signal (output_ctrl) is provided to the output synchronization control circuit 1042 in the output synchronization unit 104.

[0042] Those skilled in the art will understand that the level of the above-mentioned output control signal is set when the "high" level signal corresponds to the output of the enabled converter. If the low level signal corresponds to the output of the enabled converter in the circuit design, the level of the output control signal is opposite, and the subsequent circuit must also be adjusted according to the level logic. This situation is not described in detail in the present disclosure.

[0043] In a specific embodiment, the output synchronization control circuit 1042 can be implemented by, for example, an OC gate (open collector gate) circuit as shown in FIG. 2 or an OD gate (open drain gate) circuit as shown in FIG. 3 .

[0044] In an OC gate, when the input is low, the output is pulled low; when the input is high, the output is in a high-impedance state. This output method allows multiple OC gates to be connected and, through external pull-up resistors or pull-up power supplies, form a switching circuit to control the operation of external devices.

[0045] Therefore, the output synchronization unit 104 also includes a pull-up circuit 1044. When the output control signal output_ctrl is at a "high" level, the signal output by the output synchronization control circuit 1042 (called the pulse enable control signal pwm_ctrl) is pulled up to a "high" level, and when the output control signal output_ctrl is at a "low" level, the pulse enable control signal pwm_ctrl is also at a "low" level.

[0046] Block 1044 in Figure 1 is a schematic circuit topology diagram of a pull-up circuit. The pull-up circuit 1044 includes a power supply Vcc, a pull-up resistor R1, and an on-off switch J1.

[0047] Pull-up resistor R1 and on-off switch J1 connect the pulse enable control signal pwm_ctrl to the power supply Vcc. On-off switch J1 can be connected or disconnected by external components. For example, on-off switch J1 can use a two-pin pin connector that can be connected by a shorting cap or disconnected by removing the shorting cap. Pull-up resistor R1 prevents short circuits between the power supply Vcc and ground GND.

[0048] It is understandable that this is just a specific example of a pull-up circuit, and pull-up circuits with other circuit topologies may also be used.

[0049] Figure 2 shows an exemplary circuit topology diagram of output synchronization control circuit 1042 implemented using an OC gate circuit according to one embodiment of the present disclosure. Figure 3 shows an exemplary circuit topology diagram of output synchronization control circuit 1042 implemented using an OD gate circuit according to another embodiment of the present disclosure. The operating principle of output synchronization control circuit 1042 will be described below using the circuit in Figure 2 as an example.

[0050] As described above, when the converter is in a normal state (i.e., no fault occurs) and the converter is to be started and a drive signal is to be sent, the output control signal output_ctrl is at a "high" level; if the converter fails or the converter is to be stopped, the output control signal output_ctrl is at a "low" level.

[0051] When the output control signal output_ctrl is high, transistor Q1 is turned on, the voltage between the base and emitter of transistor Q2 is low, and transistor Q2 is turned off. The pulse enable control signal pwm_ctrl output by the output synchronization control circuit 1042 is high due to the pull-up circuit.

[0052] When the output control signal output_ctrl is at a "low" level, transistor Q1 is turned off, the voltage between the base and emitter of transistor Q2 is at a "high" level, and transistor Q2 is turned on. The pulse enable control signal pwm_ctrl output by the output synchronization control circuit 1042 is connected to the ground GND and is therefore at a "low" level.

[0053] In this disclosure, the specific functions of the resistors R1 and R2 and the capacitor C1 in FIG. 2 are not described in detail.

[0054] The working principle of the circuit in FIG3 is similar to that of the circuit in FIG2 , and the working principle of the circuit in FIG3 will not be described in detail in this disclosure.

[0055] The main control unit 102 also outputs a set of pulse-width modulated signals (PWM)_x. PWM signals (PWM)_x are drive signals generated by the converter's control logic and sent to the converter's various power semiconductor devices. These drive signals are pulse signals that use a high level and a low level to control the on / off state of the converter's various power devices (when the high level turns on). PWM signals (PWM)_x are input to the pulse control unit 106, along with a pulse enable control signal (PWM)_ctrl from the output synchronization control circuit 1042. The pulse control unit 106 then determines whether to enable PWM signals (PWM)_x based on the pulse enable control signal (PWM)_ctrl.

[0056] Specifically, the pulse enable control signal pwm_ctrl is equivalent to an enable signal. If the pulse enable control signal pwm_ctrl is at a "high" level, the pulse width modulation signal pwm_x can pass through the pulse control unit 106 normally, so that it can be transmitted to the power devices of the converter to control the opening and closing of the power devices; if the pulse enable control signal pwm_ctrl is at a "low" level, the pulse width modulation signal is not allowed to pass through, and all drive signals output by the pulse control unit 106 are at a "low" level. The "low" level signal causes all power devices of the converter to stop working (here, the "high" level in the circuit design corresponds to the power device being turned on as an example for explanation).

[0057] In one example, the above functions can be implemented using an AND gate in the pulse control unit 106. The output signal of the pulse control unit 106 is provided to the power devices of the converter to control the start and stop of the converter, which will not be described in detail here.

[0058] As can be seen from Figure 1, the controller 100 preferably also includes a two-pin terminal X2, through which the pulse enable control signal of the controller can be connected with the pulse enable control signals of other controllers. Specifically, the first terminal 1 of the two-pin terminal X2 of the controller 100 can be connected to the second terminal 2 of another controller, and the second terminal 2 of the two-pin terminal X2 of the controller 100 can be connected to the first terminal 1 of yet another controller. In this way, the pulse enable control signals of multiple controllers can be connected together.

[0059] FIG4 is a schematic diagram of a control system 400 for controlling a parallel converter system.

[0060] Control system 400 is used to control a converter system comprising multiple converters connected in parallel. In control system 400, the output synchronization control circuits of multiple controllers are connected together to implement a "wired-AND" operation between the multiple controllers, thereby connecting the pulse enable control signals of each controller together. The pulse enable control signals of each controller are only at a "high" level when the output control signals of all controllers are at a "high" level; if the output control signals of one or more controllers are at a "low" level, the pulse enable control signals of all controllers are at a "low" level. Therefore, if the output control signals of one or more controllers are at a "low" level, all converters will be controlled to stop output simultaneously.

[0061] In a specific embodiment, in the entire control system, only the pull-up circuit of one of the controllers can be used for operation. Each pull-up circuit includes an on-off switch J1, which can be used to connect or disconnect the pull-up circuit 2044, thereby flexibly adjusting the equivalent pull-up resistance value. In a "line-and" circuit, the resistance of the pull-up resistor should be determined by the power loss of the circuit, the output voltage corresponding to the "high" level / "low" level, and the maximum current that can be conducted by the transistor or MOS tube in the output synchronization control circuit. The more on-off switches are connected, the smaller the equivalent pull-up resistance, and vice versa. In addition, when there are no multiple converters connected in parallel, the on-off switch J1 can enable only one converter to operate normally.

[0062] In the control system according to the present disclosure, there is no centralized controller and no relative connection between the centralized controller and the controller of each converter. Therefore, the hardware cost is very low and the connection is simple;

[0063] In the control system according to the present disclosure, control strategy development is simple because there is no need to develop a control system for controlling all converters, nor is there a need to develop a master-slave management mechanism.

[0064] The resources of a centralized controller are limited, so the number of converters connected in parallel is also limited. However, the control system according to the present disclosure has simple wiring, is more apt to implement distributed control, and can easily expand the number of converters connected in parallel.

[0065] In the control system according to the present disclosure, synchronous output control is implemented by hardware circuits, there is no time delay, and all converters will be shut down or started at the same time.

[0066] In the control system according to the present disclosure, there is no communication connection between different converters, the hardware cost is low, and the wiring is simple.

[0067] The control system according to the present disclosure can ensure that all converters are started or stopped simultaneously and can better protect the entire system in a fast response manner. In addition, the connection is also simple and easy to implement.

[0068] The specific embodiments described above in conjunction with the accompanying drawings describe exemplary embodiments, but do not represent all embodiments that can be implemented or fall within the scope of protection of the claims. The term "exemplary" used throughout this specification means "used as an example, instance or illustration" and does not mean "preferred" or "having advantages" over other embodiments. For the purpose of providing an understanding of the described technology, the specific embodiments include specific details. However, these technologies can be implemented without these specific details. In some instances, in order to avoid obscuring the concepts of the described embodiments, well-known structures and devices are shown in block diagram form.

[0069] The foregoing description of the present disclosure is provided to enable any person skilled in the art to implement or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is intended to be consistent with the widest range of principles and novel features disclosed herein.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0071] Nouns and pronouns referring to persons in this patent application are not limited to a specific gender.

Claims

1. A controller (100) for controlling a converter, comprising: A main control unit (102), an output synchronization unit (104) and a pulse control unit (106), wherein the output synchronization unit (104) comprises an output synchronization control circuit (1042) and a pull-up circuit (1044), The main control unit (102) generates a pulse width modulation signal (pwm_x) and an output control signal (output_ctrl), wherein the pulse width modulation signal (pwm_x) is a drive signal generated by the control logic of the converter and sent to the power semiconductor device of the converter for controlling the on and off thereof, and the output control signal (output_ctrl) is a "high" level or a "low" level, respectively used to indicate "enabling" or "disabling" the pulse width modulation signal sent to the converter; The output synchronization control circuit (1042) of the output synchronization unit (104) receives an output control signal (output_ctrl) from the main control unit (102), outputs a pulse enable control signal (pwm_ctrl), and the pull-up circuit (1044) is connected to the pulse enable control signal (pwm_ctrl); The pulse control unit (106) receives the pulse enable control signal (pwm_ctrl) from the output synchronization unit (104), receives the pulse width modulation signal (pwm_x) from the main control unit (102), and controls the drive signal output to the power semiconductor device of the converter according to the pulse enable control signal (pwm_ctrl).

2. The controller (100) according to claim 1, wherein: The output synchronization control circuit (1042) is implemented by using an OC gate circuit or an OD gate circuit.

3. The controller (100) according to claim 1, wherein: The pull-up circuit (1044) includes: a power supply (Vcc), a pull-up resistor (R1) and an on-off switch (J1), wherein the pull-up resistor and the on-off switch connect the pulse enable control signal (pwm_ctrl) to the power supply (Vcc), the pull-up resistor (R1) is used to prevent a short circuit between the power supply (Vcc) and ground, and the on-off switch (J1) is used to connect or disconnect the connection between the pull-up circuit (1044) and the pulse enable control signal (pwm_ctrl).

4. The controller (100) according to claim 1 further comprises a two-pin terminal (X2), both contacts of the two-pin terminal are connected to the pulse enable control signal (pwm_ctrl), and the two-pin terminal (X2) is used to connect the controller with other controllers.

5. A control system (400) for controlling a converter, comprising a plurality of controllers (100) according to claim 1 connected together, wherein: The pulse enable control signals output by the output synchronization control circuits (1042) of the controllers (100) are connected together through two-pin terminals (X2) to realize "wired AND" between the output control signals of the multiple controllers. When the output control signals output by the main control units of all the controllers are at a "high" level, the pulse enable control signals output by the output synchronization control circuits of the controllers are at a "high" level; when the output control signals output by the main control units of one or more controllers are at a "low" level, the pulse enable control signals output by the output synchronization control circuits of all the controllers are at a "low" level.

Images